Datasheet - Spansion

Spansion® SLC NAND Flash Memory for
Embedded
1 Gb, 2 Gb, 4 Gb Densities:
1-bit ECC, x8 and x16 I/O, 1.8V VCC
S34MS01G1, S34MS02G1, S34MS04G1
Spansion® SLC NAND Flash Memory for Embedded Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S34MS01G1_04G1
Revision 08
Issue Date October 28, 2014
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Spansion® SLC NAND Flash Memory for
Embedded
1 Gb, 2 Gb, 4 Gb Densities:
1-bit ECC, x8 and x16 I/O, 1.8V VCC
S34MS01G1, S34MS02G1, S34MS04G1
Data Sheet
Distinctive Characteristics
 Density
 NAND Flash Interface
– 1 Gbit / 2 Gbit / 4 Gbit
 Architecture
– Input / Output Bus Width: 8-bits / 16-bits
– Page Size:
– x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
– x16 = 1056 (1024 + 32) words; 32 words is spare area
– Block Size: 64 Pages
– x8 = 128k + 4k bytes
– x16 = 64k + 2k words
– Plane Size:
– 1 Gbit / 2 Gbit: 1024 Blocks per Plane
x8 = 128M + 4M bytes
x16 = 64M + 2M words
– 4 Gbit: 2048 Blocks per Plane
x8 = 256M + 8M bytes
x16 = 128M + 4M words
– Device Size:
– 1 Gbit: 1 Plane per Device or 128 Mbyte
– 2 Gbit: 2 Planes per Device or 256 Mbyte
– 4 Gbit: 2 Planes per Device or 512 Mbyte
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
 Supply Voltage
– 1.8V device: Vcc = 1.7V ~ 1.95V
 Security
– One Time Programmable (OTP) area
– Hardware program/erase disabled during power transition
 Additional Features
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
 Electronic Signature
– Manufacturer ID: 01h
 Operating Temperature
– Industrial: -40°C to 85°C
– Automotive: -40°C to 105°C
Performance
 Page Read / Program
– Random access: 25 µs (Max)
– Sequential access: 45 ns (Min)
– Program time / Multiplane Program time: 250 µs (Typ)
 Block Erase (S34MS01G1)
– Block Erase time: 2.0 ms (Typ)
 Block Erase / Multiplane Erase (S34MS02G1, S34MS04G1)
– Block Erase time: 3.5 ms (Typ)
Publication Number S34MS01G1_04G1
 Reliability
– 100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least 1000
program-erase cycles with ECC
 Package Options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 9 x 11 x 1 mm
Revision 08
Issue Date October 28, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
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Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
1.
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5
Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.1 S34MS01G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.6.2 S34MS02G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.6.3 S34MS04G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.7
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.
Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Address Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
Multiplane Program — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4
Page Reprogram — S34MS02G1 and S34MS04G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6
Multiplane Block Erase — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7
Copy Back Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1 Multiplane Copy Back Program — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . .25
3.7.2 Special Read for Copy Back — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . .25
3.8
EDC Operation — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8.1 Read EDC Status Register — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . .26
3.9
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 Read Status Enhanced — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11 Read Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.13 Read Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.14 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15 Multiplane Cache Program — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . 30
3.16 Read ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.17 Read ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18 Read ONFI Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19 Read Parameter Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.20 One-Time Programmable (OTP) Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Data Protection and Power On / Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Ready/Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Write Protect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
37
38
5.
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
39
39
40
41
41
Spansion® SLC NAND Flash Memory for Embedded
19
19
19
19
19
19
19
S34MS01G1_04G1_08 October 28, 2014
Data
5.7
She et
Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Data Input Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H) . . . . . . . . . . . . . . . . . . . . . . .
6.5
Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L) . . . . . . . . . . . . . . . . . . . . .
6.6
Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Page Read Operation (Interrupted by CE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
Page Read Operation Timing with CE# Don’t Care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Page Program Operation Timing with CE# Don’t Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Page Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Random Data Output In a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Multiplane Page Program Operation — S34MS02G1 and S34MS04G1. . . . . . . . . . . . . . . .
6.14 Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Multiplane Block Erase — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Copy Back Read with Optional Data Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 Copy Back Program Operation With Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 Multiplane Copy Back Program — S34MS02G1 and S34MS04G1. . . . . . . . . . . . . . . . . . . .
6.19 Read Status Register Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 Read Status Enhanced Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22 Read Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 Multiplane Cache Program — S34MS02G1 and S34MS04G1 . . . . . . . . . . . . . . . . . . . . . . .
6.25 Read ID Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26 Read ID2 Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27 Read ONFI Signature Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28 Read Parameter Page Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29 OTP Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30 Power On and Data Protection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.31 WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.
Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1
Physical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1.1 48-Pin Thin Small Outline Package (TSOP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.1.2 63-Pin Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
8.
System Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.1
System Bad Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.2
Bad Block Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
October 28, 2014 S34MS01G1_04G1_08
Spansion® SLC NAND Flash Memory for Embedded
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
51
52
52
53
54
55
55
56
58
59
61
61
62
62
63
63
64
5
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Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Figure 1.6
Figure 1.7
Figure 3.1
Figure 3.2
Figure 4.1
Figure 4.2
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
Figure 6.21
Figure 6.22
Figure 6.23
Figure 6.24
Figure 6.25
Figure 6.26
Figure 6.27
Figure 6.28
Figure 6.29
Figure 6.30
Figure 6.31
Figure 6.32
Figure 6.33
Figure 6.34
Figure 6.35
Figure 6.36
Figure 6.37
Figure 6.38
Figure 6.39
Figure 7.1
Figure 7.2
Figure 8.1
Figure 8.2
6
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48-Pin TSOP1 Contact x8, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63-BGA Contact, x8 Device (Balls Down, Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63-BGA Contact, x16 Device (Balls Down, Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Array Organization — x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Array Organization — x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Reprogram with Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready/Busy Pin Electrical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WP# Low Timing Requirements during Program/Erase Command Sequence . . . . . . . . . . .
Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Data Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Cycle Timing (EDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Read Operation (Read One Page) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Read Operation Interrupted by CE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Read Operation Timing with CE# Don’t Care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Program Operation Timing with CE# Don’t Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Page Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Erase Operation (Erase One Block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Block Erase (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copy Back Read with Optional Data Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copy Back Program with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Copy Back Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status / EDC Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status Enhanced Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Cache Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
“Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation . . . . . . . . .
“Random” Read Cache Timing, Start (and Continuation) of Cache Operation . . . . . . . . . . .
Read Cache Timing, End Of Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplane Cache Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID2 Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ONFI Signature Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Parameter Page Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTP Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On and Data Protection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Enabling / Disabling Through WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase Enabling / Disabling Through WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . .
VBM063 — 63-Pin BGA, 11 mm x 9 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spansion® SLC NAND Flash Memory for Embedded
10
11
11
12
13
14
14
22
23
37
38
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
54
54
55
55
56
56
57
57
58
59
60
61
61
62
62
63
63
64
64
65
66
67
67
S34MS01G1_04G1_08 October 28, 2014
Data
Figure 8.3
Figure 9.1
Figure 9.2
She et
Page Programming Within a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Bad Block Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 1.6
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 9.1
8
Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Cycle Map — 1 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Cycle Map — 2 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Cycle Map — 4 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDC Register Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Organization in EDC Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Organization in EDC Units by Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID for Supported Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID Byte 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID Byte 4 Description — S34MS01G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read ID Byte 4 Description — S34MS02G1 and S34MS04G1. . . . . . . . . . . . . . . . . . . . . . .
Read ID Byte 5 Description — S34MS02G1 and S34MS04G1. . . . . . . . . . . . . . . . . . . . . . .
Parameter Page Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitance (TA = 25°C, f=1.0 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spansion® SLC NAND Flash Memory for Embedded
10
12
15
16
17
18
20
26
26
27
28
31
31
32
32
33
33
34
39
39
39
40
41
41
42
69
S34MS01G1_04G1_08 October 28, 2014
Data
She et
1. General Description
The Spansion S34MS01G1, S34MS02G1, and S34MS04G1 series is offered in 1.8 VCC and VCCQ power
supply, and with x8 or x16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid
state mass storage market. The memory is divided into blocks that can be erased independently so it is
possible to preserve valid data while old data is erased. The page size for x8 is (2048 + 64 spare) bytes; for
x16 (1024 + 32) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To
extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the
NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache
reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers
to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (x8), or 1056
words (x16) in 250 µs and an erase operation can typically be performed in 2 ms (S34MS01G1) on a 128-kB
block (x8) or 64-kword block (x16). In addition, thanks to multiplane architecture, it is possible to program two
pages at a time (one per plane) or to erase two blocks at a time (again, one per plane). The multiplane
architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 45 ns cycle time per byte. The I/O pins serve as
the ports for command and address input as well as data input/output. This interface allows a reduced pin
count and easy migration towards different densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control
pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse
repetition, where required, and internal verification and margining of data. A WP# pin is available to provide
hardware protection against program and erase operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if
the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy
pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program
operation fails the data can be directly programmed in another page inside the same array section without the
time consuming serial data insertion phase. The Copy Back operation automatically executes embedded
error detection operation: 1-bit error out of every 528 bytes (x8) or 264 words (x16) can be detected. With this
feature it is no longer necessary to use an external mechanism to detect Copy Back operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane
cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by
programing data using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page
Reprogram re-programs one page. Normally, this operation is performed after a failed Page Program
operation. Similarly, the Multiplane Page Reprogram re-programs two pages in parallel, one per plane. The
first page must be in the first plane while the second page must be in the second plane. The Multiplane Page
Reprogram operation is performed after a failed Multiplane Page Program operation. The Page Reprogram
and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted
during re-program operations.
Note: The S34MS01G1 device does not support EDC.
October 28, 2014 S34MS01G1_04G1_08
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The devices come with an OTP (one time programmable) area, which is a restricted access area where
sensitive data/code can be stored permanently. This security feature is subject to an NDA (non-disclosure
agreement) and is, therefore, not described in the data sheet. For more details, contact your nearest
Spansion sales office.
Density (bits)
Device
Main
S34MS01G1
S34MS02G1
S34MS04G1
1.1
Number of Planes
Number of Blocks
per Plane
EDC Support
1
1024
No
2
1024
Yes
2
2048
Yes
Spare
128M x 8
4M x 8
64M x 16
2M x 16
256M x 8
8M x 8
128M x 16
4M x 16
512M x 8
16M x 8
256M x 16
8M x 16
Logic Diagram
Figure 1.1 Logic Diagram
VCC
I/O0~I/O7
CE#
WE#
R/B#
RE#
ALE
CLE
WP#
VSS
Table 1.1 Signal Names
I/O7 - I/O0 (x8)
Data Input / Outputs
I/O8 - I/O15 (x16)
10
CLE
Command Latch Enable
ALE
Address Latch Enable
CE#
Chip Enable
RE#
Read Enable
WE#
Write Enable
WP#
Write Protect
R/B#
Read/Busy
VCC
Power Supply
VSS
Ground
NC
Not Connected
Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
1.2
She et
Connection Diagram
Figure 1.2 48-Pin TSOP1 Contact x8, x16 Devices
x16
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
12
13
48
NAND Flash
TSOP1
37
36
25
24
x8
x16
VSS (1)
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC (1)
NC
VCC
VSS
NC
VCC (1)
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS (1)
VSS
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
VCC
NC
VCC
VSS
NC
VCC
I/011
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
VSS
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be
bonded internally.
Figure 1.3 63-BGA Contact, x8 Device (Balls Down, Top View)
A1
A2
A9
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC (1)
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS (1)
NC
G3
G4
G5
G6
G7
G8
NC
VCC (1)
NC
NC
NC
NC
H3
H4
H5
H6
H7
H8
NC
I/O0
NC
NC
NC
Vcc
J3
J4
J5
J6
J7
J8
NC
I/O1
NC
VCC
I/O5
I/O7
K3
K4
K5
K6
K7
K8
VSS
I/O2
I/O3
I/O4
I/O6
VSS
A10
L1
L2
L9
L10
NC
NC
NC
NC
M1
M2
M9
M10
NC
NC
NC
NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be
bonded internally.
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Figure 1.4 63-BGA Contact, x16 Device (Balls Down, Top View)
A1
A2
A9
NC
NC
NC
NC
B9
B10
NC
NC
B1
NC
1.3
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS
NC
G3
G4
G5
G6
G7
G8
NC
VCC
NC
I/O13
I/O15
NC
H3
H4
H5
H6
H7
H8
I/O8
I/O0
I/O10
I/O12
I/O14
Vcc
J3
J4
J5
J6
J7
J8
I/O9
I/O1
I/O11
VCC
I/O5
I/O7
K3
K4
K5
K6
K7
K8
VSS
I/O2
I/O3
I/O4
I/O6
VSS
A10
L1
L2
L9
L10
NC
NC
NC
NC
M1
M2
M9
M10
NC
NC
NC
NC
Pin Description
Table 1.2 Pin Description
Pin Name
Description
I/O0 - I/O7 (x8)
I/O8 - I/O15 (x16)
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
CE#
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE#
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE#
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP#
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
R/B#
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when VCC is less than VLKO.
VSS
Ground.
NC
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from
the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever VCC is below 1.1V to protect the device from any involuntary program/erase
during power transitions.
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
1.4
She et
Block Diagram
Figure 1.5 Functional Block Diagram
Address
Register/
Counter
Program Erase
Controller
HV Generation
1024 Mbit + 32 Mbit (1 Gb Device)
X
2048 Mbit + 64 Mbit (2 Gb Device)
D
E
C
O
D
E
R
4096 Mbit + 128 Mbit (4 Gb Device)
ALE
CLE
NAND Flash
Memory Array
WE#
CE#
WP#
Command
Interface
Logic
RE#
PAGE Buffer
Command
Register
Y Decoder
I/O Buffer
Data
Register
I/O0~I/O7 (x8)
I/O0~I/O15 (x16)
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Array Organization
Figure 1.6 Array Organization — x8
1 Page = (2k + 64) bytes
Plane(s)
1024
Blocks
per
Plane
0
1 Block = (2k + 64) bytes x 64 pages
= (128k + 4k) bytes
1
1 Plane = (128k + 4k) bytes x 1024 Blocks
2
Note:
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
2 Gb and 4 Gb devices have two Planes
1022
1023
I/O
[7:0]
Page Buffer
2048 bytes
64 bytes
Array Organization(x8)
Figure 1.7 Array Organization — x16
1 Page = (1k + 32) words
Plane(s)
1024
Blocks
per
Plane
0
1 Block = (1k + 32) words x 64 pages
= (64k + 2k) words
1
1 Plane = (64k + 2k) words x 1024 Blocks
2
Note:
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
2 Gb and 4 Gb devices have two Planes
1022
1023
I/O0~I/O15
Page Buffer
1024 words
32 words
Array Organization(x16)
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Data
1.6
1.6.1
She et
Addressing
S34MS01G1
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle
I/O [15:8] (5)
I/O0
I/O1
I/O2
1st / Col. Add. 1
—
A0 (CA0)
A1 (CA1)
A2 (CA2)
2nd / Col. Add. 2
—
A8 (CA8)
A9 (CA9)
3rd / Row Add. 1
—
A12 (PA0)
A13 (PA1)
A14 (PA2)
4th / Row Add. 2
—
A20 (BA2)
A21 (BA3)
A22 (BA4)
I/O3
I/O4
I/O5
I/O6
I/O7
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
Low
Low
Low
Low
A15 (PA3)
A16 (PA4)
A17 (PA5)
A18 (BA0)
A19 (BA1)
A23 (BA5)
A24 (BA6)
A25 (BA7)
A26 (BA8)
A27 (BA9)
x8
A10 (CA10) A11 (CA11)
x16
1st / Col. Add. 1
Low
A0 (CA0)
A1 (CA1)
A2 (CA2)
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
2nd / Col. Add. 2
Low
A8 (CA8)
A9 (CA9)
A10 (CA10)
Low
Low
Low
Low
Low
3rd / Row Add. 1
Low
A11 (PA0)
A12 (PA1)
A13 (PA2)
A14 (PA3)
A15 (PA4)
A16 (PA5)
A17 (BA0)
A18 (BA1)
4th / Row Add. 2
Low
A19 (BA2)
A20 (BA3)
A21 (BA4)
A22 (BA5)
A23 (BA6)
A24 (BA7)
A25 (BA8)
A26 (BA9)
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. BAx = Block Address bit.
4. Block address concatenated with page address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the x8 address bits, the following rules apply:
 A0 - A11: column address in the page
 A12 - A17: page address in the block
 A18 - A27: block address
For the x16 address bits, the following rules apply:
 A0 - A10: column address in the page
 A11 - A16: page address in the block
 A17 - A26: block address
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S hee t
S34MS02G1
Table 1.4 Address Cycle Map — 2 Gb Device
Bus Cycle
I/O [15:8] (6)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add. 1
—
A0 (CA0)
A1 (CA1)
A2 (CA2)
2nd / Col. Add. 2
—
A8 (CA8)
A9 (CA9)
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
Low
Low
Low
3rd / Row Add. 1
—
A12 (PA0)
A13 (PA1)
A14 (PA2)
Low
A15 (PA3)
A16 (PA4)
A17 (PA5)
A18 (PLA0) A19 (BA0)
4th / Row Add. 2
—
A20 (BA1)
A21 (BA2)
5th / Row Add. 3
—
A28 (BA9)
Low
A22 (BA3)
A23 (BA4)
A24 (BA5)
A25 (BA6)
A26 (BA7)
A27 (BA8)
Low
Low
Low
Low
Low
Low
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
Low
Low
x8
A10 (CA10) A11 (CA11)
x16
1st / Col. Add. 1
Low
2nd / Col. Add. 2
Low
3rd / Row Add. 1
Low
4th / Row Add. 2
Low
5th / Row Add. 3
Low
A0 (CA0)
A1 (CA1)
A2 (CA2)
A8 (CA8)
A9 (CA9)
A10 (CA10)
Low
Low
Low
A11 (PA0)
A12 (PA1)
A13 (PA2)
A14 (PA3)
A15 (PA4)
A16 (PA5)
A17 (PLA0) A18 (BA0)
A19 (BA1)
A20 (BA2)
A21 (BA3)
A22 (BA4)
A23 (BA5)
A24 (BA6)
A25 (BA7)
A26 (BA8)
A27 (BA9)
Low
Low
Low
Low
Low
Low
Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the x8 address bits, the following rules apply:
 A0 - A11: column address in the page
 A12 - A17: page address in the block
 A18: plane address (for multiplane operations) / block address (for normal operations)
 A19 - A28: block address
For the x16 address bits, the following rules apply:
 A0 - A10: column address in the page
 A11 - A16: page address in the block
 A17: plane address (for multiplane operations) / block address (for normal operations)
 A18 - A27: block address
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Spansion® SLC NAND Flash Memory for Embedded
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Data
1.6.3
She et
S34MS04G1
Table 1.5 Address Cycle Map — 4 Gb Device
Bus Cycle
I/O [15:8] (6)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add. 1
—
A0 (CA0)
A1 (CA1)
A2 (CA2)
2nd / Col. Add. 2
—
A8 (CA8)
A9 (CA9)
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
Low
Low
Low
3rd / Row Add. 1
—
A12 (PA0)
A13 (PA1)
A14 (PA2)
A15 (PA3)
A16 (PA4)
Low
4th / Row Add. 2
—
A20 (BA1)
A21 (BA2)
A22 (BA3)
A23 (BA4)
A24 (BA5) A25 (BA6)
A26 (BA7)
A27 (BA8)
5th / Row Add. 3
—
A28 (BA9) A29 (BA10)
Low
Low
Low
Low
Low
Low
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
Low
Low
Low
x8
A10 (CA10) A11 (CA11)
A17 (PA5) A18 (PLA0) A19 (BA0)
x16
1st / Col. Add. 1
Low
A0 (CA0)
A1 (CA1)
A2 (CA2)
2nd / Col. Add. 2
Low
3rd / Row Add. 1
Low
A8 (CA8)
A9 (CA9)
A10 (CA10)
Low
Low
A11 (PA0)
A12 (PA1)
A13 (PA2)
A14 (PA3)
A15 (PA4)
4th / Row Add. 2
Low
A19 (BA1)
5th / Row Add. 3
Low
A27 (BA9) A28 (BA10)
A20 (BA2)
A21 (BA3)
A22 (BA4)
A23 (BA5) A24 (BA6)
Low
Low
Low
A16 (PA5) A17 (PLA0) A18 (BA0)
Low
A25 (BA7)
A26 (BA8)
Low
Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the x8 address bits, the following rules apply:
 A0 - A11: column address in the page
 A12 - A17: page address in the block
 A18: plane address (for multiplane operations) / block address (for normal operations)
 A19 - A29: block address
For the x16 address bits, the following rules apply:
 A0 - A10: column address in the page
 A11 - A16: page address in the block
 A17: plane address (for multiplane operations) / block address (for normal operations)
 A18 - A28: block address
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S hee t
Mode Selection
Table 1.6 Mode Selection
Mode
CLE
ALE
CE#
WE#
RE#
WP#
Command Input
High
Low
Low
Rising
High
X
Address Input
Low
High
Low
Rising
High
X
Command Input
High
Low
Low
Rising
High
High
Address Input
Read Mode
Program or Erase Mode
Low
High
Low
Rising
High
High
Data Input
Low
Low
Low
Rising
High
High
Data Output (on going)
Low
Low
Low
High
Falling
X
Data Output (suspended)
X
X
X
High
High
X
Busy Time in Read
X
X
X
High
High (3)
X
Busy Time in Program
X
X
X
X
X
High
Busy Time in Erase
X
X
X
X
X
High
Write Protect
X
X
X
X
X
Low
Stand By
X
X
High
X
X
0V / VCC (2)
Notes:
1. X can be VIL or VIH. High = Logic level high. Low = Logic level low.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
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Spansion® SLC NAND Flash Memory for Embedded
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Data
She et
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See Table 1.6.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
2.1
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See Figure 6.1 on page 43 and Table 5.4 on page 40 for
details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus
configuration (x8 or x16).
2.2
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34MS02G1 and
S34MS04G1 devices, five write cycles are needed to input the addresses. For the S34MS01G1, four write
cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to
S34MS01G1, which will be ignored by the NAND device without causing problems. Addresses are accepted
with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and
latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/
erase) the Write Protect pin must be high. See Figure 6.2 on page 44 and Table 5.4 on page 40 for details of
the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or
x16). Refer to Table 1.3 through Table 1.5 on page 17 for more detailed information.
2.3
Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising
edge of Write Enable. See Figure 6.3 on page 44 and Table 5.4 on page 40 for details of the timing
requirements.
2.4
Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status
Register content, the EDC register content, and the ID data. Data can be serially shifted out by toggling the
Read Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch
Enable low. See Figure 6.4 on page 45 to Figure 6.22 on page 54 and Table 5.4 on page 40 for details of the
timings requirements.
2.5
Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify
operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by
Write Enable to ensure the protection even during power up.
2.6
Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
October 28, 2014 S34MS01G1_04G1_08
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3. Command Set
Table 3.1 Command Set
Command
Acceptable
Command
during Busy
Supported on
S34MS01G1
30h
No
Yes
10h
No
Yes
No
Yes
No
Yes
No
No
1st Cycle
2nd Cycle
3rd Cycle
Page Read
00h
Page Program
80h
Random Data Input
85h
Random Data Output
05h
E0h
Multiplane Program
80h
11h
81h
10h
80h
10h
ONFI Multiplane Program
80h
11h
Page Reprogram
8Bh
10h
Multiplane Page Reprogram
8Bh
11h
Block Erase
60h
D0h
Multiplane Block Erase
60h
60h
D0h
ONFI Multiplane Block Erase
60h
D1h
60h
Copy Back Read
00h
Copy Back Program
85h
8Bh
4th Cycle
10h
No
No
No
No
No
No
No
Yes
No
No
No
No
35h
No
Yes
10h
No
Yes
D0h
Multiplane Copy Back Program
85h
11h
81h
10h
No
No
ONFI Multiplane Copy Back Program
85h
11h
85h
10h
No
No
Special Read For Copy Back
00h
36h
Read EDC Status Register
7Bh
Read Status Register
Read Status Enhanced
No
No
Yes
No
70h
Yes
Yes
78h
Yes
No
Reset
FFh
Yes
Yes
Read Cache
31h
No
Yes
Read Cache Enhanced
00h
Read Cache End
3Fh
Cache Program (End)
80h
Cache Program (Start) / (Continue)
80h
Multiplane Cache Program (Start/Continue)
80h
11h
81h
ONFI Multiplane Cache Program (Start/Continue)
80h
11h
80h
Multiplane Cache Program (End)
80h
11h
ONFI Multiplane Cache Program (End)
80h
11h
Read ID
90h
Read ID2
30h-65h-00h
31h
No
No
No
Yes
10h
No
Yes
15h
No
Yes
15h
No
No
15h
No
No
81h
10h
No
No
80h
10h
No
No
30h
No
Yes
No
Yes
Read ONFI Signature
90h
No
Yes
Read Parameter Page
ECh
No
Yes
29h-17h-04h-19h
No
Yes
One-time Programmable (OTP) Area Entry
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
3.1
She et
Page Read
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or
five cycles for S34MS01G1). Two types of operations are available: random read and serial page read.
Random read mode is enabled when the page address is changed. All data within the selected page are
transferred to the data registers. The system controller may detect the completion of this data transfer (tR) by
analyzing the output of the R/B pin. Once the data in a page is loaded into the data registers, they may be
read out in 45 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE#
signal makes the device output the data, starting from the selected column address up to the last column
address.
The device may output random data in a page instead of the sequential data by writing Random Data Output
command. The column address of next data, which is going to be out, may be changed to the address that
follows Random Data Output command. Random Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation.
Any operation other than read or Random Data Output causes the device to exit read mode.
See Figure 6.6 on page 46 and Figure 6.12 on page 49 as references.
3.2
Page Program
A page program cycle consists of a serial data loading period in which up to 2112 bytes (x8) or 1056 words
(x16) of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five
cycle address inputs (four cycles for S34MS01G1) and then serial data. The words other than those to be
programmed do not need to be loaded. The device supports Random Data Input within a page. The column
address of next data, which will be entered, may be changed to the address that follows the Random Data
Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read
the Status Register. The system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or
Reset command are valid while programming is in progress. When the Page Program is complete, the Write
Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid
command is written to the command register. Figure 6.9 on page 47 and Figure 6.11 on page 48 detail the
sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or
consecutive bytes up to 2112 bytes (x8) or 1056 words (x16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in Table 5.7 on page 42. Pages may be programmed in any order within a
block.
Users who use “EDC check” (for S34MS02G1 and S34MS04G1 only) in copy back must comply with some
limitations related to data handling during one page program sequence. Refer to Section 3.8 on page 25 for
details.
If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted page is not used for further reading or programming operations until the next
uninterrupted block erase is complete.
October 28, 2014 S34MS01G1_04G1_08
Spansion® SLC NAND Flash Memory for Embedded
21
D at a
3.3
S hee t
Multiplane Program — S34MS02G1 and S34MS04G1
The S34MS02G1 and S34MS04G1 devices support Multiplane Program, making it possible to program two
pages in parallel, one page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (x8) or
2112 words (x16) of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell. The serial data loading period begins with
inputting the Serial Data Input command (80h), followed by the five cycle address inputs and serial data for
the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device supports Random
Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has
become ready again, the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its
serial data input. The address for this page must be in the 2nd plane (PLA0 = 1). The Program Confirm
command (10h) starts parallel programming of both pages.
Figure 6.13 on page 49 describes the sequences using the legacy protocol. In this case, the block address
bits for the first plane are all zero and the second address issued selects the block for both planes.
Figure 6.14 on page 50 describes the sequences using the ONFI protocol. For both addresses issued in this
protocol, the block address bits must be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or
78h). The Read Status Register command is also available during Dummy Busy time (tDBSY). In case of
failure in either page program, the fail bit of the Status Register will be set. Refer to Section 3.9 on page 27 for
further info.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in Table 5.7 on page 42. Pages may be programmed in any order within a
block.
If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted pages are not used for further reading or programming operations until the
next uninterrupted block erases are complete for the applicable blocks.
3.4
Page Reprogram — S34MS02G1 and S34MS04G1
Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host
may call Page Reprogram. This command allows the reprogramming of the same pattern of the last (failed)
page into another memory location. The command sequence initiates with reprogram setup (8Bh), followed
by the five cycle address inputs of the target page. If the target pattern for the destination page is not changed
compared to the last page, the program confirm can be issued (10h) without any data input cycle, as
described in Figure 3.1.
Figure 3.1 Page Reprogram
As defined for Page
Program
CMD
Cycle Type
ADDR
A
ADDR
ADDR
ADDR
ADDR
Din
Din
Din
Din
CMD
D0
D1
...
Dn
10h
tADL
I/Ox
00h
C1
C2
R1
R2
R3
tWB
tPROG
SR[6]
Page N
A
Cycle Type
CMD
Dout
CMD
ADDR
ADDR
ADDR
ADDR
ADDR
CMD
I/Ox
70h
E1
8Bh
C1
C2
R1
R2
R3
10h
tWB
tPROG
SR[6]
FAIL !
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On the other hand, if the pattern bound for the target page is different from that of the previous page, data in
cycles can be issued before program confirm ‘10h’, as described in Figure 3.2.
Figure 3.2 Page Reprogram with Data Manipulation
As defined for Page
Program
CMD
Cycle Type
ADDR
A
ADDR
ADDR
ADDR
ADDR
Din
Din
Din
Din
CMD
CMD
Dout
D0
D1
...
Dn
10h
70h
E1
tADL
IOx
80h
C1
C2
R1
R2
R3
tWB
tPROG
SR[6]
Cycle Type
FAIL !
Page N
A
CMD
ADDR
ADDR
ADDR
ADDR
ADDR
Din
Din
Din
Din
CMD
D0
D1
...
Dn
10h
tADL
I/Ox
8Bh
C1
C2
R1
R2
R3
tWB
tPROG
SR[6]
Page M
The device supports Random Data Input within a page. The column address of next data, which will be
entered, may be changed to the address which follows the Random Data Input command (85h). Random
Data Input may be operated multiple times regardless of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be issued to read the Status Register. The system controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only
errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status
command mode until another valid command is written to the command register.
The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program
the data to a different plane, use the Page Program operation instead. The Multiplane Page Reprogram can
re-program two pages in parallel, one per plane. The Multiplane Page Reprogram operation is performed
after a failed Multiplane Page Program operation. The command sequence is very similar to Figure 6.13
on page 49, except that it requires the Page Reprogram Command (8Bh) instead of 80h and 81h.
If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted page is not used for further reading or programming operations until the next
uninterrupted block erase is complete.
3.5
Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles
(two cycles for S34MS01G1) initiated by an Erase Setup command (60h). Only the block address bits are
valid while the page address bits are ignored.
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process.
This two-step sequence of setup followed by the execution command ensures that memory contents are not
accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase
and erase verify. Once the erase process starts, the Read Status Register commands (70h or 78h) may be
issued to read the Status Register.
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The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit
(I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid
while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O0) may be
checked. Figure 6.15 on page 50 details the sequence.
If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted block is erased under continuous power conditions before that block can be
trusted for further programming and reading operations.
3.6
Multiplane Block Erase — S34MS02G1 and S34MS04G1
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. In this
case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion. See
Table 5.7 on page 42 for performance information.
For the Multiplane Block Erase operation, the address of the first block must be within the first plane
(PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See Figure 6.16 on page 51
for a description of the legacy protocol. In this case, the block address bits for the first plane are all zero and
the second address issued selects the block for both planes. Figure 6.17 on page 51 describes the
sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits must
be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or
78h). The Read Status Register command is also available during Dummy Busy time (tDBSY). In case of
failure in either erase, the fail bit of the Status Register will be set. Refer to Section 3.9 on page 27 for further
information.
If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted blocks are erased under continuous power conditions before those blocks
can be trusted for further programming and reading operations.
3.7
Copy Back Program
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the
system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to
be updated and the rest of the block also needs to be copied to the newly assigned free block. The operation
for performing a copy back is a sequential execution of page-read (without mandatory serial access) and
Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole page of data into the internal data register. As soon as the
device returns to the Ready state, optional data read-out is allowed by toggling RE# (see Figure 6.18
on page 52), or the Copy Back Program command (85h) with the address cycles of the destination page may
be written. The Program Confirm command (10h) is required to actually begin programming.
The source and the destination pages in the Copy Back Program sequence must belong to the same device
plane (same PLA0 for S34MS02G1 and S34MS04G1). Copy Back Read and Copy Back Program for a given
plane must be between odd address pages or between even address pages for the device to meet the
program time (tPROG) specification. Copy Back Program may not meet this specification when copying from
an odd address page (source page) to an even address page (target page) or from an even address page
(source page) to an odd address page (target page).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as
shown in Figure 6.19 on page 52. As noted in Section 1. on page 9 the device may include an automatic EDC
(for S34MS02G1 and S34MS04G1) check during the copy back operation, to detect single bit errors in EDC
units contained within the source page. More details on EDC operation and limitations related to data input
handling during one Copy Back Program sequence are available in Section 3.8 on page 25.
If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted page is not used for further reading or programming operations until the next
uninterrupted block erase is complete.
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Multiplane Copy Back Program — S34MS02G1 and S34MS04G1
The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the
Page Program. Multiplane Copy Back Program must be preceded by two single page Copy Back Read
command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane).
Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane
can be copied only to a destination page of the same plane. EDC check is available also for Multiplane Copy
Back Program only for S34MS02G1 and S34MS04G1.
When “EDC check” is used in copy back, it must comply with some limitations related to data handling during
one Multiplane Copy Back Program sequence. Please refer to Section 3.8 on page 25 for details on EDC
operation. The Multiplane Copy Back Program sequence represented in Figure 6.20 on page 53 shows the
legacy protocol. In this case, the block address bits for the first plane are all zero and the second address
issued selects the block for both planes. Figure 6.21 on page 54 describes the sequence using the ONFI
protocol. For both addresses issued in this protocol, the block address bits must be the same except for the
bit(s) that select the plane.
If a Multiplane Copy Back Program operation is interrupted by hardware reset, power failure or other means,
the host must ensure that the interrupted pages are not used for further reading or programming operations
until the next uninterrupted block erases are complete for the applicable blocks.
3.7.2
Special Read for Copy Back — S34MS02G1 and S34MS04G1
The S34MS02G1 and S34MS04G1 devices support Special Read for Copy Back. If Copy Back Read
(described in Section 3.7 and Section 3.7.1 on page 25) is triggered with confirm command ‘36h’ instead
‘35h’, Copy Back Read from target page(s) will be executed with an increased internal (VPASS) voltage.
This special feature is used in order to minimize the number of read errors due to over-program or read
disturb — it shall be used only if ECC read errors have occurred in the source page using Page Read or Copy
Back Read sequences.
Excluding the Copy Back Read confirm command, all other features described in Section 3.7 and
Section 3.7.1 for standard copy back remain valid (including the figures referred to in those sections).
3.8
EDC Operation — S34MS02G1 and S34MS04G1
Error Detection Code check is a feature that can be used during the copy back operation (both single and
multiplane) to detect single bit errors occurring in the source page(s).
Note: The S34MS01G1 device does not support EDC.
 EDC check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is
composed of 512 bytes of main array and 16 bytes of spare area (see Table 3.3 and Table 3.4
on page 27). The described 528-byte area is called an “EDC unit.”
 In the x16 device, EDC allows detection of up to 1 single bit error every 264 words, where each 264 word
group is composed by 256 words of main array and 8 words of spare area see Table 3.3 and Table 3.4
on page 27). The described 264-word area is called “EDC unit.”
EDC results can be checked through a specific Read EDC register command, available only after issuing a
Copy Back Program or a Multiplane Copy Back Program. The EDC register can be queried during the copy
back program busy time (tPROG).
For the “EDC check” feature to operate correctly, specific conditions on data input handling apply for program
operations.
For the case of Page Program, Multiplane Page Program, Page Reprogram, Multiplane Page Reprogram,
Cache Program, and Multiplane Cache Program operations:
 In Section 3.2 on page 21 it was explained that a number of consecutive partial program operations (NOP)
is allowed within the same page. In case this feature is used, the number of partial program operations
occurring in the same EDC unit must not exceed 1. In other words, page program operations must be
performed on the whole page, or on whole EDC unit at a time.
 “Random Data Input” in a given EDC unit can be executed several times during one page program
sequence, but data cannot be written to any column address more than once before the program is
initiated.
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For the case of Copy Back Program or Multiplane Copy Back Program operations:
 If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buffer.
In other words, the EDC check is possible only if the whole EDC unit is modified during one Copy Back
Program sequence.
 “Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program
sequence, but data insertion in each column address of the EDC unit must not exceed 1.
If you use copy back without EDC check, none of the limitations described above apply.
After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of
both the program operation and the Copy Back Read. If the EDC was valid and an error was reported in the
EDC (see Table 3.2 on page 26), the host may perform Special Read For Copy Back on the source page and
attempt the Copy Back Program again. If this also fails, the host can execute a Page Read operation in order
to correct a single bit error with external ECC software or hardware.
3.8.1
Read EDC Status Register — S34MS02G1 and S34MS04G1
This operation is available only after issuing a Copy Back Program and it allows the detection of errors during
Copy Back Read. In the case of multiplane copy back, it is not possible to know which of the two read
operations caused the error.
After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outputs
the content of the EDC Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
The operation is the same as the Read Status Register command. Refer to Table 3.2 for specific EDC
Register definitions:
Table 3.2 EDC Register Coding
ID
Copy Back Program
Coding
0
Pass / Fail
Pass: 0; Fail: 1
1
EDC status
No error: 0; Error: 1
2
EDC validity
Invalid: 0; Valid: 1
3
NA
—
4
NA
—
5
Ready / Busy
Busy: 0; Ready: 1
6
Ready / Busy
Busy: 0; Ready: 1
7
Write Protect
Protected: 0; Not Protected: 1
Table 3.3 Page Organization in EDC Units
Main Field (2048 Byte)
Spare Field (64 Byte)
“A” area
“B” area
“C” area
“D” area
“E” area
“F” area
“G” area
“H” area
(1st sector)
(2nd sector)
(3rd sector)
(4th sector)
(1st sector)
(2nd sector)
(3rd sector)
(4th sector)
512 byte
512 byte
512 byte
512 byte
16 byte
16 byte
16 byte
16 byte
8 words
8 words
8 words
8 words
x8
x16
256 words
26
256 words
256 words
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Table 3.4 Page Organization in EDC Units by Address
Main Field (Column 0-2047)
Spare Field (Column 2048-2111)
Sector
Area Name
Column Address
Area Name
Column Address
x8
1st 528-byte Sector
A
0-511
E
2048-2063
2nd 528-byte Sector
B
512-1023
F
2064-2079
3rd 528-byte Sector
C
1024-1535
G
2080-2095
4th 528-byte Sector
D
1536-2047
H
2096-2111
1st 256-word Sector
A
0-255
E
1024-1031
2nd 256-word Sector
B
256-511
F
1032-1039
3rd 256-word Sector
C
512-767
G
1040-1047
4th 256-word Sector
D
768-1023
H
1048-1055
x16
3.9
Read Status Register
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on
the falling edge of CE# or RE#, whichever occurs last. This two-line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to
Section 3.5 on page 28 for specific Status Register definition, and to Figure 6.22 on page 54 for timings.
If the Read Status Register command is issued during multiplane operations then Status Register polling will
return the combined status value related to the outcome of the operation in the two planes according to the
following table:
Status Register Bit
Composite Status Value
Bit 0, Pass/Fail
OR
Bit 1, Cache Pass/Fail
OR
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the
Status Register is read during a random read cycle, the read command (00h) must be issued before starting
read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack
configurations (single CE#). “Read Status Enhanced” shall be used instead.
3.10
Read Status Enhanced — S34MS02G1 and S34MS04G1
Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane.
Figure 6.23 on page 55 defines the Read Status Enhanced behavior and timings. The plane and die address
must be specified in the command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 3.5 for specific Status Register definitions. The command register remains in Status Read
mode until further commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
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Read Status Register Field Definition
Table 3.5 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced
(S34MS02G1 and S34MS04G1).
Table 3.5 Status Register Coding
3.12
ID
Page
Program /
Page
Reprogram
Block Erase
Read
Read Cache
Cache
Program /
Cache
Reprogram
Coding
0
Pass / Fail
Pass / Fail
NA
NA
Pass / Fail
N Page
Pass: 0
Fail: 1
1
NA
NA
NA
NA
Pass / Fail
N - 1 Page
Pass: 0
Fail: 1
2
NA
NA
NA
NA
NA
—
3
NA
NA
NA
NA
NA
—
4
NA
NA
NA
NA
NA
—
5
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Internal Data Operation
Active: 0
Idle: 1
6
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Busy: 0
Ready: 1
7
Write Protect
Write Protect
NA
NA
Write Protect
Protected: 0
Not Protected: 1
Reset
The Reset feature is executed by writing FFh to the command register. If the device is in the Busy state
during random read, program, or erase mode, the Reset operation will abort these operations. The contents
of memory cells being altered are no longer valid, as the data may be partially programmed or erased. The
command register is cleared to wait for the next command, and the Status Register is cleared to value E0h
when WP# is high or value 60h when WP# is low. If the device is already in reset state a new Reset
command will not be accepted by the command register. The R/B# pin transitions to low for tRST after the
Reset command is written. Refer to Figure 6.24 on page 55 for further details. The Status Register can also
be read to determine the status of a Reset operation.
3.13
Read Cache
Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 21, and it
cannot cross a block boundary. As soon as the user starts to read one page, the device automatically loads
the next page into the cache register. Serial data output may be executed while data in the memory is read
into the cache register. Read Cache is initiated by the Page Read sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6
switches to high), two command sequences can be used to continue read cache:
 Read Cache (command ‘31h’ only): once the command is latched into the command register (see
Figure 6.26 on page 56), device goes busy for a short time (tCBSYR), during which data of the first page is
transferred from the data register to the cache register. At the end of this phase, the cache register data
can be output by toggling RE# while the next page (page address M+1) is read from the memory array into
the data register.
 Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the
command register (see Figure 6.27 on page 57), device goes busy for a short time (tCBSYR), during which
data of the first page is transferred from the data register to the cache register. At the end of this phase,
cache register data can be output by toggling RE# while page N is read from the memory array into the
data register.
Note: The S34MS01G1 device does not support Read Cache Enhanced.
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Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command
sequences. If serial data output time of one page exceeds random access time (tR), the random access time
of the next page is hidden by data downloading of the previous page.
On the other hand, if 31h is issued prior to completing the random access to the next page, the device will
stay busy as long as needed to complete random access to this page, transfer its contents into the cache
register, and trigger the random access to the following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 6.28 on page 57). This
command transfers data from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh,
Read SR, or Reset (FFh). To carry out other operations, Read Cache must be terminated by the Read Cache
End command (3Fh) or the device must be reset by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready
status of the cached read operations.
 The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
 The status bit I/O5 can be used to determine when the cell reading of the current data register contents is
complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is
toggled to output the data of a given page, the first output data is related to the first byte of the page (column
address 00h). Random Data Output command can be used to switch column address.
3.14
Cache Program
Cache Program can improve the program throughput by using the cache register. The Cache Program
operation cannot cross a block boundary. The cache register allows new data to be input while the previous
data that was transferred to the data register is programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of
address, a full or partial page of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is
transferred into the data register for cell programming. At this time the device remains in the Busy state for a
short time (tCBSYW). After all data of the cache register is transferred into the data register, the device returns
to the Ready state and allows loading the next data into the cache register through another Cache Program
command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the
cache register to the data register. Cell programming the data of the data register and loading of the next data
into the cache register is consequently processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off
until cell programming of current data register contents is complete; till this moment the device will stay in a
busy state (tCBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the
pass/fail status of the cached program operations.
 The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
 The status bit I/O5 can be used to determine when the cell programming of the current data register
contents is complete.
 The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been
successfully programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit
changing to 1.
 The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while
programming page N. The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
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If the system monitors the progress of the operation only with R/B#, the last page of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. See Table 3.5 on page 28 and Figure 6.29 on page 58 for more
details.
If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted pages are not used for further reading or programming operations until the next
uninterrupted block erases are complete for the applicable blocks.
3.15
Multiplane Cache Program — S34MS02G1 and S34MS04G1
The Multiplane Cache Program enables high program throughput by programming two pages in parallel,
while exploiting the data and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
 Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st
page. Address for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to
be programmed do not need to be loaded. The device supports Random Data Input exactly like Page
Program operation.
 The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes
busy for a short time (tDBSY).
 Once device returns to ready again, 81h command must be issued, followed by 2nd page address
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of
2nd page other than those to be programmed do not need to be loaded.
 Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command
register, the data in the cache registers is transferred into the data registers for cell programming. At this
time the device remains in the Busy state for a short time (tCBSYW). After all data from the cache registers
are transferred into the data registers, the device returns to the Ready state, and allows loading the next
data into the cache register through another Cache Program command sequence.
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the
tCBSYW time needed to complete programming the current data register contents, and transferring the new
data from the cache registers. The sequence to end Multiplane Cache Program is 80h-...- 11h...-...81h......10h.
The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 6.30
on page 59 shows the legacy protocol for the Multiplane Cache Program operation. In this case, the block
address bits for the first plane are all zero and the second address issued selects the block for both planes.
Figure 6.31 on page 60 shows the ONFI protocol for the Multiplane Cache Program operation. For both
addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the
plane.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user
opts for 70h, Read Status Register will provide “global” information about the operation in the two planes.
 I/O6 indicates when both cache registers are ready to accept new data.
 I/O5 indicates when the cell programming of the current data registers is complete.
 I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not.
This status bit is valid upon I/O6 status bit changing to 1.
 I/O0 identifies if any error has been detected by the program/erase controller while programming the two
pages N. This status bit is valid upon I/O5 status bit changing to 1.
See Table 3.5 on page 28 for more details.
If the system monitors the progress of the operation only with R/B#, the last pages of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. Refer to Section 3.9 on page 27 for further information.
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Data
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If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the
host must ensure that the interrupted pages are not used for further reading or programming operations until
the next uninterrupted block erases are complete for the applicable blocks.
3.16
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed
by an address input of 00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy
command (0x00) before Read Status command (0x70).
For the S34MS02G1 and S34MS04G1 devices, five read cycles sequentially output the manufacturer code
(01h), and the device code and 3rd, 4th, and 5th cycle ID, respectively. For the S34MS01G1 device, four read
cycles sequentially output the manufacturer code (01h), and the device code and 80h, 4th cycle ID,
respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 6.32 on page 61 shows the operation sequence, while Table 3.6 to Table 3.11 explain the byte
meaning.
Table 3.6 Read ID for Supported Configurations
Density
Org
VCC
1 Gb
2 Gb
x8
4 Gb
1st
2nd
3rd
4th
01h
A1h
00h
15h
5th
—
01h
AAh
90h
15h
44h
01h
ACh
90h
15h
54h
01h
B1h
00h
55h
—
01h
BAh
90h
55h
44h
01h
BCh
90h
55h
54h
1.8V
1 Gb
2 Gb
x16
4 Gb
Table 3.7 Read ID Bytes
Device Identifier Byte
1st
Description
Manufacturer Code
2nd
Device Identifier
3rd
Internal chip number, cell type, etc.
4th
Page Size, Block Size, Spare Size, Serial Access Time, Organization
5th (S34MS02G1, S34MS04G1)
ECC, Multiplane information
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3rd ID Data
Table 3.8 Read ID Byte 3 Description
Description
Internal Chip Number
Cell type
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
1
00
2
01
4
10
8
11
2-level cell
00
4-level cell
01
8-level cell
10
16-level cell
Number of simultaneously
programmed pages
11
1
00
2
01
4
10
8
Interleave program
Between multiple chips
Cache Program
I/O1 I/O0
11
Not supported
0
Supported
1
Not supported
0
Supported
1
4th ID Data
Table 3.9 Read ID Byte 4 Description — S34MS01G1
Description
Page Size
(without spare area)
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
00
2 kB
01
4 kB
10
8 kB
Block Size
(without spare area)
Spare Area Size
(byte / 512 byte)
Serial Access Time
I/O1 I/O0
1 kB
11
64 kB
00
128 kB
01
256 kB
10
512 kB
11
0
8
16
1
45 ns
0
0
25 ns
0
1
Reserved
1
0
Reserved
1
1
x8
0
x16
1
Organization
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
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Table 3.10 Read ID Byte 4 Description — S34MS02G1 and S34MS04G1
Description
Page Size
(without spare area)
Block Size
(without spare area)
Spare Area Size
(byte / 512 byte)
Serial Access Time
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
1 kB
00
2 kB
01
4 kB
10
8 kB
11
64 kB
00
128 kB
01
256 kB
10
512 kB
11
8
0
16
1
50 ns / 30 ns
0
0
25 ns
1
0
Reserved
0
1
Reserved
1
1
x8
0
x16
1
Organization
5th ID Data
Table 3.11 Read ID Byte 5 Description — S34MS02G1 and S34MS04G1
Description
Plane Number
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
1
00
2
01
4
10
8
Plane Size
(without spare area)
3.17
I/O0
0
0
11
64 Mb
000
128 Mb
001
256 Mb
010
512 Mb
011
1 Gb
100
2 Gb
101
4 Gb
Reserved
I/O1
110
0
Read ID2
The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command
register, followed by address inputs, followed by command 30h. The address for S34MS01G1 will be
00h-02h-02h-00h. The address for S34MS02G1 and S34MS04G1 will be 00h-02h-02h-00h-00h. The ID2
data can then be read from the device by pulsing RE#. The command register remains in Read ID2 mode
until further commands are issued to it. Figure 6.33 on page 61 shows the Read ID2 command sequence.
Read ID2 values are all 0xFs, unless specific values are requested when ordering from Spansion.
3.18
Read ONFI Signature
To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is
not valid to enter an address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the
ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields
indeterminate values. Figure 6.34 on page 62 shows the operation sequence.
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3.19
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Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command
register, followed by an address input of 00h. The host may monitor the R/B# pin or wait for the maximum
data transfer time (tR) before reading the Parameter Page data. The command register remains in Parameter
Page mode until further commands are issued to it. If the Status Register is read to determine when the data
is ready, the Read Command (00h) must be issued before starting read cycles. Figure 6.35 on page 62
shows the operation sequence, while Table 3.12 explains the parameter fields.
For x16 devices, the upper eight I/Os are not used and are 0xFF.
Table 3.12 Parameter Page Description (Sheet 1 of 3)
Byte
O/M
Description
Values
Revision Information and Features Block
0-3
4-5
6-7
8-9
M
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M
Revision number
2-15
Reserved (0)
1
1 = supports ONFI version 1.0
0
Reserved (0)
02h, 00h
M
Features supported
5-15
Reserved (0)
4
1 = supports odd to even page Copyback
3
1 = supports interleaved operations
2
1 = supports non-sequential page programming
1
1 = supports multiple LUN operations
0
1 = supports 16-bit data bus width
S34MS01G100 (x8): 14h, 00h
S34MS02G100 (x8): 1Ch, 00h
S34MS04G100 (x8): 1Ch, 00h
S34MS01G104 (x16): 15h, 00h
S34MS02G104 (x16): 1Dh, 00h
S34MS04G104 (x16): 1Dh, 00h
M
Optional commands supported
6-15
Reserved (0)
5
1 = supports Read Unique ID
4
1 = supports Copyback
3
1 = supports Read Status Enhanced
2
1 = supports Get Features and Set Features
1
1 = supports Read Cache commands
0
1 = supports Page Cache Program command
S34MS01G1: 13h, 00h
S34MS02G1: 1Bh, 00h
S34MS04G1: 1Bh, 00h
Reserved (0)
00h
10-31
Manufacturer Information Block
32-43
M
Device manufacturer (12 ASCII characters)
53h, 50h, 41h, 4Eh, 53h, 49h,
4Fh, 4Eh, 20h, 20h, 20h, 20h
S34MS01G1: 53h, 33h, 34h,
4Dh, 53h, 30h, 31h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
S34MS02G1: 53h, 33h, 34h,
4Dh, 53h, 30h, 32h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
S34MS04G1: 53h, 33h, 34h,
4Dh, 53h, 30h, 34h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
64
M
JEDEC manufacturer ID
01h
65-66
O
Date code
00h
67-79
Reserved (0)
00h
Memory Organization Block
34
80-83
M
Number of data bytes per page
84-85
M
Number of spare bytes per page
40h, 00h
86-89
M
Number of data bytes per partial page
00h, 02h, 00h, 00h
90-91
M
Number of spare bytes per partial page
10h, 00h
Spansion® SLC NAND Flash Memory for Embedded
00h, 08h, 00h, 00h
S34MS01G1_04G1_08 October 28, 2014
Data
She et
Table 3.12 Parameter Page Description (Sheet 2 of 3)
Byte
O/M
92-95
M
Description
Values
Number of pages per block
40h, 00h, 00h, 00h
S34MS01G1: 00h, 04h, 00h, 00h
S34MS02G1: 00h, 08h, 00h, 00h
S34MS04G1: 00h, 10h, 00h, 00h
96-99
M
Number of blocks per logical unit (LUN)
100
M
Number of logical units (LUNs)
01h
101
M
Number of address cycles
4-7
Column address cycles
0-3
Row address cycles
S34MS01G1: 22h
S34MS02G1: 23h
S34MS04G1: 23h
102
M
Number of bits per cell
01h
103-104
M
Bad blocks maximum per LUN
S34MS01G1: 14h, 00h
S34MS02G1: 28h, 00h
S34MS04G1: 50h, 00h
105-106
M
Block endurance
01h, 05h
107
M
Guaranteed valid blocks at beginning of target
01h
108-109
M
Block endurance for guaranteed valid blocks
01h, 03h
110
M
Number of programs per page
04h
111
M
Partial programming attributes
5-7
Reserved
4
1 = partial page layout is partial page data followed by
partial page spare
1-3
Reserved
0
1 = partial page programming has constraints
00h
112
M
Number of bits ECC correctability
01h
M
Number of interleaved address bits
4-7
Reserved (0)
0-3
Number of interleaved address bits
S34MS01G1: 00h
S34MS02G1: 01h
S34MS04G1: 01h
O
Interleaved operation attributes
4-7
Reserved (0)
3
Address restrictions for program cache
2
1 = program cache supported
1
1 = no block address restrictions
0
Overlapped / concurrent interleaving support
S34MS01G1: 00h
S34MS02G1: 04h
S34MS04G1: 04h
Reserved (0)
00h
113
114
115-127
Electrical Parameters Block
128
M
I/O pin capacitance
0Ah
M
Timing mode support
6-15
Reserved (0)
5
1 = supports timing mode 5
4
1 = supports timing mode 4
3
1 = supports timing mode 3
2
1 = supports timing mode 2
1
1 = supports timing mode 1
0
1 = supports timing mode 0, shall be 1
03h, 00h
131-132
O
Program cache timing mode support
6-15
Reserved (0)
5
1 = supports timing mode 5
4
1 = supports timing mode 4
3
1 = supports timing mode 3
2
1 = supports timing mode 2
1
1 = supports timing mode 1
0
1 = supports timing mode 0
03h, 00h
133-134
M
tPROG Maximum page program time (µs)
BCh, 02h
135-136
M
tBERS Maximum block erase time (µs)
S34MS01G1: B8h, 0Bh
S34MS02G1: 10h, 27h
S34MS04G1: 10h, 27h
137-138
M
tR Maximum page read time (µs)
19h, 00h
139-140
M
tCCS Minimum Change Column setup time (ns)
64h, 00h
Reserved (0)
00h
129-130
141-163
Vendor Block
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Table 3.12 Parameter Page Description (Sheet 3 of 3)
Byte
O/M
164-165
M
166-253
254-255
M
Description
Values
Vendor specific Revision number
00h
Vendor specific
00h
Integrity CRC
S34MS01G100 (x8): 81h, 4Fh
S34MS02G100 (x8): 45h, E9h
S34MS04G100 (x8): 3Bh, A2h
S34MS01G104 (x16): F3h, 39h
S34MS02G104 (x16): 37h, 9Fh
S34MS04G104 (x16): 49h, D4h
Redundant Parameter Pages
256-511
M
Value of bytes 0-255
512-767
M
Value of bytes 0-255
Repeat Value of bytes 0-255
Repeat Value of bytes 0-255
768+
O
Additional redundant parameter pages
FFh
Note:
1. O” Stands for Optional, “M” for Mandatory.
3.20
One-Time Programmable (OTP) Entry
The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to
the command register. The device is then ready to accept Page Read and Page Program commands (refer to
Page Read and Page Program on page 21). The OTP area is of a single erase block size (64 pages), and
hence only row addresses between 00h and 3Fh are allowed. The host must issue the Reset command (refer
to Reset on page 28) to exit the OTP area and access the normal flash array. The Block Erase command is
not allowed in the OTP area. Refer to Figure 6.36 on page 63 for more detail on the OTP Entry command
sequence.
Note: The OTP feature in the S34MS01G1 does not have non-volatile protection.
4. Signal Descriptions
4.1
Data Protection and Power On / Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An
internal voltage detector disables all functions whenever VCC is below about 1.1V.
The power-up and power-down sequence is shown in Figure 6.37 on page 63, in this case VCC and VCCQ on
the one hand (and VSS and VSSQ on the other hand) are shorted together at all times.
The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum
values (as specified on), and shall return to one within 5 ms (max).
During this busy time, the device executes the initialization process (cam reading), and dissipates a current
ICC0 (30 mA max), in addition, it disregards all commands excluding Read Status Register (70h).
At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page
read command, the 00h command may be skipped.
The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and
power-down. A recovery time of minimum 100 µs is required before the internal circuit gets ready for any
command sequences as shown in Figure 6.37 on page 63. The two-step command sequence for
program/erase provides additional software protection.
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Ready/Busy
The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback,
or read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset,
read, program, or erase operation). It returns to high when the internal controller has finished the operation.
The pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because the pull-up
resistor value is related to tr (R/B#) and the current drain during busy (ibusy) and output load capacitance is
related to tf, an appropriate value can be obtained with the reference chart shown in Figure 4.1.
Figure 4.1 Ready/Busy Pin Electrical Application
Rp
Vcc
ibusy
Ready
VCC
R/B#
open drain output
VOH
VOL : 0.1V, VOH : VCC - 0.1V
CL
VOL
Busy
tf
tr
GND
Device
Rp vs. tr, tf and Rp vs. ibusy
200n
@ Vcc = 1.8V, Ta = 25°C, CL=30 pF
2m
1.7
Legend
ibusy [A]
120
100n
0.9
= tr (ns)
= ibusy (mA)
= tf (ns)
1m
90
0.6
0.4
60
30
15
15
15
15
tr,tf [s]
1k
2k
3k
4k
Rp (ohm)
Rp value guidence
Rp (min.) =
Vcc (Max.) - VOL (Max.)
I OL + ∑I
L
=
1.85V
3mA + ∑I L
where I L is the sum of the input currents of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr.
October 28, 2014 S34MS01G1_04G1_08
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Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about
100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of
memory cells being altered are no longer valid, as the data will be partially programmed or erased. The
R/B# pin will stay low for tRST (similarly to Figure 6.24 on page 55). At the end of this time, the command
register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7
value will be related to the WP# value. Refer to Table 3.5 on page 28 for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to
issuing the setup commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin
for the set up command, as explained in Figure 6.38 and Figure 6.39 on page 64.
Figure 4.2 WP# Low Timing Requirements during Program/Erase Command Sequence
WE#
I/O[7:0]
Valid
WP#
> 100 ns
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Sequence
Aborted
S34MS01G1_04G1_08 October 28, 2014
Data
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5. Electrical Characteristics
5.1
Valid Blocks
Table 5.1 Valid Blocks
Device
5.2
Symbol
Min
Typ
Max
Unit
S34MS01G1
NVB
1004
—
1024
Blocks
S34MS02G1
NVB
2008
—
2048
Blocks
S34MS04G1
NVB
4016
—
4096
Blocks
Absolute Maximum Ratings
Table 5.2 Absolute Maximum Ratings
Parameter
Symbol
Ambient Operating Temperature (Industrial Temperature Range)
Temperature under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Value
Unit
TA
-40 to +85
°C
TBIAS
-50 to +125
°C
TSTG
-65 to +150
°C
VIO (2)
-0.6 to +2.7
V
VCC
-0.6 to +2.7
V
Notes:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any
other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
3. Maximum Voltage may overshoot to VCC +2.0V during transition and for less than 20 ns during transitions.
5.3
AC Test Conditions
Table 5.3 AC Test Conditions
Parameter
Input Pulse Levels
Input Rise And Fall Times
Input And Output Timing Levels
Output Load (1.7V - 1.95V)
October 28, 2014 S34MS01G1_04G1_08
Value
0.0V to VCC
5 ns
VCC / 2
1 TTL Gate and CL = 30 pF
Spansion® SLC NAND Flash Memory for Embedded
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5.4
S hee t
AC Characteristics
Table 5.4 AC Characteristics
Symbol
Min
Max
Unit
ALE to RE# delay
Parameter
tAR
10
—
ns
ALE hold time
tALH
10
—
ns
ALE setup time
tALS
25
—
ns
tADL
100
—
ns
tCEA (4)
—
45
ns
CE# low to RE# low
tCR
10
—
ns
CE# hold time
tCH
10
—
ns
CE# high to output High-Z
tCHZ
—
30
ns
CLE hold time
tCLH
10
—
ns
CLE to RE# delay
tCLR
10
—
ns
CLE setup time
tCLS
25
—
ns
Address to data loading time
CE# Access Time
tCOH (3)
15
—
ns
tCSD
10
—
ns
CE# setup time
tCS
35
—
ns
Data hold time
tDH
10
—
ns
Data setup time
tDS
20
—
ns
Data transfer from cell to register
tR
—
25
µs
CE# high to output hold
CE# high to ALE or CLE don't care
Output High-Z to RE# low
tIR
0
—
ns
Read cycle time
tRC
45
—
ns
RE# access time
tREA
—
30
ns
RE# high hold time
tREH
15
—
ns
tRHOH (3)
15
—
ns
tRHW
100
—
ns
RE# high to output hold
RE# high to WE# low
tRHZ
—
100
ns
tRLOH (5)
—
—
ns
RE# pulse width
tRP
25
—
ns
Ready to RE# low
tRR
20
—
ns
RE# high to output High-Z
RE# low to output hold
Device resetting time (Read/Program/Erase)
tRST
—
5/10/500 (2)
µs
WE# high to busy
tWB
—
100
ns
Write cycle time
tWC
45
—
ns
WE# high hold time
tWH
15
—
ns
WE# high to RE# low
ns
tWHR
60
—
WE# pulse width
tWP
25
—
ns
Write protect time
tWW
100
—
ns
Notes:
1. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.
2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.
3. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either
tCOH or tRHOH will be met.
4. During data output, tCEA depends partly on tCR (CE# low to RE# low). If tCR exceeds the minimum value specified, then the maximum
time for tCEA may also be exceeded (tCEA = tCR + tREA).
5. tRLOH is only relevant for EDO timing (tRC < 30 ns), which does not apply for this device.
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Data
5.5
She et
DC Characteristics
Table 5.5 DC Characteristics and Operating Conditions
Parameter
Symbol
Power-On Current
(S34MS02G1, S34MS04G1)
ICC0
Sequential
Read
Program
ICC1
ICC2
Operating Current
Erase
ICC3
Standby Current, (TTL)
ICC4
Standby Current, (CMOS)
ICC5
Test Conditions
Min
Typ
Max
Units
—
15
30
mA
—
10
20
mA
Normal (S34MS01G1)
—
10
20
mA
Normal (S34MS02G1)
—
10
20
mA
Normal (S34MS04G1)
—
—
20
mA
Cache (S34MS02G1)
—
15
30
mA
Cache (S34MS04G1)
—
—
30
mA
— (S34MS01G1)
—
10
20
mA
— (S34MS02G1)
—
—
20
mA
— (S34MS04G1)
—
10
20
mA
—
—
1
mA
—
10
50
µA
Power-Up Current
(Refer to Section 4.1)
tRC = see Table 5.4
CE#=VIL, IOUT = 0 mA
CE# = VIH,
WP# = 0V/Vcc
CE# = VCC –0.2,
WP# = 0/VCC
Input Leakage Current
ILI
VIN = 0 to 3.6V
—
—
±10
µA
Output Leakage Current
ILO
VOUT = 0 to 3.6V
—
—
±10
µA
Input High Voltage
VIH
—
VCC x 0.8
—
VCC + 0.3
V
Input Low Voltage
VIL
—
-0.3
—
VCC x 0.2
V
Output High Voltage
VOH
IOH = -100 µA
VCC –0.1
—
—
V
Output Low Voltage
VOL
IOL = 100 µA
0.1
V
IOL(R/B#)
VOL = 0.1V
3
4
—
mA
VLKO
—
—
1.1
—
V
Output Low Current (R/B#)
VCC Supply Voltage
(erase and program lockout)
Notes:
1. All VCCQ and VCC pins, and VSS and VSSQ pins respectively are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and VCCQ and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to
Section 4.1 for more details.
5.6
Pin Capacitance
Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz)
Symbol
Test Condition
Min
Max
Unit
Input
Parameter
CIN
VIN = 0V
—
10
pF
Input / Output
CIO
VIL = 0V
—
10
pF
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
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5.7
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Program / Erase Characteristics
Table 5.7 Program / Erase Characteristics
Description
Min
Typ
Max
Unit
Program Time / Multiplane Program Time (2)
Parameter
tPROG
—
250
700
µs
Dummy Busy Time for Multiplane Program (S34MS02G1, S34MS04G1)
tDBSY
—
0.5
1
µs
tCBSYW
—
5
tPROG
µs
Cache Program short busy time (S34MS02G1, S34MS04G1)
Number of partial Program Cycles in the same page
NOP
—
—
4
Cycle
Block Erase Time / Multiplane Erase Time (S34MS02G1, S34MS04G1)
Main + Spare
tBERS
—
3.5
10
ms
Block Erase Time (S34MS01G1)
tBERS
—
2
3
ms
Read Cache busy time
tCBSYR
—
3
tR
µs
Notes:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (VCC = 1.8V, 25°C).
2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the
device to meet the program time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd
address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page
(target page).
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Data
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6. Timing Diagrams
6.1
Command Latch Cycle
Command Input bus operation is used to give a command to the memory device. Commands are accepted
with Chip Enable low, Command Latch Enable High, Address Latch Enable low, and Read Enable High and
latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/
erase) the Write Protect pin must be high.
Figure 6.1 Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE#
tWP
WE#
tALS
tALH
ALE
tDS
I/Ox
tDH
Command
= Don’t Care
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6.2
S hee t
Address Latch Cycle
Address Input bus operation allows the insertion of the memory address. To insert the 27 (x8 Device)
addresses needed to access the 1 Gb, four write cycles are needed. Addresses are accepted with Chip
Enable low, Address Latch Enable High, Command Latch Enable low, and Read Enable High and latched on
the rising edge of Write Enable. Moreover, for commands that start a modify operation (write/ erase) the Write
Protect pin must be high.
Figure 6.2 Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE#
tWP
tWP
tWP
tWP
WE#
tWH
tALH
tALS
tALS
tWH
tALH
tALS
tWH
tALS tALH
tWH
tALH
tALS
tALH
ALE
tDH
tDH
tDH
tDS
Col.
Add2
Col.
Add1
I/Ox
tDH
tDS
tDS
tDS
Row.
Add2
Row.
Add1
tDH
tDS
Row.
Add3
= Don’t Care
6.3
Data Input Cycle Timing
Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serially, and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising
edge of Write Enable.
Figure 6.3 Input Data Latch Cycle
tCLH
CLE
tCH
CE#
tWC
tALS
ALE
tWP
tWP
WE#
tWH
tWH
tDS
I/Ox
tDH
Din 0
tWP
tDS
tDH
Din
tDS
tDH
Din final
= Don’t Care
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Data
6.4
She et
Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H)
Figure 6.4 Data Output Cycle Timing
tRC
tCHZ
CE#
tREH
tREA
RE#
tREA
tREA
tCOH
tRHZ
tRHZ
tRHOH
I/Ox
Dout
Dout
Dout
tRR
R/B#
Notes:
1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRHOH starts to be valid when frequency is lower than 33 MHz.
6.5
Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L)
Figure 6.5 Data Output Cycle Timing (EDO)
CE#
tCR
tRC
RE#
tRP
tCHZ
tCOH
tREH
tREA
tRLOH
tREA
I/Ox
Dout
tRHZ
tRHOH
Dout
tRR
R/B#
= Don’t Care
Notes:
1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRLOH is valid when frequency is higher than 33 MHz.
4. tRHOH starts to be valid when frequency is lower than 33 MHz.
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Page Read Operation
Figure 6.6 Page Read Operation (Read One Page)
CLE
tCLR
CE#
tWC
WE#
tCSD
tWB
tAR
ALE
tR
RE#
I/Ox
tRC
tRHZ
tRR
00h
Col.
Add. 1
Col.
Add. 2
Column Address
Row
Add. 2
Row
Add. 1
Row
Add. 3
30h
Dout
N +1
Dout N
Dout
M
Row Address
R/B#
Busy
= Don’t Care
Note:
1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data
can be read from the page buffer.
6.7
Page Read Operation (Interrupted by CE#)
Figure 6.7 Page Read Operation Interrupted by CE#
CLE
tCLR
CE#
tCSD
tCHZ
WE#
tCOH
tWB
tAR
ALE
tRC
tR
RE#
tRR
I/Ox
00h
Col.
Col.
Add. 2
Add. 1
Column Address
Row
Add. 1
Row
Add. 2
Row
Add. 3
Dout N
30h
Dout
N +1
Dout
N +2
Row Address
R/B#
Busy
= Don’t Care
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Spansion® SLC NAND Flash Memory for Embedded
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Data
6.8
She et
Page Read Operation Timing with CE# Don’t Care
Figure 6.8 Page Read Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
tRC
RE#
tRR
00h
I/Ox
Col.
Add. 1
Col.
Add. 2
Row
Add. 1
Row
Add. 2
Row
Add. 3
Dout
N
30h
Dout
N+1
Dout
N+2
Dout
N+3
Dout
N+4
Dout
N+5
Dout
M
Dout
M+1
Dout
M+2
tR
R/B#
= Don’t Care (VIH or VIL)
tCR
CE#
tREA
RE#
I/Ox
6.9
Dout
Page Program Operation
Figure 6.9 Page Program Operation
CLE
CE#
tWC
tWC
tWC
WE#
tADL
tWB
tPROG
tWHR
ALE
RE#
I/Ox
Col.
Row.
Col.
Row.
Row.
80h
Add2
Add3
Add1
Add2
Add1
Serial Data
Column
Address
Row
Address
Input Command
Din
N
1 up to m byte
Serial Input
Din
M
10h
Program
Command
70h
I/O0
Read Status
Command
R/B#
I/O0=0 Successful Program
I/O0=1 Error in Program
= Don’t Care
Note:
1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
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S hee t
Page Program Operation Timing with CE# Don’t Care
Figure 6.10 Page Program Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
RE#
I/Ox
Col.
Add. 1
80h
Col.
Add. 2
Row
Add. 1
Row
Add. 2
Row
Add. 3
Din
N
Din
M
Din
N+1
Din
P
Din
R
Din
P+1
10h
= Don’t Care
tWP
WE#
6.11
tCH
tCS
CE#
Page Program Operation with Random Data Input
Figure 6.11 Random Data Input
CLE
CE#
tWC
tWC
tWC
WE#
tADL
tADL
tWB
tPROG
tWHR
ALE
RE#
I/Ox
Col.
Add1
80h
Serial Data
Input Command
Col.
Add2
Column Address
Row
Add1
Row
Add2
Row Address
Row
Add3
Din
N
Din
M
85h
Random Data
Input Command
Col.
Add1
Col.
Add2
Column Address
Din
J
Din
K
Serial Input
10h
Program
Command
70h
IO0
Read Status
Command
R/B#
= Don’t Care
Notes:
1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
2. For EDC operation only one Random Data Input is allowed at each EDC Unit.
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Spansion® SLC NAND Flash Memory for Embedded
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Data
6.12
She et
Random Data Output In a Page
Figure 6.12 Random Data Output
CLE
tCLR
CE#
WE#
tWB
tAR
tWHR
tRHW
ALE
tRC
tR
tREA
RE#
tRR
00h
I/Ox
Col.
Col.
Add. 2
Add. 1
Column Address
Row
Row
Row
Add. 2 Add. 3
Add. 1
Row Address
Dout N
30h
Dout
N +1
Col.
Col.
Add. 2
Add. 1
Column Address
05h
E0h
Dout M
Dout
M +1
R/B#
Busy
6.13
= Don’t Care
Multiplane Page Program Operation — S34MS02G1 and S34MS04G1
Figure 6.13 Multiplane Page Program
CLE
CE#
tWC
WE#
tDBSY
tWB
tWB
tPROG
tWHR
ALE
RE#
I/Ox
tADL
tADL
80h
Col.
Add1
Col.
Add2
Row
Add1
Row Row
Add2 Add3
Serial Data
Column Address Page Row Address
Input Command
Din
N
Din
M
1 up to 2112 byte
Data Serial Input
81h
11h
Program
Command
(Dummy)
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Din
M
Din
N
10h
Program Confirm
Command (True)
70h
IO
Read Staus
Command
R/B#
Ex.) Address Restriction for Multiplane Page Program
I/O0~7
tPROG
tDBSY
R/B#
80h
Address & Data Input
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19 ~ A28: Fixed ‘Low’
11h
81h
(Note 1)
Address & Data Input
10h
70h
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Valid
A18: Fixed ‘High’
A19 ~ A28: Valid
Notes:
1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.
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Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol)
Cycle Type
CMD ADDR ADDR ADDR ADDR ADDR
DIN
DIN
DIN
DIN
CMD
D0A
D1A
...
DnA
11h
tADL
DQx
80h
C1A
C2A
R2A
R1A
R3A
tADL
tIPBSY
SR[6]
A
Cycle Type
CMD ADDR ADDR ADDR ADDR ADDR
DIN
DIN
DIN
DIN
CMD
D0B
D1B
...
DnB
10h
tADL
80h
DQx
C1B
C2B
R1B
R2B
R3B
tADL
tPROG
SR[6]
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. D0A-DnA Data to program for page A.
4. C1B-C2B Column address for page B. C1B is the least significant byte.
5. R1B-R3B Row address for page B. R1B is the least significant byte.
6. D0B-DnB Data to program for page B.
7. The block address bits must be the same except for the bit(s) that select the plane.
6.14
Block Erase Operation
Figure 6.15 Block Erase Operation (Erase One Block)
CE#
tWC
WE#
tWB
tBERS
tWHR
ALE
RE#
I/Ox
60h
Row Add1 Row Add2 Row Add3
70h
D0h
I/O0
Row Address
BUSY
R/B#
Auto Block Erase
Setup Command
Erase Command
Read Status
Command
I/O0=0 Successful Erase
I/O0=1 Error in Erase
= Don’t Care
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
6.15
She et
Multiplane Block Erase — S34MS02G1 and S34MS04G1
Figure 6.16 Multiplane Block Erase
CLE
CE#
tWC
tWC
WE#
tWB
tWHR
tBERS
ALE
RE#
60h
I/Ox
60h
Row Add1 Row Add2 Row Add3
Row Add1 Row Add2 Row Add3
D0h
I/O0
70h
Row Address
Row Address
Busy
R/B#
Block Erase Setup Command1
Block Erase Setup Command2
Erase Confirm Command
Read Status Command
I/O 1 = 0 Successful Erase
I/O 1 = 1 Error in plane
Ex.) Address Restriction for Multiplane Block Erase Operation
R/B#
I/O0~7
tBERS
Address
60h
Address
60h
Row Add1,2,3
Row Add1,2,3
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Valid
D0h
70h
Note:
1. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.
Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
60h
R1 A
SR[6]
R2A
R3A D1h
60h
t
R1B
R2B
R3B
D0h
IEBSY
t
BERS
Notes:
1. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.
2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.
3. The block address bits must be the same except for the bit(s) that select the plane.
October 28, 2014 S34MS01G1_04G1_08
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6.16
S hee t
Copy Back Read with Optional Data Readout
Figure 6.18 Copy Back Read with Optional Data Readout
I/O
Source
Add Inputs
00h
35h
Data Outputs
Target
Add Inputs
85h
70h/
7Bh
10h
SR0/
EDC Reg
Read Status Register/
EDC Register
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
6.17
Busy
Copy Back Program Operation With Random Data Input
Figure 6.19 Copy Back Program with Random Data Input
I/O
00h
Source
Add Inputs
35h
85h
Target
Add Inputs
Data
85h
2 Cycle
Add Inputs
Data
70h
10h
SR0
Read Status Register
Unlimited number of repetitions
R/B#
tR
(Read Busy time)
tPROG
(Program Busy time)
Busy
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Spansion® SLC NAND Flash Memory for Embedded
Busy
S34MS01G1_04G1_08 October 28, 2014
Data
6.18
She et
Multiplane Copy Back Program — S34MS02G1 and S34MS04G1
Figure 6.20 Multiplane Copy Back Program
tR
tR
R/B#
I/Ox
00h
Add. (5 cycles)
35h
00h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 0
35h
Add. (5 cycles)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 1
1
tDBSY
tPROG
R/B#
I/Ox
85h
Add. (5 cycles)
81h
11h
Add. (5 cycles)
10h
70h
(Note 2)
1
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Valid
A18
: Fixed ‘High’
A19 ~ A28 : Valid
Plane 0
Plane 1
Source Page
Source Page
Target Page
(1)
Data Field
(1) : Copy Back Read on Plane 0
(2) : Copy Back Read on Plane 1
(3) : Multiplane Copy Back Program
Target Page
(2)
(3)
Spare Field
Data Field
(3)
Spare Field
Notes:
1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
3. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.
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Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
85h
C1 A
C2 A
R1A R2A R3A
85h
11h
C1B
C2B
R1B
R2B
R3B
10h
t IPBSY
SR[6]
t PROG
A
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. C1B-C2B Column address for page B. C1B is the least significant byte.
4. R1B-R3B Row address for page B. R1B is the least significant byte.
5. The block address bits must be the same except for the bit(s) that select the plane.
6.19
Read Status Register Timing
Figure 6.22 Status / EDC Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE#
tCH
tWP
WE#
tCEA
tWHR
tCHZ
tCOH
RE#
tRHZ
tDS
I/Ox
tDH
70h or 7Bh
tIR
tREA
tRHOH
Status Output
= Don’t Care
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
6.20
She et
Read Status Enhanced Timing
Figure 6.23 Read Status Enhanced Timing
CLE
tWHR
WE#
ALE
RE#
tAR
I/O0-7
6.21
78h
R1
R2
R3
SR
Reset Operation Timing
Figure 6.24 Reset Operation Timing
WE#
ALE
CLE
RE#
I/O7:0
FF
t RST
R/B#
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Spansion® SLC NAND Flash Memory for Embedded
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Read Cache
Figure 6.25 Read Cache Operation Timing
A
CE#
CLE
tWC
ALE
WE#
tWB
tWB
tWB
tRC
RE#
tRC
tRR
tRR
I/Ox
Col.
Add 1
00h
Col.
Add 2
Row
Add 1
Column Address 00h
Row
Add 2
Row
Add 3
30h
Dout
1
Dout
0
31h
Col. Add. 0
Page Address N
Dout
1
Page N + 1
Col. Add. 0
Page N
tCBSYR
tCBSYR
tR
R/B#
Dout
0
31h
Dout
5
1
2
3
A
4
CE#
CLE
ALE
WE#
tWB
tWB
tRC
tRC
RE#
tRR
I/Ox
Dout
tRR
Dout
0
31h
Dout
1
Dout
Col. Add. 0
tCBSYR
6
5
8
7
9
Page N
Data Cache
2
1
Page Buffer
Dout
Page N + 3
Col. Add. 0
tCBSYR
R/B#
Dout
1
Dout
0
3Fh
Page N + 2
Page N + 1
4
3
Page N + 2
6
5
3
5
Page N + 3
8
7
9
Page N + 3
Page N + 2
Page N + 1
Page N
1
= Don’t Care
7
Cell Array
Page N
Page N + 1
Page N + 2
Page N + 3
Figure 6.26 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined for
Read
Cycle Type
CMD
CMD
Dout
Dout
Dout
CMD
I/Ox
30h
31h
D0
...
Dn
31h
tWB
SR[6]
56
tWB
tR
tRR
tCBSYR
Spansion® SLC NAND Flash Memory for Embedded
Dout
D0
tWB
tRR
tCBSYR
S34MS01G1_04G1_08 October 28, 2014
Data
She et
Figure 6.27 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined
for Read
Cycle Type
A
CMD
CMD
ADDR
ADDR
C1
C2
ADDR
ADDR
ADDR
CMD
R3
31h
Dout
Dout
Dout
D0
...
Dn
Page N
I/Ox
30h
00h
R1
R2
tRR
tR
tWB
SR[6]
tRR
tWB
tCBSYR
A
Cycle Type
CMD
ADDR
ADDR
I/Ox
00h
C1
C2
ADDR
ADDR
ADDR
CMD
R3
31h
Dout
Page R
R1
R2
D0
tWB
SR[6]
tRR
tCBSYR
Figure 6.28 Read Cache Timing, End Of Cache Operation
As defined for
Read Cache
(Sequential or Random)
Cycle Type
CMD
I/Ox
31h
tWB
SR[6]
October 28, 2014 S34MS01G1_04G1_08
tRR
tCBSYR
Dout
Dout
Dout
CMD
D0
...
Dn
3Fh
tWB
Dout
Dout
Dout
D0
...
Dn
tRR
tCBSYR
Spansion® SLC NAND Flash Memory for Embedded
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Cache Program
Figure 6.29 Cache Program
CLE
CE#
tWC
tWC
WE#
tWB
ALE
RE#
80h
I/Ox
Col.
Add1
Col.
Add2
Row.
Add1
Column Address
Row.
Add2
Row.
Add3
Din
N
Din
M
15h
Col.
Add1
80h
Row Address
Col.
Add2
Row.
Add1
Column Address
Row.
Add2
Row.
Add3
Din
N
Din
M
15h
Row Address
R/B#
tCBSYW
tCBSYW
1
CLE
CE#
tWC
WE#
ALE
RE#
tADL
I/Ox
80h
Col.
Add1
Col.
Add2
Column Address
Row.
Add1
Row.
Add2
Row.
Add3
Din
N
Din
M
10h
70h Status
Row Address
R/B#
1
58
tPROG
Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
6.24
She et
Multiplane Cache Program — S34MS02G1 and S34MS04G1
Figure 6.30 Multiplane Cache Program
Command Input
Address Input
80h
11h
Data Input
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
RY/BY#
Data Input
Address Input
81h
15h
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
tDBSY
tCBSYW
1
Return to 1
Repeat a max of 63 times
Command Input
Address Input
80h
11h
Data Input
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
RY/BY#
Data Input
Address Input
81h
10h
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
tDBSY
tPROG
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
tADL
I/Ox
80h
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
tADL
Din
M
11h
81h
Row Address
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
15h
Row Address
R/B#
tDBSY
tCBSYW
1
CLE
CE#
tWC
tWB
WE#
ALE
RE#
I/Ox
80h
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
81h
11h
Row Address
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
10h
70h
Status
Row Address
R/B#
1
tDBSY
tPROG
Notes:
1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.
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Figure 6.31 Multiplane Cache Program (ONFI 1.0 Protocol)
Command Input
Address Input
80h
11h
Data Input
Data Input
Address Input
80h
15h
tDBSY
RY/BY#
tCBSYW
1
Return to 1
Repeat a max of 63 times
Command Input
Address Input
80h
11h
Data Input
Data Input
Address Input
80h
10h
tPROG
tDBSY
RY/BY#
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
tADL
IOx
80h
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
tADL
Din
N
Din
M
11h
80h
Row Address
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
15h
Row Address
R/B#
tDBSY
tCBSYW
1
CLE
CE#
tWC
tWB
WE#
ALE
RE#
80h
IOx
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
80h
11h
Row Address
Col.
Add1
Col.
Add2
Row
Add1
Column Address
Row
Add2
Row
Add3
Din
N
Din
M
10h
70h
Status
Row Address
R/B#
1
tPROG
tDBSY
Notes:
1. The block address bits must be the same except for the bit(s) that select the plane.
2. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
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Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
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She et
Read ID Operation Timing
Figure 6.32 Read ID Operation Timing
CLE
CE#
WE#
tWHR
tAR
ALE
tREA
RE#
1 Gb Device
I/Ox
2 Gb Device
I/Ox
I/Ox
4 Gb Device
90h
00h
01h
A1h
00h
1Dh
90h
00h
01h
AAh
90h
95h
44h
09h
00h
01h
ACh
90h
95h
54h
4th Cycle
5th Cycle
ID2 Data
ID2 Data
4th Cycle
5th Cycle
Read ID
Command
6.26
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle
Read ID2 Operation Timing
Figure 6.33 Read ID2 Operation Timing
CLE
CE#
WE#
tR
ALE
RE#
I/Ox
30h 65h 00h 00h 02h 02h 00h 30h
Read ID2
Commands
4 Cycle Address
Read ID2
Confirm
Command
ID2 Data
ID2 Data
ID2 Data
1st Cycle
2nd Cycle
3rd Cycle
R/B#
(Note 1)
Busy
Notes:
1. 4-cycle address is shown for the S34MS01G1. For S34MS02G1 and S34MS04G1, insert an additional address cycle of 00h.
2. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be issued before
ID2 data can be read from the flash.
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Read ONFI Signature Timing
Figure 6.34 ONFI Signature Timing
CLE
WE#
ALE
RE#
IO0~7
t WHR
90h
20h
4Fh
4Eh
46h
49h
tREA
6.28
Read Parameter Page Timing
Figure 6.35 Read Parameter Page Timing
CLE
WE#
ALE
RE#
IO0-7
R/B#
ECh
00h
P00
P10
...
P01
P11
...
tR
Note:
1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data
can be read from the page buffer.
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Data
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OTP Entry Timing
Figure 6.36 OTP Entry Timing
CLE
WE#
ALE
I/O0-7
6.30
29h 17h
04h
19h
Power On and Data Protection Timing
Figure 6.37 Power On and Data Protection Timing
Vcc(min)
Vcc(min)
VTH
VTH
VCC
0V
don’t
care
don’t
care
CE
WP
VIH
VIL
5 ms max
Operation
100 µs max
Invalid
VIL
don’t
care
Ready/Busy
Note:
1. VTH = 1.2 volts.
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WP# Handling
Figure 6.38 Program Enabling / Disabling Through WP# Handling
WE#
WE#
tWW
I/Ox
tWW
80h
10h
I/Ox
WP#
WP#
R/B#
R/B#
80h
10h
Figure 6.39 Erase Enabling / Disabling Through WP# Handling
WE#
WE#
tWW
I/Ox
64
tWW
60h
D0h
I/Ox
WP#
WP#
R/B#
R/B#
Spansion® SLC NAND Flash Memory for Embedded
60h
D0h
S34MS01G1_04G1_08 October 28, 2014
Data
She et
7. Physical Interface
7.1
7.1.1
Physical Diagram
48-Pin Thin Small Outline Package (TSOP1)
Figure 7.1 TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
PACKAGE
NOTES:
TS/TSR 48
JEDEC
MO-142 (D) DD
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.05
---
0.15
A2
0.95
1.00
1.05
b1
0.17
0.20
0.23
b
0.17
0.22
0.27
c1
0.10
---
0.16
c
0.10
---
0.21
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
E
11.90
12.00
12.10
e
L
0.50 BASIC
0.50
0.60
0˚
---
8
R
0.08
---
0.20
October 28, 2014 S34MS01G1_04G1_08
DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3.
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4.
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
THE SEATING PLANE.
9.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.70
O
N
1.
48
Spansion® SLC NAND Flash Memory for Embedded
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63-Pin Ball Grid Array (BGA)
Figure 7.2 VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
NOTES:
PACKAGE
VBM 063
JEDEC
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
M0-207(M)
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.00 mm x 9.00 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.25
---
---
NOTE
PROFILE
4.
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
D
11.00 BSC.
BODY SIZE
E
9.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
n
b
63
0.40
0.45
BALL COUNT
0.50
eE
0.80 BSC.
BALL PITCH
0.80 BSC.
BALL PITCH
SD
0.40 BSC.
SOLDER BALL PLACEMENT
SE
0.40 BSC.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL DIAMETER
eD
A3-A8,B2-B8,C1,C2,C9,C10
D1,D2,D9,D10,E1,E2,E9,E10
F1,F2,F9,F10,G1,G2,G9,G10
H1,H2,H9,H10,J1,J2,J9,J10
K1,K2,K9,K10
L3-L8,M3-M8
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g5011\ 16-038.25 \ 6.5.13
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8. System Interface
To simplify system interface, CE# may be unasserted during data loading or sequential data reading as
shown in Figure 8.1. By operating in this way, it is possible to connect NAND flash to a microprocessor.
Figure 8.1 Program Operation with CE# Don't Care
CLE
CE# don’t care
CE#
WE#
ALE
I/Ox
80h
St art Add. (5 Cycle)
Dat a I nput
Data Input
10h
Figure 8.2 Read Operation with CE# Don't Care
CLE
CE# don’t care
CE#
RE#
ALE
R/B#
tR
WE#
I/Ox
00h
October 28, 2014 S34MS01G1_04G1_08
St art Add. (5 Cycle)
30h
Dat a Out put ( sequent ial)
Spansion® SLC NAND Flash Memory for Embedded
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Figure 8.3 Page Programming Within a Block
Page 63
(64)
Page 63
(64)
Page 31
(32)
Page 31
(1)
Page 2
(3)
Page 2
(3)
Page 1
Page 0
(2)
(1)
Page 1
Page 0
(32)
(1)
Data Register
Data Register
From the LSB page to MSB page
DATA IN : Data (1)
68
Data (64)
Spansion® SLC NAND Flash Memory for Embedded
Ex.) Random page program (Optional)
DATA IN : Data (1)
Data (64)
S34MS01G1_04G1_08 October 28, 2014
Data
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9. Error Management
9.1
System Bad Block Replacement
Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be
replaced by copying any valid data to a new block. These additional Bad Blocks can be identified whenever a
program or erase operation reports “Fail” in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, thus the
block can be replaced by re-programming the current data and copying the rest of the replaced block to an
available valid block. Refer to Table 9.1 and Figure 9.1 for the recommended procedure to follow if an error
occurs during an operation.
Table 9.1 Block Failure
Operation
Recommended Procedure
Erase
Block Replacement
Program
Block Replacement
Read
ECC (1 bit / 512+16 byte)
Figure 9.1 Bad Block Replacement
Block A
Block B
(2)
Data
th
N page
Data
th
Failure (1)
N page
(3)
FFh
FFh
buffer memory of the controller
Notes:
1. An error occurs on the Nth page of Block A during a program operation.
2. Data in Block A is copied to the same location in Block B, which is a valid block.
3. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
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Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices
where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is
isolated from the bit line and common source line by a select transistor. The devices are supplied with all the
locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block
where the 1st byte in the spare area of the 1st or 2nd or last page does not contain FFh is a Bad Block. That
is, if the first page has an FF value and should have been a non-FF value, then the non-FF value in the
second page or the last page will indicate a bad block.The Bad Block Information must be read before any
erase is attempted, as the Bad Block Information may be erased. For the system to be able to recognize the
Bad Blocks based on the original information, it is recommended to create a Bad Block table following the
flowchart shown in Figure 9.2. The host is responsible to detect and track bad blocks, both factory bad blocks
and blocks that may go bad during operation. Once a block is found to be bad, data should not be written to
that block.The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 9.2 Bad Block Management Flowchart
Start
Block Address=
Block 0
Increment
Block Address
Data (1)
=FFh?
No
Update
Bad Block Table
Yes
Last
Block?
No
Yes
End
Note:
1. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages.
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10. Ordering Information
The ordering part number is formed by a valid combination of the following:
S34MS
04G
1
00
T
F
I
00
0
Packing Type
0
= Tray
3
= 13” Tape and Reel
Model Number
00 =
Standard Interface / ONFI (x8)
00 =
Standard Interface (x16)
01 = ONFI (x16)
Temperature Range
I
= Industrial (-40°C to +85°C)
A
= –40°C to + 85°C, GT-grade
V
= Automotive (–40°C to + 105°C)
B
= –40°C to + 105°C, GT-grade
Materials Set
F
= Lead (Pb)-free
H
= Lead (Pb)-free Low Halogen
Package
B
= BGA
T
= TSOP
Bus Width
00 =
x8 NAND, single die
04 =
x16 NAND, single die
Technology
1
=
Spansion NAND Revision 1 (4x nm)
Density
01G =
02G =
04G =
1 Gb
2 Gb
4 Gb
Device Family
S34MS - 1.8V
Spansion SLC NAND Flash Memory for Embedded
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Device
Family
Density
S34MS
02G
Technology
Bus
Width
Package
Type
Temperature
Range
1
00, 04
TF, BH
A (2)
01G
Additional
Ordering Options
Packing
Type
Package
Description
00, 01
0, 3
TSOP, BGA (1)
I
V, B (2)(3)
04G
Notes:
1. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number.
2. A, V, B: 4G x8 (00 in bus width) available.
3. S34MS01G1 @ 105°C (V) and 105°C GT-Grade (B) needs 2-bit ECC / 512+16 bytes.
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11. Revision History
Section
Description
Revision 01 (August 29, 2012)
Initial release
Revision 02 (September 6, 2012)
48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts
Connection Diagram
63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pinouts
Command Set
Reorganized section
AC Characteristics
Corrected TALS Min and TDS Min
Revision 03 (October 1, 2012)
Address Cycle Map — 1 Gb Device: corrected data
Addressing
Address Cycle Map — 2 Gb Device: corrected data
Address Cycle Map — 4 Gb Device: corrected data
Multiplane Program — S34MS02G1
and S34MS04G1
Added text
Block Erase
Added text
Multiplane Block Erase — S34MS02G1
and S34MS04G1
Added text
Copy Back Program
Added text
Multiplane Copy Back Program —
S34MS02G1 and S34MS04G1
Added text
Multiplane Cache Program —
S34MS02G1 and S34MS04G1
Added text
Multiplane Page Program Operation —
S34MS02G1 and S34MS04G1
Added note to Multiplane Page Program figure
Multiplane Block Erase — S34MS02G1
and S34MS04G1
Added note to Multiplane Block Erase figure
Added note to Multiplane Page Program (ONFI 1.0 Protocol) figure
Changed note to Multiplane Block Erase (ONFI 1.0 Protocol) figure
Added note to Multiplane Copy Back Program figure
Multiplane Copy Back Program (ONFI 1.0 Protocol) figure:
Multiplane Copy Back Program —
S34MS02G1 and S34MS04G1
corrected IOx values
updated note
Added note to Multiplane Cache Program figure
Multiplane Cache Program (ONFI 1.0 Protocol):
Multiplane Cache Program —
S34MS02G1 and S34MS04G1
removed address values from RY/BY#
changed IOx value from F1h to 70h
updated note
Revision 04 (November 30, 2012)
Absolute Maximum Ratings table:
Absolute Maximum Ratings
updated Input or Output Voltage, and Supply Voltage values
added note
AC Characteristics table:
AC Characteristics
updated values
added note for tCOH and tRHOH
DC Characteristics
DC Characteristics and Operating Conditions table: updated ICC0, ICC2, VOH, and VOH for
S34MS01G1
Ordering Information
Valid Combinations table: updated Additional Ordering Options
Revision 05 (December 19, 2012)
Command Set
72
Added Page Reprogram command
Reorganized Command Set table
Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
She et
Section
Page Reprogram
Description
Moved section
Added paragraph
Copy Back Program
Added paragraph
Reset
Updated paragraph
Read ID2
Added text
Parameter Page Description table:
Read Parameter Page
fixed Values of Bytes 6-7 and 254-255
fixed Description of Bytes 129-130 and 131-132
DC Characteristics and Operating Conditions table:
Power-On Reset Current (S34ML01G1): removed row
Operating Current: removed ICC1: tRC = tRC (min)
Input Leakage Current: removed VIN = 0 to VCC (max)
Output Leakage Current: removed VOUT = 0 to VCC (max)
Output High Voltage: removed IOH = 100 µA, IOH = -400 µA, and IOH = 400 µA rows
Output Low Voltage: removed IOL = 2.1 mA row
Output Low Current (R/B#): removed VOL = 0.4V row
DC Characteristics
AC Characteristics
AC Characteristics table: added note
Page Read Operation
Page Read Operation (Read One Page) figure: added note
Read ID2 Operation Timing figure:
Read ID2 Operation Timing
Bad Block Management
replaced tWHR with tR and added R/B# timing signal
added note
Added text
Bad Block Management Flowchart: updated note
Revision 06 (August 9, 2013)
Global
Distinctive Characteristics
Performance
General Description
Addressing
Data Sheet designation updated from Advance Information to Preliminary
Note that the S34MS04G1 is in the Advanced Information designation
Security: removed Serial number (unique ID)
Operating Temperature: removed Commercial and Extended temperatures
Updated Reliability
Updated text
Removed bullets: ReadID2 extension and Serial number (unique identifier)
Appended Note in all Address Cycle Map tables
Added text to Bus Cycle column in all Address Cycle Map tables
Command Set table:
added data to ‘Acceptable Command during Busy’ column
removed Nth Page entries
Command Set
Changed status of Cache Program (End) and Cache Program (Start) / (Continue) to ‘Supported
on S34ML01G1’
Page Read
Updated text
Page Program
Added paragraph
Multiplane Program — S34MS02G1
and S34MS04G1
Added paragraph
Added paragraph
Page Reprogram — S34MS02G1 and
S34MS04G1
Corrected Page Reprogram figure
Corrected Page Reprogram with Data Manipulation figure
Block Erase
Added paragraph
Multiplane Block Erase — S34MS02G1
and S34MS04G1
Added paragraph
Copy Back Program
Added paragraph
Multiplane Copy Back Program —
S34MS02G1 and S34MS04G1
Added paragraph
Read Status Register Field Definition
Updated Status Register Coding table
October 28, 2014 S34MS01G1_04G1_08
Spansion® SLC NAND Flash Memory for Embedded
73
D at a
S hee t
Section
Description
Cache Program
Added paragraph
Multiplane Cache Program —
S34MS02G1 and S34MS04G1
Added paragraph
Read ID
Read ID Bytes table: updated Description
Read Parameter Page
Parameter Page Description table: corrected values for bits 6-7, 8-9, 129-130; bits 131-132; and bits
254-255
Updated section
Ready/Busy
Updated Ready/Busy Pin Electrical Application figure
Modified Valid Blocks table
Updated Absolute Maximum Ratings table
Electrical Characteristics
AC Test Conditions table: corrected Output Load CL value
AC Characteristics
AC Characteristics table: added Note
Data Output Cycle Timing (CLE=L,
WE#=H, ALE=L, WP#=H)
Data Output Cycle Timing figure: removed Note
Multiplane Page Program Operation —
S34MS02G1 and S34MS04G1
Updated Multiplane Page Program figure
Corrected Multiplane Page Program (ONFI 1.0 Protocol) figure
Copy Back Read with Optional Data
Readout
Corrected Copy Back Read with Optional Data Readout figure
Copy Back Program Operation With
Random Data Input
Modified Copy Back Program Operation With Random Data Input figure
Status / EDC Read Cycle figure: removed Note
Read Status Register Timing
Removed Read Status Enhanced Cycle figure
Read Status Enhanced Timing
Removed Read Status Timing figure
Updated Read Cache Operation Timing figure
Read Cache
Removed Cache Timing heading
Cache Program
Cache Program figure: corrected I/Ox timing
Multiplane Cache Program —
S34MS02G1 and S34MS04G1
Multiplane Cache Program figure: corrected I/Ox timing
Read ID Operation Timing
Read ID Operation Timing figure: corrected Device Code data
Multiplane Cache Program (ONFI 1.0 Protocol) figure: corrected I/Ox timing
Read Parameter Page Timing
Added Note to Read Parameter Page Timing figure
One-Time Programmable (OTP) Entry
Added Note stating that the OTP feature in the S34MS01G1 does not have non-volatile protection
Updated figures:
Physical Interface
TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
System Interface
Updated Read Operation with CE# Don't Care figure
Ordering Information
Clarified Materials Set: H = Lead (Pb)-free and Low Halogen
Added Note to Valid Combinations table
Revision 07 (June 24, 2014)
Global
Added Automotive temperature option
Revision 08 (October 28, 2014)
Global
74
Data Sheet designation updated from Preliminary to Full Production
Spansion® SLC NAND Flash Memory for Embedded
S34MS01G1_04G1_08 October 28, 2014
Data
She et
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2012-2014 Spansion LLC. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
HyperBus™, HyperFlash™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and
other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
October 28, 2014 S34MS01G1_04G1_08
Spansion® SLC NAND Flash Memory for Embedded
75