HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 2Gb NAND FLASH HY27UF082G2A HY27UF162G2A This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.4 / Mar. 2007 1 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Document Title 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Memory Revision History Revision No. 0.01 History Initial Draft. Draft Date Remark Jan. 24. 2006 Preliminary May. 18. 2006 Preliminary Sep. 07. 2006 Preliminary 1) Change NOP 0.1 2) Correct 5th Read ID 3) Chnage AC Timing Characteristics 0.2 1) Add x16 features. 1) Chnage AC Timing Characteristics 0.3 tR tCRRH tRHOH tRLOH Before 25 50 100 15 After 20 100 15 5 Nov. 21. 2006 2) Add AC Timing Characteristics - tCOH = 15ns (min) 3) Correct copy back function 4) Delet Preliminary. 0.4 1) Delete cache read function in x16 product Rev 0.4 / Mar. 2007 Mar. 21. 2007 2 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities FAST BLOCK ERASE - Block erase time: 2ms (Typ.) STATUS REGISTER ELECTRONIC SIGNATURE - 1st cycle: Manufacturer Code - 2nd cycle: Device Code SUPPLY VOLTAGE - VCC = 2.7 to 3.6V : HY27UFxx2G2A - 3rd cycle: Internal chip number, Cell Type, Number of Memory Cell Array - 4th cycle: Page size, Block size, Organization, Spare size = (2K+64) Bytes x 64 Pages x 2,048 Blocks - 5th cycle: Plane Number, Plane Size Simultaneously Programmed Pages. = (1K+32) Words x 64pages x 1,024 Blocks CHIP ENABLE DON’T CARE PAGE SIZE - Simple interface sith microcontroller - x8 device : (2K+64 spare) Bytes : HY27UF082G2A SERIAL NUMBER OPTION - x16 device : (1K+32 spare) Words : HY27UF162G2A BLOCK SIZE - x8 device: (128K + 4K spare) Bytes - x16 device : (64K + 2K spare) Words PAGE READ / PROGRAM - Random access: 25us (max.) - Sequential access: 30ns (min.) - Page program time: 200us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC) - 10 years Data Retention PACKAGE - HY27UF(08/16)2G2A-T(P) : 48-pin TSOP1(12 x 20 x 1.2 mm) - HY27UF(08/16)2G2A-T (Lead) - HY27UF(08/16)2G2A-TP (Lead Free) - HY27UF082G2A-UP : 52-ULGA (12 x 17 x 0.65 mm) - HY27UF082G2A-UP (Lead Free) CACHE PROGRAM - Internal (2048+64) Byte buffer to improve the program throughput Rev 0.4 / Mar. 2007 3 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 1. SUMMARY DESCRIPTION The Hynix HY27UF(08/16)2G2A series is a 256Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block. Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input pin or using the extended lock block feature described later. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27UF(08/16)2G2A extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature (x8) is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out. The HYNIX HY27UF(08/16)2G2A series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm. 1.1 Product List PART NUMBER ORIZATION HY27UF082G2A x8 HY27UF162G2A x16 Rev 0.4 / Mar. 2007 VCC RANGE 2.7V - 3.6 Volt PACKAGE 48TSOP1 / 52-ULGA 48TSOP1 4 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 9&& ,2a,2 &( ,2a,2[2QO\ :( 5% 5( $/( &/( :3 966 Figure1: Logic Diagram IO15 - IO8 Data Inputs / Outputs (x16 Only) IO7 - IO0 Data Inputs / Outputs CLE Command latch enable ALE Address latch enable CE Chip Enable RE Read Enable WE Write Enable WP Write Protect R/B Ready / Busy Vcc Power Supply Vss Ground NC No Connection Table 1: Signal Names Rev 0.4 / Mar. 2007 5 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 9VV ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 9FF 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9VV Figure 2. 48TSOP1 Contactions, x8 and x16 Device Rev 0.4 / Mar. 2007 6 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 1& 1& 966 1& 1& 1& 5% :( :3 1& 1& + - 1& ,2 966 1& 1& . / 1& 1& 9&& 1& ) * ,2 966 1& 1& 1& ,2 ,2 1& ' ,2 ,2 & ( 1& 1& ,2 1& 1& 966 ,2 1& 5( $ % 1& 1& 1& 1& 9&& 1& $/( 1& &( &/( 0 1 1& 1& 1& Figure 3. 52-ULGA Contactions, x8 Device (Top view through package) Rev 0.4 / Mar. 2007 7 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 1.2 PIN DESCRIPTION Pin Name Description IO0-IO7 IO8-IO15(1) DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. CLE COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ALE ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CE CHIP ENABLE This input controls the selection of the device. When the device is busy CE low does not deselect the memory. WE WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments theocolumn address counter by one. WP WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. R/B READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. VCC SUPPLY VOLTAGE The VCC supplies the power for all the operations (Read, Write, Erase). VSS GROUND NC NO CONNECTION Table 2: Pin Description NOTE: 1. For x16 version only 2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. 3. An internal voltage detector disables all functions whenever VCC is below 2.0V (3.3V version) version to protect the device from any involuntary program/erase buring power transitions. Rev 0.4 / Mar. 2007 8 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A8 A9 A10 A11 L(1) L(1) L(1) L(1) 3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27 5th Cycle A28 L(1) L(1) L(1) L(1) L(1) L(1) L(1) Table 3: Address Cycle Map(x8) NOTE: 1. L must be set to Low. IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1) 2nd Cycle A8 A9 A10 L(1) L(1) L(1) L(1) L(1) L(1) 3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 L(1) 4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 L(1) 5th Cycle A27 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1) Table 4: Address Cycle Map(x16) NOTE: 1. L must be set to Low. FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE READ 1 00h 30h - - READ FOR COPY-BACK 00h 35h - - READ ID 90h - - - RESET FFh - - - PAGE PROGRAM 80h 10h - - COPY BACK PGM 85h 10h - - BLOCK ERASE 60h D0h - - READ STATUS REGISTER 70h - - - CACHE PROGRAM 80h 15h - - RANDOM DATA INPUT 85h - - - RAMDOM DATA OUTPUT 05h E0h - - 00h 31h - - 34h - - - CACHE READ START CACHE READ EXIT (1) (1) Acceptable command during busy Yes Yes Table 5: Command Set NOTE: 1. Only for x8 product Rev 0.4 / Mar. 2007 9 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash CLE ALE CE WE RE WP MODE H L L Rising H X L H L Rising H X H L L Rising H H L H L Rising H H L L L Rising H H Data Input L L L(1) H Falling X Sequential Read and Data Output L L L H H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) X X X X X L Write Protect X X H X X 0V/Vcc Read Mode Write Mode Command Input Address Input(5 cycles) Command Input Address Input(5 cycles) Stand By Table 6: Mode Selection NOTE: 1. With the CE high during latency time does not stop the read operation Rev 0.4 / Mar. 2007 10 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 2. BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. 2.1 Command Input. Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 5 and table 13 for details of the timings requirements. Command codes are always applied on IO7:0, disregarding the bus configuration (X8/x16). 2.2 Address Input. Address Input bus operation allows the insertion of the memory address. To insert the 29 addresses needed to access the 2Gbit 5 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 13 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/x16). 2.3 Data Input. Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 7 and table 13 for details of the timings requirements. 2.4 Data Output. Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 8,9,10,11 and table 13 for details of the timings requirements. 2.5 Write Protect. Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev 0.4 / Mar. 2007 11 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 3. DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read operations, the second one does need 00h command, which five address cycles and 30h command initiates that operation. Second read operation always requires setup command if first read operation was executed using also random data out command. Two types of operations are available: random read. The random read mode is enabled when the page address is changed. The 2112bytes (X8 device) or 1056words (x16 device) of data within the selected page are transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time (3.3V version) by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Random data output is not available in cache read (x8). 3.2 Page Program. The device is programmed basically by page, but it does allow multiple partial page programming of a word or consecutive bytes up to 2112 (X8 device) or 1056 (x16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array (X8 device:1time/512byte, x16 device:1time/256word) and 4 times for spare array (X8 device:1time/16byte, x16 device:1tme/8word). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes (X8 device) or 1056words (x16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The P/E/R controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 13 details the sequence. Rev 0.4 / Mar. 2007 12 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 3.3 Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A28 (X8) or A17 to A27 (x16) is valid while A12 to A17 (X8) or A11 to A16 (x16) are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the P/E/R controller handles erase and erase-verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 17 details the sequence. 3.4 Copy-Back Program. The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or 1056word (x16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 15. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 15 shows the command sequence for the copy-back operation. The Copy Back Program operation requires three steps: 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 5 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page Buffer. 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 5bus cycles to input the target page address. The value for A28 from second to the last page address must be same as the value given to A28 in first address. 3. Then the confirm command is issued to start the P/E/R Controller. Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, It’s prohibited to operate copy-back program from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages. Rev 0.4 / Mar. 2007 13 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 3.5 Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE# or CE# does not need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. See figure 9 for details of the Read Status operation. 3.6 Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence, while tables 16 explain the byte meaning. 3.7 Reset. The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to figure 23. Rev 0.4 / Mar. 2007 14 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 3.8 Cache program Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (x16) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2112byte (X8 device) or 1056word (x16 device) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/ O6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked. See figure 16 for more details. NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tPROG= Program time for the last page+ Program time for the ( last -1 ) page - (Program command cycle time + Last page data loading time) The value for A28 from second to the last page address must be same as the value given to A28 in first address. Rev 0.4 / Mar. 2007 15 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 3.9 Cache Read (x8) Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device. Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - R/B ( “0” means latency ongoing, download not possible, “1” means download of n page possible, even if device internally is active on n+1 page) - Status register (SR<6> behave like R/B, SR<5> is “0” when device is internally reading and “1” when device is idle) To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time (both device idle and reading). If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time shorter then tRBSY before becoming again idle and ready to accept any further commands. If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. Random data output is not available in cache read. Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks. Rev 0.4 / Mar. 2007 16 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 4. OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V version). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 24. The two-step command sequence for program/erase provides additional software protection. If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed the data. Power protection function is only available during the power on/off sequence. 4.2 Ready/Busy. The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the P/E/R controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Figure 25). Its value can be determined by the following guidance. Rev 0.4 / Mar. 2007 17 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Parameter Symbol Min Valid Block Number NVB 2008 Typ Max Unit 2048 Blocks Table 7: Valid Blocks Number NOTE: 1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes) Symbol Parameter Value 3.3V Unit Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 ℃ Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 ℃ TBIAS Temperature Under Bias -50 to 125 ℃ TSTG Storage Temperature -65 to 150 ℃ VIO(2) Input or Output Voltage -0.6 to 4.6 V Supply Voltage -0.6 to 4.6 V TA Vcc Table 8: Absolute maximum ratings NOTE: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev 0.4 / Mar. 2007 18 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash $a$ $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 $/( &/( :( &( :3 5( ; 0ELW0ELW 1$1')ODVK 0(025<$55$< ' ( & 2 ' ( 5 &200$1' ,17(5)$&( /2*,& 3$*(%8))(5 &200$1' 5(*,67(5 <'(&2'(5 '$7$ 5(*,67(5 %8))(56 ,2 Figure 4: Block Diagram Rev 0.4 / Mar. 2007 19 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Parameter Symbol Test Conditions Sequential Read ICC1 Program Erase 3.3Volt Unit Min Typ Max tRC=30ns CE=VIL, IOUT=0mA - 15 30 mA ICC2 - - 15 30 mA ICC3 - - 15 30 mA Stand-by Current (TTL) ICC4 CE=VIH, WP=0V/Vcc - 1 mA Stand-by Current (CMOS) ICC5 CE=Vcc-0.2, WP=0V/Vcc - 10 50 uA Input Leakage Current ILI VIN=0 to Vcc (max) - - ± 10 uA Output Leakage Current ILO VOUT =0 to Vcc (max) - - ± 10 uA Input High Voltage VIH - Vccx0.8 - Vcc+0.3 V Input Low Voltage VIL - -0.3 - 0.2xVcc V Output High Voltage Level VOH IOH=-400uA 2.4 - - V Output Low Voltage Leve VOL IOL=2.1mA - - 0.4 V Output Low Current (R/B) IOL (R/B) VOL=0.4V 8 10 - mA Operating Current Table 9: DC and Operating Characteristics Value Parameter 3.3Volt Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc / 2 Output Load (2.7V - 3.6V) 1 TTL GATE and CL=50pF Table 10: AC Conditions Rev 0.4 / Mar. 2007 20 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Item Symbol Test Condition Min Max Unit Input / Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Symbol Min Typ Max Unit Program Time tPROG - 200 700 us Dummy Busy Time for Cache Program tCBSY - 3 700 us Main Array NOP - - 4 Cycles Spare Array NOP - - 4 Cycles tBERS - 2 3 ms Number of partial Program Cycles in the same page Block Erase Time Table 12: Program / Erase Characteristics Rev 0.4 / Mar. 2007 21 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Parameter Symbol 3.3Volt Min Max 15 Unit CLE Setup time tCLS ns CLE Hold time tCLH 5 ns CE setup time tCS 25 ns CE hold time tCH 5 ns WE pulse width tWP 15 ns ALE setup time tALS 15 ns ALE hold time tALH 5 ns Data setup time tDS 15 ns Data hold time tDH 5 ns Write Cycle time tWC 30 ns WE High hold time tWH 10 ns tADL(2) 100 ns Address to Data Loading time Data Transfer from Cell to register tR ALE to RE Delay tAR 15 20 ns CLE to RE Delay tCLR 15 ns Ready to RE Low tRR 20 ns RE Pulse Width tRP 15 ns WE High to Busy tWB 100 30 us ns Read Cycle Time tRC RE Access Time tREA 25 ns ns RE High to Output High Z tRHZ 50 ns CE High to Output High Z tCHZ 50 ns Cache Read RE high tCRRH 100 ns RE High to Output hold tRHOH 15 ns RE Low to Output hold tRLOH 5 ns CE High to Output Hold tCOH 15 ns RE High Hold Time tREH 10 ns tIR 0 ns Output High Z to RE low CE Access Time tCEA WE High to RE low tWHR Device Resetting Time (Read / Program / Erase) tRST tWW(3) Write Protection time 30 60 5/10/500(1) 100 ns ns us ns Table 13: AC Timing Characteristics NOTE: 1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 2. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle. 3. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High. Rev 0.4 / Mar. 2007 22 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash IO Pagae Program Block Erase Read CODING 0 Pass / Fail Pass / Fail NA Pass: ‘0’ Fail: ‘1’ 1 NA NA NA Pass: ‘0’ Fail: ‘1’ 2 NA NA NA - 3 NA NA NA - 4 NA NA NA - 5 Ready/Busy Ready/Busy Ready/Busy Active: ‘0’ Idle: ‘1’ 6 Ready/Busy Ready/Busy Ready/Busy Busy: ‘0’ Ready’: ‘1’ 7 Write Protect Write Protect Write Protect Protected: ‘0’ Not Protected: ‘1’ Table 14: Status Register Coding DEVIIDENTIFIER CYCLE DESCRIPTION 1st Manufacturer Code 2nd Device Identifier Internal chip number, cell Type, Number of Simultaneously Programmed pages. 3rd 4th Page size, spare size, Block size, Organization 5th Plane Number, Plane Size Table 15: Device Identifier Coding Bus 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle Width (Manufacture Code) (Device Code) Part Number Voltage HY27UF082G2A 3.3V x8 ADh DAh 80h 1Dh 00h HY27UF162G2A 3.3V x16 ADh CAh 80h 5Dh 00h Table 16: Read ID Data Table Rev 0.4 / Mar. 2007 23 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Description Die / Package String Type Number of Simultaneously Programmed Pages IO7 IO6 IO5 IO4 IO3 IO2 1 2 4 Reserved 0 0 1 1 Single Level 2x Multi-level Reserved Reservedl 0 0 1 1 1 2 3 4 Interleave Program Between different dice Not Support Support Write Cache Not Support Support IO1 IO0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 17: 3rd Byte of Device Idendifier Description Description Page Size (Without Spare Area) Spare Area Size (Byte / 512 Byte) 8 16 Serial Access Time 50ns 30ns 25ns Reserved Block Size (Without Spare Area) Organization IO7 IO6 IO5-4 IO3 IO2 1KB 2KB 4KB Reserved 64KB 128KB 256KB 512KB X8 X16 IO1-0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 Table 18: 4th Byte of Device Identifier Description Rev 0.4 / Mar. 2007 24 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Description Plane Number Plane Size (Without Redundant Area) Reserved IO7 IO6 IO5-4 1 2 3 4 1Gb 2Gb 4Gb 8Gb Reserved Reserved Reserved Reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 IO3 IO2 0 0 1 1 1 0 0 1 IO1-0 0 1 0 1 0 1 0 1 0 0 0 Table 19: 5th Byte of Device Identifier Description Rev 0.4 / Mar. 2007 25 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash &/( W&/6 W&/+ W&6 W&+ &( W:3 :( W$/6 W$/+ $/( W'6 ,2[ W'+ &RPPDQG Figure 5: Command Latch Cycle W&/6 &/( W&6 W:& &( :( W:& W:3 W:3 W$/+ W:+ W$/6 W:& W:3 W:+ W$/6 W:& W$/+ W:3 W:+ W$/6 W$/+ W:+ W$/6 W$/+ W$/6 W$/+ $/( ,2[ W'+ W'+ W'+ W'6 W'6 &RO$GG &RO$GG W'6 5RZ$GG W'+ W'+ W'6 5RZ$GG W'6 5RZ$GG Figure 6: Address Latch Cycle Rev 0.4 / Mar. 2007 26 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash W&/+ &/( W&+ &( W:& $/( W$/6 W:3 W:3 :( W:3 W:+ W'6 ,2[ W'+ W'6 ',1 W'+ ',1 W'6 W'+ ',1ILQDO 1RWHV',1ILQDOPHDQV Figure 7. Input Data Latch Cycle tCEA CE tREA tREH tRP tCHZ* tREA tREA tOH RE tRHZ tRHZ* tOH I/Ox Dout tRR Dout Dout tRC R/B Notes : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.4 / Mar. 2007 27 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash tCLR CLE t CLS tCLH tCS CE tCH tWP WE tCEA t2H tCHZ tWHR RE tDS I/Ox tDH tIR t2H tREA tRH= Status Output 70h Figure 9: Status Read Cycle W&/5 &/( &( W:& :( W:% W$5 $/( W5 W5& W5+= 5( W55 ,2[ K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG &ROXPQ$GGUHVV 5' K 'RXW1 'RXW1 'RXW0 5RZ$GGUHVV %XV\ Figure 10: Read1 Operation (Read One Page) Rev 0.4 / Mar. 2007 28 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash &/( &( :( W:% W&+= W$5 W&2+ $/( W5 W5& 5( W55 ,2[ K 5% &RO &RO $GG $GG &ROXPQ$GGUHVV 5RZ $GG 5RZ 5RZ $GG $GG 5RZ$GGUHVV 'RXW 1 K 'RXW 1 'RXW 1 %XV\ Figure 11: Read1 Operation intercepted by CE Rev 0.4 / Mar. 2007 29 Rev 0.4 / Mar. 2007 5% ,2[ 5( $/( :( &( &/( &ROXPQ$GGUHVV 5RZ$GGUHVV K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG K W55 W$5 %XV\ W5 W:% 'RXW1 W5& 'RXW1 W5+: K &RO$GG &RO$GG &ROXPQ$GGUHVV (K W:+5 W&/5 'RXW0 W5($ 'RXW0 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 12 : Random Data output 30 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash &/( &( W:& W:& W:& :( W$'/ W:% W352* $/( 5( ,2[ K &RO $GG &RO $GG 6HULDO'DWD ,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ $GG 5RZ $GG 5RZ $GG 5RZ$GGUHVV 'LQ 1 XSWRP%\WH 6HULDO,QSXW 'LQ 0 K 3URJUDP &RPPDQG K ,2R 5HDG6WDWXV &RPPDQG 5% ,2R 6XFFHVVIXO3URJUDP ,2R (UURULQ3URJUDP Figure 13: Page Program Operation Rev 0.4 / Mar. 2007 31 Rev 0.4 / Mar. 2007 5% ,2[ 5( $/( :( &( &/( W:& W$'/ 5RZ$GGUHVV &RO$GG &RO$GG 5ZR$GG 5ZR$GG 5ZR$GG 6HULDO'DWD ,QSXW&RPPDQG &ROXPQ$GGUHVV K W:& 'LQ 0 K 5DQGRP'DWD 6HULDO,QSXW ,QSXW&RPPDQG 'LQ 1 W:& &RO$GG &ROXPQ$GGUHVV &RO$GG W$'/ 6HULDO,QSXW 'LQ - 'LQ . K 3URJUDP &RPPDQG W:% W352* K 5HDG6WDWXV &RPPDQG ,2 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 14 : Random Data In 32 Rev 0.4 / Mar. 2007 5% ,2[ 5( $/( :( &( &/( K W:& &RO $GG &ROXPQ$GGUHVV &RO $GG 5RZ $GG 5RZ $GG 5RZ$GGUHVV 5RZ $GG K K &RO $GG 5RZ $GG &ROXPQ$GGUHVV &RO $GG &RS\%DFN'DWD ,QSXW&RPPDQG %XV\ W5 W:% 5RZ $GG 5RZ$GGUHVV 5RZ $GG 'DWD W$'/ 'DWD1 K W:% %XV\ W352* %KK ,2[ HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 15 : Copy Back Program 33 Rev 0.4 / Mar. 2007 5% ,2[ 5( $/( :( &( &/( &RO $GG &RO $GG 5RZ $GG 5RZ $GG 5RZ $GG ,2[ 5% $GGUHVV 'DWD,QSXW K K W&%6< K $GGUHVV 'DWD,QSXW W&%6<PD[XV 3URJUDP &RPPDQG 'XPP\ W:% W&%6< &RO$GG5RZ$GG'DWD K ([&DFKH3URJUDP 'LQ 0 6HULDO,QSXW 'LQ 1 0D[WLPHVUHSHDWDEOH 6HULDO'DWD &ROXPQ$GGUHVV 5RZ$GGUHVV ,QSXW&RPPDQG K W:& K K W&%6< K &RO $GG &RO $GG 5RZ $GG 'LQ 1 'LQ 0 W&%6< K K K $GGUHVV 'DWD,QSXW 3URJUDP&RQILUP &RPPDQG7UXH /DVW3DJH,QSXW3URJUDP 5RZ $GG $GGUHVV 'DWD,QSXW 5RZ $GG W:% W352* K W352* K K ,2 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 16 : Cache Program 34 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash &/( &( W:& :( W:% W%(56 $/( 5( ,2[ K 5RZ 5RZ 5RZ $GG $GG $GG 5RZ$GGUHVV 'K K 5% ,2 %86< (UDVH&RPPDQG $XWR%ORFN(UDVH 6HWXS&RPPDQG 5HDG6WDWXV &RPPDQG ,2 6XFFHVVIXO(UDVH ,2 (UURULQ(UDVH Figure 17: Block Erase Operation (Erase One Block) &/( &( :( W$5 $/( 5( W5($ K K 5HDG,'&RPPDQG $GGUHVVF\FOH ,2[ $'K '$K 0DNHU&RGH 'HYLFH&RGH K 'K K UG&\FOH WK&\FOH WK&\FOH Figure 18: Read ID Operation Rev 0.4 / Mar. 2007 35 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash &/( $/( :( ' 'K $GG $GG $GG $GG $GG K ' ' ' ' ' ' ' ' ' ' ' ' V 5( ,QWHUQDORSHUDWLRQ 5HDGVWSDJH 5HDGQGSDJH ,GOH V 5HDGUGSDJH V V 6WDWXV5HJLVWHU 65! 5HDGWKSDJH ,GOH V V V Figure 19: start address at page start :after 1st latency uninterrupted data flow &/( 8VHUFDQ KHUHILQLVK UHDGLQJ1 SDJH $/( :( ' ' ' ' ' ' ' K QSDJH QSDJH 5( 1SDJH FDQQRWEH UHDG VW5%6< 5% ,QWHUQDO RSHUDWLRQ 5HDGQSDJH ,GOH ,QWHUUXSWHG 5HDG QSDJH ,GOH V V 6WDWXV5HJLVWHU 65! Figure 20: exit from cache read in 5us when device internally is reading (x8) Rev 0.4 / Mar. 2007 36 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function. &/( &(GRQ¶WFDUH &( :( $/( ,2[ K 6WDUW$GG&\FOH 'DWD,QSXW 'DWD,QSXW K Figure 21: Program Operation with CE don’t-care. &/( ,IVHTXHQWLDOURZUHDGHQDEOHG &(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH &( 5( $/( 5% W5 :( ,2[ K 6WDUW$GG&\FOH K 'DWD2XWSXWVHTXHQWLDO Figure 22: Read Operation with CE don’t-care. Rev 0.4 / Mar. 2007 37 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash :( $/( &/( 5( ,2[ ))K W567 5% Figure 23: Reset Operation 9FF 97+ W :3 :( XV Figure 24: Power On and Data Protection Timing VTH = 2.5 Volt for 3.3 Volt Supply devices Rev 0.4 / Mar. 2007 38 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 5S LEXV\ 9FF 5HDG\ 9FF 5% RSHQGUDLQRXWSXW 92+ &/ 92/ %XV\ WI WU *1' 'HYLFH #9FF 97D &&/ S) LEXV\ Q WUWI>V@ Q Q P P N WI N N N LEXV\>$@ P 5SRKP 5SYDOXHJXLGHQFH 5SPLQ9SDUW 9FF0D[92/0D[ ,2/,/ 9 P$,/ ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ 5SPD[LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU Figure 25: Ready/Busy Pin electrical specifications Rev 0.4 / Mar. 2007 39 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte / 1st Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 26. The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See the “Copy Back Program” section for more details. Refer to Table 20 for the recommended procedure to follow if an error occurs during an operation. Operation Recommended Procedure Erase Block Replacement Program Block Replacement or ECC (with 1bit/528byte) Read ECC (with 1bit/528byte) Table 20: Block Failure 67$57 %ORFN$GGUHVV %ORFN ,QFUHPHQW %ORFN$GGUHVV 'DWD ))K" 1R 8SGDWH %DG%ORFNWDEOH <HV /DVW EORFN" 1R <HV (1' Figure 26: Bad Block Management Flowchart Rev 0.4 / Mar. 2007 40 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 27~30) :( W :: ,2[ K K :3 5% Figure 27: Enable Programming :( W :: ,2[ K K :3 5% Figure 28: Disable Programming Rev 0.4 / Mar. 2007 41 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash :( W :: K ,2[ 'K :3 5% Figure 29: Enable Erasing :( W :: ,2[ K 'K :3 5% Figure 30: Disable Erasing Rev 0.4 / Mar. 2007 42 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash H ' $ $ % $ Į / ',( ( ( & &3 Figure 31: 48pin-TSOP1, 12 x 20mm, Package Outline millimeters Symbol Min Typ A Max 1.200 A1 0.050 0.150 A2 0.980 1.030 B 0.170 0.250 C 0.100 0.200 CP 0.100 D 11.910 12.000 12.120 E 19.900 20.000 20.100 E1 18.300 18.400 18.500 e 0.500 L 0.500 0.680 alpha 0 5 Table 21: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data Rev 0.4 / Mar. 2007 43 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash % % % ' ' & & & FS 0 & $% $ $ $ FS 0 & $% ( Figure 32. 52-ULGA, 12 x 17mm, Package Outline (Top view through package) Symbol A millimeters Min Typ Max 16.90 17.00 17.10 A1 13.00 A2 B 12.00 11.90 12.00 B1 10.00 B2 6.00 C 1.00 C1 1.50 C2 2.00 D 1.00 D1 12.10 1.00 E 0.55 0.60 0.65 CP1 0.65 0.70 0.75 CP2 0.95 1.00 1.05 Table 22: 52-ULGA, 12 x 17mm, Package Mechanical Data Rev 0.4 / Mar. 2007 44 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash MARKING INFORMATION - TSOP1/ULGA P a ck a g TSO P1 / ULGA M a rk in g E x a m p le H Y 2 7 x x x x U F - h y n ix : H yn ix S ym b ol - KOR : O rigin C o u n try - H Y27UFxx2G 2A xxxx : P a rt N u m b e r x K O R x 2 G 2 A Y W W x x H Y : H yn ix 2 7 : N A N D Fla sh U : P o w e r S u p p ly : U (2 .7 V ~ 3 .6 V ) F : C la ssifica tion : S in g le Le vel C e ll+ S in gle D ie + La rge B lo ck x x : B it O rg a n iza tion : 0 8 (x8 ), 1 6 (x1 6) 2 G : D e n sity : 2 G bit 2 : M o de : 1 n C E & 1 R /n B ; S e qu e n tia l R ow R e ad D isa ble A : V e rsion : 2 n d G e n era tion x : P acka ge T yp e : T (4 8 -T S O P 1 ), U (5 2 -U LG A ) x : P acka g e M a te ria l : B lan k(N o rm al), P (Lead Free) x : O p eratin g T e m perature : C (0 ℃ ~ 7 0 ℃ ) I(-4 0℃ ~ 8 5 ℃ ) x : B ad B lo ck : B (In clu d ed B ad B lo ck), S (1 ~ 5 B ad B lo ck), P (A ll G o o d B lock) - Y : Y e ar (ex: 5= year 20 0 5 , 06 = year 20 0 6 ) - w w : W o rk W eek (e x: 12 = w ork w eek 12 ) - x x : P roce ss C o d e N o te - C a p ita l L e tte r : Fixed Ite m - S m a ll L e tte r : N o n -fixe d Item Rev 0.4 / Mar. 2007 45