The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS705-00001-2v1-E 32-bit Microcontroller CMOS FR60 MB91460T Series MB91F467TA, MB91F469TA*1 ■ DESCRIPTION MB91460T series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family*2 of CPUs. This series contains the LIN-USART and CAN controllers. ■ FEATURES 1. FR60 CPU core • • • • • • • • 32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) (Continued) For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.7 MB91460T Series (Continued) • Harvard architecture enabling program access and data access to be performed simultaneously • Instructions compatible with the FR family 2. Internal peripheral resources • General-purpose ports : Maximum 109 ports • DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) Activation source can be selected using software Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) • A/D converter (successive approximation type) 10-bit resolution: 32 channels *3 Conversion time: minimum 1 μs • External interrupt inputs : 12 channels *3 8 channels shared with A/D converter AN8-15 • Bit search module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word • LIN-USART (full duplex double buffer): 11 channels *3 Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator • I2C bus interface (supports 400 kbps): 4 channels *3 Master/slave transmission and reception Arbitration function, clock synchronization function • CAN controller (C-CAN): Maximum of 2 channels Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers • Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) • Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) • 16-bit PPG timer : 14 channels *3 • 16-bit PFM timer : 1 channel *3 • 16-bit reload timer: 8 channels • 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) *3 • Input capture: 8 channels (operates in conjunction with the free-run timer) • Output compare: 8 channels (operates in conjunction with the free-run timer) • Up/Down counter: 2 channels (4*8-bit or 2*16-bit) *3 • Watchdog timer Note: *1 This device is planned. Note: *2 FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor Limited. Note: *3 The maximum channel count is given; the real number depends on port multiplexing. (Continued) 2 DS705-00001-2v1-E MB91460T Series (Continued) • Real-time clock • Low-power consumption modes : Sleep/stop mode function • Low voltage detection circuit • Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. • Clock modulator • Clock monitor • Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator • Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter • Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. Package and technology • • • • Package: QFP-144 CMOS 0.18 μm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between − 40°C and + 105°C / + 125°C *1 Note *1: For maximum ambient temperature TA(max), please refer to “ORDERING INFORMATION” on page 130. DS705-00001-2v1-E 3 MB91460T Series ■ PRODUCT LINEUP Feature MB91V460A MB91FV460B *4 MB91F467TA MB91F469TA *3 Max. core frequency (CLKB) 80MHz 100MHz 100MHz 100MHz Max. resource frequency (CLKP) 40MHz 50MHz 50MHz 50MHz Max. external bus freq. (CLKT) 40MHz 50MHz 50MHz 50MHz Max. CAN frequency (CLKCAN) 20MHz 50MHz 50MHz 50MHz Max. FlexRay frequency (SCLK) - - - - 0.35μm 0.18um 0.18μm 0.18μm yes yes yes yes Technology Watchdog yes (disengageable) yes (disengageable) yes yes Bit Search yes yes yes yes Reset input (INITX) yes yes yes yes Hardware Standby input (HSTX) yes yes no no Clock Modulator yes yes yes yes Clock Monitor yes yes yes yes Watchdog (RC osc. based) Low Power Mode yes yes yes yes DMA 5 ch 5 ch 5 ch 5 ch MAC (μDSP) MMU/MPU Flash no no no no MPU (16 ch) 1) MPU (16 ch) 1) MPU (8 ch) 1) MPU (8 ch) 1) Emulation SRAM 32bit read data Internal Flash memory 2112KB + external emulation SRAM with 64bit read data 1088 KByte 2112 KByte Satellite Flash - - no no Flash Protection - yes yes yes 64 KByte 64 KByte 32 KByte 64 KByte D-RAM ID-RAM 64 KByte 64 KByte 32 KByte 64 KByte Flash-Cache (Instruction cache) 16 KByte 16 KByte 8 KByte 16 KByte 4 KByte fixed 16 KByte Boot Flash + 1KB Boot ROM 4 KByte 4 KByte Boot-ROM / BI-ROM RTC 1 ch 1 ch 1 ch 1 ch Free Running Timer 8 ch 12 ch 8 ch*2 8 ch*2 ICU 8 ch 10 ch 8 ch*2 8 ch*2 OCU 8 ch 8 ch 8 ch*2 8 ch*2 Reload Timer 8 ch 16 ch 8 ch 8 ch PPG 16-bit 16 ch 32 ch 14 ch*2 14 ch*2 PFM 16-bit 1 ch 1 ch 1 ch*2 1 ch*2 Sound Generator 1 ch 1 ch (old) + 1 ch (new) 1 ch Up/Down Counter (8/16-bit) C_CAN LIN-USART I2C (400k) 4 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit) 1 ch *2 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit)*2 6 ch (128msg) 6 ch (128msg) 2 ch (32msg) 2 ch (32msg) 4 ch + 4 ch FIFO + 8 ch 16 ch FIFO 4 ch + 4 ch FIFO + 3 ch*2 4 ch + 4 ch FIFO + 3 ch*2 4 ch 8 ch 4 ch*2 4 ch*2 DS705-00001-2v1-E MB91460T Series Feature FR external bus MB91V460A yes (32bit addr, 32bit data) MB91FV460B *4 MB91F467TA MB91F469TA *3 yes (32bit addr, 32bit data) yes (24bit addr, 16bit data) yes (24bit addr, 16bit data) External Interrupts 16 ch 32 ch 12 ch*2 12 ch*2 NMI Interrupts 1 ch 1 ch 1 ch 1 ch SMC 6 ch 6 ch - - LCD controller (40x4) 1 ch 1 ch - - ADC (10 bit) 32 ch 32 ch + 22 ch 32 ch*2 32 ch*2 Alarm Comparator 2 ch 2 ch - - Supply Supervisor yes yes yes yes Clock Supervisor yes yes yes yes 4MHz 4MHz 4MHz 4MHz Main clock oscillator Sub clock oscillator 32kHz 32kHz 32kHz 32kHz RC Oscillator 100kHz 100kHz 100kHz / 2MHz 100kHz / 2MHz x 20 x 25 x 25 x 25 PLL DSU4 yes DSU4 - - EDSU yes (32 BP) *1 yes (32 BP) *1 yes (16 BP) *1 yes (16 BP) *1 3V / 5V 1.8V + 3V / 5V 3V / 5V 3V / 5V Supply Voltage Regulator yes - yes yes Power Consumption n.a. <3W < 1.3 W < 1.3 W Temperature Range (TA) 0..70 C 0..70 C -40..105 C -40..105 C Package BGA660 BGA-896 QFP144 QFP144 Power on to PLL run < 20 ms < 20 ms < 20 ms < 20 ms Flash Download Time n.a. < 8 sec typical < 5 sec. typical < 6 sec typical *1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU). *2 : Maximum channel count is shown; function is multiplexed with other pins *3 : This device is planned. *4 : The new emulation device MB91FV460B can emulate the MB91460T series special pin multiplexing as well as the behaviour of the external bus at startup. DS705-00001-2v1-E 5 MB91460T Series ■ PIN ASSIGNMENT 1. MB91F467TA, MB91F469TA 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD35 P07_7/A7 or P26_7/AN31 P07_6/A6 or P26_6/AN30 P07_5/A5 or P26_5/AN29 P07_4/A4 or P26_4/AN28 P07_3/A3 or P26_3/AN27 P07_2/A2 or P26_2/AN26 P07_1/A1 or P26_1/AN25 P07_0/A0 or P26_0/AN24 P20_6/SCK3/ZIN1/CK3 or P27_7/AN23 P20_5/SOT3/BIN1 or P27_6/AN22 P20_4/SIN3/AIN1 or P27_5/AN21 P20_2/SCK2/ZIN0/CK2 or P27_4/AN20 P20_1/SOT2/BIN0 or P27_3/AN19 P20_0/SIN2/AIN0 or P27_2/AN18 P16_1/PPG9 or P27_1/AN17 P16_0/PPG8 or P27_0/AN16 VSS5 VDD5 P24_7/INT7/SCL3 or P28_7/AN15 P24_6/INT6/SDA3 or P28_6/AN14 P24_5/INT5/SCL2 or P28_5/AN13 P24_4/INT4/SDA2 or P28_4/AN12 P24_3/INT3 or P28_3/AN11 P24_2/INT2 or P28_2/AN10 P24_1/INT1 or P28_1/AN9 P24_0/INT0 or P28_0/AN8 P29_7/AN7 P29_6/AN6 P35_6/SCK9 or P29_5/AN5 P35_5/SOT9 or P29_4/AN4 P35_4/SIN9 or P29_3/AN3 P35_2/SCK8 or P29_2/AN2 P35_1/SOT8 or P29_1/AN1 P35_0/SIN8 or P29_0/AN0 VSS5 (TOP VIEW) FPT-144P-M08 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 QFP-144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD5 AVCC5 AVRH5 AVSS5 P17_5/PPG5 P18_6/SCK7/ZIN3/CK7 P18_5/SOT7/BIN3 P18_4/SIN7/AIN3 P18_2/SCK6/ZIN2/CK6 P18_1/SOT6/BIN2 P18_0/SIN6/AIN2 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5 VSS5 P10_0/SYSCLK P10_1/ASX P10_3/WEX P09_0/CSX0 P09_1/CSX1 P09_2/CSX2 P08_0/WRX0 P08_1/WRX1 P08_4/RDX P08_7/RDY P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14/PFM P16_7/PPG15/AGTX VDD5 VSS5 P23_0/RX0/INT8 P23_1/TX0 P23_2/RX1/INT9 P23_3/TX1 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P14_0/ICU0/TIN0/TTG8/0 P14_1/ICU1/TIN1/TTG9/1 P14_2/ICU2/TIN2/TTG10/2 P14_3/ICU3/TIN3/TTG11/3 P15_0/OCU0/TOT0 P15_1/OCU1/TOT1 P15_2/OCU2/TOT2 P15_3/OCU3/TOT3 VDD5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VSS5 P06_0/A8 or P21_0/SIN0 P06_1/A9 or P21_1/SOT0 P06_2/A10 or P21_2/SCK0/CK0 P06_3/A11 or P17_4/PPG4 P06_4/A12 or P14_4/ICU4/TIN4/TTG12/4 P06_5/A13 or P14_5/ICU5/TIN5/TTG13/5 P06_6/A14 or P14_6/ICU6/TIN6/TTG14/6 P06_7/A15 or P14_7/ICU7/TIN7/TTG15/7 P05_0/A16 or P16_0/PPG8 P05_1/A17 or P16_1/PPG9 P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10) P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10) P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10) P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11) P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11) P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11) VDD35 VSS5 P01_0/D16 or P17_0/PPG0 P01_1/D17 or P17_1/PPG1 P01_2/D18 or P17_2/PPG2 P01_3/D19 or P17_3/PPG3 P01_4/D20 or P15_4/OCU4/TOT4 P01_5/D21 or P15_5/OCU5/TOT5 P01_6/D22 or P15_6/OCU6/TOT6 P01_7/D23 or P15_7/OCU7/TOT7 P00_0/D24 or P24_0/INT0 P00_1/D25 or P24_1/INT1 P00_2/D26 or P24_2/INT2 P00_3/D27 or P24_3/INT3 P00_4/D28 or P24_4/INT4 P00_5/D29 or P24_5/INT5 P00_6/D30 or P24_6/INT6 P00_7/D31 or P24_7/INT7 VDD35 6 DS705-00001-2v1-E MB91460T Series ■ PIN DESCRIPTION 1. MB91F467TA, MB91F469TA Pin no. Pin name P06_0 A8 I/O I/O circuit type* MUX I/O A PPMUX.PS4=0 2 General-purpose input/output port Signal pin of external address bus (bit8) OR P21_0 SIN0 P06_1 A9 I/O A PPMUX.PS4=1 I/O A PPMUX.PS4=0 3 General-purpose input/output port Data input pin of USART0 General-purpose input/output port Signal pin of external address bus (bit9) OR P21_1 SOT0 P06_2 A10 4 Function I/O A PPMUX.PS4=1 I/O A PPMUX.PS4=0 General-purpose input/output port Data output pin of USART0 General-purpose input/output port Signal pin of external address bus (bit10) OR P21_2 SCK0 General-purpose input/output port I/O A PPMUX.PS4=1 CK0 P06_3 A11 Clock input/output pin of USART0 External clock input pin of free-run timer 0 I/O A 5 PPMUX.PS4=0 General-purpose input/output port Signal pin of external address bus (bit11) OR P17_4 PPG4 I/O A PPMUX.PS4=1 P06_4 to P06_7 A12 to A15 General-purpose input/output port Output pin of PPG timer General-purpose input/output ports I/O A PPMUX.PS4=0 Signal pins of external address bus (bit12 to bit15) OR P14_4 to P14_7 6 to 9 General-purpose input/output ports ICU4 to ICU7 Input capture input pins TIN4 to TIN7 TTG12/4 TTG13/5 TTG14/6 TTG15/7 DS705-00001-2v1-E External trigger input pins of reload timer I/O A PPMUX.PS4=1 External trigger input pins of PPG timer 7 MB91460T Series Pin no. Pin name I/O I/O circuit type* MUX Function P05_0 A16 General-purpose input/output ports I/O A 10 PPMUX.PR10=0 Signal pins of external address bus (bit16) OR P16_0 PPG8 I/O A PPMUX.PR10=1 P05_1 A17 General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports I/O A 11 PPMUX.PR11=0 Signal pins of external address bus (bit17) OR P16_1 I/O PPG9 P05_2 A18 I/O A PPMUX.PR11=1 A PPMUX.PR12=0 General-purpose input/output ports Output pins of PPG timer General-purpose input/output port Signal pin of external address bus (bit18) OR P20_0 12 SIN2 I/O A AIN0 PPMUX.PR12=1 and PPMUX.PRPS0=1 General-purpose input/output port Data input pin of USART2 Up/down counter input pin OR P34_0 SIN10 P05_3 A19 I/O A PPMUX.PR12=1 and PPMUX.PRPS0=0 I/O A PPMUX.PR13=0 General-purpose input/output port Data input pin of USART10 General-purpose input/output port Signal pin of external address bus (bit19) OR P20_1 13 SOT2 I/O A BIN0 PPMUX.PR13=1 and PPMUX.PRPS0=1 General-purpose input/output port Data output pin of USART2 Up/down counter input pin OR P34_1 SOT10 8 I/O A PPMUX.PR13=1 and PPMUX.PRPS0=0 General-purpose input/output port Data output pin of USART10 DS705-00001-2v1-E MB91460T Series Pin no. Pin name P05_4 A20 I/O I/O circuit type* MUX I/O A PPMUX.PR14=0 Function General-purpose input/output port Signal pin of external address bus (bit20) OR P20_2 SCK2 14 ZIN0 General-purpose input/output port I/O A PPMUX.PR14=1 and PPMUX.PRPS0=1 CK2 Clock input/output pin of USART2 Up/down counter input pin External clock input pin of free-run timer 2 OR P34_2 SCK10 P05_5 A21 I/O A PPMUX.PR14=1 and PPMUX.PRPS0=0 I/O A PPMUX.PR15=0 General-purpose input/output port Clock input/output pin of USART10 General-purpose input/output port Signal pin of external address bus (bit21) OR P20_4 15 SIN3 I/O A AIN1 PPMUX.PR15=1 and PPMUX.PRPS0=1 General-purpose input/output port Data input pin of USART3 Up/down counter input pin OR P34_4 SIN11 P05_6 A22 I/O A PPMUX.PR15=1 and PPMUX.PRPS0=0 I/O A PPMUX.PR16=0 General-purpose input/output port Data input pin of USART11 General-purpose input/output port Signal pin of external address bus (bit22) OR P20_5 16 SOT3 I/O A BIN1 General-purpose input/output port PPMUX.PR16=1 and Data output pin of USART3 PPMUX.PRPS0=1 Up/down counter input pin OR P34_5 SOT11 DS705-00001-2v1-E I/O A PPMUX.PR16=1 General-purpose input/output port and PPMUX.PRPS0=0 Data output pin of USART11 9 MB91460T Series Pin no. Pin name P05_7 A23 I/O I/O circuit type* MUX I/O A PPMUX.PR17=0 Function General-purpose input/output port Signal pin of external address bus (bit23) OR P20_6 SCK3 17 ZIN1 General-purpose input/output port I/O A PPMUX.PR17=1 and PPMUX.PRPS0=1 CK3 Clock input/output pin of USART3 Up/down counter input pin External clock input pin of free-run timer 3 OR P34_6 SCK11 I/O A PPMUX.PR17=1 and PPMUX.PRPS0=0 P01_0 to P01_3 D16 to D19 I/O A PPMUX.PS3=0 PPG0 to PPG3 I/O A PPMUX.PS3=1 I/O A PPMUX.PS3=0 P01_4 to P01_7 D20 to D23 Output pins of PPG timer Signal pins of external data bus (bit20 to bit23) OR P15_4 to P15_7 OCU4 to OCU7 General-purpose input/output ports I/O A PPMUX.PS3=1 TOT4 to TOT7 D24 to D31 Output compare output pins Reload timer output pins P00_0 to P00_7 General-purpose input/output ports I/O A PPMUX.PR0=0 28 to 35 Signal pins of external data bus (bit24 to bit31) OR P24_0 to P24_7 INT0 to INT7 10 General-purpose input/output ports General-purpose input/output ports 24 to 27 40 Signal pins of external data bus (bit16 to bit19) OR P17_0 to P17_3 39 Clock input/output pin of USART11 General-purpose input/output ports 20 to 23 38 General-purpose input/output port P10_0 SYSCLK P10_1 ASX P10_3 WEX I/O A PPMUX.PR0=1 I/O A -- I/O A - I/O A - General-purpose input/output ports External interrupt input pins General-purpose input/output port External bus clock output pin General-purpose input/output port Address strobe output pin General-purpose input/output port Write enable output pin DS705-00001-2v1-E MB91460T Series Pin no. Pin name 41 to 43 P09_0 to P09_2 CSX0 to CSX2 44, 45 46 47 48, 49 P08_0, P08_1 WRX0, WRX1 P08_4 RDX P08_7 RDY P16_2, P16_3 PPG10, PPG11 I/O I/O circuit type* MUX I/O A - I/O A - I/O A - I/O A - I/O A - P16_4 50 51 52 PPG12 I/O A - PPG13 I/O A - External read strobe output pin General-purpose input/output port External ready input pin General-purpose input/output ports Output pins of PPG timer Output pin of PPG timer Output pin of PPG timer SGO SGO output pin of sound generator P16_6 General-purpose input/output port PPG14 I/O A - PPG15 Output pin of PPG timer Pulse frequency modulator output pin General-purpose input/output port I/O A - Output pin of PPG timer ATGX A/D converter external trigger input pin P23_0 General-purpose input/output port RX0 I/O A - P23_1 TX0 RX1 P23_3 TX1 SDA0 INT14 DS705-00001-2v1-E RX input/output pin of CAN0 External interrupt input pin I/O A - General-purpose input/output port TX output pin of CAN0 General-purpose input/output port I/O A - RX input/output pin of CAN1 External interrupt input pin I/O A - P22_4 60 General-purpose input/output port General-purpose input/output port INT9 59 External write strobe output pins P16_5 P23_2 58 General-purpose input/output ports SGA output pin of sound generator INT8 57 Chip select output pins SGA P16_7 56 General-purpose input/output ports General-purpose input/output port PFM 53 Function General-purpose input/output port TX output pin of CAN1 General-purpose input/output port I/O C - I2C bus DATA input/output pin (open drain) External interrupt input pin 11 MB91460T Series Pin no. 61 Pin name P22_5 SCL0 I/O I/O circuit type* MUX I/O C - P22_6 62 SDA1 P22_7 SCL1 I/O C - I/O C - I/O A - External trigger input pins of reload timer General-purpose input/output ports I/O A - TOT0 to TOT3 Output compare output pins Reload timer output pins 74 MD_0 I G - Mode setting pin 75 MD_1 I G - Mode setting pin 76 MD_2 I G - Mode setting pin 77 MONCLK O M - Clock Monitor pin 78 MD_3 I G - Fast clock input pin 79 X1 - J1 - Clock (oscillation) output 80 X0 - J1 - Clock (oscillation) input 82 X0A - J2 - Sub clock (oscillation) input 83 X1A - J2 - Sub clock (oscillation) output 84 INITX I H - External reset input pin 85 NMIX I H - Non-maskable interrupt input pin I/O A - I/O A - 92 93 P19_0 SIN4 P19_1 SOT4 P19_2 94 SCK4 95 P19_4 SIN5 General-purpose input/output port Data input pin of USART4 General-purpose input/output port Data output pin of USART4 General-purpose input/output port I/O A - CK4 12 I2C bus clock input/output pin (open drain) External trigger input pins of PPG timer P15_0 to P15_3 OCU0 to OCU3 General-purpose input/output port Input capture input pins TTG8/0 to TTG11/3 68 to 71 I2C bus DATA input/output pin (open drain) General-purpose input/output ports ICU0 to ICU3 TIN0 to TIN3 I2C bus clock input/output pin (open drain) External interrupt input pin P14_0 to P14_3 64 to 67 General-purpose input/output port General-purpose input/output port INT15 63 Function Clock input/output pin of USART4 External clock input pin of free-run timer 4 I/O A - General-purpose input/output port Data input pin of USART5 DS705-00001-2v1-E MB91460T Series Pin no. 96 Pin name P19_5 SOT5 I/O I/O circuit type* MUX I/O A - Function General-purpose input/output port Data output pin of USART5 P19_6 97 SCK5 General-purpose input/output port I/O A - Clock input/output pin of USART5 CK5 External clock input pin of free-run timer 5 P18_0 98 SIN6 General-purpose input/output port I/O A - Data input pin of USART6 AIN2 Up/down counter input pin P18_1 99 SOT6 General-purpose input/output port I/O A - Data output pin of USART6 BIN2 Up/down counter input pin P18_2 100 SCK6 ZIN2 General-purpose input/output port I/O A Clock input/output pin of USART6 - Up/down counter input pin CK6 External clock input pin of free-run timer 6 P18_4 101 SIN7 General-purpose input/output port I/O A - Data input pin of USART7 AIN3 Up/down counter input pin P18_5 102 SOT7 General-purpose input/output port I/O A - Data output pin of USART7 BIN3 Up/down counter input pin P18_6 103 SCK7 ZIN3 General-purpose input/output port I/O A Clock input/output pin of USART7 - Up/down counter input pin CK7 104 P17_5 PPG5 P35_0 SIN8 External clock input pin of free-run timer 7 General-purpose input/output port I/O A - I/O B PPMUX.PS5=0 110 Output pin of PPG timer General-purpose input/output port Data input pin of USART8 OR P29_0 AN0 DS705-00001-2v1-E I/O B PPMUX.PS5=1 General-purpose input/output port Analog input pin of A/D converter 13 MB91460T Series Pin no. Pin name P35_1 SOT8 I/O I/O circuit type* MUX I/O B PPMUX.PS5=0 111 AN1 P35_2 SCK8 I/O B PPMUX.PS5=1 I/O B PPMUX.PS5=0 112 Data output pin of USART8 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Clock input/output pin of USART8 OR P29_2 AN2 P35_4 SIN9 I/O B PPMUX.PS5=1 I/O B PPMUX.PS5=0 113 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Data input pin of USART9 OR P29_3 AN3 P35_5 SOT9 I/O B PPMUX.PS5=1 I/O B PPMUX.PS5=0 114 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Data output pin of USART9 OR P29_4 AN4 P35_6 SCK9 I/O B PPMUX.PS5=1 I/O B PPMUX.PS5=0 115 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port Clock input/output pin of USART9 OR P29_5 AN5 P29_6, P29_7 AN6, AN7 I/O B PPMUX.PS5=1 I/O B - I/O B PPMUX.PS2=0 and PPMUX.PR0=0 P24_0 to P24_3 INT0 to INT3 118 to 121 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports External interrupt input pins OR P28_0 to P28_3 AN8 to AN11 14 General-purpose input/output port OR P29_1 116, 117 Function I/O B PPMUX.PS2=1 or PPMUX.PR0=1 General-purpose input/output ports Analog input pins of A/D converter DS705-00001-2v1-E MB91460T Series Pin no. Pin name I/O I/O circuit type* MUX D PPMUX.PS2=0 and PPMUX.PR0=0 P24_4 INT4 I/O SDA2 122 Function General-purpose input/output port External interrupt input pin I2C bus DATA input/output pin (open drain) OR P28_4 AN12 I/O D PPMUX.PS2=1 or PPMUX.PR0=1 D PPMUX.PS2=0 and PPMUX.PR0=0 P24_5 INT5 I/O SCL2 123 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port External interrupt input pin I2C bus clock input/output pin (open drain) OR P28_5 AN13 I/O D PPMUX.PS2=1 or PPMUX.PR0=1 D PPMUX.PS2=0 and PPMUX.PR0=0 P24_6 INT6 I/O SDA3 124 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port External interrupt input pin I2C bus DATA input/output pin (open drain) OR P28_6 AN14 I/O D PPMUX.PS2=1 or PPMUX.PR0=1 C PPMUX.PS2=0 and PPMUX.PR0=0 P24_7 INT7 I/O SCL3 125 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output port External interrupt input pin I2C bus clock input/output pin (open drain) OR P28_7 AN15 I/O B P16_0, P16_1 PPG8, PPG9 I/O A 128, 129 PPMUX.PS2=1 or PPMUX.PR0=1 General-purpose input/output port Analog input pin of A/D converter General-purpose input/output ports PPMUX.PS1=0 and_not (PPMUX.PR11=1 Output pins of PPG timer and PPMUX.PRPS0=1) OR P27_0, P27_1 AN16, AN17 DS705-00001-2v1-E I/O A General-purpose input/output ports PPMUX.PS1=1 or (PPMUX.PR11=1 Analog input pins of A/D converter and PPMUX.PRPS0=1) 15 MB91460T Series Pin no. Pin name I/O I/O circuit type* P20_0 SIN2 I/O A AIN0 130 Function General-purpose input/output port PPMUX.PS1=0 and_not Data input pin of USART2 (PPMUX.PR12=1 and Up/down counter input pin PPMUX.PRPS0=1) OR A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR12=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) A PPMUX.PS1=0 General-purpose input/output port and_not (PPMUX.PR13=1 and Data output pin of USART2 PPMUX.PRPS0=1) Up/down counter input pin P27_2 AN18 I/O P20_1 I/O SOT2 131 MUX BIN0 OR A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR13=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) A PPMUX.PS1=0 and_not (PPMUX.PR14=1 and PPMUX.PRPS0=1) P27_3 AN19 I/O P20_2 SCK2 ZIN0 I/O CK2 132 Clock input/output pin of USART2 Up/down counter input pin External clock input pin of free-run timer 2 OR A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR14=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) A General-purpose input/output port PPMUX.PS1=0 and_not Data input pin of USART3 (PPMUX.PR15=1 and Up/down counter input pin PPMUX.PRPS0=1) P27_4 AN20 I/O P20_4 SIN3 I/O AIN1 OR 133 P27_5 AN21 16 General-purpose input/output port I/O A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR15=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) DS705-00001-2v1-E MB91460T Series Pin no. Pin name I/O I/O circuit type* P20_5 SOT3 I/O A BIN1 MUX Function General-purpose input/output port PPMUX.PS1=0 and_not Data output pin of USART3 (PPMUX.PR16=1 and Up/down counter input pin PPMUX.PRPS0=1) OR 134 A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR16=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) A PPMUX.PS1=0 and_not (PPMUX.PR17=1 and PPMUX.PRPS0=1) P27_6 AN22 I/O P20_6 SCK3 ZIN1 I/O CK3 135 General-purpose input/output port Clock input/output pin of USART3 Up/down counter input pin External clock input pin of free-run timer 3 OR P27_7 AN23 I/O A General-purpose input/output port PPMUX.PS1=1 or (PPMUX.PR17=1 Analog input pin of A/D converter and PPMUX.PRPS0=1) P07_0 to P07_7 A0 to A7 General-purpose input/output ports I/O A PPMUX.PS0=0 136 to 143 Signal pins of external address bus (bit0 to bit7) OR P26_0 to P26_7 AN24 to AN31 I/O A PPMUX.PS0=1 General-purpose input/output ports Analog input pins of A/D converter * : For information about the I/O circuit type, refer to ■ “I/O CIRCUIT TYPES” on page 19. DS705-00001-2v1-E 17 MB91460T Series [Power supply/Ground pins] Pin no. Pin name I/O Function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 VSS5 18, 36, 144 VDD35 Power supply pins for external data bus 54, 72, 90, 108, 126 VDD5 Power supply pins 88, 89 VDD5R 105 AVSS5 Analog ground pin for A/D converter 107 AVCC5 Power supply pin for A/D converter 106 AVRH5 Reference power supply pin for A/D converter 87 VCC18C Capacitor connection pin for internal regulator 18 Ground pins Supply Power supply pins for internal regulator DS705-00001-2v1-E MB91460T Series ■ I/O CIRCUIT TYPES Type Circuit A Remarks pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown B pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input DS705-00001-2v1-E 19 MB91460T Series Type Circuit C Remarks pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown D pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input 20 DS705-00001-2v1-E MB91460T Series Type Circuit E Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown F pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input DS705-00001-2v1-E 21 MB91460T Series Type Circuit Remarks G R Hysteresis inputs H Mask ROM and EVA device: CMOS Hysteresis input pin Flash device: CMOS input pin 12 V withstand (for MD [2:0]) CMOS Hysteresis input pin Pull-up resistor value: 50 kΩ approx. Pull-up Resistor R Hysteresis inputs J1 X1 R 0 Xout 1 High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode. FCI R X0 FCI or osc disable J2 Xout X1A Low-speed oscillation circuit: • Feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled. R R X0A osc disable 22 DS705-00001-2v1-E MB91460T Series Type Circuit K Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. LCD SEG/COM output R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown LCD SEG/COM L pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input LCD Voltage input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown VLCD DS705-00001-2v1-E 23 MB91460T Series Type Circuit Remarks M CMOS level tri-state output (IOL = 5mA, IOH = -5mA) tri-state control data line N Analog input pin with protection analog input line 24 DS705-00001-2v1-E MB91460T Series ■ PORT MULTIPLEXING 1. PPMUX Register MB91F467TA and MB91F469TA use port multiplexing. This means that there are more implemented resources than actual pins. Which ports/resources are multiplexed to which pin depends on the PPMUX register setting. 0x049A 0x049B 15 14 13 12 11 10 9 8 PR17 PR16 PR15 PR14 PR13 PR12 PR11 PR10 7 6 5 4 3 2 1 0 PRPS0 PR0 PS5 PS4 PS3 PS2 PS1 PS0 The PPMUX register can only be written as a half-word. It is writable only once. The PPMUX register is reset by INIT or by a soft reset (the initial value is 0x0000 then). Note: Port relocation (via PRx) always has higher priority than Port Switching (via PSx). DS705-00001-2v1-E 25 MB91460T Series 2. Multiplex Pinout MB91F467TA, MB91F469TA if ANxx channel is enabled (via PFR & EPFR), pin is switched to analogue input, digital input is then disabled (independant of PPMUX.PS/PR bits) 1 configbit (PPMUX.PS1) to switch between the two port layouts if ANxx channel is enabled (via PFR) pin is switched to analogue input, digital input is then disabled (independant of PPMUX.PS/PR bits) 1 configbit (PPMUX.PS2) to switch between the two port layouts if ANxx channel is enabled (via PFR), pin is switched to analogue input, digital input is then disabled (independant of PPMUX.PS/PR bits) 1 configbit (PPMUX.PS5) to switch between the two port layouts 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD35 P07_7/A7 or P26_7/AN31 P07_6/A6 or P26_6/AN30 P07_5/A5 or P26_5/AN29 P07_4/A4 or P26_4/AN28 P07_3/A3 or P26_3/AN27 P07_2/A2 or P26_2/AN26 P07_1/A1 or P26_1/AN25 P07_0/A0 or P26_0/AN24 P20_6/SCK3/ZIN1/CK3 or P27_7/AN23 P20_5/SOT3/BIN1 or P27_6/AN22 P20_4/SIN3/AIN1 or P27_5/AN21 P20_2/SCK2/ZIN0/CK2 or P27_4/AN20 P20_1/SOT2/BIN0 or P27_3/AN19 P20_0/SIN2/AIN0 or P27_2/AN18 P16_1/PPG9 or P27_1/AN17 P16_0/PPG8 or P27_0/AN16 VSS5 VDD5 P24_7/INT7/SCL3 or P28_7/AN15 P24_6/INT6/SDA3 or P28_6/AN14 P24_5/INT5/SCL2 or P28_5/AN13 P24_4/INT4/SDA2 or P28_4/AN12 P24_3/INT3 or P28_3/AN11 P24_2/INT2 or P28_2/AN10 P24_1/INT1 or P28_1/AN9 P24_0/INT0 or P28_0/AN8 P29_7/AN7 P29_6/AN6 P35_6/SCK9 or P29_5/AN5 P35_5/SOT9 or P29_4/AN4 P35_4/SIN9 or P29_3/AN3 P35_2/SCK8 or P29_2/AN2 P35_1/SOT8 or P29_1/AN1 P35_0/SIN8 or P29_0/AN0 VSS5 1 configbit (PPMUX.PS0) to switch between the two port layouts if ANxx channel is enabled (via PFR & EPFR), pin is switched to analogue input, digital input is then disabled (independant of PPMUX.PS/PR bits) 1 configbit (PPMUX.PS4) to switch between external bus (default) or peripheral function (all 8 pins) 1 configbit (PPMUX.PRPS0) to determine wether PPMUX.PR17 to PPMUX.PR12 relocate pins from P20 or switch Pins to P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 configbyte (PPMUX.PR17 to PPMUX.PR10) to relocate peripheral function (all 8 pins, but not ANxx), external bus functon is disabled when relocated 1 configbit (PPMUX.PR0) to relocate peripheral function (all 8 pins, but not ANxx and not I2C), external bus functon is disabled when relocated VDD5 AVCC5 AVRH5 AVSS5 P17_5/PPG5 P18_6/SCK7/ZIN3/CK7 P18_5/SOT7/BIN3 P18_4/SIN7/AIN3 P18_2/SCK6/ZIN2/CK6 P18_1/SOT6/BIN2 P18_0/SIN6/AIN2 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5 VSS5 P10_0/SYSCLK P10_1/ASX P10_3/WEX P09_0/CSX0 P09_1/CSX1 P09_2/CSX2 P08_0/WRX0 P08_1/WRX1 P08_4/RDX P08_7/RDY P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14/PFM P16_7/PPG15/AGTX VDD5 VSS5 P23_0/RX0/INT8 P23_1/TX0 P23_2/RX1/INT9 P23_3/TX1 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P14_0/ICU0/TIN0/TTG8/0 P14_1/ICU1/TIN1/TTG9/1 P14_2/ICU2/TIN2/TTG10/2 P14_3/ICU3/TIN3/TTG11/3 P15_0/OCU0/TOT0 P15_1/OCU1/TOT1 P15_2/OCU2/TOT2 P15_3/OCU3/TOT3 VDD5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 configbit (PPMUX.PS3) to switch between external bus (default) or peripheral function (all 8 pins) VSS5 P06_0/A8 or P21_0/SIN0 P06_1/A9 or P21_1/SOT0 P06_2/A10 or P21_2/SCK0/CK0 P06_3/A11 or P17_4/PPG4 P06_4/A12 or P14_4/ICU4/TIN4/TTG12/4 P06_5/A13 or P14_5/ICU5/TIN5/TTG13/5 P06_6/A14 or P14_6/ICU6/TIN6/TTG14/6 P06_7/A15 or P14_7/ICU7/TIN7/TTG15/7 P05_0/A16 or P16_0/PPG8 P05_1/A17 or P16_1/PPG9 P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10) P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10) P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10) P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11) P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11) P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11) VDD35 VSS5 P01_0/D16 or P17_0/PPG0 P01_1/D17 or P17_1/PPG1 P01_2/D18 or P17_2/PPG2 P01_3/D19 or P17_3/PPG3 P01_4/D20 or P15_4/OCU4/TOT4 P01_5/D21 or P15_5/OCU5/TOT5 P01_6/D22 or P15_6/OCU6/TOT6 P01_7/D23 or P15_7/OCU7/TOT7 P00_0/D24 or P24_0/INT0 P00_1/D25 or P24_1/INT1 P00_2/D26 or P24_2/INT2 P00_3/D27 or P24_3/INT3 P00_4/D28 or P24_4/INT4 P00_5/D29 or P24_5/INT5 P00_6/D30 or P24_6/INT6 P00_7/D31 or P24_7/INT7 VDD35 26 DS705-00001-2v1-E MB91460T Series ■ HANDLING DEVICES 1. Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35) or less than (VSS5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. 2. Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly. 3. Power supply pins In MB91460T series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460T series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic capacitor) to VCC18C pin for the regulator. 4. Crystal oscillator circuit Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. 5. Notes on using external clock When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued) DS705-00001-2v1-E 27 MB91460T Series (Continued) Example of using opposite phase supply X0 (X0A) X1 (X1A) 6. Mode pins (MD_x) These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. 7. Notes on operating in PLL clock mode If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed. 8. Pull-up control The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin. 9. Notes on PS register As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. • The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. D0 and D1 flags are updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1. • The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. 1. The PS register is updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1. 28 DS705-00001-2v1-E MB91460T Series ■ NOTES ON DEBUGGER 1. Execution of the RETI Command If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 2. Break function If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks). 3. Operand break It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break. DS705-00001-2v1-E 29 MB91460T Series ■ BLOCK DIAGRAM 1. MB91F467TA, MB91F469TA FR60 CPU core WATCHDOG D-RAM Flash-Cache 8 Kbytes (MB91F467TA) 16 Kbytes (MB91F469TA) I-bus 32 32 Kbytes (MB91F467TA) 64 Kbytes (MB91F469TA) Bit search Flash memory 1088 Kbytes (MB91F467TA) 2112 Kbytes (MB91F469TA) D-bus 32 CAN 2 channels RX0 to RX1 TX0 to TX1 32 <-> 16 bus adapter ID-RAM 32 Kbytes (MB91F467TA) 64 Kbytes (MB91F469TA) External bus interface Bus converter WEX ASX RDX WRX0 to WRX1 CSX0 to CSX2 A0 to A23 D16 to D31 R-bus 16 Clock modulator Clock supervisor Clock control TTG0/8 to TTG7/15 PPG0 to PPG5, PPG8 to PPG15 PPG timer 14 channels TIN0 to TIN7 TOT0 to TOT7 Reload timer 8 channels CK0, CK2 to CK7 ICU0 to ICU7 Free-run timer 8 channels Input capture 8 channels Clock monitor MONCLK Interrupt controller External interrupt 12 channels INT0 to INT7, INT8, INT9, INT14, INT15 GPIO LIN-USART 11 channels SIN0,SIN2 to SIN7 SOT0,SOT2 to SOT7 SCK0,SCK2 to SCK7 I2C 4 channels SDA0 to SDA3 SCL0 to SCL3 Real time clock OCU0 to OCU3 AIN0 to AIN3 BIN0 to BIN3 ZIN0 to ZIN3 PFM 30 Output compare 8 channels Up/down counter 4 channels PFM timer 1 channel AN0 to AN31 A/D converter 32 channels ATGX Sound generator 1 channel SGA SG0 NMI 1 channel DS705-00001-2v1-E MB91460T Series ■ CPU AND CONTROL UNIT The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications. 1. Features • Adoption of RISC architecture Basic instruction: 1 instruction per cycle • General-purpose registers: 32-bit × 16 registers • 4 Gbytes linear memory space • Multiplier installed 32-bit × 32-bit multiplication: 5 cycles 16-bit × 16-bit multiplication: 3 cycles • Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) • Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction Basic instruction word length: 16 bits • Low-power consumption Sleep mode/stop mode 2. Internal architecture • The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. • A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. • A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. DS705-00001-2v1-E 31 MB91460T Series 3. Programming model 3.1. Basic programming model 32 bits Initial value R0 XXXX XXXXH R1 ... General-purpose registers ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Program counter PC Program status RS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiply & divide registers MDH ILM SCR CCR MDL 32 DS705-00001-2v1-E MB91460T Series 4. Registers 4.1. General-purpose register 32 bits Initial value R0 XXXX XXXXH ... R1 ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). 4.2. PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid. Bit position → bit 31 bit 20 bit 16 ILM DS705-00001-2v1-E bit 10 bit 8 bit 7 SCR bit 0 CCR 33 MB91460T Series 4.3. CCR (Condition Code Register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SV S I N Z V C Initial value - 000XXXXB SV : Supervisor flag S : Stack flag I : Interrupt enable flag N : Negative enable flag Z : Zero flag V : Overflow flag C : Carry flag 4.4. SCR (System Condition Register) bit 10 bit 9 D1 bit 8 D0 Initial value T XX0B Flag for step division (D1, D0) This flag stores interim data during execution of step division. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. 4.5. ILM (Interrupt Level Mask register) bit 20 bit 19 bit 18 bit 17 bit 16 Initial value ILM4 ILM3 ILM2 ILM1 ILM0 01111B This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value “01111B” at reset. 4.6. PC (Program Counter) bit 31 bit 0 Initial value XXXXXXXXH The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. 34 DS705-00001-2v1-E MB91460T Series 4.7. TBR (Table Base Register) bit 0 Initial value bit 31 000FFC00H The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. 4.8. RP (Return Pointer) bit 31 bit 0 Initial value XXXXXXXXH The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. 4.9. USP (User Stack Pointer) bit 31 bit 0 Initial value XXXXXXXXH The user stack pointer, when the S flag is “1”, this register functions as the R15 register. • The USP register can also be explicitly specified. The initial value at reset is undefined. • This register cannot be used with RETI instructions. 4.10. Multiply & divide registers bit 31 bit 0 MDH MDL These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined. DS705-00001-2v1-E 35 MB91460T Series ■ EMBEDDED PROGRAM/DATA MEMORY (FLASH) 1. Flash features • • • • • • • MB91F467TA: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes = 8.5 Mbits) MB91F469TA: 2112 Kbytes (32 × 64 Kbytes + 8 × 8 Kbytes = 16.5 Mbits) Programmable wait state for read/write access MB91F467TA: Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F MB91F469TA: Flash and Boot security with security vector at 0x0024:8000 - 0x0024:800F Boot security Basic specification: Same as MBM29LV400TC (except size and part of sector configuration) 2. Operation modes (1) 64-bit CPU mode: • CPU reads and executes programs in word (32-bit) length units. • Flash writing is not possible. • Actual Flash Memory access is performed in d-word (64-bit) length units. (2) 32-bit CPU mode : • CPU reads, writes and executes programs in word (32-bit) length units. • Actual Flash Memory access is performed in word (32-bit) length units. (3) 16-bit CPU mode : • CPU reads and writes in half-word (16-bit) length units. • Program execution from the Flash is not possible. • Actual Flash Memory access is performed in half-word (16-bit) length units. Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access Mode Switching". 36 DS705-00001-2v1-E MB91460T Series 3. Flash access in CPU mode 3.1. Flash configuration 3.1.1. Flash memory map MB91F467TA Address 0014:FFFFh 0014:C000h SA6 (8KB) SA7 (8KB) 0014:BFFFh 0014:8000h SA4 (8KB) SA5 (8KB) 0014:7FFFh 0014:4000h SA2 (8KB) SA3 (8KB) 0014:3FFFh 0014:0000h SA0 (8KB) SA1 (8KB) 0013:FFFFh 0012:0000h SA22 (64KB) SA23 (64KB) 0011:FFFFh 0010:0000h SA20 (64KB) SA21 (64KB) 000F:FFFFh 000E:0000h SA18 (64KB) SA19 (64KB) ROMS5 000D:FFFFh 000C:0000h SA16 (64KB) SA17 (64KB) ROMS4 000B:FFFFh 000A:0000h SA14 (64KB) SA15 (64KB) ROMS3 0009:FFFFh 0008:0000h SA12 (64KB) SA13 (64KB) ROMS2 0007:FFFFh 0006:0000h SA10 (64KB) SA11 (64KB) ROMS1 0005:FFFFh 0004:0000h SA8 (64KB) SA9 (64KB) ROMS0 ROMS7 ROMS6 addr+0 16bit read/write 32bit read/write 64bit read DS705-00001-2v1-E addr+1 addr+2 dat[31:16] addr+3 addr+4 dat[15:0] addr+5 addr+6 dat[31:16] dat[31:0] addr+7 dat[15:0] dat[31:0] dat[63:0] 37 MB91460T Series 3.1.2. Flash memory map MB91F469TA Address 0024:FFFFh 0024:C000h SA6 (8KB) SA7 (8KB) 0024:BFFFh 0024:8000h SA4 (8KB) SA5 (8KB) 0024:7FFFh 0024:4000h SA2 (8KB) SA3 (8KB) 0024:3FFFh 0024:0000h SA0 (8KB) SA1 (8KB) 0023:FFFFh 0022:0000h SA38 (64KB) SA39 (64KB) 0021:FFFFh 0020:0000h SA36 (64KB) SA37 (64KB) 001F:FFFFh 001E:0000h SA34 (64KB) SA35 (64KB) 001D:FFFFh 001C:0000h SA32 (64KB) SA33 (64KB) 001B:FFFFh 001A:0000h SA30 (64KB) SA31 (64KB) ROMS10 ROMS9 ROMS8 0019:FFFFh 0018:0000h SA28 (64KB) SA29 (64KB) 0017:FFFFh 0016:0000h SA26 (64KB) SA27 (64KB) ROMS7 0015:FFFFh 0014:0000h SA24 (64KB) SA25 (64KB) 0013:FFFFh 0012:0000h SA22 (64KB) SA23 (64KB) ROMS6 0011:FFFFh 0010:0000h SA20 (64KB) SA21 (64KB) 000F:FFFFh 000E:0000h SA18 (64KB) SA19 (64KB) ROMS5 000D:FFFFh 000C:0000h SA16 (64KB) SA17 (64KB) ROMS4 000B:FFFFh 000A:0000h SA14 (64KB) SA15 (64KB) ROMS3 0009:FFFFh 0008:0000h SA12 (64KB) SA13 (64KB) ROMS2 0007:FFFFh 0006:0000h SA10 (64KB) SA11 (64KB) ROMS1 0005:FFFFh 0004:0000h SA8 (64KB) SA9 (64KB) ROMS0 addr+0 16bit write mode 32bit write mode 38 addr+1 addr+2 dat[31:16] addr+3 dat[15:0] dat[31:0] addr+4 addr+5 addr+6 dat[31:16] addr+7 dat[15:0] dat[31:0] DS705-00001-2v1-E MB91460T Series 3.2. Flash access timing settings in CPU mode The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access. 3.2.1. Flash read timing settings for MB91F467TA (synchronous read) Core clock (CLKB) ATD ALEH EQ WEXH WTC to 24 MHz 0 0 0 - 1 to 48 MHz 0 0 1 - 2 to 100 MHz 1 1 3 - 4 3.2.2. Flash write timing settings for MB91F467TA (synchronous write) Core clock (CLKB) ATD ALEH EQ WEXH WTC to 16 MHz 0 - - 0 3 to 32 MHz 0 - - 0 4 to 48 MHz 0 - - 0 5 to 64 MHz 1 - - 0 6 to 96 MHz 1 - - 0 7 to 100 MHz 1 - - 1 8 3.2.3. Flash read timing settings for MB91F469TA (synchronous read) Core clock (CLKB) ATD ALEH EQ WEXH WTC Flash/Main supply voltage to 24 MHz 0 0 0 - 1 1.9V *1 to 48 MHz 0 0 1 - 2 1.9V *1 to 100 MHz 1 1 3 - 4 1.9V *1 *1: In order to enter this mode, please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1. 3.2.4. Flash write timing settings for MB91F469TA (synchronous write) Core clock (CLKB) ATD ALEH EQ WEXH WTC Flash/Main supply voltage to 16 MHz 0 - - 0 3 1.9V *1 to 32 MHz 0 - - 0 4 1.9V *1 to 48 MHz 0 - - 0 5 1.9V *1 to 64 MHz 1 - - 0 6 1.9V *1 to 96 MHz 1 - - 0 7 1.9V *1 to 100 MHz 1 - - 1 8 1.9V *1 *1: In order to enter this mode, please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1. DS705-00001-2v1-E 39 MB91460T Series 3.3. Address mapping from CPU to parallel programming mode The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming. 3.3.1. Address mapping MB91F467TA CPU Address Condition (addr) Flash sectors FA (flash address) Calculation 14:0000h to 14:FFFFh addr[2]==0 SA0, SA2, SA4, SA6 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 14:0000h to 14:FFFFh addr[2]==1 SA1, SA3, SA5, SA7 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 05:0000h 04:0000h to 13:FFFFh addr[2]==0 SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22 (64 Kbyte) FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h 04:0000h to 13:FFFFh addr[2]==1 SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23 (64 Kbyte) FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 + 0C:0000h Note: FA result is without 20:0000h offset for parallel Flash programming. Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”. 3.3.2. Address mapping MB91F469TA CPU Address Condition (addr) Flash sectors FA (flash address) Calculation 24:0000h to 24:FFFFh addr[2]==0 SA0, SA2, SA4, SA6 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 24:0000h to 24:FFFFh addr[2]==1 SA1, SA3, SA5, SA7 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h + 00:2000h addr[2]==0 SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22, SA24, SA26, SA28, SA30, SA32, SA34, SA36, SA38 (64 Kbyte) FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 1C:0000h addr[2]==1 SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23, SA25, SA27, SA29, SA31, SA33, SA35, SA37, SA39 (64 Kbyte) FA := addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 1C:0000h + 01:0000h 04:0000h to 23:FFFFh 04:0000h to 23:FFFFh Note: FA result is without 40:0000h offset for parallel Flash programming . Set offset by keeping FA[22] = 1 as described in section “Parallel Flash programming mode”. 40 DS705-00001-2v1-E MB91460T Series 4. Parallel Flash programming mode 4.1. Flash configuration in parallel Flash programming mode Parallel Flash programming mode (MD[2:0] = 111): MB91F467TA FA[21:0] 003F:FFFFh 003F:0000h SA23 (64KB) 003E:FFFFh 003E:0000h SA22 (64KB) 003D:FFFFh 003D:0000h SA21 (64KB) 003C:FFFFh 003C:0000h SA20 (64KB) 003B:FFFFh 003B:0000h SA19 (64KB) 003A:FFFFh 003A:0000h SA18 (64KB) 0039:FFFFh 0039:0000h SA17 (64KB) 0038:FFFFh 0038:0000h SA16 (64KB) 0037:FFFFh 0037:0000h SA15 (64KB) 0036:FFFFh 0036:0000h SA14 (64KB) 0035:FFFFh 0035:0000h SA13 (64KB) 0034:FFFFh 0034:0000h SA12 (64KB) 0033:FFFFh 0033:0000h SA11 (64KB) 0032:FFFFh 0032:0000h SA10 (64KB) 0031:FFFFh 0031:0000h SA9 (64KB) 0030:FFFFh 0030:0000h SA8 (64KB) 002F:FFFFh 002F:E000h SA7 (8KB) 002F:DFFFh 002F:C000h SA6 (8KB) 002F:BFFFh 002F:A000h SA5 (8KB) 002F:9FFFh 002F:8000h SA4 (8KB) 002F:7FFFh 002F:6000h SA3 (8KB) 002F:5FFFh 002F:4000h SA2 (8KB) 002F:3FFFh 002F:2000h SA1 (8KB) 002F:1FFFh 002F:0000h SA0 (8KB) 16bit write mode FA[1:0]=00 FA[1:0]=10 DQ[15:0] DQ[15:0] DS705-00001-2v1-E 41 MB91460T Series MB91F469TA FA[21:0] 42 003F:FFFFh 003F:0000h SA39 (64KB) 002A:FFFFh 002A:0000h SA18 (64KB) 003E:FFFFh 003E:0000h SA38 (64KB) 0029:FFFFh 0029:0000h SA17 (64KB) 003D:FFFFh 003D:0000h SA37 (64KB) 0028:FFFFh 0028:0000h SA16 (64KB) 003C:FFFFh 003C:0000h SA36 (64KB) 0027:FFFFh 0027:0000h SA15 (64KB) 003B:FFFFh 003B:0000h SA35 (64KB) 0026:FFFFh 0026:0000h SA14 (64KB) 003A:FFFFh 003A:0000h SA34 (64KB) 0025:FFFFh 0025:0000h SA13 (64KB) 0039:FFFFh 0039:0000h SA33 (64KB) 0024:FFFFh 0024:0000h SA12 (64KB) 0038:FFFFh 0038:0000h SA32 (64KB) 0023:FFFFh 0023:0000h SA11 (64KB) 0037:FFFFh 0037:0000h SA31 (64KB) 0022:FFFFh 0022:0000h SA10 (64KB) 0036:FFFFh 0036:0000h SA30 (64KB) 0021:FFFFh 0021:0000h SA9 (64KB) 0035:FFFFh 0035:0000h SA29 (64KB) 0020:FFFFh 0020:0000h SA8 (64KB) 0034:FFFFh 0034:0000h SA28 (64KB) 001F:FFFFh 001F:E000h SA7 (8KB) 0033:FFFFh 0033:0000h SA27 (64KB) 001F:DFFFh 001F:C000h SA6 (8KB) 0032:FFFFh 0032:0000h SA26 (64KB) 001F:BFFFh 001F:A000h SA5 (8KB) 0031:FFFFh 0031:0000h SA25 (64KB) 001F:9FFFh 001F:8000h SA4 (8KB) 0030:FFFFh 0030:0000h SA24 (64KB) 001F:7FFFh 001F:6000h SA3 (8KB) 002F:FFFFh 002F:0000h SA23 (64KB) 001F:5FFFh 001F:4000h SA2 (8KB) 002E:FFFFh 002E:0000h SA22 (64KB) 001F:3FFFh 001F:2000h SA1 (8KB) 002D:FFFFh 002D:0000h SA21 (64KB) 001F:1FFFh 001F:0000h SA0 (8KB) 002C:FFFFh 002C:0000h SA20 (64KB) 002B:FFFFh 002B:0000h SA19 (64KB) 16bit write mode FA[1:0]=00 FA[1:0]=10 DQ[15:0] DQ[15:0] Remark: Always keep FA[0] = 0 and FA[22] = 1 DS705-00001-2v1-E MB91460T Series 4.2. Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory’s Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MBM29LV400T MB91F467TA external pins C FR-CPU mode Flash memory Normal function Pin number mode External pins Comment - INITX - INITX 84 RESET - FRSTX NMIX 85 - - MD_2 MD_2 76 Set to ‘1’ - - MD_1 MD_1 75 Set to ‘1’ - - MD_0 MD_0 74 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX GP19_0 92 BYTE Internally fixed to ‘H’ BYTEX GP19_2 94 WE WEX GP18_0 98 OE OEX GP19_6 97 CEX GP19_5 96 ATDIN MD03 78 Set to ‘0’ EQIN MONCLK 77 Set to ‘0’ - TESTX GP19_4 95 Set to ‘1’ - RDYI GP19_1 93 Set to ‘0’ A-1 FA0 GP17_5 104 Set to ‘0’ A0 to A3 FA1 to FA4 GP06_0 to GP06_3 2 to 5 A4 to A7 FA5 to FA8 GP06_4 to GP06_7 6 to 9 FA9 to FA12 GP05_0 to GP05_3 10 to 13 FA13 to FA16 GP05_4 to GP05_7 14 to 17 A16 to A19 FA17 to FA20 GP18_1, GP18_2, GP18_4, GP18_5 99 to 102 - FA21 GP18_6 103 DQ0 to DQ7 GP01_0 to GP01_7 20 to 27 DQ8 to DQ15 GP00_0 to GP00_7 28 to 35 CE - A8 to A11 A12 to A15 Internal control signal + control via interface circuit Internal address bus DQ0 to DQ7 DQ8 to DQ15 Internal data bus DS705-00001-2v1-E Set to ‘1’ 43 MB91460T Series MBM29LV400TC MB91F469TA external pins FR-CPU mode Flash memory mode Normal function Pin number - INITX - INITX 84 RESET - FRSTX NMIX 85 - - MD_2 MD_2 76 Set to ‘1’ - - MD_1 MD_1 75 Set to ‘1’ - - MD_0 MD_0 74 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX GP19_0 92 BYTE Internally fixed to ‘H’ BYTEX GP19_2 94 WE WEX GP18_0 98 OE OEX GP19_6 97 CEX GP19_5 96 ATDIN MD03 78 Set to ‘0’ EQIN MONCLK 77 Set to ‘0’ - TESTX GP19_4 95 Set to ‘1’ - RDYI GP19_1 93 Set to ‘0’ A-1 FA0 GP17_5 104 Set to ‘0’ A0 to A7 FA1 to FA8 GP06_0 to GP06_7 2 to 9 A8 to A15 FA9 to FA16 GP05_0 to GP05_7 10 to 17 A16 to A19 FA17 to FA21 GP18_1, GP18_2, GP18_4, GP18_5, GP18_6 99 to 103 - FA22 GP35_0 110 DQ0 to DQ7 DQ0 to DQ7 GP01_0 to GP01_7 20 to 27 DQ8 to DQ15 GP00_0 to GP00_7 28 to 35 External pins CE - Internal control signal + control via interface circuit Internal address bus DQ8 to DQ15 44 Internal data bus Comment Set to ‘1’ DS705-00001-2v1-E MB91460T Series 5. Poweron Sequence in parallel programming mode The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: • Minimum wait time after VDD5/VDD5R power on: • Minimum wait time after INITX rising: 2.76 ms 1.0 ms 6. Flash Security 6.1. Vector addresses Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: For MB91F467TA: FSV1: 0x14:8000 FSV2: 0x14:8008 BSV1: 0x14:8004 BSV2: 0x14:800C For MB91F469TA: FSV1: 0x24:8000 FSV2: 0x24:8008 6.2. BSV1: 0x24:8004 BSV2: 0x24:800C Security Vector FSV1 The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 Kbytes sectors. 6.2.1. FSV1 (bit31 to bit16) The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1 [31:16] FSV1[18] FSV1[17] FSV1[16] FSV1[31:19] Write Protection Write Protection Read Protection Level Flash Security Mode set all to “0” set to “0” set to “0” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set all to “0” set to “0” set to “1” set to “0” Write Protection (all device modes, without exception) set all to “0” set to “0” set to “1” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes) set all to “0” set to “1” set to “0” set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set all to “0” set to “1” set to “1” set to “0” Write Protection (all device modes, except INTVEC mode MD[2:0] = “000”) set to “1” Read Protection (all device modes, except INTVEC mode MD[2:0] = “000”) and Write Protection (all device modes except INTVEC mode MD[2:0] = “000”) set all to “0” DS705-00001-2v1-E set to “1” set to “1” 45 MB91460T Series 6.2.2. FSV1 (bit15 to bit0) The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV1 [15:0] Enable Write Disable Write FSV1 bit Sector Protection Protection Comment FSV1[0] SA0 set to “0” set to “1” FSV1[1] SA1 set to “0” set to “1” FSV1[2] SA2 set to “0” set to “1” FSV1[3] SA3 set to “0” set to “1” FSV1[4] SA4 set to “0” ⎯ FSV1[5] SA5 set to “0” set to “1” FSV1[6] SA6 set to “0” set to “1” FSV1[7] SA7 set to “0” set to “1” FSV1[8] ⎯ set to “0” set to “1” not available FSV1[9] ⎯ set to “0” set to “1” not available FSV1[10] ⎯ set to “0” set to “1” not available FSV1[11] ⎯ set to “0” set to “1” not available FSV1[12] ⎯ set to “0” set to “1” not available FSV1[13] ⎯ set to “0” set to “1” not available FSV1[14] ⎯ set to “0” set to “1” not available FSV1[15] ⎯ set to “0” set to “1” not available Write protection is mandatory! Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash content or manipulate data by writing. See section “Flash access in CPU mode” on page 37 for an overview about the sector organization of the Flash Memory. 46 DS705-00001-2v1-E MB91460T Series 6.3. Security Vector FSV2 The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set. Explanation of the bits in the Flash Security Vector FSV2[31:0] Enable Write Disable Write FSV2 bit Sector Protection Protection Comment FSV2[0] SA8 set to “0” set to “1” FSV2[1] SA9 set to “0” set to “1” FSV2[2] SA10 set to “0” set to “1” FSV2[3] SA11 set to “0” set to “1” FSV2[4] SA12 set to “0” set to “1” FSV2[5] SA13 set to “0” set to “1” FSV2[6] SA14 set to “0” set to “1” FSV2[7] SA15 set to “0” set to “1” FSV2[8] SA16 set to “0” set to “1” FSV2[9] SA17 set to “0” set to “1” FSV2[10] SA18 set to “0” set to “1” FSV2[11] SA19 set to “0” set to “1” FSV2[12] SA20 set to “0” set to “1” FSV2[13] SA21 set to “0” set to “1” FSV2[14] SA22 set to “0” set to “1” FSV2[15] SA23 set to “0” set to “1” FSV2[16] SA24 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[17] SA25 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[18] SA26 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[19] SA27 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[20] SA28 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[21] SA29 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[22] SA30 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[23] SA31 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[24] SA32 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[25] SA33 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[26] SA34 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[27] SA35 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[28] SA36 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[29] SA37 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[30] SA38 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA FSV2[31] SA39 (MB91F469TA) set to “0” set to “1” not available in MB91F467TA DS705-00001-2v1-E 47 MB91460T Series Note : See section “Flash access in CPU mode” on page 37 for an overview about the sector organization of the Flash Memory. 48 DS705-00001-2v1-E MB91460T Series 7. Notes About Flash Memory CRC Calculation The Flash Security macro contains a feature to calculate the 32-bit checksum over addresses located in the Flash Memory address space. This feature is described in the MB91460 Series Hardware Manual, chapter 55.4.1 “Flash Security Control Register”. Additional notes are given here: The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the CRC calculation may not start correctly. ■ MEMORY SPACE The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH DS705-00001-2v1-E 49 MB91460T Series ■ MEMORY MAPS 1. MB91F467TA, MB91F469TA MB91F467TA 00000000H 00000400H 00001000H MB91F469TA 00000000H I/O (direct addressing area) I/O DMA 00000400H 00001000H 00002000H 00002000H 00004000H 00006000H Flash-Cache (8 KBytes) 00006000H 00007000H 00007000H Flash memory control I/O (direct addressing area) I/O DMA Flash-Cache (16 KBytes) Flash memory control 00008000H 00008000H 0000B000H 0000B000H 0000C000H Boot ROM (4 Kbytes) 0000C000H CAN 0000D000H Boot ROM (4 Kbytes) CAN 0000D000H 00020000H 00028000H 00030000H D-RAM (0 wait, 32 Kbytes) 00030000H ID-RAM (32 Kbytes) D-RAM (0 wait, 64 Kbytes) ID-RAM (64 Kbytes) 00040000H 00038000H 00040000H Flash memory (2112 Kbytes) Flash memory (1088 Kbytes) 00150000H 00250000H 00180000H 00280000H External bus area 00500000H External bus area 00500000H External data bus FFFFFFFFH Note: External data bus FFFFFFFFH Access prohibited areas Note: 50 Access prohibited areas DS705-00001-2v1-E MB91460T Series ■ I/O MAP 1. MB91F467TA, MB91F469TA Register Address 000000H +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit port data register Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 2) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: “ 1 ” : Initial value “ 1 ” “ 0 ” : Initial value “ 0 ” “ X ” : Initial value “ undefined ” “ - ” : No physical register at this location Access is barred with an undefined data access attribute. DS705-00001-2v1-E 51 MB91460T Series Address Register +0 +1 +2 +3 000000H PDR00 [R/W] XXXXXXXX PDR01 [R/W] XXXXXXXX Reserved Reserved 000004H Reserved PDR05 [R/W] XXXXXXXX PDR06 [R/W] XXXXXXXX PDR07 [R/W] XXXXXXXX 000008H PDR08 [R/W] X - - X - -XX PDR09 [R/W] - - - - - XXX PDR10 [R/W] - - - - X - XX Reserved 00000CH Reserved Reserved PDR14 [R/W] XXXXXXXX PDR15 [R/W] XXXXXXXX 000010H PDR16 [R/W] XXXXXXXX PDR17 [R/W] - - XXXXXX PDR18 [R/W] - XXX - XXX PDR19 [R/W] - XXX - XXX 000014H PDR20 [R/W] - XXX - XXX PDR21 [R/W] - - - - - XXX PDR22 [R/W] XXXX - - - - PDR23 [R/W] - - - - XXXX 000018H PDR24 [R/W] XXXXXXXX Reserved PDR26 [R/W] XXXXXXXX PDR27 [R/W] XXXXXXXX 00001CH PDR28 [R/W] - -XXXXX PDR29 [R/W] XXXXXXXX Reserved Reserved 000020H Reserved Reserved PDR34 [R/W] - XXX - XXX PDR35 [R/W] - XXX - XXX 000024H to 00002CH Block R-bus Port Data Register Reserved 000030H EIRR0 [R/W] XXXXXXXX ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 External Interrupt 0 to 7 NMI 000034H EIRR1 [R/W] XXXXXXXX ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 External Interrupt 8 to 15 000038H DICR [R/W] -------0 HRCL [R/W] 0 - - 11111 Reserved Delay Interrupt 00003CH Reserved 000040H SCR00 [R/W,W] 00000000 SMR00 [R/W,W] 00000000 000044H ESCR00 [R/W] 00000X00 ECCR00 [R/W,R,W] -00000XX 000048H to 00004CH 000050H 000054H 52 SSR00 [R/W,R] 00001000 RDR00/TDR00 [R/W] 00000000 Reserved LIN-USART 0 Reserved SCR02 [R/W,W] 00000000 SMR02 [R/W,W] 00000000 ESCR02 [R/W] 00000X00 ECCR02 [R/W,R,W] -00000XX SSR02 [R/W,R] 00001000 RDR02/TDR02 [R/W] 00000000 LIN-USART 2 Reserved DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 SCR03[R/W,W] 00000000 SMR03 [R/W,W] 00000000 SSR03 [R/W,R] 00001000 RDR03/TDR02 [R/W] 00000000 00005CH ESCR03 [R/W] 00000X00 ECCR03 [R/W,R,W] -00000XX 000060H SCR04 [R/W,W] 00000000 SMR04 [R/W,W] 00000000 SSR04 [R/W,R] 00001000 RDR04/TDR04 [R/W] 00000000 000064H ESCR04 [R/W] 00000X00 ECCR04 [R/W,R,W] -00000XX FSR04 [R] - - - 00000 FCR04 [R/W] 0001 - 000 000068H SCR05 [R/W,W] 00000000 SMR05 [R/W,W] 00000000 SSR05 [R/W,R] 00001000 RDR05/TDR05 [R/W] 00000000 00006CH ESCR05 [R/W] 00000X00 ECCR05 [R/W,R,W] -00000XX FSR05 [R] - - - 00000 FCR05 [R/W] 0001 - 000 000070H SCR06 [R/W,W] 00000000 SMR06 [R/W,W] 00000000 SSR06 [R/W,R] 00001000 RDR06/TDR06 [R/W] 00000000 000074H ESCR06 [R/W] 00000X00 ECCR06 [R/W,R,W] -00000XX FSR06 [R] - - - 00000 FCR06 [R/W] 0001 - 000 000078H SCR07 [R/W,W] 00000000 SMR07 [R/W,W] 00000000 SSR07 [R/W,R] 00001000 RDR07/TDR07 [R/W] 00000000 00007CH ESCR07 [R/W] 00000X00 ECCR07 [R/W,R,W] -00000XX FSR07 [R] - - - 00000 FCR07 [R/W] 0001 - 000 000080H BGR100 [R/W] 00000000 BGR000 [R/W] 00000000 Reserved Reserved 000084H BGR102 [R/W] 00000000 BGR002 [R/W] 00000000 BGR103 [R/W] 00000000 BGR003 [R/W] 00000000 000088H BGR104 [R/W] 00000000 BGR004 [R/W] 00000000 BGR105 [R/W] 00000000 BGR005 [R/W] 00000000 00008CH BGR106 [R/W] 00000000 BGR006 [R/W] 00000000 BGR107 [R/W] 00000000 BGR007 [R/W] 00000000 000058H 0000CCH DS705-00001-2v1-E Block LIN-USART 3 Reserved LIN-USART 4 with FIFO LIN-USART 5 with FIFO LIN-USART 6 with FIFO LIN-USART 7 with FIFO Baudrate Generator LIN-USART 0 to 7 Reserved 53 MB91460T Series Address Register +0 +1 +2 +3 0000D0H IBCR0 [R/W] 00000000 IBSR0 [R] 00000000 ITBAH0 [R/W] - - - - - - 00 ITBAL0 [R/W] 00000000 0000D4H ITMKH0 [R/W] 00 - - - - 11 ITMKL0 [R/W] 11111111 ISMK0 [R/W] 01111111 ISBA0 [R/W] - 0000000 0000D8H Reserved IDAR0 [R/W] 00000000 ICCR0 [R/W] - 0011111 Reserved 0000DCH IBCR1 [R/W] 00000000 IBSR1 [R] 00000000 ITBAH1 [R/W] - - - - - - 00 ITBAL1 [R/W] 00000000 0000E0H ITMKH1 [R/W] 00 - - - - 11 ITMKL1 [R/W] 11111111 ISMK1 [R/W] 01111111 ISBA1 [R/W] - 0000000 0000E4H Reserved IDAR1 [R/W] 00000000 ICCR1 [R/W] - 0011111 Reserved 0000E8H to 0000FCH Block I2C 0 I2C 1 Reserved 000100H GCN10 [R/W] 00110010 00010000 Reserved GCN20 [R/W] - - - - 0000 PPG Control 0 to 3 000104H GCN11 [R/W] 00110010 00010000 Reserved GCN21 [R/W] - - - - 0000 PPG Control 4-7 000108H GCN12 [R/W] 00110010 00010000 Reserved GCN22 [R/W] - - - - 0000 PPG Control 8 to 11 000110H PTMR00 [R] 11111111 11111111 000114H PDUT00 [W] XXXXXXXX XXXXXXXX 000118H PTMR01 [R] 11111111 11111111 00011CH PDUT01 [W] XXXXXXXX XXXXXXXX 000120H PTMR02 [R] 11111111 11111111 000124H PDUT02 [W] XXXXXXXX XXXXXXXX 000128H PTMR03 [R] 11111111 11111111 00012CH PDUT03 [W] XXXXXXXX XXXXXXXX 000130H PTMR04 [R] 11111111 11111111 000134H PDUT04 [W] XXXXXXXX XXXXXXXX 54 PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 - PCNL00 [R/W] 000000 - 0 PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 - PCNL01 [R/W] 000000 - 0 PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 - PCNL02 [R/W] 000000 - 0 PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 - PCNL03 [R/W] 000000 - 0 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 - PCNL04 [R/W] 000000 - 0 PPG 0 PPG 1 PPG 2 PPG 3 PPG 4 DS705-00001-2v1-E MB91460T Series Register Address +0 +1 000138H PTMR05 [R] 11111111 11111111 00013CH PDUT05 [W] XXXXXXXX XXXXXXXX 000140H to 00014CH +3 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 - PCNL05 [R/W] 000000 - 0 PTMR08 [R] 11111111 11111111 000154H PDUT08 [W] XXXXXXXX XXXXXXXX 000158H PTMR09 [R] 11111111 11111111 00015CH PDUT09 [W] XXXXXXXX XXXXXXXX 000160H PTMR10 [R] 11111111 11111111 000164H PDUT10 [W] XXXXXXXX XXXXXXXX 000168H PTMR11 [R] 11111111 11111111 00016CH PDUT11 [W] XXXXXXXX XXXXXXXX P0TMCSRH [R/W] - 0000000 PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 - PPG 5 PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 - PCNL09 [R/W] 000000 - 0 PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 - PCNL10 [R/W] 000000 - 0 PCSR11 [W] XXXXXXXX XXXXXXXX P0TMCSRL [R/W] 01000000 PPG 8 PCNL08 [R/W] 000000 - 0 PCNH11 [R/W] 0000000 - PCNL11 [R/W] 000000 - 0 P1TMCSRH [R/W] - 0000000 P1TMCSRL [R/W] 01000000 000174H P0TMRLR [W] XXXXXXXX XXXXXXXX P0TMR [R] XXXXXXXX XXXXXXXX 000178H P1TMRLR [W] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX PPG 9 PPG 10 PPG 11 Pulse Frequency Modulator Reserved 00017CH 000180H Block Reserved 000150H 000170H +2 Reserved ICS01 [R/W] 00000000 Reserved ICS23 [R/W] 00000000 000184H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 000188H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX DS705-00001-2v1-E Input Capture 0 to 3 55 MB91460T Series Address Register +0 +1 +2 +3 00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 000198H SGCRH [R/W] 0000 - - 00 SGCRL [R/W] - - 0 - - 000 00019CH SGAR [R/W] 00000000 Reserved 0001A0H ADERH [R/W] 00000000 00000000 SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX ADCS1 [R/W] 00000000 ADCS0 [R/W] 00000000 ADCR1 [R] 000000XX ADCR0 [R] XXXXXXXX 0001A8H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] - - - 00000 ADECH [R/W] - - - 00000 TMRLR0 [W] XXXXXXXX XXXXXXXX 0001B4H Reserved 0001B8H TMRLR1 [W] XXXXXXXX XXXXXXXX 0001BCH Reserved 0001C0H TMRLR2 [W] XXXXXXXX XXXXXXXX 0001C4H Reserved 0001C8H TMRLR3 [W] XXXXXXXX XXXXXXXX 0001CCH Reserved 0001D0H TMRLR4 [W] XXXXXXXX XXXXXXXX 0001D4H 56 Reserved Output Compare 0 to 3 Sound Generator ADERL [R/W] 00000000 00000000 0001A4 0001B0H Block TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000 TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 TMCSRL3 [R/W] 0 - 000000 TMR4 [R] XXXXXXXX XXXXXXXX TMCSRCH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000 A/D Converter Reload Timer 0 (PPG 0 to 1) Reload Timer 1 (PPG 2 to 3) Reload Timer 2 (PPG 4 to 5) Reload Timer 3 (PPG 6 to 7) Reload Timer 4 (PPG 8 to 9) DS705-00001-2v1-E MB91460T Series Register Address 0001D8H +0 +1 TMRLR5 [W] XXXXXXXX XXXXXXXX 0001DCH Reserved 0001E0H TMRLR6 [W] XXXXXXXX XXXXXXXX 0001E4H Reserved 0001E8H TMRLR7 [W] XXXXXXXX XXXXXXXX 0001ECH Reserved 0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX +2 +3 TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000 TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000 TMR7 [R] XXXXXXXX XXXXXXXX TMCSRCH7 [R/W] - - - 00000 TMCSRCL7 [R/W] 0 - 000000 Reserved TCCS0 [R/W] 00000000 Block Reload Timer 5 (PPG10 to 11) Reload Timer 6 (PPG 12 to 13) Reload Timer 7 (PPG 14 to 15) Free Running Timer 0 (ICU 0 to 1) 0001F4H TCDT1 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS1 [R/W] 00000000 Free Running Timer 1 (ICU 2 to 3) 0001F8H TCDT2 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS2 [R/W] 00000000 Free Running Timer 2 (OCU 0 to 1) 0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS3 [R/W] 00000000 Free Running Timer 3 (OCU 2 to 3) DS705-00001-2v1-E 57 MB91460T Series Address Register +0 +1 +2 +3 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H to 00023CH Reserved 000240H DMACR [R/W] 00 - - 0000 DMAC Reserved 000244H to 00024CH Reserved 000250H DMATEST0 [R/W] XXXXXXXX 00000000 00000000 0000XXXX 000254H DMATEST1 [R] XXXXXXXX XXXXX000 00000000 00000000 000248H to 00027CH Reserved 000280H SCR08 [R/W,W] 00000000 SMR08 [R/W,W] 00000000 000284H ESCR08 [R/W] 00000X00 ECCR08 [R/W,R,W] -00000XX 000288H SCR09 [R/W,W] 00000000 SMR09 [R/W,W] 00000000 58 Block SSR08 [R/W,R] 00001000 RDR08/TDR08 [R/W] 00000000 Reserved LIN-USART 8 Reserved SSR09 [R/W,R] 00001000 RDR09/TDR09 [R/W] 00000000 LIN-USART 9 DS705-00001-2v1-E MB91460T Series Register Address +0 +1 00028CH ESCR09 [R/W] 00000X00 ECCR09 [R/W,R,W] -00000XX 000290H SCR10 [R/W,W] 00000000 SMR10 [R/W,W] 00000000 000294H ESCR10 [R/W] 00000X00 ECCR10 [R/W,R,W] -00000XX 000298H SCR11 [R/W,W] 00000000 SMR11 [R/W,W] 00000000 00029CH ESCR11 [R/W] 00000X00 ECCR11 [R/W,R,W] -00000XX 0002A0H to 0002BCH +2 +3 Reserved SSR10 [R/W,R] 00001000 RDR10/TDR10 [R/W] 00000000 LIN-USART 10 Reserved SSR11 [R/W,R] 00001000 RDR11/TDR11 [R/W] 00000000 LIN-USART 11 Reserved Reserved 0002C0H BGR108 [R/W] 00000000 BGR008 [R/W] 00000000 BGR109 [R/W] 00000000 BGR009 [R/W] 00000000 0002C4H BGR110 [R/W] 00000000 BGR010 [R/W] 00000000 BGR111 [R/W] 00000000 BGR011 [R/W] 00000000 0002C8H to 0002CCH 0002D0H Block Baudrate Generator LIN-USART 8 to 11 Reserved Reserved ICS45 [R/W] 00000000 Reserved ICS67 [R/W] 00000000 0002D4H IPCP4 [R] XXXXXXXX XXXXXXXX IPCP5 [R] XXXXXXXX XXXXXXXX 0002D8H IPCP6 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX 0002DCH OCS45 [R/W] - - -0 - -00 0000 - -00 OCS67 [R/W] - - -0 - -00 0000 - -00 0002E0H OCCP4 [R/W] XXXXXXXX XXXXXXXX OCCP5 [R/W] XXXXXXXX XXXXXXXX 0002E4H OCCP6 [R/W] XXXXXXXX XXXXXXXX OCCP7 [R/W] XXXXXXXX XXXXXXXX 0002E8H to 0002ECH DS705-00001-2v1-E Input Capture 4 to 7 Output Compare 4 to 7 Reserved 59 MB91460T Series Address Register +0 +1 +2 +3 Block 0002F0H TCDT4 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS4 [R/W] 00000000 Free Running Timer 4 (ICU 4 to 5) 0002F4H TCDT5 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS5 [R/W] 00000000 Free Running Timer 5 (ICU 6 to 7) 0002F8H TCDT6 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS6 [R/W] 00000000 Free Running Timer 6 (OCU 4 to 5) 0002FCH TCDT7 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS7 [R/W] 00000000 Free Running Timer 7 (OCU 6 to 7) 000300H UDRC1 [W] 00000000 UDRC0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000304H UDCCH0 [R/W] 00000000 UDCCL0 [R/W] 00000000 Reserved UDCS0 [R/W] 00000000 000308H UDCCH1 [R/W] 00000000 UDCCL1 [R/W] 00000000 Reserved UDCS1 [R/W] 00000000 00030CH Reserved 000310H UDRC3 [W] 00000000 UDRC2 [W] 00000000 UDCR3 [R] 00000000 UDCR2 [R] 00000000 000314H UDCCH2 [R/W] 00000000 UDCCL2 [R/W] 00000000 Reserved UDCS2 [R/W] 00000000 000318H UDCCH3 [R/W] 00000000 UDCCL3 [R/W] 00000000 Reserved UDCS3 [R/W] 00000000 00031CH 000320H Up/Down Counter 2 to 3 Reserved GCN13 [R/W] 00110010 00010000 000324H to 00032CH Reserved GCN23 [R/W] - - - - 0000 PPG Control 12 to 15 Reserved 000330H PTMR12 [R] 11111111 11111111 000334H PDUT12 [W] XXXXXXXX XXXXXXXX 000338H PTMR13 [R] 11111111 11111111 00033CH PDUT13 [W] XXXXXXXX XXXXXXXX 000340H PTMR14 [R] 11111111 11111111 000344H PDUT14 [W] XXXXXXXX XXXXXXXX 60 Up/Down Counter 0 to 1 PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 - PCNL12 [R/W] 000000 - 0 PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 - PCNL13 [R/W] 000000 - 0 PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 - PCNL14 [R/W] 000000 - 0 PPG 12 PPG 13 PPG 14 DS705-00001-2v1-E MB91460T Series Register Address +0 +1 000348H PTMR15 [R] 11111111 11111111 00034CH PDUT15 [W] XXXXXXXX XXXXXXXX +2 +3 PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 - PCNL15 [R/W] 000000 - 0 000368H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH2 [R/W] - - - - - - 00 ITBAL2 [R/W] 00000000 00036CH ITMKH2 [R/W] 00 - - - - 11 ITMKL2 [R/W] 11111111 ISMK2 [R/W] 01111111 ISBA2 [R/W] - 0000000 000370H Reserved IDAR2 [R/W] 00000000 ICCR2 [R/W] - 0011111 Reserved 000374H IBCR3 [R/W] 00000000 IBSR3 [R] 00000000 ITBAH3 [R/W] - - - - - - 00 ITBAL3 [R/W] 00000000 000378H ITMKH3 [R/W] 00 - - - - 11 ITMKL3 [R/W] 11111111 ISMK3 [R/W] 01111111 ISBA3 [R/W] - 0000000 00037CH Reserved IDAR3 [R/W] 00000000 ICCR3 [R/W] - 0011111 Reserved 000380H to 00038CH 000390H Block PPG 15 I2C 2 I2C 3 Reserved ROMS [R] 11111111 00000000 (MB91F467TA) 11111000 00000000 (MB91F469TA) Reserved 000394H to 0003ECH Reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H to 00043CH DS705-00001-2v1-E ROM Select Register Bit Search Module Reserved 61 MB91460T Series Address Register Block +0 +1 +2 +3 000440H ICR00 [R/W] ---11111 ICR01 [R/W] ---11111 ICR02 [R/W] ---11111 ICR03 [R/W] ---11111 000444H ICR04 [R/W] ---11111 ICR05 [R/W] ---11111 ICR06 [R/W] ---11111 ICR07 [R/W] ---11111 000448H ICR08 [R/W] ---11111 ICR09 [R/W] ---11111 ICR10 [R/W] ---11111 ICR11 [R/W] ---11111 00044CH ICR12 [R/W] ---11111 ICR13 [R/W] ---11111 ICR14 [R/W] ---11111 ICR15 [R/W] ---11111 000450H ICR16 [R/W] ---11111 ICR17 [R/W] ---11111 ICR18 [R/W] ---11111 ICR19 [R/W] ---11111 000454H ICR20 [R/W] ---11111 ICR21 [R/W] ---11111 ICR22 [R/W] ---11111 ICR23 [R/W] ---11111 000458H ICR24 [R/W] ---11111 ICR25 [R/W] ---11111 ICR26 [R/W] ---11111 ICR27 [R/W] ---11111 00045CH ICR28 [R/W] ---11111 ICR29 [R/W] ---11111 ICR30 [R/W] ---11111 ICR31 [R/W] ---11111 000460H ICR32 [R/W] ---11111 ICR33 [R/W] ---11111 ICR34 [R/W] ---11111 ICR35 [R/W] ---11111 000464H ICR36 [R/W] ---11111 ICR37 [R/W] ---11111 ICR38 [R/W] ---11111 ICR39 [R/W] ---11111 000468H ICR40 [R/W] ---11111 ICR41 [R/W] ---11111 ICR42 [R/W] ---11111 ICR43 [R/W] ---11111 00046CH ICR44 [R/W] ---11111 ICR45 [R/W] ---11111 ICR46 [R/W] ---11111 ICR47 [R/W] ---11111 000470H ICR48 [R/W] ---11111 ICR49 [R/W] ---11111 ICR50 [R/W] ---11111 ICR51 [R/W] ---11111 000474H ICR52 [R/W] ---11111 ICR53 [R/W] ---11111 ICR54 [R/W] ---11111 ICR55 [R/W] ---11111 000478H ICR56 [R/W] ---11111 ICR57 [R/W] ---11111 ICR58 [R/W] ---11111 ICR59 [R/W] ---11111 00047CH ICR60 [R/W] ---11111 ICR61 [R/W] ---11111 ICR62 [R/W] ---11111 ICR63 [R/W] ---11111 000480H RSRR [R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXX – 00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] ---- 0000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 000488H CTEST [R/W] XXXX00XX Reserved Reserved Reserved Reserved 00048CH PLLDIVM [R/W] - - - 00000 PLLDIVN [R/W] - - - 00000 PLLDIVG [R/W] - - - 00000 PLLDIVG [W] 00000000 PLL Clock Gear Unit 000490H PLLCTRL [R/W] - - - - 0000 Reserved Reserved Reserved 62 Interrupt Control Unit Interrupt Control Unit Clock Control Unit DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 000494H OSCC1 [R/W] - - - - - 010 OSCS1 [R/W] 00001111 OSCC2 [R/W] - - - - - 010 OSCS2 [R/W] 00001111 000498H PORTEN [R/W] - - - - - - 00 Reserved 00049CH PPMUX [R/W] *1 00000000 00000000 Block Main/Sub Oscillator Control Port Input Enable Control / PortMux Control Reserved WTCER [R/W] - - - - - - 00 WTCR [R/W] 00000000 000 – 00 – 0 0004A0H Reserved 0004A4H Reserved 0004A8H WTHR [R/W] - - - 00000 WTMR [R/W] - - 000000 WTSR [R/W] - - 000000 Reserved 0004ACH CSVTR [R/W] - - - 00010 CSVCR [R/W] 00011100 CSCFG [R/W] 0X000000 CMCFG [R/W] 00000000 WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX 0004B0H CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTD [R/W] 10000000 00000000 0004B4H CUTR1 [R] - - - - - - - - 00000000 CUTR2 [R] 00000000 00000000 0004B8H CMPR [R/W] - - 000010 11111101 0004BCH CMT1 [R/W] 00000000 1 - - - 0000 Reserved CMCR [R/W] - 001 - - 00 CMT2 [R/W] - - 000000 - - 000000 Real Time Clock (Watch Timer) ClockSupervisor / Selector / Monitor Calibration Unit of Sub Oscillation Clock Modulation 0004C0H CANPRE [R/W] 0 - - - 0000 CANCKD [R/W] - - - - - 000 *2 Reserved Reserved CAN Clock Control 0004C4H LVSEL [R/W] 00000111 LVDET [R/W] 0000 0 - 00 HWWDE [R/W] - - - - - - 00 HWWD [R/W,W] 00011000 LV Detection / HardwareWatchdog 0004C8H OSCRH [R/W] 000 - - 001 OSCRL [R/W] - - - - - 000 WPCRH [R/W] 00 - - - 000 WPCRL [R/W] - - - - - - 00 Main-/Sub-Oscillation Stabilization Timer REGCTR [R/W] - - - 0 - - 00 Main-Oscillation Standby Control Main/Sub Regulator Control 0004CCH OSCCR [R/W] - - - - - - 00 000500H to 00063CH DS705-00001-2v1-E Reserved REGSEL [R/W] - - 000110 Reserved 63 MB91460T Series Address Register +0 +1 +2 +3 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 1111**00 00100000 *3 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX ACR1 [R/W] XXXXXXXX XXXXXXXX 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX 000650H ASR4 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX 000654H ASR5 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX 000658H ASR6 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX 00065CH ASR7 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX 000660H AWR0 [R/W] 01111111 11111011 AWR1 [R/W] XXXXXXXX XXXXXXXX 000664H AWR2 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX 000668H AWR4 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX 00066CH AWR6 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX 000670H MCRA [R/W] XXXXXXXX 000674H 000678H MCRB [R/W] XXXXXXXX IOWR0 [R/W] XXXXXXXX IOWR1 [R/W] XXXXXXXX CSER [R/W] 00000001 CHER [R/W] 11111111 000684H RCRH [R/W] 00XXXXXX RCRL [R/W] XXXX0XXX 000688H to 0007F8H 64 Reserved IOWR2 [R/W] XXXXXXXX IOWR3 [R/W] XXXXXXXX Reserved 000680H 000800H to 000BFCH External Bus Unit Reserved 00067CH 0007FCH Block Reserved TCR [R/W] 0000 *4 External Bus Unit Reserved Reserved Reserved MODR [W] XXXXXXXX Reserved Reserved Mode Register Reserved DS705-00001-2v1-E MB91460T Series Register Address 000C00H +0 +1 +2 +3 TVCTW [W] XXXXXXXX TVCTR [R] - - XXXXXX Reserved IOS [R/W] 00000000 000C04H to 000CFCH Block Reserved Reserved 000D00H PDRD00 [R] XXXXXXXX PDRD01 [R] XXXXXXXX Reserved Reserved 000D04H Reserved PDRD05 [R] XXXXXXXX PDRD06 [R] XXXXXXXX PDRD07 [R] XXXXXXXX 000D08H PDRD08 [R] X - -X - -XX PDRD09 [R] - - - - - XXX PDRD10 [R] - - - - X - XX Reserved 000D0CH Reserved Reserved PDRD14 [R] XXXXXXXX PDRD15 [R] XXXXXXXX 000D10H PDRD16 [R] XXXXXXXX PDRD17 [R] - - XXXXXX PDRD18 [R] - XXX - XXX PDRD19 [R] - XXX - XXX 000D14H PDRD20 [R] - XXX - XXX PDRD21 [R] - - - - - XXX PDRD22 [R] XXXX - - - - PDRD23 [R] - - - - XXXX 000D18H PDRD24 [R] XXXXXXXX Reserved PDRD26 [R] XXXXXXXX PDRD27 [R] XXXXXXXX 000D1CH PDRD28 [R] XXXXXXXX PDRD29 [R] XXXXXXXX Reserved Reserved 000D20H Reserved Reserved PDRD34 [R] - XXX - XXX PDRD35 [R] - XXX - XXX 000D24H to 000D3CH DS705-00001-2v1-E R-bus Port Data Direct Read Register Reserved 65 MB91460T Series Address Register +0 +1 +2 +3 000D40H DDR00 [R/W] 00000000 DDR01 [R/W] 00000000 Reserved Reserved 000D44H Reserved DDR05 [R/W] 00000000 DDR06 [R/W] 00000000 DDR07 [R/W] 00000000 000D48H DDR08 [R/W] 0 - - 0 - - 00 DDR09 [R/W] - - - - - 000 DDR10 [R/W] - - - - 0 - 00 Reserved 000D4CH Reserved Reserved DDR14 [R/W] 00000000 DDR15 [R/W] 00000000 000D50H DDR16 [R/W] 00000000 DDR17 [R/W] - - 000000 DDR18 [R/W] - 000 - 000 DDR19 [R/W] - 000 - 000 000D54H DDR20 [R/W] - 000 - 000 DDR21 [R/W] - - - - - 000 DDR22 [R/W] 0000 - - - - DDR23 [R/W] - - - - 0000 000D58H DDR24 [R/W] 00000000 Reserved DDR26 [R/W] 00000000 DDR27 [R/W] 00000000 000D5CH DDR28 [R/W] 00000000 DDR29 [R/W] 00000000 Reserved Reserved 000D60H Reserved Reserved DDR34 [R/W] - 000 - 000 DDR35 [R/W] - 000 - 000 000D64H to 000D7CH PFR00 [R/W] 00000000 *5 PFR01 [R/W] 00000000 *5 Reserved Reserved 000D84H Reserved PFR05 [R/W] 00000000 *5 PFR06 [R/W] 00000000 *5 PFR07 [R/W] 00000000 *5 000D88H PFR08 [R/W] 0 - - 0- - 00 *5 PFR09 [R/W] - - - - - 000 *5 PFR10 [R/W] - - - - 0 - 00 *5 Reserved 000D8CH Reserved Reserved PFR14 [R/W] 00000000 PFR15 [R/W] 00000000 000D90H PFR16 [R/W] 00000000 PFR17 [R/W] - - 000000 PFR18 [R/W] - 000 - 000 PFR19 [R/W] - 000 - 000 000D94H PFR20 [R/W] - 000 - 000 PFR21 [R/W] - - - - - 000 PFR22 [R/W] 0000 - - - - PFR23 [R/W] - - - - 0000 000D98H PFR24 [R/W] 00000000 Reserved PFR26 [R/W] 00000000 PFR27 [R/W] 00000000 000D9CH PFR28 [R/w] 00000000 PFR29 [R/W] 00000000 Reserved Reserved 000DA0H Reserved Reserved PFR34 [R/W] - 000 - 000 PFR35 [R/W] - 000 - 000 66 R-bus Port Direction Register Reserved 000D80H 000DA4H to 000DBCH Block R-bus Port Function Register Reserved DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 000DC0H Reserved Reserved Reserved Reserved 000DC4H Reserved Reserved Reserved Reserved 000DC8H Reserved Reserved EPFR10 [R/W] -------0 Reserved 000DCCH Reserved Reserved EPFR14 [R/W] 00000000 EPFR15 [R/W] 00000000 000DD0H EPFR16 [R/W] 0000 - - - - Reserved EPFR18 [R/W] - 000 - 000 EPFR19 [R/W] -0---0-- 000DD4H EPFR20 [R/W] - 000 - 000 EPFR21 [R/W] -----0-- Reserved Reserved 000DD8H Reserved Reserved EPFR26 [R/W] 00000000 EPFR27 [R/W] 00000000 000DDCH Reserved Reserved Reserved Reserved 000DE0H Reserved Reserved EPFR34 [R/W] - 000 - 000 EPFR35 [R/W] - 000 - 000 000DE4H to 000DFCH Block R-bus Port Extra Function Register Reserved 000E00H PODR00 [R/W] 00000000 PODR01 [R/W] 00000000 Reserved Reserved 000E04H Reserved PODR05 [R/W] 00000000 PODR06 [R/W] 00000000 PODR07 [R/W] 00000000 000E08H PODR08 [R/W] 0 - -0 - - 00 PODR09 [R/W] - - - - - 000 PODR10 [R/W] - - - - 0 - 00 Reserved 000E0CH Reserved Reserved PODR14 [R/W] 00000000 PODR15 [R/W] 00000000 000E10H PODR16 [R/W] 00000000 PODR17 [R/W] - - 000000 PODR18 [R/W] - 000 - 000 PODR19 [R/W] - 000 - 000 000E14H PODR20 [R/W] - 000 - 000 PODR21 [R/W] - - - - - 000 Reserved PODR23 [R/W] - - - - 0000 000E18H PODR24 [R/W] - - - - 0000 Reserved PODR26 [R/W] 00000000 PODR27 [R/W] 00000000 000E1CH PODR28 [R/W] 0000000 PODR29 [R/W] 00000000 Reserved Reserved 000E20H Reserved Reserved PODR34 [R/W] - 000 - 000 PODR35 [R/W] - 000 - 000 000E24H to 000E3CH DS705-00001-2v1-E R-bus Port Output Drive Select Register Reserved 67 MB91460T Series Address Register +0 +1 +2 +3 000E40H PILR00 [R/W] 00000000 PILR01 [R/W] 00000000 Reserved Reserved 000E44H Reserved PILR05 [R/W] 00000000 PILR06 [R/W] 00000000 PILR07 [R/W] 00000000 000E48H PILR08 [R/W] 0 - - 0 - - 00 PILR09 [R/W] - - - - - 000 PILR10 [R/W] - - - -0- - 00 Reserved 000E4CH Reserved Reserved PILR14 [R/W] 00000000 PILR15 [R/W] 00000000 000E50H PILR16 [R/W] 00000000 PILR17 [R/W] - - 000000 PILR18 [R/W] - 000 - 000 PILR19 [R/W] - 000 - 000 PILR20 [R/W] - 000 - 000 PILR21 [R/W] - - - - - 000 PILR22 [R/W] 0000 - - - - PILR23 [R/W] - - - - 0000 000E58H PILR24 [R/W] 00000000 Reserved PILR26 [R/W] 00000000 PILR27 [R/W] 00000000 000E5CH PILR28 [R/W] 00000000 PILR29 [R/W] 00000000 Reserved Reserved 000E60H Reserved Reserved PILR34 [R/W] - 000 - 000 PILR35 [R/W] - 000 - 000 000E54H 000E64H to 000E7CH EPILR00[R/W] 00000000 EPILR01 [R/W] 00000000 Reserved Reserved 000E84H Reserved EPILR05 [R/W] 00000000 EPILR06 [R/W] 00000000 EPILR07 [R/W] 00000000 000E88H EPILR08 [R/W] 0 - - 0 - - 00 EPILR09 [R/W] - - - - - 000 EPILR10 [R/W] - - - - 0 - 00 Reserved 000E8CH Reserved Reserved EPILR14 [R/W] 00000000 EPILR15 [R/W] 00000000 000E90H EPILR16 [R/W] 00000000 EPILR17 [R/W] - - 000000 EPILR18 [R/W] - 000 - 000 EPILR19 [R/W] - 000 - 000 000E94H EPILR20 [R/W] - 000 - 000 EPILR21 [R/W] - - - - - 000 EPILR22 [R/W] 0000 - - - - EPILR23 [R/W] - - - - 0000 000E98H EPILR24 [R/W] 00000000 Reserved EPILR26 [R/W] 00000000 EPILR27 [R/W] 00000000 000E9CH EPILR28 [R/W] 0000000 EPILR29 [R/W] 00000000 Reserved Reserved 000EA0H Reserved Reserved EPILR34 [R/W] - 000 - 000 EPILR35 [R/W] - 000 - 000 68 R-bus Port Input Level Select Register Reserved 000E80H 000EA4H to 000EBCH Block R-bus Port Extra Input Level Select Register Reserved DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 000EC0H PPER00 [R/W] 00000000 PPER01 [R/W] 00000000 Reserved Reserved 000EC4H Reserved PPER05 [R/W] 00000000 PPER06 [R/W] 00000000 PPER07 [R/W] 00000000 000EC8H PPER08 [R/W] 0 - - 0 - - 00 PPER09 [R/W] - - - - - 000 PPER10 [R/W] - - - - 0 - 00 Reserved 000ECCH Reserved Reserved PPER14 [R/W] 00000000 PPER15 [R/W] 00000000 000ED0H PPER16 [R/W] 00000000 PPER17 [R/W] - - 000000 PPER18 [R/W] - 000 - 000 PPER19 [R/W] - 000 - 000 000ED4H PPER20 [R/W] - 000 - 000 PPER21 [R/W] - - - - - 000 Reserved PPER23 [R/W] - - - - 0000 000ED8H PPER24 [R/W] - - - - 0000 Reserved PPER26 [R/W] 00000000 PPER27 [R/W] 00000000 000EDCH PPER28 [R/W] 0000000 PPER29 [R/W] 00000000 Reserved Reserved 000EE0H Reserved Reserved PPER34 [R/W] - 000 - 000 PPER35 [R/W] - 000 - 000 000EE4H to 000EFCH Block R-bus Port Pull-Up/Down Enable Register Reserved 000F00H PPCR00 [R/W] 11111111 PPCR01 [R/W] 11111111 Reserved Reserved 000F04H Reserved PPCR05 [R/W] 11111111 PPCR06 [R/W] 11111111 PPCR07 [R/W] 11111111 000F08H PPCR08 [R/W] 1 - - 1 - - 11 PPCR09 [R/W] - - - - - 111 PPCR10 [R/W] - - - - 1 - 11 Reserved 000F0CH Reserved Reserved PPCR14 [R/W] 11111111 PPCR15 [R/W] 11111111 000F10H PPCR16 [R/W] 11111111 PPCR17 [R/W] - - 111111 PPCR18 [R/W] - 111 - 111 PPCR19 [R/W] - 111 - 111 000F14H PPCR20 [R/W] - 111 - 111 PPCR21 [R/W] - - - - - 111 Reserved PPCR23 [R/W] - - - - 1111 000F18H PPCR24 [R/W] - - - - 1111 Reserved PPCR26 [R/W] 11111111 PPCR27 [R/W] 11111111 000F1CH PPCR28 [R/W] - - 11111 PPCR29 [R/W] 11111111 Reserved Reserved 000F20H Reserved Reserved PPCR34 [R/W] - 000 - 000 PPCR35 [R/W] - 000 - 000 000F24H to 000FFCH DS705-00001-2v1-E R-bus Port Pull-Up/Down Control Register Reserved 69 MB91460T Series Address Register +0 +1 +2 +3 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H to 01FFCH Reserved 002000H to 006FFCH MB91F467TA Flash-cache size is 8 KB: 004000H to 005FFCH MB91F469TA Flash-cache size is 16 KB: 004000H to 005FFCH 007000H 007004H FMCS [R/W] 01101000 FMCR [R] - - - 00000 FMWT [R/W] 11111111 11111111 FCHCR [R/W] - - - - - - 00 10000011 FMWT2 [R] - 001 - - - - FMPS [R/W] - - - - - 000 007008H FMAC [R] 00000000 00000000 00000000 00000000 00700CH FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000 007010H FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000 007014H to 007FFCH Reserved 008000H to 00BFFCH MB91F467TA Boot-ROM size is 4KB: 00B000H to 00BFFCH MB91F469TA Boot-ROM size is 4KB: 00B000H to 00BFFCH (instruction access is 1 waitcycle, data access is 1 waitcycle) 70 Block DMAC Flash-cache / I-RAM area Flash Memory/ F-Cache Control Register I-Cache Non-cacheable area setting Register Boot ROM area DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 00C000H CTRLR0 [R/W] 00000000 00000001 STATR0 [R/W] 00000000 00000000 00C004H ERRCNT0 [R] 00000000 00000000 BTR0 [R/W] 00100011 00000001 00C008H INTR0 [R] 00000000 00000000 TESTR0 [R/W] 00000000 X0000000 00C00CH BRPE0 [R/W] 00000000 00000000 Reserved 00C010H IF1CREQ0 [R/W] 00000000 00000001 IF1CMSK0 [R/W] 00000000 00000000 00C014H IF1MSK20 [R/W] 11111111 11111111 IF1MSK10 [R/W] 11111111 11111111 00C018H IF1ARB20 [R/W] 00000000 00000000 IF1ARB10 [R/W] 00000000 00000000 00C01CH IF1MCTR0 [R/W] 00000000 00000000 Reserved 00C020H IF1DTA10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 00C024H IF1DTB10 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 00C028H to 00C02CH Block CAN 0 Control Register CAN 0 IF 1 Register Reserved 00C030H IF1DTA20 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 00C034H IF1DTB20 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 00C038H to 00C03CH DS705-00001-2v1-E Reserved 71 MB91460T Series Address Register +0 +1 +2 +3 00C040H IF2CREQ0 [R/W] 00000000 00000001 IF2CMSK0 [R/W] 00000000 00000000 00C044H IF2MSK20 [R/W] 11111111 11111111 IF2MSK10 [R/W] 11111111 11111111 00C048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 00C04CH IF2MCTR0 [R/W] 00000000 00000000 Reserved 00C050H IF2DTA10 [R/W] 00000000 00000000 IF2DTA20 [R/W] 00000000 00000000 00C054H IF2DTB10 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 00C058H to 00C05CH IF2DTA20 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 00C064H IF2DTB20 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 00C068H to 00C07CH Reserved TREQR20 [R] 00000000 00000000 00C084H to 00C08CH 00C090H NEWDT20 [R] 00000000 00000000 00C0B4H to 00C0FCH 72 NEWDT10 [R] 00000000 00000000 CAN 0 Status Flags Reserved INTPND20 [R] 00000000 00000000 00C0A4H to 00C0ACH 00C0B0H TREQR10 [R] 00000000 00000000 Reserved 00C094H to 00C09CH 00C0A0H CAN 0 IF 2 Register Reserved 00C060H 00C080H Block INTPND10 [R] 00000000 00000000 Reserved MSGVAL20 [R] 00000000 00000000 MSGVAL10 [R] 00000000 00000000 Reserved DS705-00001-2v1-E MB91460T Series Register Address +0 +1 +2 +3 00C100H CTRLR1 [R/W] 00000000 00000001 STATR1 [R/W] 00000000 00000000 00C104H ERRCNT1 [R] 00000000 00000000 BTR1 [R/W] 00100011 00000001 00C108H INTR1 [R] 00000000 00000000 TESTR1 [R/W] 00000000 X0000000 00C10CH BRPE1 [R/W] 00000000 00000000 Reserved 00C110H IF1CREQ1 [R/W] 00000000 00000001 IF1CMSK1 [R/W] 00000000 00000000 00C114H IF1MSK21 [R/W] 11111111 11111111 IF1MSK11 [R/W] 11111111 11111111 00C118H IF1ARB21 [R/W] 00000000 00000000 IF1ARB11 [R/W] 00000000 00000000 00C11CH IF1MCTR1 [R/W] 00000000 00000000 Reserved 00C120H IF1DTA11 [R/W] 00000000 00000000 IF1DTA21 [R/W] 00000000 00000000 00C124H IF1DTB11 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 00C128H to 00C12CH Block CAN 1 Control Register CAN 1 IF 1 Register Reserved 00C130H IF1DTA21 [R/W] 00000000 00000000 IF1DTA11 [R/W] 00000000 00000000 00C134H IF1DTB21 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 00C138H to 00C13CH Reserved 00C140H IF2CREQ1 [R/W] 00000000 00000001 IF2CMSK1 [R/W] 00000000 00000000 00C144H IF2MSK21 [R/W] 11111111 11111111 IF2MSK11 [R/W] 11111111 11111111 00C148H IF2ARB21 [R/W] 00000000 00000000 IF2ARB11 [R/W] 00000000 00000000 00C14CH IF2MCTR1 [R/W] 00000000 00000000 Reserved 00C150H IF2DTA11 [R/W] 00000000 00000000 IF2DTA21 [R/W] 00000000 00000000 DS705-00001-2v1-E CAN 1 IF 2 Register 73 MB91460T Series Address 00C154H Register +0 +1 +2 IF2DTB11 [R/W] 00000000 00000000 00C158H to 00C15CH +3 IF2DTB21 [R/W] 00000000 00000000 Reserved 00C160H IF2DTA21 [R/W] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 00C164H IF2DTB21 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 00C168H to 00C17CH 00C180H TREQR21 [R] 00000000 00000000 NEWDT21 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 CAN 1 Status Flags Reserved INTPND21 [R] 00000000 00000000 00C1A4H to 00C1ACH 00C1B0H TREQR11 [R] 00000000 00000000 Reserved 00C194H to 00C19CH 00C1A0H INTPND11 [R] 00000000 00000000 Reserved MSGVAL21 [R] 00000000 00000000 MSGVAL11 [R] 00000000 00000000 00C1B4H to 00EFF H Reserved 00F000H BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 00F008H BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F00CH BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F010H BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 74 CAN 1 IF 2 Register Reserved 00C184H to 00C18CH 00C190H Block EDSU / MPU DS705-00001-2v1-E MB91460T Series Address Register +0 +1 +2 00F014H to 00F01CH Reserved 00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 00F030H to 00F07CH Reserved 00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DS705-00001-2v1-E +3 Block EDSU / MPU EDSU / MPU 75 MB91460T Series Address Register +0 +1 +2 +3 Block 00F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C0H to 027FFCH Reserved 020000H to 02FFFCH MB91F467TA D-RAM size is 32KB: 028000H to 02FFFCH MB91F469TA D-RAM size is 64KB: 020000H to 02FFFCH (data access is 0 waitcycles) D-RAM area 030000H to 03FFFCH MB91F467TA ID-RAM size is 32KB: 030000H to 037FFCH MB91F469TA ID-RAM size is 64KB: 030000H to 03FFFCH (instruction access is 0 waitcycles, data access is 1 waitcycle) ID-RAM area EDSU / MPU *1 : Writable only once as half-word. PPMUX is reset by INIT and RST *2: depends on the number of available CAN channels *3 : ACR0 [11 : 10] depends on bus width setting in Mode vector fetch information *4 : TCR [3 : 0] INIT value = 0000, keeps value after RST *5: PFR initial values for ports 00..10 depend on the selected mode at the mode pins MD_0..MD_2: internal usermode (000): PFR00..PFR10 initialized to all 0 external usermode (001): PFR00..PFR10 initialized to all 1 76 DS705-00001-2v1-E MB91460T Series 2. Flash memory and external bus area 2.1. MB91F467TA 32bit read/write 16bit read/write Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 040000H to 05FFF8H SA8 (64kB) SA9 (64kB) ROMS0 060000H to 07FFF8H SA10 (64kB) SA11 (64kB) ROMS1 080000H to 09FFF8H SA12 (64kB) SA13 (64kB) ROMS2 0A0000H to 0BFFF8H SA14 (64kB) SA15 (64kB) ROMS3 0C0000H to 0DFFF8H SA16 (64kB) SA17 (64kB) ROMS4 0E0000H to 0FFFF0H SA18 (64kB) SA19 (64kB) 0FFFF8H FMV [R] 06 00 00 00H FRV [R] 00 00 BF F8H 100000H to 11FFF8H SA20 (64kB) SA21 (64kB)) 120000H to 13FFF8H SA22 (64kB) SA23 (64kB) 140000H to 143FF8H SA0 (8kB) SA1 (8kB) 144000H to 147FF8H SA2 (8kB) SA3 (8kB) 148000H to 14BFF8H SA4 (8kB) SA5 (8kB) 14C000H to 14FFF8H SA6 (8kB) SA7 (8kB) DS705-00001-2v1-E ROMS5 ROMS6 ROMS7 77 MB91460T Series 32bit read/write 16bit read/write Address 150000H to 17FFF8H dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 Reserved +5 +6 +7 Block ROMS7 180000H to 1BFFF8H ROMS8 1C0000H to 1FFFF8H ROMS9 200000H to 27FFF8H ROMS10 280000H to 2FFFF8H ROMS11 300000H to 37FFF8H Reserved ROMS12 380000H to 3FFFF8H ROMS13 400000H to 47FFF8H ROMS14 480000H to 4FFFF8H ROMS15 Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. 78 DS705-00001-2v1-E MB91460T Series 2.2. MB91F469TA 32bit read/write 16bit read/write Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 040000H to 05FFFFH SA8 (64kB) SA9 (64kB) ROMS0 060000H to 07FFFFH SA10 (64kB) SA11 (64kB) ROMS1 080000H to 09FFFFH SA12 (64kB) SA13 (64kB) ROMS2 0A0000H to 0BFFFFH SA14 (64kB) SA15(64kB) ROMS3 0C0000H to 0DFFFFH SA16 (64kB) SA17 (64kB) ROMS4 0E0000H to 0FFFF4H SA18 (64kB) SA19 (64kB) 0FFFF8H FMV [R] 06 00 00 00H FRV [R] 00 00 BF F8H 100000H to 11FFFFH SA20 (64kB) SA21 (64kB) 120000H to 13FFFFH SA22 (64kB) SA23 (64kB) 140000H to 15FFFFH SA24 (64kB) SA25 (64kB) 160000H to 17FFFFH SA26 (64kB) SA27 (64kB) 180000H to 19FFFFH SA28 (64kB) SA29 (64kB) 1A0000H to 1BFFFFH SA30 (64kB) DS705-00001-2v1-E ROMS5 ROMS6 ROMS7 ROMS8 SA31 (64kB) 79 MB91460T Series 32bit read/write 16bit read/write Address dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 1C0000H to 1DFFFFH SA32 (64kB) 1E0000H to 1FFFFFH SA34 (64kB) SA35 (64kB) 200000H to 21FFFFH SA36 (64kB) SA37 (64kB) 220000H to 23FFFFH SA38 (64kB) SA39 (64kB) 240000H to 243FFFH SA0 (8kB) SA1 (8kB) 244000H to 247FFFH SA2 (8kB) SA3 (8kB) 248000H to 24BFFFH SA4 (8kB) SA5 (8kB) 24C000H to 24FFFFH SA6 (8kB) SA7 (8kB) 250000H to 27FFFFH 80 dat[31:0] +7 Block SA33 (64kB) ROMS9 ROMS10 reserved DS705-00001-2v1-E MB91460T Series 280000H to 2FFFF8H ROMS11 300000H to 37FFF8H 380000H to 3FFFF8H 400000H to 47FFF8H 480000H to 4FFFF8H ROMS12 External Bus Area ROMS13 ROMS14 ROMS15 Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. DS705-00001-2v1-E 81 MB91460T Series ■ INTERRUPT VECTOR TABLE Interrupt number Interrupt level *1 Interrupt vector *2 DMA *3 Resource Number Decimal Hexadecimal Setting Register Register address Offset Default Vector address Reset 0 00 - - 3FCH 000FFFFC - Mode vector 1 01 - - 3F8H 000FFFF8 - System reserved 2 02 - - 3F4H 000FFFF4 - System reserved 3 03 - - 3F0H 000FFFF0 - System reserved 4 04 - - 3ECH 000FFFEC - CPU supervisor mode (INT #5 instruction) *6 5 05 - - 3E8H 000FFFE8 - Memory Protection exception *6 6 06 - - 3E4H 000FFFE4 - System reserved 7 07 - - 3E0H 000FFFE0 - System reserved 8 08 - - 3DCH 000FFFDC - System reserved 9 09 - - 3D8H 000FFFD8 - System reserved 10 0A - - 3D4H 000FFFD4 - System reserved 11 0B - - 3D0H 000FFFD0 - System reserved 12 0C - - 3CCH 000FFFCC - System reserved 13 0D - - 3C8H 000FFFC8 - Undefined instruction exception 14 0E - - 3C4H 000FFFC4 - NMI request 15 0F 3C0H 000FFFC0 - External Interrupt 0 16 10 3BCH 000FFFBC 0, 16 3B8H 000FFFB8 1, 17 3B4H 000FFFB4 2, 18 3B0H 000FFFB0 3, 19 3ACH 000FFFAC 20 3A8H 000FFFA8 21 3A4H 000FFFA4 22 3A0H 000FFFA0 23 39CH 000FFF9C - 398H 000FFF98 - Interrupt FH fixed ICR00 External Interrupt 1 17 11 External Interrupt 2 18 12 ICR01 External Interrupt 3 19 13 External Interrupt 4 20 14 ICR02 External Interrupt 5 21 15 External Interrupt 6 22 16 ICR03 External Interrupt 7 23 17 External Interrupt 8 24 18 ICR04 External Interrupt 9 82 25 19 440H 441H 442H 443H 444H DS705-00001-2v1-E MB91460T Series Interrupt number Interrupt Reserved Decimal Hexadecimal 26 1A Reserved 27 1B Reserved 28 1C Interrupt level *1 Setting Register Register address ICR05 445H ICR06 Reserved 29 1D External Interrupt 14 30 1E ICR07 External Interrupt 15 31 1F Reload Timer 0 32 20 ICR08 Reload Timer 1 33 21 Reload Timer 2 34 22 ICR09 Reload Timer 3 35 23 Reload Timer 4 36 24 ICR10 Reload Timer 5 37 25 Reload Timer 6 38 26 ICR11 Reload Timer 7 39 27 Free Run Timer 0 40 28 ICR12 Free Run Timer 1 41 29 Free Run Timer 2 42 2A ICR13 Free Run Timer 3 43 2B Free Run Timer 4 44 2C ICR14 Free Run Timer 5 45 2D Free Run Timer 6 46 2E ICR15 Free Run Timer 7 47 2F CAN 0 48 30 ICR16 CAN 1 49 31 Reserved 50 32 ICR17 Reserved 51 33 Reserved 52 34 ICR18 Reserved DS705-00001-2v1-E 53 35 Interrupt vector *2 DMA *3 Resource Number Offset Default Vector address 394H 000FFF94 - 390H 000FFF90 - 38CH 000FFF8C - 388H 000FFF88 - 384H 000FFF84 - 380H 000FFF80 - 37CH 000FFF7C 4, 32 378H 000FFF78 5, 33 374H 000FFF74 34 370H 000FFF70 35 36CH 000FFF6C 36 368H 000FFF68 37 364H 000FFF64 38 360H 000FFF60 39 35CH 000FFF5C 40 358H 000FFF58 41 354H 000FFF54 42 350H 000FFF50 43 34CH 000FFF4C 44 348H 000FFF48 45 344H 000FFF44 46 340H 000FFF40 47 33CH 000FFF3C - 338H 000FFF38 - 334H 000FFF34 - 330H 000FFF30 - 32CH 000FFF2C - 328H 000FFF28 - 446H 447H 448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 83 MB91460T Series Interrupt number Interrupt LIN-USART 0 RX Decimal Hexadecimal 54 36 LIN-USART 0 TX 55 37 Reserved 56 38 Interrupt level *1 Setting Register Register address ICR19 453H ICR20 Reserved 57 39 LIN-USART 2 RX 58 3A ICR21 LIN-USART 2 TX 59 3B LIN-USART 3 RX 60 3C ICR22 LIN-USART 3 TX 61 3D System reserved 62 3E ICR23 *4 Delayed Interrupt 63 3F System reserved *5 64 40 (ICR24) System reserved *5 65 41 LIN-USART (FIFO) 4 RX 66 42 ICR25 LIN-USART (FIFO) 4 TX 67 43 LIN-USART (FIFO) 5 RX 68 44 ICR26 LIN-USART (FIFO) 5 TX 69 45 LIN-USART (FIFO) 6 RX 70 46 ICR27 LIN-USART (FIFO) 6 TX 71 47 LIN-USART (FIFO) 7 RX 72 48 ICR28 LIN-USART (FIFO) 7 TX 73 49 I2C 0 / I2C 2 74 4A ICR29 I2C 1 / I2C 3 75 4B LIN-USART 8 RX 76 4C ICR30 LIN-USART 8 TX 77 4D LIN-USART 9 RX 78 4E ICR31 LIN-USART 9 TX 79 4F LIN-USART 10 RX 80 50 ICR32 LIN-USART 10 TX 84 81 51 Interrupt vector *2 DMA *3 Resource Number Offset Default Vector address 324H 000FFF24 6, 48 320H 000FFF20 7, 49 31CH 000FFF1C 8, 50 318H 000FFF18 9, 51 314H 000FFF14 52 310H 000FFF10 53 30CH 000FFF0C 54 308H 000FFF08 55 304H 000FFF04 - 300H 000FFF00 - 2FCH 000FFEFC - 2F8H 000FFEF8 - 2F4H 000FFEF4 10, 56 2F0H 000FFEF0 11, 57 2ECH 000FFEEC 12, 58 2E8H 000FFEE8 13, 59 2E4H 000FFEE4 60 2E0H 000FFEE0 61 2DCH 000FFEDC 62 2D8H 000FFED8 63 2D4H 000FFED4 - 2D0H 000FFED0 - 2CCH 000FFECC 64 2C8H 000FFEC8 65 2C4H 000FFEC4 66 2C0H 000FFEC0 67 2BCH 000FFEBC 68 2B8H 000FFEB8 69 454H 455H 456H 457H (458H) 459H 45AH 45BH 45CH 45DH 45EH 45FH 460H DS705-00001-2v1-E MB91460T Series Interrupt number Interrupt LIN-USART 11 RX Decimal Hexadecimal 82 52 LIN-USART 11 TX 83 53 Reserved 84 54 Interrupt level *1 Setting Register Register address ICR33 461H ICR34 Reserved 85 55 Reserved 86 56 ICR35 Reserved 87 57 Reserved 88 58 ICR36 Reserved 89 59 Reserved 90 5A ICR37 Reserved 91 5B Input Capture 0 92 5C ICR38 Input Capture 1 93 5D Input Capture 2 94 5E ICR39 Input Capture 3 95 5F Input Capture 4 96 60 ICR40 Input Capture 5 97 61 Input Capture 6 98 62 ICR41 Input Capture 7 99 63 Output Compare 0 100 64 ICR42 Output Compare 1 101 65 Output Compare 2 102 66 ICR43 Output Compare 3 103 67 Output Compare 4 104 68 ICR44 Output Compare 5 105 69 Output Compare 6 106 6A ICR45 Interrupt vector *2 DMA *3 Resource Number Offset Default Vector address 2B4H 000FFEB4 70 2B0H 000FFEB0 71 2ACH 000FFEAC 72 2A8H 000FFEA8 73 2A4H 000FFEA4 74 2A0H 000FFEA0 75 29CH 000FFE9C 76 298H 000FFE98 77 294H 000FFE94 78 290H 000FFE90 79 28CH 000FFE8C 80 288H 000FFE88 81 284H 000FFE84 82 280H 000FFE80 83 27CH 000FFE7C 84 278H 000FFE78 85 274H 000FFE74 86 270H 000FFE70 87 26CH 000FFE6C 88 268H 000FFE68 89 264H 000FFE64 90 260H 000FFE60 91 25CH 000FFE5C 92 258H 000FFE58 93 254H 000FFE54 94 462H 463H 464H 465H 466H 467H 468H 469H 46AH 46BH 46CH 46DH Output Compare 7 107 6B 250H 000FFE50 95 Sound Generator 108 6C 24CH 000FFE4C - Phase Frequency Modulator 109 6D 248H 000FFE48 - DS705-00001-2v1-E ICR46 46EH 85 MB91460T Series Interrupt number Interrupt System reserved Decimal Hexadecimal 110 6E System reserved 111 6F PPG 0 112 70 Interrupt level *1 Setting Register Register address ICR47 *4 46FH ICR48 PPG 1 113 71 PPG 2 114 72 ICR49 PPG 3 115 73 PPG 4 116 74 ICR50 PPG 5 117 75 Reserved 118 76 ICR51 Reserved 119 77 PPG 8 120 78 ICR52 PPG 9 121 79 PPG 10 122 7A ICR53 PPG 11 123 7B PPG 12 124 7C ICR54 PPG 13 125 7D PPG 14 126 7E ICR55 PPG 15 127 7F Up/Down Counter 0 128 80 ICR56 Up/Down Counter 1 129 81 Up/Down Counter 2 130 82 ICR57 Up/Down Counter 3 131 83 Real Time Clock 132 84 ICR58 Calibration Unit 133 85 A/D Converter 0 134 86 ICR59 Interrupt vector *2 DMA *3 Resource Number Offset Default Vector address 244H 000FFE44 - 240H 000FFE40 - 23CH 000FFE3C 15, 96 238H 000FFE38 97 234H 000FFE34 98 230H 000FFE30 99 22CH 000FFE2C 100 228H 000FFE28 101 224H 000FFE24 102 220H 000FFE20 103 21CH 000FFE1C 104 218H 000FFE18 105 214H 000FFE14 106 210H 000FFE10 107 20CH 000FFE0C 108 208H 000FFE08 109 204H 000FFE04 110 200H 000FFE00 111 1FCH 000FFDFC - 1F8H 000FFDF8 - 1F4H 000FFDF4 - 1F0H 000FFDF0 - 1ECH 000FFDEC - 1E8H 000FFDE8 - 1E4H 000FFDE4 14, 112 470H 471H 472H 473H 474H 475H 476H 477H 478H 479H 47AH 47BH - 135 87 1E0H 000FFDE0 - Reserved 136 88 1DCH 000FFDD C - 1D8H 000FFDD8 - ICR60 Reserved 86 137 89 47CH DS705-00001-2v1-E MB91460T Series Interrupt number Interrupt Low Voltage Detection Decimal Hexadecimal 138 8A Interrupt level *1 Setting Register Register address ICR61 47DH Interrupt vector *2 DMA *3 Resource Number Offset Default Vector address 1D4H 000FFDD4 - Reserved 139 8B 1D0H 000FFDD0 - Timebase Overflow 140 8C 1CCH 000FFDC C - ICR62 47EH PLL Clock Gear 141 8D 1C8H 000FFDC8 - DMA Controller 142 8E 1C4H 000FFDC4 - Main/Sub OSC stability wait 143 8F 1C0H 000FFDC0 - Security vector 144 90 - - 1BCH 000FFDBC - Used by the INT instruction 145 to 255 91 to FF - - 1B8H to 000H 000FFDB8 to 000FFC00 - ICR63 47FH *1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : DMA Resource Number is the resource number used for DMA operation. No number means that this resource interrupt cannot be used to trigger a DMA transfer. *4 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]). *5 : Used by REALOS *6 : Memory Protection Unit (MPU) support DS705-00001-2v1-E 87 MB91460T Series ■ RECOMMENDED SETTINGS 1. PLL and Clockgear settings Please note that for MB91F467TA the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash *1. Please note that for MB91F469TA the core base clock frequencies are valid in the 1.9V operation mode of the Main regulator and Flash *2. Please refer to “Absolute maximum ratings” on page 94 to find the maximum allowed frequency of Core Base Clock (fCLKB) at high temperature. Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Core Base Output (X) Clock [MHz] [MHz] DIVM DIVN DIVG MULG 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12 Remarks MULG *1 : Keep REGSEL_FLASHSEL=0 and REGSEL_MAINSEL=0 at their initial value *2 : Set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1 88 DS705-00001-2v1-E MB91460T Series 2. Clock Modulator settings The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Please refer to “Absolute maximum ratings” on page 94 to find the maximum allowed frequency of Fmax (fCLKB) at high temperature. Clock Modulator settings, frequency range and supported supply voltage Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 3 026F 88 79.5 98.5 1 3 026F 84 76.1 93.8 1 3 026F 80 72.6 89.1 1 5 02AE 80 68.7 95.8 2 3 046E 80 68.7 95.8 1 3 026F 76 69.1 84.5 1 5 02AE 76 65.3 90.8 1 7 02ED 76 62 98.1 2 3 046E 76 65.3 90.8 3 3 066D 76 62 98.1 1 3 026F 72 65.5 79.9 1 5 02AE 72 62 85.8 1 7 02ED 72 58.8 92.7 2 3 046E 72 62 85.8 3 3 066D 72 58.8 92.7 1 3 026F 68 62 75.3 1 5 02AE 68 58.7 80.9 1 7 02ED 68 55.7 87.3 1 9 032C 68 53 95 2 3 046E 68 58.7 80.9 2 5 04AC 68 53 95 3 3 066D 68 55.7 87.3 4 3 086C 68 53 95 1 3 026F 64 58.5 70.7 1 5 02AE 64 55.3 75.9 1 7 02ED 64 52.5 82 1 9 032C 64 49.9 89.1 1 11 036B 64 47.6 97.6 2 3 046E 64 55.3 75.9 2 5 04AC 64 49.9 89.1 DS705-00001-2v1-E 89 MB91460T Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 3 3 066D 64 52.5 82 4 3 086C 64 49.9 89.1 5 3 0A6B 64 47.6 97.6 1 3 026F 60 54.9 66.1 1 5 02AE 60 51.9 71 1 7 02ED 60 49.3 76.7 1 9 032C 60 46.9 83.3 1 11 036B 60 44.7 91.3 2 3 046E 60 51.9 71 2 5 04AC 60 46.9 83.3 3 3 066D 60 49.3 76.7 4 3 086C 60 46.9 83.3 5 3 0A6B 60 44.7 91.3 1 3 026F 56 51.4 61.6 1 5 02AE 56 48.6 66.1 1 7 02ED 56 46.1 71.4 1 9 032C 56 43.8 77.6 1 11 036B 56 41.8 84.9 1 13 03AA 56 39.9 93.8 2 3 046E 56 48.6 66.1 2 5 04AC 56 43.8 77.6 2 7 04EA 56 39.9 93.8 3 3 066D 56 46.1 71.4 3 5 06AA 56 39.9 93.8 4 3 086C 56 43.8 77.6 5 3 0A6B 56 41.8 84.9 6 3 0C6A 56 39.9 93.8 1 3 026F 52 47.8 57 1 5 02AE 52 45.2 61.2 1 7 02ED 52 42.9 66.1 1 9 032C 52 40.8 71.8 1 11 036B 52 38.8 78.6 1 13 03AA 52 37.1 86.8 1 15 03E9 52 35.5 96.9 2 3 046E 52 45.2 61.2 2 5 04AC 52 40.8 71.8 2 7 04EA 52 37.1 86.8 90 DS705-00001-2v1-E MB91460T Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 3 3 066D 52 42.9 66.1 3 5 06AA 52 37.1 86.8 4 3 086C 52 40.8 71.8 5 3 0A6B 52 38.8 78.6 6 3 0C6A 52 37.1 86.8 7 3 0E69 52 35.5 96.9 1 3 026F 48 44.2 52.5 1 5 02AE 48 41.8 56.4 1 7 02ED 48 39.6 60.9 1 9 032C 48 37.7 66.1 1 11 036B 48 35.9 72.3 1 13 03AA 48 34.3 79.9 1 15 03E9 48 32.8 89.1 2 3 046E 48 41.8 56.4 2 5 04AC 48 37.7 66.1 2 7 04EA 48 34.3 79.9 3 3 066D 48 39.6 60.9 3 5 06AA 48 34.3 79.9 4 3 086C 48 37.7 66.1 5 3 0A6B 48 35.9 72.3 6 3 0C6A 48 34.3 79.9 7 3 0E69 48 32.8 89.1 1 3 026F 44 40.6 48.1 1 5 02AE 44 38.4 51.6 1 7 02ED 44 36.4 55.7 1 9 032C 44 34.6 60.4 1 11 036B 44 33 66.1 1 13 03AA 44 31.5 73 1 15 03E9 44 30.1 81.4 2 3 046E 44 38.4 51.6 2 5 04AC 44 34.6 60.4 2 7 04EA 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066D 44 36.4 55.7 3 5 06AA 44 31.5 73 4 3 086C 44 34.6 60.4 4 5 08A8 44 28.9 92.1 DS705-00001-2v1-E 91 MB91460T Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 5 3 0A6B 44 33 66.1 6 3 0C6A 44 31.5 73 7 3 0E69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026F 40 37 43.6 1 5 02AE 40 34.9 46.8 1 7 02ED 40 33.1 50.5 1 9 032C 40 31.5 54.8 1 11 036B 40 30 59.9 1 13 03AA 40 28.7 66.1 1 15 03E9 40 27.4 73.7 2 3 046E 40 34.9 46.8 2 5 04AC 40 31.5 54.8 2 7 04EA 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066D 40 33.1 50.5 3 5 06AA 40 28.7 66.1 3 7 06E7 40 25.3 95.8 4 3 086C 40 31.5 54.8 4 5 08A8 40 26.3 83.3 5 3 0A6B 40 30 59.9 6 3 0C6A 40 28.7 66.1 7 3 0E69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026F 36 33.3 39.2 1 5 02AE 36 31.5 42 1 7 02ED 36 29.9 45.3 1 9 032C 36 28.4 49.2 1 11 036B 36 27.1 53.8 1 13 03AA 36 25.8 59.3 1 15 03E9 36 24.7 66.1 2 3 046E 36 31.5 42 2 5 04AC 36 28.4 49.2 2 7 04EA 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066D 36 29.9 45.3 92 DS705-00001-2v1-E MB91460T Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 3 5 06AA 36 25.8 59.3 3 7 06E7 36 22.8 85.8 4 3 086C 36 28.4 49.2 4 5 08A8 36 23.7 74.7 5 3 0A6B 36 27.1 53.8 6 3 0C6A 36 25.8 59.3 7 3 0E69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026F 32 29.7 34.7 1 5 02AE 32 28 37.3 1 7 02ED 32 26.6 40.2 1 9 032C 32 25.3 43.6 1 11 036B 32 24.1 47.7 1 13 03AA 32 23 52.5 1 15 03E9 32 22 58.6 2 3 046E 32 28 37.3 2 5 04AC 32 25.3 43.6 2 7 04EA 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066D 32 26.6 40.2 3 5 06AA 32 23 52.5 3 7 06E7 32 20.3 75.9 4 3 086C 32 25.3 43.6 4 5 08A8 32 21.1 66.1 5 3 0A6B 32 24.1 47.7 5 5 0AA6 32 19.5 89.1 6 3 0C6A 32 23 52.5 7 3 0E69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 DS705-00001-2v1-E 93 MB91460T Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Parameter Symbol Rating Unit Min Max ⎯ ⎯ 50 V/ms Power supply voltage 1* VDD5R - 0.3 + 6.0 V Power supply voltage 2*1 VDD5 - 0.3 + 6.0 V Power supply voltage 4*1 VDD35 - 0.3 + 6.0 V Power supply slew rate 1 Relationship of the supply voltages VDD5-0.3 VDD5+0.3 V VSS5-0.3 VDD5+0.3 V AVCC5 Remarks At least one pin of the Ports 25 to 29 (AN*) is used as digital input or output. All pins of the Ports 25 to 29 (AN*) follow the condition of VIA Analog power supply voltage*1 AVCC5 - 0.3 + 6.0 V *2 Analog reference power supply voltage*1 AVRH - 0.3 + 6.0 V *2 VI1 Vss5 - 0.3 VDD5 + 0.3 V VI2 Vss5 - 0.3 VDD35 + 0.3 V Input voltage 1*1 1 Input voltage 2* 1 External bus VIA AVss5 - 0.3 AVcc5 + 0.3 V Output voltage 1* 1 VO1 Vss5 - 0.3 VDD5 + 0.3 V Output voltage 2* 1 VO2 Vss5 - 0.3 VDD35 + 0.3 V ICLAMP - 4.0 + 4.0 mA *3 Σ |ICLAMP| ⎯ 20 mA *3 IOL ⎯ 10 mA “L” level average output current*5 IOLAV ⎯ 8 mA “L” level total maximum output current ΣIOL ⎯ 100 mA ΣIOLAV ⎯ 50 mA IOH ⎯ - 10 mA “H” level average output current*5 IOHAV ⎯ -4 mA “H” level total maximum output current ΣIOH ⎯ - 100 mA ΣIOHAV ⎯ - 25 mA Analog pin input voltage* Maximum clamp current Total maximum clamp current “L” level maximum output current*4 “L” level total average output current*6 “H” level maximum output current*4 “H” level total average output current*6 94 External bus DS705-00001-2v1-E MB91460T Series Parameter Permitted operating frequency MB91F467TA, MB91F467TAH, MB91F469TA Permitted operating frequency MB91F467TAH Permitted power dissipation *7 Operating temperature Storage temperature Symbol Rating Unit Remarks Min Max fmax, CLKB ⎯ 100 fmax, CLKP ⎯ 50 fmax, CLKT ⎯ 50 fmax, CLKCAN ⎯ 50 fmax, CLKB ⎯ 96 fmax, CLKP ⎯ 48 fmax, CLKT ⎯ 48 fmax, CLKCAN ⎯ 48 ⎯ 1300 *8 mW TA ≤ 75 °C ⎯ *8 mW TA ≤ 85 °C mW TA ≤ 105 °C 1150 MHz TA ≤ 105 °C MHz 105 °C ≤ TA ≤ 125 °C ⎯ 570 ⎯ 1300 *8 mW TA ≤ 100 °C, no Flash program/erase *9 ⎯ 1000 *8 mW TA ≤ 115 °C, no Flash program/erase *9 ⎯ 750 *8 mW TA ≤ 125 °C, no Flash program/erase *9 TA - 40 TA(max) °C For TA(max), refer to the ordering information Tstg - 55 + 150 °C PD *8 *1 : The parameter is based on VSS5 = 0.0 V. *2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V. *3 : • Use within recommended operating conditions. • Use with DC voltage (current). • +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. • The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal is input. • Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. • Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the microcontroller may partially operate. • Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. DS705-00001-2v1-E 95 MB91460T Series • Do not leave +B input pins open. • Example of recommended circuit : • Input/output equivalent circuit Protective diode VCC Limiting resistor P-ch +B input (0 V to 16 V) N-ch R *4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. *7 : The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = Σ (|VSS-VOL| * IOL + |VDD-VOH| * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VDD5R * ICC + AVCC5 * IA + AVRH5 * IR (internal power dissipation) *8 : Worst case value for the QFP package mounted on a 4-layer PCB at specified TA without air flow. *9 : Please contact Fujitsu for reliability limitations when using under these conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. WARNING: 96 DS705-00001-2v1-E MB91460T Series 2. Recommended operating conditions (VSS5 = 0.0 V) Parameter Power supply voltage Smoothing capacitor at VCC18C pin Symbol Max VDD5 3.0 ⎯ 5.5 V VDD5R 3.0 ⎯ 5.5 V Internal regulator VDD35 3.0 ⎯ 5.5 V External bus AVCC5 3.0 ⎯ 5.5 V A/D converter CS ⎯ 4.7 ⎯ μF Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. ⎯ ⎯ 50 V/ms − 40 ⎯ TA(max) °C TA 10 0.6 Vsurge 2 fRC100kHz fRC2MHz 50 1 For TA(max), refer to the ordering information ms Lock-up time PLL (4 MHz ->16 ...100MHz) RC Oscillator Remarks Typ Main Oscillation stabilization time ESD Protection (Human body model) Unit Min Power supply slew rate Operating temperature Value ms kV 100 2 200 4 Rdischarge = 1.5kΩ Cdischarge = 100pF kHz VDDCORE > 1.65V MHz WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. WARNING: VCC18C VSS5 AVSS5 CS DS705-00001-2v1-E 97 MB91460T Series 3. DC characteristics Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins. In the following tables, “VSS” means VSS5 for all pins. (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to TA(max)) Parameter Symbol Pin name Min Unit Remarks Typ Max ⎯ VDD + 0.3 V CMOS hysteresis input ⎯ VDD + 0.3 V 4.5 V < VDD < 5.5 V ⎯ VDD + 0.3 V 3 V < VDD < 4.5 V Port inputs if CMOS Hysteresis 0.8/0.2 0.8 × VDD input is selected ⎯ Port inputs if CMOS 0.7 × VDD Hysteresis 0.7/0.3 0.74 × VDD input is selected ⎯ AUTOMOTIVE Hysteresis input is selected 0.8 × VDD ⎯ VDD + 0.3 V ⎯ Port inputs if TTL input is selected 2.0 ⎯ VDD + 0.3 V VIHR INITX ⎯ 0.8 × VDD ⎯ VDD + 0.3 V INITX input pin (CMOS Hysteresis) VIHM MD_2 to MD_0 ⎯ VDD − 0.3 ⎯ VDD + 0.3 V Mode input pins VIHX0S X0, X0A ⎯ 2.5 ⎯ VDD + 0.3 V External clock in “Oscillation mode” VIHX0F X0 ⎯ 0.8 × VDD ⎯ VDD + 0.3 V External clock in “Fast Clock Input mode” ⎯ Port inputs if CMOS Hysteresis 0.8/0.2 input is selected VSS − 0.3 ⎯ 0.2 × VDD V ⎯ Port inputs if CMOS Hysteresis 0.7/0.3 input is selected VSS − 0.3 ⎯ 0.3 × VDD V VSS − 0.3 ⎯ 0.5 × VDD V 4.5 V < VDD < 5.5 V ⎯ Port inputs if AUTOMOTIVE Hysteresis input is selected VSS − 0.3 ⎯ 0.46 × VDD V 3 V < VDD < 4.5 V ⎯ Port inputs if TTL input is selected VSS − 0.3 ⎯ 0.8 V VIL Input “L” voltage 98 Value ⎯ VIH Input “H” voltage Condition VILR INITX ⎯ VSS − 0.3 ⎯ 0.2 × VDD V INITX input pin (CMOS Hysteresis) VILM MD_2 to MD_0 ⎯ VSS − 0.3 ⎯ VSS + 0.3 V Mode input pins VILXDS X0, X0A ⎯ VSS − 0.3 ⎯ 0.5 V External clock in “Oscillation mode” DS705-00001-2v1-E MB91460T Series (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to TA(max)) Parameter Input “L” voltage Output “H” voltage Symbol Pin name Condition VILXDF X0 ⎯ VOH2 Normal outputs VOH5 Normal outputs VOH3 I2C outputs VOL2 Output “L“ voltage Input leakage current Normal outputs VOL5 Normal outputs VOL3 I2C outputs IIL Pnn_m *1 Value Max VSS − 0.3 ⎯ 0.2 × VDD V External clock in “Fast Clock Input mode” VDD − 0.5 ⎯ ⎯ V Driving strength set to 2 mA VDD − 0.5 ⎯ ⎯ V Driving strength set to 5 mA 3.0V ≤ VDD ≤ 5.5V, VDD − 0.5 IOH = − 3mA ⎯ ⎯ V ⎯ ⎯ 0.4 V Driving strength set to 2 mA ⎯ ⎯ 0.4 V Driving strength set to 5 mA 3.0V ≤ VDD ≤ 5.5V, IOL = + 3mA ⎯ ⎯ 0.4 V 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA=25 °C −1 ⎯ +1 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA=TA(max) −3 ⎯ +3 3.0V ≤ VDD ≤ 5.5V TA=25 °C −1 ⎯ +1 μA 3.0V ≤ VDD ≤ 5.5V TA=TA(max) −3 ⎯ +3 μA 4.5V ≤ VDD ≤ 5.5V, IOH = − 2mA 3.0V ≤ VDD ≤ 4.5V, IOH = − 1.6mA 4.5V ≤ VDD ≤ 5.5V, IOH = − 5mA 3.0V ≤ VDD ≤ 4.5V, IOH = − 3mA 4.5V ≤ VDD ≤ 5.5V, IOL = + 2mA 3.0V ≤ VDD ≤ 4.5V, IOL = + 1.6mA 4.5V ≤ VDD ≤ 5.5V, IOL = + 5mA 3.0V ≤ VDD ≤ 4.5V, IOL = + 3mA μA IAIN Pull-up resistance RUP Pnn_m *4, INITX 3.0V ≤ VDD ≤ 3.6V 40 100 160 4.5V ≤ VDD ≤ 5.5V 25 50 100 Pull-down resistance RDOWN Pnn_m *4 3.0V ≤ VDD ≤ 3.6V 40 100 180 4.5V ≤ VDD ≤ 5.5V 25 50 100 DS705-00001-2v1-E Remarks Typ Analog input leakage current ANn *3 Unit Min kΩ kΩ 99 MB91460T Series Parameter Input capacitance Symbol CIN ICC ICCH Pin name VDD5R VDD5R Value Unit Min Typ Max - 5 15 pF CLKB: 100 MHz CLKP: 50 MHz CLKT: 50 MHz CLKCAN: 50 MHz ⎯ 110 140 mA TA = + 25 °C ⎯ 30 150 μA TA = + 105 °C ⎯ 300 2000 μA TA = + 125 °C ⎯ 600 4000 μA TA = + 25 °C ⎯ 100 500 μA TA = + 105 °C ⎯ 500 2200 μA TA = + 125 °C ⎯ 800 4400 μA TA = + 25 °C ⎯ 50 250 μA TA = + 105 °C ⎯ 400 2100 TA = + 125 °C ⎯ 700 4200 μA All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS, AVRH5 Power supply current MB91F467TA Remarks Code fetch from Flash At stop mode *2 RTC : 4 MHz mode *2 RTC : 100 kHz mode *2 32 kHz mode *5 ILVE VDD5 ⎯ ⎯ 70 150 μA External low voltage detection ILVI VDD5R ⎯ ⎯ 50 100 μA Internal low voltage detection ⎯ ⎯ 250 500 μA Main clock (4 MHz) ⎯ ⎯ 20 40 μA Sub clock (32 kHz) IOSC 100 Condition VDD5 DS705-00001-2v1-E MB91460T Series Parameter Symbol ICC ICCH Pin name Condition VDD5R VDD5R Power supply current MB91F469TA (target data) Value Unit Remarks Min Typ Max CLKB: 100 MHz CLKP: 50 MHz CLKT: 50 MHz CLKCAN: 50 MHz ⎯ 140 170 mA TA = + 25 °C ⎯ 50 210 μA TA = + 105 °C ⎯ 0.6 2.8 mA TA = + 25 °C ⎯ 120 560 μA TA = + 105 °C ⎯ 0.7 3.2 RTC : *2 mA 4 MHz mode TA = + 25 °C ⎯ 70 310 μA TA = + 105 °C ⎯ 0.65 3.0 RTC : 100 kHz mode*2 mA 32 kHz mode *5 Code fetch from Flash At stop mode*2 ILVE VDD5 ⎯ ⎯ 70 150 μA External low voltage detection ILVI VDD5R ⎯ ⎯ 50 100 μA Internal low voltage detection ⎯ ⎯ 250 500 μA Main clock (4 MHz) ⎯ ⎯ 20 40 μA Sub clock (32 kHz) IOSC VDD5 *1 Pnn_m includes all pins unless the pins, which include analog inputs. *2 Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled. *3 ANn includes all pins where AN channels are enabled. *4 Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. *5 Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled, RC oscillator enabled. Additional current consumption of Sub oscillator IOSC has to be taken into account. DS705-00001-2v1-E 101 MB91460T Series 4. A/D converter characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to TA(max)) Parameter Symbol Pin name Value Min Typ Max Unit Resolution ⎯ ⎯ ⎯ ⎯ 10 bit Total error ⎯ ⎯ -3 ⎯ +3 LSB Nonlinearity error ⎯ ⎯ - 2.5 ⎯ + 2.5 LSB Differential nonlinearity error ⎯ ⎯ - 1.9 ⎯ + 1.9 LSB Zero reading voltage VOT ANn AVRL-1.5 AVRL + 0.5 AVRL + 2.5 LSB LSB LSB V Full scale reading voltage VFST ANn AVRH-3.5 LSB V Compare time Sampling time Conversion time Input capacitance Input resistance Tcomp Tsamp Tconv CIN RIN AVRH−1.5 AVRH + 0.5 LSB LSB 0.6 ⎯ 16,500 μs 4.5 V < AVCC5 < 5.5 V 2.0 ⎯ ⎯ μs 3.0 V < AVCC5 < 4.5 V 0.4 ⎯ ⎯ μs 4.5 V < AVCC5 < 5.5 V, REXT < 2 kΩ 1.0 ⎯ ⎯ μs 3.0 V < AVCC5 < 4.5 V, REXT < 1 kΩ 1.0 ⎯ ⎯ μs 4.5 V < AVCC5 < 5.5 V 3.0 ⎯ ⎯ μs 3.0 V < AVCC5 < 4.5 V ⎯ ⎯ 11 pF ⎯ ⎯ 2.6 kΩ 4.5 V < AVCC5 < 5.5 V ⎯ ⎯ 12.1 kΩ 3.0 V < AVCC5 < 4.5 V -1 ⎯ +1 μA TA = + 25 °C -3 ⎯ +3 μA TA = + 105 °C ⎯ ⎯ ⎯ ANn ANn Analog input leakage current IAIN ANn Analog input voltage range VAIN ANn AVRL ⎯ AVRH V ⎯ ANn ⎯ ⎯ 4 LSB Offset between input channels Remarks (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller 102 DS705-00001-2v1-E MB91460T Series (Continued) Parameter Symbol Pin name Reference voltage current per ADC macro *3 Min Typ Max Unit Remarks AVRH AVRH5 0.75 × AVCC5 ⎯ AVCC5 V AVRL AVSS5 AVSS5 ⎯ AVCC5 × 0.25 V IA AVCC5 ⎯ 2.5 5 mA A/D Converter active IAH AVCC5 ⎯ ⎯ 5 μA A/D Converter not operated *1 IR AVRH5 ⎯ 0.7 1 mA A/D Converter active IRH AVRH5 ⎯ ⎯ 5 μA A/D Converter not operated *2 Reference voltage range Power supply current per ADC macro *3 Value *1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the current values have to be multiplied by the number of macros. Sampling Time Calculation Tsamp = (2.25 kOhm + REXT) × 10.7pF × 7; Tsamp = (13.6 kOhm + REXT) × 10.7pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V for 3.0V ≤ AVCC5 ≤ 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp DS705-00001-2v1-E 103 MB91460T Series Definition of A/D converter terms • Resolution Analog variation that is recognizable by the A/D converter. • Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B). • Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. • Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. Total error 3FFH 3FEH 1.5 LSB’ Actual conversion characteristics Digital output 3FDH {1 LSB’ (N - 1) + 0.5 LSB’} 004H VNT (measurement value) 003H Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB' AVSS5 AVRH Analog input 1LSB' (ideal value) = AVRH − AVSS5 [V] 1024 Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued) 104 DS705-00001-2v1-E MB91460T Series (Continued) Nonlinearity error 3FFH Differential nonlinearity error Actual conversion characteristics Actual conversion characteristics (N+1)H 3FEH {1 LSB (N - 1) + VOT} VFST 004H VNT (measurement value) 003H 002H Ideal characteristics (measurement value) Digital output Digital output 3FDH NH (N-1)H VFST Actual conversion characteristics VNT (measurement value) Ideal characteristics (N-2)H 001H Actual conversion characteristics VTO (measurement value) AVSS5 AVSS5 AVRH Analog input Nonlinearity error of digital output N = VFST − VOT 1022 AVRH Analog input VNT − {1LSB × (N − 1) + VOT} [LSB] 1LSB Differential nonlinearity error of digital output N = 1LSB = (measurement value) V (N + 1) T − VNT 1LSB − 1 [LSB] [V] N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH. DS705-00001-2v1-E 105 MB91460T Series 5. FLASH memory program/erase characteristics 5.1. MB91F467TA, MB91F469TA (TA = 25oC, Vcc = 5.0V) Parameter Value Unit Remarks 2.0 s Erasure programming time not included n*0.5 n*2.0 s n is the number of Flash sector of the device 6 100 μs System overhead time not included Min Typ Max Sector erase time - 0.5 Chip erase time - Word programming time - Programme/Erase cycle 10 000 cycle Flash data retention time 20 year *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 106 DS705-00001-2v1-E MB91460T Series 6. AC characteristics 6.1. Clock timing (VDD5 = 3.0 V to 5.5 V, Vss5 = 0 V, TA = −40°C to TA(max)) Parameter Symbol Pin name Clock frequency fC Value Unit Condition 16 MHz Opposite phase external supply or crystal 100 kHz Min Typ Max X0 X1 3.5 4 X0A X1A 32 32.768 • Clock timing condition tC X0, X1, X0A, X1A 0.8 VCC 0.2 VCC PWH DS705-00001-2v1-E PWL 107 MB91460T Series 6.2. Reset input ratings (VDD5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40°C to TA(max)) Parameter INITX input time (at power-on) INITX input time (other than the above) Symbol tINTL Pin name Condition Value Unit Min Max 10 ⎯ ms 20 ⎯ μs ⎯ INITX tINTL INITX 108 0.2 VCC DS705-00001-2v1-E MB91460T Series 6.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements • All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - TA = -40 to TA(max) - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 x VDD5, - VOH = 0.8 x VDD5 - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40°C to TA(max)) Parameter Symbol Pin name Serial clock cycle time tSCYCI SCKn SCK ↓ → SOT delay time tSLOVI SCKn SOTn SOT → SCK ↓ delay time tOVSHI SCKn SOTn Valid SIN → SCK ↑ setup time tIVSHI SCKn SINn SCK ↑ → valid SIN hold time tSHIXI Serial clock “H” pulse width Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Unit Min Max Min Max 4 tCLKP ⎯ 4 tCLKP ⎯ ns - 30 30 - 20 20 ns m× tCLKP - 30* ⎯ m× tCLKP - 20* ⎯ ns tCLKP + 55 ⎯ tCLKP + 45 ⎯ ns SCKn SINn 0 ⎯ 0 ⎯ ns tSHSLE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn SOTn ⎯ 2 tCLKP + 55 ⎯ 2 tCLKP + 45 ns Valid SIN → SCK ↑ setup time tIVSHE SCKn SINn 10 ⎯ 10 ⎯ ns SCK ↑ → valid SIN hold time tSHIXE SCKn SINn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK rising time tFE SCKn ⎯ 20 ⎯ 20 ns SCK falling time tRE SCKn ⎯ 20 ⎯ 20 ns Internal clock operation (master mode) External clock operation (slave mode) * : Parameter m depends on tSCYCI and can be calculated as : • if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. DS705-00001-2v1-E 109 MB91460T Series • Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOH VOL VOL VOH SCKn for ESCR:SCES = 1 VOH VOL tSLOVI tOVSHI VOH VOL SOTn tIVSHI tSHIXI VIH VIL SINn VIH VIL • External clock mode (slave mode) tSLSHE SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tSHSLE VOH VOL VOL VOH VOH VOL VOH VOL tRE tFE tSLOVE SOTn VOH VOL tIVSHE SINn 110 VIH VIL tSHIXE VIH VIL DS705-00001-2v1-E MB91460T Series 6.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - TA = − 40 °C to TA(max) - Cl = 50 pF - VOL = 0.3 × VDD5 - VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to TA(max)) Parameter Symbol Pin name fSCL Value Unit Min Max SCLn 0 400 kHz tHD;STA SCLn, SDAn 0.6 ⎯ μs LOW period of the SCL clock tLOW SCLn 1.3 ⎯ μs HIGH period of the SCL clock tHIGH SCLn 0.6 ⎯ μs Setup time for a repeated START condition tSU;STA SCLn, SDAn 0.6 ⎯ μs Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 μs Data setup time tSU;DAT SCLn SDAn 100 ⎯ ns Rise time of both SDA and SCL signals tr SCLn, SDAn 20 + 0.1Cb 300 ns Fall time of both SDA and SCL signals tf SCLn, SDAn 20 + 0.1Cb 300 ns Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 ⎯ μs Bus free time between a STOP and START condition tBUF SCLn, SDAn 1.3 ⎯ μs Capacitive load for each bus line Cb SCLn, SDAn ⎯ 400 pF Pulse width of spike suppressed by input filter tSP SCLn, SDAn 0 (1..1.5) × tCLKP ns SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated Remark *1 *1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. DS705-00001-2v1-E 111 112 SCL SDA tHD;STA tf S tr tHD;DAT tLOW tHIGH tSU;DAT tSU;STA Sr tHD;STA tSP tr P tSU;STO tBUF S tf MB91460T Series DS705-00001-2v1-E MB91460T Series 6.5. Free-run timer clock (VDD5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to TA(max)) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL CKn ⎯ Value Min Max 4tCLKP ⎯ Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn tTIWH 6.6. tTIWL Trigger input timing (VDD5 = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to TA(max)) Parameter Input capture input trigger A/D converter trigger Symbol Pin name Condition tINP ICUn tATGX ATGX Value Unit Min Max ⎯ 5tCLKP ⎯ ns ⎯ 5tCLKP ⎯ ns Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX DS705-00001-2v1-E 113 MB91460T Series 6.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 5 mA - VSS5 = 0 V - TA = − 40 °C to TA(max) - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 6.7.1. Basic Timing (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to Address valid delay time Symbol tCLCH tCHCL Pin name Max 1/2 × tCLKT − 7 1/2 × tCLKT + 7 ns 1/2 × tCLKT − 7 1/2 × tCLKT + 7 ns ⎯ 9 ns ⎯ 8 ns −5 +2 ns SYSCLK ASX ⎯ 8 ns ⎯ 8 ns SYSCLK A23 to A0 ⎯ 11 ns SYSCLK SYSCLK CSXn tCHCSL tCLASL tCLASH tCLAV Unit Min tCLCSL tCLCSH Value Note : tCLKT is the cycle time of the external bus clock. 114 DS705-00001-2v1-E MB91460T Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS DS705-00001-2v1-E 115 MB91460T Series 6.7.2. Synchronous/Asynchronous read access (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter SYSCLK ↑ to RDX delay time Symbol Pin name TCHRL SYSCLK RDX TCHRH Value Unit Min Max −5 2 ns −5 2 ns Data valid to RDX ↑ setup time TDSRH RDX D31 to D16 20 ⎯ ns RDX ↑ to Data valid hold time TRHDX RDX D31 to D16 0 ⎯ ns ⎯ 9 ns −1 ⎯ ns ⎯ 9 ns ⎯ 8 ns TCLWRL SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRH TCLCSL SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK WRXn SYSCLK CSXn SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN 116 DS705-00001-2v1-E MB91460T Series 6.7.3. Synchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter SYSCLK ↓ to WEX delay time Symbol Pin name TCLWL TCLWH Value Unit Min Max SYSCLK WEX ⎯ 9 ns 2 ⎯ ns Data valid to WEX ↓ setup time TDSWL WEX D31 to D16 − 11 ⎯ ns WEX ↑ to Data valid hold time TWHDH WEX D31 to D16 tCLKT − 10 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRL SYSCLK WRXn ⎯ 9 ns −1 ⎯ ns ⎯ 9 ns ⎯ 8 ns SYSCLK ↓ to CSXn delay time TCLWRH TCLCSL SYSCLK CSXn TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT DS705-00001-2v1-E 117 MB91460T Series 6.7.4. Synchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter SYSCLK ↓ to WRXn delay time Symbol Pin name TCLWRL SYSCLK WRXn TCLWRH Value Unit Min Max ⎯ 9 ns −1 ⎯ ns Data valid to WRXn ↓ setup time TDSWRL WRXn D31 to D16 − 12 ⎯ ns WRXn ↑ to Data valid hold time TWRHDH WRXn D31 to D16 tCLKT − 8 ⎯ ns SYSCLK CSXn ⎯ 9 ns ⎯ 8 ns SYSCLK ↓ to CSXn delay time TCLCSL TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT 118 DS705-00001-2v1-E MB91460T Series 6.7.5. Asynchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter Symbol Pin name WEX ↓ to WEX ↑ pulse width TWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT − 2 ⎯ ns TDSWL WEX D31 to D16 1/2 × tCLKT − 13 ⎯ ns TWHDH WEX D31 to D16 1/2 × tCLKT − 10 ⎯ ns WEX WRXn ⎯ 1/2 × tCLKT + 2 ns 1/2 × tCLKT − 4 ⎯ ns ⎯ 1/2 × tCLKT ns 1/2 × tCLKT − 5 ⎯ ns TWRLWL TWHWRH TCLWL TWHCH WEX CSXn CSXn tWHCH tCLWL WRXn (as byte enable) tWHWRH tWRLWL tWLWH WEX tDSWL tWHDH DATA OUT DS705-00001-2v1-E 119 MB91460T Series 6.7.6. Asynchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = − 40 °C to TA(max)) Parameter Symbol Pin name WRXn ↓ to WRXn ↑ pulse width TWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT − 1 ⎯ ns TDSWRL WRXn D31 to D16 1/2 × tCLKT − 14 ⎯ ns TWRHDH WRXn D31 to D16 1/2 × tCLKT − 7 ⎯ ns WRXn CSXn ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT − 3 ⎯ ns TCLWRL TWRHCH CSXn tWRHCH tCLWRL tWRLWRH WRXn tDSWRL tWRHDH DATA OUT 120 DS705-00001-2v1-E MB91460T Series 6.7.7. RDY waitcycle insertion (VDD35 = 4.5 V to 5.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter Symbol Pin name RDY setup time TRDYS RDY hold time TRDYH Value Unit Min Max SYSCLK RDY 21 ⎯ ns SYSCLK RDY 0 ⎯ ns SYSCLK tRDYS tRDYH RDY DS705-00001-2v1-E 121 MB91460T Series 6.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - TA = − 40 °C to TA(max) - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 6.8.1. Basic Timing (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to Address valid delay time 122 Symbol TCLCH TCHCL Pin name Max 1/2 × tCLKT − 13 1/2 × tCLKT + 13 ns 1/2 × tCLKT − 13 1/2 × tCLKT + 13 ns ⎯ 6 ns ⎯ 7 ns − 11 0 ns SYSCLK ASX ⎯ 6 ns ⎯ 9 ns SYSCLK A23 to A0 ⎯ 13 ns SYSCLK SYSCLK CSXn TCHCSL TCLASL TCLASH TCLAV Unit Min TCLCSL TCLCSH Value DS705-00001-2v1-E MB91460T Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS DS705-00001-2v1-E 123 MB91460T Series 6.8.2. Synchronous/Asynchronous read access (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter SYSCLK ↑ to RDX delay time Symbol Pin name TCHRL SYSCLK RDX TCHRH Value Unit Min Max − 12 0 ns −9 1 ns Data valid to RDX ↑ setup time TDSRH RDX D31 to D16 29 ⎯ ns RDX ↑ to Data valid hold time (internal SYSCLK → MCLKI / /MCLKI feedback) TRHDX RDX D31 to D16 0 ⎯ ns SYSCLK WRXn ⎯ 6 ns 0 ⎯ ns SYSCLK CSXn ⎯ 6 ns ⎯ 7 ns TCLWRL SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRH TCLCSL SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN 124 DS705-00001-2v1-E MB91460T Series 6.8.3. Synchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter SYSCLK ↓ to WEX delay time Symbol Pin name TCLWL TCLWH Value Unit Min Max SYSCLK WEX ⎯ 7 ns 1 ⎯ ns Data valid to WEX ↓ setup time TDSWL WEX D31 to D16 − 20 ⎯ ns WEX ↑ to Data valid hold time TWHDH WEX D31 to D16 tCLKT − 19 ⎯ ns SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRL SYSCLK WRXn ⎯ 6 ns 0 ⎯ ns SYSCLK CSXn ⎯ 6 ns ⎯ 7 ns SYSCLK ↓ to CSXn delay time TCLWRH TCLCSL TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT DS705-00001-2v1-E 125 MB91460T Series 6.8.4. Synchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter SYSCLK ↓ to WRXn delay time Symbol Pin name TCLWRL TCLWRH Value Unit Min Max SYSCLK WRXn ⎯ 6 ns 0 ⎯ ns Data valid to WRXn ↓ setup time TDSWRL WRXn D31 to D16 − 20 ⎯ ns WRXn ↑ to Data valid hold time TWRHDH WRXn D31 to D16 tCLKT − 14 ⎯ ns SYSCLK CSXn ⎯ 6 ns ⎯ 7 ns SYSCLK ↓ to CSXn delay time TCLCSL TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT 126 DS705-00001-2v1-E MB91460T Series 6.8.5. Asynchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter Symbol Pin name WEX ↓ to WEX ↑ pulse width TWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT − 2 ⎯ ns TDSWL WEX D31 to D16 1/2 × tCLKT − 20 ⎯ ns TWHDH WEX D31 to D16 1/2 × tCLKT − 20 ⎯ ns WEX WRXn ⎯ 1/2 × tCLKT + 3 ns 1/2 × tCLKT − 7 ⎯ ns ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT − 4 ⎯ ns TWRLWL TWHWRH TCLWL WEX CSXn TWHCH CSXn tWHCH tCLWL WRXn (as byte enable) tWHWRH tWRLWL tWLWH WEX tDSWL tWHDH DATA OUT DS705-00001-2v1-E 127 MB91460T Series 6.8.6. Asynchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40 °C to TA(max)) Parameter Symbol Pin name WRXn ↓ to WRXn ↑ pulse width TWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT − 2 ⎯ ns TDSWRL WRXn D31 to D16 1/2 × tCLKT − 21 ⎯ ns TWRHDH WRXn D31 to D16 1/2 × tCLKT − 18 ⎯ ns WRXn CSXn ⎯ 1/2 × tCLKT − 1 ns 1/2 × tCLKT − 4 ⎯ ns TCLWRL TWRHCH CSXn tWRHCH tCLWRL tWRLWRH WRXn tDSWRL tWRHDH DATA OUT 128 DS705-00001-2v1-E MB91460T Series 6.8.7. RDY waitcycle insertion (VDD35 = 3.0 V to 4.5 V, Vss5 = 0 V, TA = −40°C to TA(max)) Parameter Symbol Pin name RDY setup time TRDYS RDY hold time TRDYH Value Unit Min Max SYSCLK RDY 37 ⎯ ns SYSCLK RDY 0 ⎯ ns SYSCLK tRDYS tRDYH RDY DS705-00001-2v1-E 129 MB91460T Series ■ ORDERING INFORMATION Part number MB91F467TAPMC-GSE2 MB91F469TAPMC-GSE2 *1 Package 144-pin plastic QFP (FPT-144P-M08) Maximum ambient temperature TA(max) + 125 °C + 105 °C Remarks Lead-free package * 1: This device is planned. 130 DS705-00001-2v1-E MB91460T Series ■ PACKAGE DIMENSION 144-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20 g Code (Reference) P-LFQFP144-20×20-0.50 (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 0.145±0.055 (.006±.002) 73 109 72 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0°~8° INDEX 144 37 "A" LEAD No. 1 36 0.50(.020) C 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) M 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS705-00001-2v1-E 131 MB91460T Series ■ REVISION HISTORY Version Date 2.0 2008-09-02 2.1 2008-11-17 Remark Initial version Pinout re-drawn Port Multiplexing: Chapter updated and pinout re-drawn Chapter Memo and Disclaimer added Notes on PS register: Updated for better readability Embedded Program/Data Memory: - Corrected Flash and Boot security vector addresses - Added note about flash memory operation mode switching - Added section Poweron Sequence in parallel programming mode Flash Security: - Corrected FSV2 table header - Sector SA23 is available on F467TA Absolute Maximum Ratings: - corrected Relationship of the supply voltages (Remarks only) - added maximal output currents DC Characteristics: - Added Analog input leakage current - Corrected Pull-Up and Pull Down resistance A/D converter characteristics - added Offset between input channels - updated drawings (regarding nonlinearity error) Chapter Memo and Disclaimer added 2.2 2009-01-09 Flash Security: added Notes About Flash Memory CRC Calculation F469T: DC characteristics: corrected the current consumption values ICC, ICCH Version 1E Page Section 2009-06-01 Change Results ■ PIN ASSIGNMENT 1. MB91F467TA, MB91F469TA Corrected the pin name (No.38) in figure. (P10_0/SYSCLK/SYSCLK → P10_0/SYSCLK) ■ PIN DESCRIPTION 1. MB91F467TA, MB91F469TA 8 Corrected "Pin name" and "Function" of the pin no.10 in the table. (A16, A17 → A16 (bit16, bit17) → (bit16) PPG8, PPG9 → PPG8) Corrected "Pin name" and "Function" of the pin no.11 in the table. (A16, A17 → A17 (bit16, bit17) → (bit17) PPG8, PPG9 → PPG9) 11 Corrected "Function" of the pin no.51 in the table. (SG0 → SGO) 6 26 132 ■ PORT MULTIPLEXING Corrected the pin name(No.38 and No.87 to No.89) in figure. 2. Multiplex Pinout MB91F467TA, (VDD5R_2 → VDD5R MB91F469TA VDD5R_1 → VDD5R VCC18C_1 → VCC18C P10_0/SYSCLK/SYSCLK → P10_0/SYSCLK) DS705-00001-2v1-E MB91460T Series Version 1E Page 2009-06-01 Section Change Results 30 ■ BLOCK DIAGRAM 1. MB91F467TA, MB91F469TA 43 ■ EMBEDDED PROGRAM/DATA Corrected the table of MB91F467TA external pins. (MD2 → MD_2 MEMORY (FLASH) MD1 → MD_1 4.2. Pin connections in parallel MD0 → MD_0) programming mode 44 Corrected the table of MB91F469TA external pins. (MD2 → MD_2 MD1 → MD_1 MD0 → MD_0) 53 ■ I/O MAP 1. MB91F467TA, MB91F469TA 71 99 110 111 Deleted the line of "000080H" of the table. Corrected "Block" in the table. (Flash Memory/-Cache Control Register → Flash Memory/ F-Cache Control Register) ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Corrected "Condition" of Output “L” voltage. (IOH → IOL) 4. A/D converter characteristics Corrected "Value" and "Unit" of Zero reading voltage. (AVRL − 1.5 → AVRL − 1.5 LSB AVRL + 0.5 → AVRL + 0.5 LSB AVRL + 2.5 → AVRL + 2.5 LSB LSB → V) Corrected "Value" and "Unit" of Full scale reading voltage. (AVRH − 3.5 → AVRH − 3.5 LSB AVRH − 1.5 → AVRH − 1.5 LSB AVRH + 0.5 → AVRH + 0.5 LSB LSB → V) 102 109 Corrected the pin name in figure. (SG0 → SGO) 6.3. LIN-USART Timings at VDD5 Corrected the sentences. = 3.0 to 5.5 V (- Ta = -40 to +105 °C → - Ta = -40 to +105°C) • Internal clock mode (master mode) • External clock mode (slave mode) Corrected the figure. (VOH → VIH VOL → VIL) 6.4. I2C AC Timings at VDD5 = 3.0 Corrected "Value" of Rise time of both SDA and SCL signals. (20 + 0.1Cb → 20 + 0.1Cb) to Corrected "Value" of Fall time of both SDA and SCL signals. 5.5 V (20 + 0.1Cb → 20 + 0.1Cb) 112 DS705-00001-2v1-E Corrected the position of figure. 133 MB91460T Series Version 1E Page 2009-06-01 Section 115 6.7.1. Basic Timing 116 6.7.2. Synchronous/ Asynchronous read access 117 6.7.3. Synchronous write access - byte control type 118 6.7.4. Synchronous write access - no byte control type 121 6.7.7. RDY waitcycle insertion 123 6.8.1. Basic Timing 124 6.8.2. Synchronous/ Asynchronous read access 125 6.8.3. Synchronous write access - byte control type 126 6.8.4. Synchronous write access - no byte control type 129 6.8.7. RDY waitcycle insertion Change Results Corrected "Pin name" in the figure. (MCLKO → SYSCLK) ■ MAIN CHANGES IN THIS EDITION Version 2E Page 3 130 5 88 89 Section ■ FEATURES 3. Package and technology ■ ORDERING INFORMATION ■ PRODUCT LINEUP, Power Consumption 2010-04-30 Changes for TA = 125 °C Introduced maximal ambient temperature TA(max), defined in chapter ORDERING INFORMATON, for parameters at TA=125 °C Changed MB91F467T and MB91F469T from <1W to <1.3W ■ RECOMMENDED SETTINGS 1. PLL and Clockgear settings Added notes that the maximum allowed frequencies should be ■ RECOMMENDED SETTINGS checked in section “Absolute maximum ratings” on page 94. 2. Clock Modulator settings 95 ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Added permitted operating frequency and permitted power dissipation per device, depending on TA(max) ; changed operating temperature to TA(max) 97 ■ ELECTRICAL CHARACTERISTICS 2. Recommended operating conditions Changed operating temperature to TA(max) 98 ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Table head lines: Changed TA from 105 °C to TA(max) 134 DS705-00001-2v1-E MB91460T Series Version 2E Page Section 2010-04-30 Changes for TA = 125 °C 99 ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Input leakage current, Analog input leakage current: changed hi temp condition from 105 °C to TA(max) 100 ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Power supply current MB91F467TA: Added ICCH values for TA=125 °C Added ICCH remark for 32kHz mode (same as RTC 100 kHz mode) 101 ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Power supply current MB91F469TA (target data): Added ICCH remark for 32kHz mode (same as RTC 100 kHz mode) 102 ■ ELECTRICAL CHARACTERISTICS 4. A/D converter characteristics Table head lines: Changed TA from 105 °C to TA(max) 107 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics Table head lines and condition listings: Changed max TA from 105 °C to TA(max). Version 2E Page Section 2 Front page note 5 ■ PRODUCT LINEUP 130 ■ ORDERING INFORMATION 2010-04-30 Other Changes Changed the notes for MB91F469TA from “this device is under development” into “this device is planned” 4 ■ PRODUCT LINEUP Added new emulation device MB91FV460B 32 ■ CPU AND CONTROL UNIT 3.1. Basic programming model Corrected the name of the Program Status (PS) register 51 ■ I/O MAP Changed the I/O map so that the table header can be seen on each page ■ I/O MAP, addresses 0001B0H to 0001ECH Corrected the register names of all Reload Timers, added Reload Timer 3. 64 ■ I/O MAP, address 000678H Renamed registers IORW0 to 2 into IOWR0 to 2, added IOWR3 66 ■ I/O MAP, addresses 000D80H, 000D84H, 000D88H Added note 5 (about external bus PFR initial values) to the PFRs PFR01 to PFR10 82 ■ INTERRUPT VECTOR TABLE Added correct table heading on each page, corrected the foot notes 94 ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Added Power supply slew rate (50 V/ms) Note: Relationship of the supply voltages has not been changed although there are change bars in the document. 103 ■ ELECTRICAL CHARACTERISTICS 4. A/D converter characteristics Sampling Time Calculation formulas corrected 108 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics 6.2. Reset input ratings INITX input time (at power on) tINTL changed from 8 ms to 10 ms to match the main oscillation stabilization time, see also “Recommended operating conditions” on page 97. 56 to 57 DS705-00001-2v1-E 135 MB91460T Series Version 2E Page Section 5 ■ PRODUCT LINEUP 109, 111, 114, 122 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics 2010-04-30 Other Changes Corrected symbol for ambient temperature from “Ta” into “TA” 6 ■ PIN ASSIGNMENT, 1. MB91F467TA, MB91F469TA 26 ■ PORT MULTIPLEXING, 2. Multiplex Pinout MB91F467TA, MB91F469TA 10 ■ PIN DESCRIPTION Corrected pin 40 (WEX) from P10_2 into P10_3 111 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics 6.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V In the waveform, changed tSU;ST0 into tSU;STO 119 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics 6.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V 6.7.1. Basic Timing 127 136 ■ ELECTRICAL CHARACTERISTICS 6. AC characteristics 6.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V 6.8.1. Basic Timing Corrected pin 47 from P08_5/RDY into P08_7/RDY, corrected pins 7 to 9 from P06_4 into P06_5, P06_6 and P06_7, corrected pin 31 from P24_4 into P24_3, corrected pin 105 from AVSS_1 into AVSS5. Removed the signal BAAX from the waveform drawings (BAAX does not exist on MB91460T series) DS705-00001-2v1-E MB91460T Series MEMO DS705-00001-2v1-E 137 MB91460T Series MEMO 138 DS705-00001-2v1-E MB91460T Series MEMO DS705-00001-2v1-E 139 MB91460T Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. 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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department