Crystal oscillator SELECTABLE-OUTPUT CRYSTAL OSCILLATOR SPG series • Capable of selecting 57 varieties of frequency output. • Low current consumption. • Easy to mount DIP 16-pin package. Actual size Specifications (characteristics) Item Soldering condition (lead part) TSOL Frequency tolerance ∆f/f0 8640BN 8640CN 1 MHz 768 kHz 8650A 60 kHz 8650B 100 kHz 8650C 8650E 96 kHz 32.768 kHz L. input voltage -30 °C to +80 °C -10 °C to +70 °C Under +260 °C within 10 s ±50 x 10-6 -10 °C to +60 °C (VDD=5 V±0.5 V, Ta=-10 to +70 ˚C CL ≤ 15 pF) Unit Typ. Max. 0.8 V VDD IRL -30 -5 Reset=GND H input current (Reset) IRH 0.5 Reset=VDD IIL -0.5 IIH 5 (input terminal except for Reset) H. output voltage VOH VDD-1.0 L. output current IOL 1.6 H. output current IOH No load condition Three drops on a hard wooden board form 750 mm Symbol Specifications 1 MHz max. lop About 2 mA tTLH Output fall time tTHL 25 tRW 50 tR Reset release synchronous error tE External signal input frequency FIN External signal input pulse width tIN 50 % Output waveform 1/2VDD 20 %VDD Except in the case of 1/3 and 1/5 % VOL t THL tW-∗ 1 1/2 to tW 1M Hz 8640 N only µs 12 13 (Unit: mm) SPG 8650 B EPSON 0103B TEST 14 10 20.5 Max. 4 3 2 CTL1 to 3 7 6 5 CTL4 to 6 OUT 4 3 2 CTL1 to 3 1/1 to 1/10 7 Program Divider 7 6 5 CTL4 to 6 9 2.54 SPG-8650O only 8640N 53 Pull-up and pull-down resistance 400 kΩ (Typ.) 7.62 OUT 0.1 Min. Program Divider 9 1/1 to 1/12 Program Divider 3.0 Min. 4.5 Max. 11 FOUT 1/1 to 1/10 7 VOH tw ∗3 s 1 CLOCK ENABLE RESET 10 B External dimensions 6.65 TEST tE A Block diagram 14 tR µs ∗ 1 to=oscillation source cycle. ∗ 2 tw=1/2 cycle of preset frequency. ∗ 3 For more than 1 ms until VDD=0→4.5 V. Time at 4.5 V is to be 0. EXC. CSEL. RESET t TLH VSS ∗2 0.5 0.2 VDD 80 %VDD 1.0 tOSC Duty=B/A x 100 % RESET ns 1.0 Reset delay time Oscillation start up time 60 VOH=VDD-1.0 V mA µA 60 40 Duty CSEL No load condition RESET timing IOH= -40 µA V -40 Output rise time 1/1 to 1/12 Program Divider Remarks 8650 O VOL=0.4 V 30 Min. reset pulse width IOL=1.6 mA 0.4 VOL O S C. VDD=5 V, Ta=+25 °C, first year RESET timing µA 30 L. output voltage 13 VDD=4.5 to 5.5 V tRW H input current 12 ±5 x 10-6 ±3 x 10-6/year Max. Divider IC (without quartz crystal) Item VDD-1.0 VDD=5 V, Ta=+25 °C 0.5 mA Max. ±10 x 10-6 Max. Model name Input clock frequency Current consumption VIH ±5 x 10-6 ∗1 VDD=5 V Remarks L. input current (Reset) (input terminal except for Reset) Package should be less than +150 °C +10/-120 x 10-6 ±10 x 10-6 ±20 x 10-6 ±5 x 10-6/year Max. H. input voltage L. input current For output frequency, refer to the table in the next page 5.0 V±0.5 V ±20 x 10-6 ±10 x 10-6 Symbol Min. VIL 0 8651B 8651E 100 kHz 32.768 kHz -55 °C to +125 °C Aging fa Current consumption 1.0 mA Max. 2.0 mA Max. 1.5 mA Max. lop Shock resistance ±5 x 10-6 Max. ±5 x 10-6 Max.(From 500 mm) S.R. ∗1 Frequency tolerance of 8651 system shows the value guaranteed at the time of shipment. Item 8651A 60 kHz -0.3 V to +7.0 V ±100 x 10-6 Frequency temperature characteristics Frequency voltage characteristics Electric characteristics Remarks Specifications Symbol Model name 8640AN Oscillation source frequency fo 600 kHz Power source Max. supply voltage VDD-GND voltage VDD Operating voltage TSTG Temperature Storage temperature range TOPR Operating temperature 0.5 17.78 90° to 105° 0.25 Crystal oscillator Terminal connection 8650A 8651A No. Pin terminal 1 NC 2 CTL 3 3 CTL 2 4 CTL 1 5 CTL 6 6 CTL 5 7 CTL 4 8 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 No. Pin terminal 16 VDD 15 NC 14 RESET 13 NC (CSEL) 12 NC (EXC) 11 FOUT 10 TEST 9 OUT Set terminal CTL1 0 0 0 0 1 1 1 1 CTL4 CTL5 0 0 0 60k 6k 30k 20k 15k 12k 10k 5k CTL6 CTL2 CTL3 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 6.0k 600 3.0k 2.0k 1.5k 1.2k 1.0k 500 0 1 0 600 60 300 200 150 120 100 50 0 1 1 60 6 30 20 15 12 10 5 1 0 0 6.0 0.6 3.0 2.0 1.5 1.2 1.0 0.5 1 0 1 0.6 0.06 0.3 0.2 0.15 0.12 0.1 0.05 1 1 0 0.06 0.006 0.03 0.02 0.015 0.012 0.01 0.005 0.006 0.0006 0.003 0.002 0.0015 0.0012 0.001 0.0005 1 1 1 ( ) shown 8640N only For 8650 O 11. NC 12. CLOCK 13. ENABLE NC: Do not connect to the external terminal. Explanation of terminal Programs dividing ratio. (pull-down resistor incorporated.) Output frequency preset by CTL1 to 6. (refer to the procedure for setting output frequency.) Constantly outputs the oscillation source frequency of builtin (c) FOUT : crystal unit. Stops output at RESET= “L”. (d) RESET : (pull-up resistor incorporated.) Used for the input terminal for testing. When CTL4 is H, (e) TEST : output will be 1000 times larger than the preset value at TEST= “H”. (pull-down resistor incorporated.) Serves as input terminal when using an external clock by (f) EXC (8640N only) : changing to the builtin oscillator. Effective only when CSEL is H. (g) CSEL (8640N only) : When this terminal is made H, the external clock is selected. (pull-down resistor incorporated.) (a) CTL 1 to 6 : (b) OUT : 8650B 8651B Set terminal CTL1 0 0 CTL3 0 1 0 1 0 1 0 1 CTL2 0 0 1 1 0 0 1 1 Dividing ratio 1/1 1/10 1/2 1/3 1/4 1/5 1/6 1/12 CTL4 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 100k 10k 1k 100 10 1 1/10 1k 100 10 1 1/10 1/100 1/1000 50k 5k 500 50 5 1/2 1/20 1/200 0 1 1 33.3k 33.3 3.33 1/3 1/30 1/300 1 0 0 25k 2.5k 250 25 2.5 1/4 1/40 1/400 1 0 1 20k 2k 200 20 2 1/5 1/50 1/500 1 1 0 16.6k 1.6k 166.6 16.6 1.6 1/6 1/60 1/600 1 1 1 83.3 8.3 0.83 1/12 1/120 1/1200 8650E 8651E CTL4 0 0 0 0 1 1 1 1 CTL5 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 3.276 0.327 1.638 1.092 0.819 0.655 0.546 0.273 0.3276 0.0327 0.1638 0.1092 0.0819 0.0655 0.0546 0.0273 0.03276 0.00327 0.01638 0.01092 0.00819 0.00655 0.00546 0.00273 0.00327 0.00032 0.00163 0.00109 0.00081 0.00065 0.00054 0.00027 CTL2 CTL3 CTL6 0 0 0 32768 0 1 3276.8 0 1 0 1/1 0 1 1 1/10 1 0 0 1 0 1 1 1 0 1 1 1 1/103 1/104 1/10 3.3k 333.3 8.3k 833.3 Dividing ratio 1/102 1 1/100 10k 0 CTL6 0 1 0 1 0 1 0 1 0 1 0 0 CTL5 0 0 1 1 0 0 1 1 0 0 1 CTL1 Setting of divider output CTL1 0 0 0 0 1 1 1 1 0 0 CTL2 CTL3 CTL6 0 0 0 1 Set terminal (a) CLOCK: Clock input (Max. 1 MHz) (b) ENABLE: Be sure to connect to VDD 0 CTL5 0 (Note) Treatment of empty terminals. When RESET terminal is not used, this should be connected to VDD, and when TEST terminal, CSEL terminal, and CTL 1 to 6 terminals are not used, to GND. Explanation of terminal (8650 O) CTL4 3276.8 327.68 1638.4 1092.26 819.2 655.36 546.13 273.06 16384 10922.6 8192 6553.6 5461.3 2730.6 327.68 32.768 32.768 3.276 163.84 16.384 109.226 10.922 81.92 8.192 65.536 6.553 54.613 5.461 27.306 2.730 Note: Lower digits are omitted. 5 1/106 1/107 0= “L” 1=“H” Setting of output frequency 8640AN CTL4 CTL5 Set terminal CTL1 CTL2 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 (Unit: Hz) CTL3 CTL6 0 1 0 1 0 1 0 1 0 0 0 600k 60k 300k 200k 150k 120k 100k 50k 0 0 1 60k 6k 30k 20k 15k 12k 10k 5k 0 1 0 6k 600 3k 2k 1.5k 1.2k 1k 500 0 1 1 600 60 300 200 150 120 100 50 1 0 0 60 6 30 20 15 12 10 5 1 0 1 6.0 0.6 3.0 2.0 1.5 1.2 1.0 0.5 1 1 0 0.6 0.06 0.3 0.2 0.15 0.12 0.1 0.05 1 1 1 0.06 0.006 0.03 0.02 0.015 0.012 0.01 0.005 1 0 0 100 10 50 33.3 25 20 16.6 8.3 1 0 1 10 1 5 3.33 2.5 2 1.6 0.83 1 1 0 1 1/10 1/2 1/3 1/4 1/5 1/6 1/12 1 1 1 1/10 1/100 1/20 1/30 1/40 1/50 1/60 1/120 Baud rate generator 8640CN CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 Output frequency Baud rate output example (fo/16) 0 0 0 0 0 0 768 kHz 48000 bits/s 1 0 1 0 0 0 153.6 9600 0 0 1 0 0 0 76.8 4800 0 1 0 0 0 1 38.4 2400 1 0 0 0 0 1 19.2 1200 8640BN Set terminal CTL1 0 0 0 0 1 1 1 1 CTL2 0 0 1 1 0 0 1 1 CTL4 CTL5 CTL3 CTL6 0 1 0 1 0 1 0 1 0 0 0 1M 100k 500k 333.3k 250k 200k 166.6k 83.3k 0 0 0 0 1 1 1 0 1 100k 10k 1k 10k 1k 100 50k 5k 500 33.3k 3.3k 333.3 25k 2.5k 250 20k 2k 200 16.6k 1.6k 166.6 8.3k 833.3 83.3 8650C CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 Output frequency Baud rate output example (to/16) 0 0 0 0 0 0 96.0 kHz 6000 bits/s 1 0 1 0 0 0 19.2 1200 0 0 1 0 0 0 9.6 600 0 1 0 0 0 1 4.8 300 0 1 1 0 0 1 3.2 200 1 0 0 0 0 1 2.4 150 1 1 0 0 0 1 1.6 100 1 1 1 0 0 1 0.8 50 54