CDB5560 50 kSps, 24-bit, High-throughput ΔΣ ADC Evaluation Board Features General Description Two Analog Input Channels Multiplexed to the CS5560 ADC Pre-configured to require a minimum number of external connections to your data acquisition system. All functionality accessible through the connector interface and board-level options. On-board 4.096 V Reference Pre-configured for Master mode SPI™ communication to a data capture system. The CDB5560 is a versatile tool designed for evaluating the functionality and performance of the CS5560 ADC (Analog-to-Digital Converter). The SPI serial port on the CDB5560 evaluation board is configured in Master mode and will start transmitting data after power-up upon reset. This evaluation board is designed to connect to your data capture system or will interface to the CapturePlus II data acquisition system available from Cirrus Logic. The CS5560 delta-sigma ADC produces fully settled conversions to full specified accuracy at 50 kSps. This ability to produce fully settled conversions for every sample makes it suitable for converting multiplexed input signals. To help evaluate this feature, the CDB5560 includes two differential analog inputs multiplexed into the CS5560. The multiplexer can be switched at the CS5560 ADC sample speed and the ADC will produce fully settled conversion data for each input channel. All evaluation board functionality for evaluating the CS5560 ADC is accessed through the connector interface and board-level options. Schematics in PADS™ PowerLogic™ format are available for download at: http://www.cirrus.com/en/products/pro/detail/P1120.html. ORDERING INFORMATION CDB5560 www.cirrus.com Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved) Evaluation Board OCT ‘09 DS713DB4 CDB5560 TABLE OF CONTENTS 1. INTRODUCTION ....................................................................................................................... 3 1.1 Overview ............................................................................................................................ 4 2. QUICK START .......................................................................................................................... 5 3. HARDWARE DESCRIPTION ................................................................................................... 6 3.1 Absolute Maximum Ratings ............................................................................................... 6 3.2 Power Supply ..................................................................................................................... 6 3.3 Analog Section ................................................................................................................... 6 3.3.1 Analog Input Buffers .............................................................................................. 6 3.3.2 Multiplexer ............................................................................................................. 7 3.3.3 ADC Reset ............................................................................................................ 7 3.3.4 Voltage Reference ................................................................................................ 7 3.3.5 ADC Reference Frequency ................................................................................... 7 3.4 Digital Section .................................................................................................................... 8 3.4.1 Hardware Configuration ........................................................................................ 8 3.4.2 SPI™ Serial Port Communications ....................................................................... 8 APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5560 ........................................ 9 A.1 PCB Layout Considerations .............................................................................................. 9 A.2 Hardware Considerations .................................................................................................. 9 APPENDIX B. BILL OF MATERIALS ........................................................................................ 10 APPENDIX C. SCHEMATICS ..................................................................................................... 11 APPENDIX D. LAYER PLOTS ................................................................................................... 16 APPENDIX E. CALIBRATION FUNCTION ................................................................................. 25 APPENDIX E. REVISION HISTORY .......................................................................................... 26 LIST OF FIGURES Figure 1. CDB5560 Block Diagram ................................................................................................. 4 Figure 2. CDB5560 Board Layout ................................................................................................... 5 Figure 3. Schematic - Block Diagram............................................................................................ 11 Figure 4. Schematic - Power Supplies .......................................................................................... 12 Figure 5. Schematic - Input Buffers and Multiplexer ..................................................................... 13 Figure 6. Schematic - CS5560 ...................................................................................................... 14 Figure 7. Schematic - Configuration & Misc. ................................................................................. 15 Figure 8. Top Silkscreen ............................................................................................................... 16 Figure 9. Top Solder Mask ............................................................................................................ 17 Figure 10. Top Routing.................................................................................................................. 18 Figure 11. Ground Plane ............................................................................................................... 19 Figure 12. Power Plane................................................................................................................. 20 Figure 13. Bottom Solder Mask..................................................................................................... 21 Figure 14. Bottom Silkscreen ........................................................................................................ 22 Figure 15. Top Solder Paste Mask................................................................................................ 23 Figure 16. Bottom Routing ............................................................................................................ 24 LIST OF TABLES Table 1. Power Supply Connections ............................................................................................... 6 Table 2. Analog Input Connections ................................................................................................. 6 Table 3. Analog Input Channel Selection ........................................................................................ 7 Table 4. Hardware Configuration Signals........................................................................................ 8 Table 5. Serial Interface Connections ............................................................................................. 8 2 DS713DB4 CDB5560 1. INTRODUCTION The CDB5560 evaluation board is a platform for evaluating the CS5560 ADC performance. The evaluation board is designed to connect to the SPI serial port of a processor or data capture system or will interface directly to the CapturePlus II data acquisition system available from Cirrus Logic. The CapturePlus II data acquisition system is a powerful integrated hardware/software tool designed to fully exercise the CDB5560 and other Cirrus Logic evaluation boards. The CDB5560 evaluation board is designed to simplify the hardware setup required to evaluate the CS5560. Interfacing the CDB5560 evaluation board to a user-supplied data capture system can be as simple as connecting the SPI port and using the CDB5560 default hardware configuration. In this configuration, simply press the Reset switch on the CDB5560 and it will automatically begin transmitting data to the data capture system. All evaluation board functionality for evaluating the CS5560 ADC is accessed through the connector interface and board-level options. The CS5560 delta-sigma ADC produces fully settled conversions to full specified accuracy at 50 kSps. The ability to produce fully settled conversions for every sample makes it suitable for converting multiplexed input signals. To help evaluate this feature, the CDB5560 includes two differential analog inputs multiplexed into the CS5560. The multiplexer can be switched at the CS5560 ADC sample speed and the ADC will produce fully settled conversion data for each input channel. For detailed information on the CS5560 ADC, please reference data sheet DS713 at www.cirrus.com. DS713DB4 3 CDB5560 1.1 Overview The CDB5560 evaluation board has both analog and digital circuit sections. The analog section consists of the CS5560 ADC, two analog input signal buffers, controlled through a multiplexer, that condition the signals into the ADC, and a precision 4.096 V reference. The digital section consists of board operation configuration control signals, reset circuitry, an SPI™ serial port, a jumper connection for initiating ADC calibration, and an EEPROM for evaluation board identification. The evaluation board operates from +2.5V, -2.5V, +3.3V and communicates through an SPI™ serial port. Figure 1 illustrates the CDB5560 block diagram. Differential Analog Inputs VREF 4.096 V LMP7732 INPUT A LMP7732 M U X CS5560 J8 Master/Slave Serial Port J6 Digital Inputs to ADC J7 Digital Outputs from ADC INPUT B XTAL 16 MHz Communication/Control Interface +2.5V GND -2.5V GND +3.3V GND Figure 1. CDB5560 Block Diagram 4 DS713DB4 CDB5560 2. QUICK START Buffer Enable DC Supply Digital Control Signals to ADC & Mux Calibrate 2 4.096 V Reference ADC Reset Master/Slave SPI ADC MCLK Out Analog Inputs NOTES: 1. Shaded boxes marked with "OPT. CONFIG." are not necessary for operation in an end user product. 2. Calibration function has been removed from the device but still appears on the PCB. J2 must be shorted (grounded) for proper operation. See Appendix E for details. Figure 2. CDB5560 Board Layout The CDB5560 evaluation board is designed to interface with a data acquisition system. To connect and configure the CDB5560 perform the following initialization procedure: 1. Verify that the power supplies are off. 2. Connect the power supplies to the CDB5560 as shown in Table 1 on page 6. 3. Verify that the power is off to the analog input signal & control signal sources. 4. Connect the analog input signal sources to the evaluation board per Table 2 on page 6. Verify from Table 4 on page 8 that the analog input channel selected is INPUT A. 5. Configure the CDB5560 by connecting the control signal sources to the evaluation board as shown in Table 3 on page 7. Apply logic-level inputs as required to override the resistor pull-ups/pull-downs. 6. Make connections to the SPI™ serial port connector as shown in Table 5 on page 8. The CS5560 ADC serial port is configured by default to operate in the SSC (Synchronous Self Clocking) mode. Refer to the CS5560 data sheet for more information on serial communication modes and signal timing. 7. Turn on the power supplies to the evaluation board. 8. Apply power to the signal source. 9. Press the Reset switch on the evaluation board. 10. The CS5560 ADC's SPI™ serial port should now be communicating data. DS713DB4 5 CDB5560 3. HARDWARE DESCRIPTION 3.1 Absolute Maximum Ratings Observe the following limits to ensure the CDB5560 component ratings are not exceeded. • CS5560 – The absolute maximum supply voltage that can be applied to the +3.3V power supply connection is +3.6V. – The absolute maximum power supply voltage that can be applied between pins VL and V1is 6.1 V. • LMP7732 – The absolute maximum power supply voltage that can be applied between the +2.5V and -2.5V power supply connections is +5.5V. 3.2 Power Supply Power supply connections and requirements are specified in Table 1. below. Table 1. Power Supply Connections Power Supply Requirement Power Supply Connection Associated Ground Return Associated Test Points +2.5 V DC, ±5%, <50 mA E5 E3 TP2, TP1 (GND) -2.5 V DC, ±5%, <50 mA E9 E7 TP4, TP3 (GND) +3.3 V DC, ±5%, <50 mA E16 E13 TP6, TP5 (GND) Important: It is recommended that all power supplies be isolated from utility ground to prevent the introduction of a ground loop. One ground connection may already exist through the serial port connection to utility ground. Using the Cirrus Logic CapturePlus II system simplifies making connections to the CDB5560 by providing electrical isolation between the two. Using twisted/shielded wire will reduce electrical noise induced onto the power supply cables. Power supplies are to be adequately regulated and sufficiently low noise to meet the application requirements. 3.3 3.3.1 Analog Section Analog Input Buffers The analog input signal connections to the input buffers are made at the INPUT A and INPUT B connectors, as specified in Table 2. Table 2. Analog Input Connections Channel Analog Input Connection Differential Input Signal Voltage Range Impedance INPUT A J4 -4.096 V to +4.096 V 50 Ohms INPUT B J5 -4.096 V to +4.096 V 50 Ohms There are two analog input channels on the evaluation board. National Semiconductor LMP7732. Each analog input channel consists of two low-noise amplifiers configured as unity gain non-inverting buffers. The buffers utilize two National Semiconductor LMP7732 precision, low-noise, low-voltage, dual opamps. These op-amps enable both the inputs and outputs of the analog input buffer to operate virtually rail to rail. The channel input impedance is 50 Ohms. 6 DS713DB4 CDB5560 For detailed information on the LMP7732 precision industrial op-amps, please visit National Semiconductor’s website at www.national.com. The analog inputs are designed for connections to differential input signals. The usable input voltage range is -4.096 V to +4.096 V. The theoretical input frequency range of the CS5560 is from DC to the Nyquist frequency of 25 kHz. The analog input buffer amplifiers are configured for a cutoff frequency of 16.8 kHz to band-limit noise into the ADC. Changing the cutoff frequency will change the noise bandwidth accordingly. 3.3.2 Multiplexer Analog input channel selection is controlled through the multiplexer. The multiplexer is configured with a pull-down resistor on the MUX control line to enable input channel labeled "INPUT A" by default. To select channel B, apply 3.3 V to the multiplexer input control line (MUX). Signal levels for controlling the multiplexer that selects between analog input channels A and B is shown in Table 3. Table 3. Analog Input Channel Selection Multiplexer Control Input (MUX) Input Channel Enabled 0V A 3.3 V B During multiplexing, the maximum sample rate for each channel is half that of the ADC’s maximum sample rate. Additionally, the Nyquist frequency for each channel is half of the ADC’s Nyquist frequency. 3.3.3 ADC Reset The CS5560 ADC makes use of an externally generated power-on reset. Therefore, after power is applied to the ADC, the reset pin must be driven low then released. Pressing the Reset button generates a reset cycle. A reset cycle can be generated at any time during ADC operation. The ADC RST pin (active low) is held inactive through a pull-up resistor. 3.3.4 Voltage Reference The voltage reference IC provided generates a 4.096 V precision reference. 3.3.5 ADC Reference Frequency The reference frequency for the CS5560 ADC is provided by a 16.000 MHz oscillator. DS713DB4 7 CDB5560 3.4 Digital Section 3.4.1 Hardware Configuration The CDB5560 evaluation board hardware comes pre-configured so the only connection required between it and a data acquisition system is the serial port connection. The hardware setup is reconfigurable through the hardware control interface connectors. Configure the evaluation board by setting the appropriate control line to the appropriate logic level. Table 4. Hardware Configuration Signals Function Default Level Label Connector Test Point Input Channel Select INPUT A = Selected (Low) MUX J6, Pin 16 J3, Pin 2 Analog Input Buffers Buffers = Enabled (High) BUFEN J1 J3, Pin1 Serial Port Mode Sync. Self Clock = Enabled (High) SMODE J6, Pin 12 J3, Pin 3 Data Ready Flag Data Ready When Set (Low) RDY J8, Pin 10 J3, Pin 4 Reset Reset = Inactive (High) RST J6, Pin 6; S1 J3, Pin 6 Bipolar / Unipolar Mode Bipolar = Enabled (High) BP / UP J6, Pin 2 J3, Pin 8 Sleep Mode Sleep = Inactive (High) SLEEP J6, Pin 4 J3, Pin 9 Serial Port Communication Chip Select = Enabled (Low) CS J8, Pin 2 E23 Data Conversion Mode Continuous Conversion = Active (Low) CONV J8, Pin 12 E21 3.4.2 SPI™ Serial Port Communications The CS5560 ADC communications port features an SPI™ serial port. It can be configured for SSC mode (Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial communications. Connections to the serial interface are made according to the following table. Table 5. Serial Interface Connections 8 Function Label Connector Test Point Chip Select CS J8, Pin 2 E23 Serial Data Input SDI J8, Pin 4 E24 Serial Data Output SDO J8, Pin 6 E25 Serial Clock SCLK J8, Pin 8 E26 DS713DB4 CDB5560 APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5560 A.1 PCB Layout Considerations • Keep the signal path short between the CS5560 ADC input capacitors C20, C28, C37, C44 and the ADC input pins to minimize trace inductance. • The analog input buffer amplifiers and ADC input buffer capacitors are placed before the multiplexer. Placing the buffer amplifiers before the multiplexer allows the amplifiers driving the ADC buffer capacitors to be fully settled when sampled by the ADC. Therefore, the multiplexer must be of a low on-resistance type to prevent distortion or latency issues. • Power supply noise is a major design consideration and the power supplies need adequate bypassing and bulk capacitance. • When operating the ADC from +2.5 V and -2.5 V split supplies, place the power supply & buffer amplifier bypass capacitor ground connections close together. • Keep all ground connections on each differential buffer amplifier as close to the device as possible to avoid introducing differential noise through high-impedance connections. • Keep trace lengths short between the ADC and the voltage reference IC negative supply pins. • Route the oscillator output away from analog circuitry. • Use a solid ground plane in the PCB layout. • Provide adequate separation between analog and digital signals. • To minimize distortion within the analog signal path, consider using components with smaller voltage dependencies. • Minimize ADC digital output edge transition current loading. A.2 Hardware Considerations At a system level, use shielded cable for interconnects. Keep interconnect cable lengths as short as possible. Route analog and digital signals connecting to the PCB away from each other. DS713DB4 9 10 Cirrus P/N 001-03713-Z1 001-04345-Z1 012-00012-Z1 001-03987-Z1 001-10036-Z1 001-02976-Z1 001-06472-Z1 001-03710-Z1 070-00111-Z1 070-00010-Z1 000-00025-Z1 115-00052-Z1 115-00217-Z1 115-00202-Z1 115-00239-Z1 115-00238-Z1 115-00241-Z1 304-00012-Z1 021-00435-Z1 021-00363-Z1 020-02044-Z1 020-01895-Z1 021-00387-Z1 021-00423-Z1 023-00002-Z1 020-01667-Z1 021-01430-Z1 120-00057-Z1 110-00045-Z1 110-00024-Z1 110-00025-Z1 060-00351-Z1 065-00212-Z3 060-00430-Z1 060-00352-Z1 060-00386-Z1 062-00064-Z1 300-00002-Z1 102-00097-Z1 603-00216-Z1 240-00216-Z1 600-00216-Z1 Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 43 CIRRUS LOGIC CDB5560-Z_REV_C2.PL C C C2 A A A A A A A A A B0 A A A A A A A A A A A A A A A A A A A A A A A A A A A Rev A A ASSY DWG CDB5560-1-Z NPb PCB CDB5560-1-Z NPb SCHEM CDB5560-Z NPb IC LNR ANA SW 4OHM SPDT NPb MSOP10 IC LNR DIFF COMP HS 5.25V NPb SOIC8 IC PGM SPI EEPROM 8kX8 2MHz NPb SO8 SCREW 4-40X1/4" PH NYLON NPb OSC 16MHz 50ppm 3.3V NPb SMD 3x5 CON TEST PT .1"CTR TIN PLAT NPb BLK CON TEST PT .1" TIN PLT RED NPb TH CON TEST PT .1" TIN PLATE WHT NPb IC LNR PREC VREF 4.096Vout NPb SO8 IC CRUS ADC 1CH 24BIT NPb SSOP24 IC LNR 2.9nV LNSE PREC AMP NPb SO8 RES 49.9 OHM 1/10W ±.5% NPb 0805 TN RES 49.9 OHM 1/8W ±1% NPb 0805 FILM RES 33k OHM 1/8W ±5% NPb 0805 FILM SWT SPST 130G 0/1 7mm TACT ESD NPb RES 100 OHM 1/8W ±5% NPb 0805 FILM RES 3.3k OHM 1/8W ±5% NPb 0805 FIL RES 10k OHM 1/8W ±5% NPb 0805 FILM RES 10 OHM 1/8W ±5% NPb 0805 FILM RES 100k OHM 1/8W ±1% NPb 0805 FILM RES 4.99k OHM 1/8W ±1% NPb 0805 FLM HDR 2x1 ML .1"CTR 093 GLD NPb HDR 10X1 FML .1" 093 GLD NPb TH HDR 3X1 ML .1" PCH .062BD NPb TH HDR 8X2 093BD FML .1" .331" NPb TH HDR 5X2 093BD FML .1" .331" NPb TH HDR 6X2 093BD FML .1" .331" NPb TH SPCR STANDOFF NYL HEX750/4-40TH NPb CAP 10uF ±20% 16V ELEC NPb CASE A CAP 4700pF ±10% 50V X7R NPb 0805 CAP 2200pF ±5% 50V C0G NPb 0805 CAP 47pF ±10% 50V C0G NPb 0805 CAP 4700pF ±5% 50V C0G NPb 1206 CAP 1000pF ±5% 50V C0G NPb 0805 DIODE TR 6.8V 600W NPb DO-214AA DIODE SCHTKY BAR 30V 0.2A NPb SOT23 NO POP 040 PAD 064 NPb TH Description CAP 1000pF ±10% 50V X7R NPb 0805 CAP 0.1uF ±10% 50V X7R NPb 0805 REF 1 REF 1 1 1 4 1 3 2 1 1 1 2 4 4 1 1 1 1 9 4 5 16 0 0 2 1 1 1 4 3 1 0 4 4 0 3 1 0 Qty 2 29 U4 U6 U7 XMH1 XMH2 XMH3 XMH4 Y1 TP1 TP3 TP5 TP2 TP6 TP4 U1 U2 U3 U5 R18 R26 R35 R44 R20 R29 R37 R47 R41 S1 R1 R2 R7 R8 R31 R32 R39 R40 R42 R3 R21 R22 R25 R4 R5 R6 R10 R30 R9 R11 R12 R14 R15 R16 R19 R24 R27 R28 R33 R34 R36 R43 R45 R46 R13 R17 Reference Designator C1 C2 C3 C4 C5 C9 C10 C12 C15 C16 C17 C18 C19 C21 C22 C23 C25 C26 C27 C29 C30 C32 C33 C35 C36 C38 C40 C41 C42 C43 C46 C6 C7 C13 C8 C11 C47 C48 C49 C14 C31 C34 C45 C20 C28 C37 C44 C24 C39 D1 D2 D3 D4 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 J1 J2 J3 J4 J5 J6 J7 J8 MH1 MH2 MH3 MH4 BILL OF MATERIAL CIRRUS LOGIC CIRRUS LOGIC CIRRUS LOGIC KEYSTONE KEYSTONE KEYSTONE MAXIM CIRRUS LOGIC NATIONAL SEMICONDUCTOR MAXIM TEXAS INSTRUMENTS MICROCHIP BUILDING FASTENERS ABRACON SUSUMU DALE DALE ITT INDUSTRIES DALE DALE DALE DALE DALE DALE SAMTEC SAMTEC MOLEX SAMTEC SAMTEC SAMTEC KEYSTONE PANASONIC KEMET KEMET KEMET KEMET KEMET LITTELFUSE PHILIPS NO POP MFG KEMET KEMET ECO521, ECO542 ECO542 INSTALL AFTER WASH PROCESS REQUIRES SCREW 4-40X1X4" PH NYLON, 300-00002-Z1 NO POP NO POP NO POP NO POP NO POP Notes MAX4635EUB+ TL712CD 25LC640-I/SN NY PMS 440 0025 PH ASFL1-16.000MHZ-ECT 603-00216-Z1 240-00216-Z1 600-00216-Z1 ECO521, ECO542 5001 5000 5002 MAX6126AASA41+ CS5560-ISZ/B0 LMP7732MA RR1220Q-49R9-D-M CRCW080549R9FKEA CRCW080533K0JNEA PTS645TL70 CRCW0805100RJNEA CRCW08053K300JNEA CRCW080510K0JNEA CRCW080510R0JNEA CRCW0805100KFKEA CRCW08054K99FKEA TSW-102-26-G-S SSW-110-01-G-S 22-66-2030 SSW-108-01-G-D SSW-105-01-G-D SSW-106-01-G-D 1902D EEE1CS100SR C0805C472K5RAC C0805C222J5GAC C0805C470K5GAC C1206C472J5GAC C0805C102J5GAC P6SMBJ6.8A BAT54 NP-PAD-040 MFG P/N C0805C102K5RAC C0805C104K5RAC CDB5560 APPENDIX B. BILL OF MATERIALS DS713DB4 CDB5560 Figure 3. Schematic - Block Diagram APPENDIX C. SCHEMATICS DS713DB4 11 Figure 4. Schematic - Power Supplies CDB5560 12 DS713DB4 Figure 5. Schematic - Input Buffers and Multiplexer CDB5560 DS713DB4 13 Figure 6. Schematic - CS5560 CDB5560 14 DS713DB4 Figure 7. Schematic - Configuration & Misc. CDB5560 DS713DB4 15 16 Figure 8. Top Silkscreen Calibration function has been removed from the device but still appears on the PCB. J2 must be shorted (grounded) for proper operation. See Appendix E for details. CDB5560 APPENDIX D. LAYER PLOTS DS713DB4 Figure 9. Top Solder Mask CDB5560 DS713DB4 17 Figure 10. Top Routing CDB5560 18 DS713DB4 Figure 11. Ground Plane CDB5560 DS713DB4 19 Figure 12. Power Plane CDB5560 20 DS713DB4 Figure 13. Bottom Solder Mask CDB5560 DS713DB4 21 Figure 14. Bottom Silkscreen CDB5560 22 DS713DB4 Figure 15. Top Solder Paste Mask CDB5560 DS713DB4 23 Figure 16. Bottom Routing CDB5560 24 DS713DB4 CDB5560 APPENDIX E. CALIBRATION FUNCTION The calibration function has been removed from the CS5560. All references to calibration have been removed from this document. However, calibration still appears on the PCB. A jumper must be added to J2 for proper operation. DS713DB4 25 CDB5560 REVISION HISTORY Revision Date Changes DB1 APR 2007 Initial Release. DB2 JUN 2007 Updated schematics & layer plots to reflect rev C assembly, non-inverting buffers. DB3 DEC 2007 Changed op amps to LMP7732. DB4 OCT 2009 Removed calibration function / added Appendix E. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. PADS and PowerLogic are trademarks of Mentor Graphics. National Semiconductor is a registered trademark of National Semiconductor Corporation. 26 DS713DB4