Low-power, 4-in/6-out HD Audio CODEC with Headphone Amp

CS4207
Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
ANALOG to DIGITAL FEATURES
 DAC1 (Headphone)
 ADC1 & ADC2
–
–
101 dB Dynamic Range (A-wtd)
-89 dB THD+N
–
–
–
 Headphone Amplifier - GND Centered
–
–
–
Integrated Negative-voltage Regulator
No DC-blocking Capacitor Required
50 mW Power/Channel into 16 Ω
–
 DAC2 & DAC3 (Line Outs)
–
–
–
 MIC Inputs
110 dB Dynamic Range (A-wtd)
-94 dB THD+N
Differential Balanced or Single-ended
–
 Each DAC Supports 32 kHz to 192 kHz Sample
Rates Independently.
Rates Independently
+6.0 dB to -57.5 dB in 0.5 dB Steps
Zero Cross and/or Soft Ramp Transitions
 Independent Support of D0 and D3 Power
States for Each DAC
 Additional Digital Attenuation Control
–
–
-13.0 dB to -51.0 dB in 1.0 dB steps
Zero Cross and/or Soft Ramp Transitions
 Digital Interface for Two Dual Digital Mic Inputs
 Fast D3 to D0 Transition
–
–
Pre-amplifier with Selectable 0 dB, +10 dB,
+20 dB, and +30 dB Gain Settings
Programmable, Low-noise MIC Bias Level
 Each ADC Supports 8 kHz to 96 kHz Sample
 Digital Volume Control
–
–
105 dB Dynamic Range (A-wtd)
-88 dB THD+N
Differential Balanced or Single-ended
Inputs
Analog Programmable Gain Amplifier
(PGA) ±12 dB, 1.0 dB Steps, with Zero
Cross Transitions and Mute
 Independent Support of D0 and D3 Power
Audio Playback in Less Than 50 ms
States for Each ADC
VD
(1.5 V to 1.8 V)
VA, VA_REF
(3.3 V to 5.0 V)
VA_HP
(3.3 V to 5.0 V)
Chrg
Pump
Buck
Chrg
Pump
Invert
HD Audio
Bus
VL_HD
(1.5 V to 3.3 V)
Level Translator
+VHP
GPIO
Level Translator
VL_IF
(3.3 V)
HD
Audio
Interface
GPIO
S/PDIF OUT 2
S/PDIF OUT 1
Vol/Mute
S/PDIF IN
SPDIF
TX2
SPDIF
TX1
HD Bus
Fs
SPDIF
RX
128Fs Clock
Multiplier
SPDIF
RX SRC
SRC &
Multibit ΔΣ
Modulator
-VHP
Headphone
Amp - GND
Centered
Left HP Out
Right HP Out
+Left Line Out
+
Right Line Out
+Left Line Out
+
Right Line Out
-
Vol/Mute
SRC &
Multibit ΔΣ
Modulator
2-Chnl
DAC2
Line
Out
Vol/Mute
SRC &
Multibit ΔΣ
Modulator
2-Chnl
DAC3
Line
Out
Vol/Boost/
Mute
Digital
Filter &
SRC
2-Chnl
ADC1
PGA
+
- Line/Mic In L
Line/Mic In R
+
Vol/Boost/
Mute
Digital
Filter &
SRC
2-Chnl
ADC2
PGA
+
- Mic/Line In L
+Mic/Line In R
-
D-Mic Clock
D-Mic In
http://www.cirrus.com
2-Chnl
DAC1
Jack
Sense
Copyright  Cirrus Logic, Inc. 2009
(All Rights Reserved)
MIC
Bias
Mic Bias
SENSE_A
JUL '09
DS880PB1
CS4207
Digital Audio Interface Receiver
General Description
 Complete EIAJ CP1201, IEC-60958, S/PDIF
The CS4207 is a highly integrated multi-channel lowpower HD Audio CODEC featuring 192 kHz DACs,
96 kHz ADCs, 192 kHz S/PDIF Transmitters and Receiver, Microphone pre-amp and bias voltage, and a
ground centered Headphone driver. Based on multi-bit,
delta-sigma modulation, it allows infinite sample rate
adjustment between 32 kHz and 192 kHz.
Compatible Receiver
 32 kHz to 192 kHz Sample Rate Range
 Automatic Detection of Compressed Audio
Streams
 Integrated Sample Rate Converter
–
–
–
–
128 dB Dynamic Range
-120 dB THD+N
Supports Sample Rates up to 192 kHz
1:1 Input/Output Sample Rate Ratios
Digital Audio Interface Transmitters
 Two Independent EIAJ CP1201, IEC-60958,
S/PDIF Compatible Transmitters
 32 kHz to 192 kHz Sample Rate Range
System Features
 Very Low D3 Power Dissipation of <7 mW
–
–
Jack Detect Active in D3
HDA Bus BITCLK not required for D3 State
 Jack Detect Does not Require HDA Bus
BITCLK
 All Configuration Settings are Preserved in D3
State
 Pop/Click Suppression in State Transitions
 Detects Wake Event and Generates Power
State Change Request when HDA Bus
Controller is in D3
 Variable Power Supplies
– 1.5 V to 1.8 V Digital Core Voltage
– 3.3 V to 5.0 V Analog Core Voltage
– 3.3 V to 5.0 V Headphone Drivers
– 1.5 V to 3.3 V HD Bus Interface Logic
– 3.3 V Interface Logic levels for GPIO,
S/PDIF, and Digital Mic.
The ADC input path allows control of a number of features. The microphone input path includes a selectable
programmable-gain pre-amplifier stage and a low-noise
MIC bias voltage supply. A PGA is available for line and
microphone inputs and provides analog gain with soft
ramp and zero cross transitions. The ADC also features
an additional digital volume attenuator with soft ramp
transitions.
The stereo headphone amplifier is powered from a separate internally generated positive supply, with an
integrated charge pump providing a negative supply.
This allows a ground-centered analog output with a
wide signal swing and eliminates external DC-blocking
capacitors.
The integrated digital audio interface receiver and transmitters utilize a 24-bit, high-performance, monolithic
CMOS stereo asynchronous sample rate converter to
clock align the PCM samples to/from the S/PDIF interfaces. Auto detection of non-PCM encoded data
disables the sample rate conversion to preserve bit accuracy of the data.
In addition to its many features, the CS4207 operates
from a low-voltage analog and digital core, making this
part ideal for portable systems that require low power
consumption in a minimal amount of space.
The CS4207 is available in a 48-pin WQFN package in
both Automotive (-40°C to +105°C) and Commercial (40°C to +85°C) grades. The CS4207 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on p 8 for complete ordering information.
 Individual Power-down Managed
–
2
ADCs, DACs, PGAs, Headphone Driver,
S/PDIF Receiver, and Transmitters
DS880PB1
CS4207
SPDIF_OUT1
SPDIF_IN
VA_HP
FLYP
VHP_FILT+
FLYC
FLYN
VHP_FILT-
HPOUT_R
HPREF
HPOUT_L
LINEOUT_R1-
1. PIN DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
VL_IF
1
36
LINEOUT_R1+
GPIO0/DMIC_SDA1
2
35
LINEOUT_L1+
VL_HD
3
34
LINEOUT_L1-
DMIC_SCL
4
33
LINEOUT_R2-
SDO
5
32
LINEOUT_R2+
BITCLK
6
31
LINEOUT_L2+
Thermal Pad
DGND
7
30
LINEOUT_L2-
SDI
8
29
VBIAS (DAC)
VD
9
28
VCOM
SYNC
10
27
VREF+ (ADC)
RESET#
11
26
AGND
GPIO1/DMIC_SDA2
/SPDIF_OUT2
12
25
VA
Pin Name
GPIO2
GPIO3
MICBIAS
MICIN_L-
MICIN_L+
19
20
21
22
23
24
VA_REF
18
LINEIN_R+
17
LINEIN_C-
16
LINEIN_L+
15
MICIN_R-
14
MICIN_R+
13
SENSE_A
HPREF
Top-Down (Through Package) View
48-Pin QFN Package
#
Pin Description
VL_IF
1
Digital Interface Signal Level (Input) - Determines the required signal level for the GPIO, S/PDIF and
Digital Mic interfaces. Refer to the Recommended Operating Conditions for appropriate voltages.
GPIO0/
DMIC_SDA1
2
General Purpose I/O (Input/Output) - General purpose input or output line, or
Digital Mic Data Input (Input) - The second data input line from a digital microphone.
VL_HD
3
Digital Interface Signal Level (Input) - Determines the required signal level for the HD Audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
DMIC_SCL
4
Digital Mic Clock (Output) - The high speed clock output to the digital microphone.
SDO
5
Serial Data Input (Input) - Serial data input stream from the HD Audio Bus.
BITCLK
6
Bit Clock (Input) - 24 MHz bit clock from the HD Audio Bus.
DGND
7
Digital Ground (Input) - Ground reference for the internal digital section.
SDI
8
Serial Data Output (Input/Output) - Serial data output stream to the HD Audio Bus.
VD
9
Digital Power (Input) - Positive power for the internal digital section.
SYNC
10
SYNC Clock (Input) - 48 kHz sync clock from the HD Audio Bus.
RESET#
11
Reset (Input) - The device enters a low power mode when this pin is driven low.
DS880PB1
3
CS4207
GPIO1/
DMIC_SDA2/
SPDIF_OUT2
12
General Purpose I/O (Input/Output) - General purpose input or output line, or
Digital Mic Data Input (Input) - The second data input line from a digital microphone, or
S/PDIF Output (Output) - Output from internal S/PDIF Transmitter.
SENSE_A
13
Jack Sense Pin (Input/Output) - Jack sense detect.
GPIO2
14
General Purpose I/O (Input/Output) - General purpose input or output lines.
GPIO3
15
General Purpose I/O (Input/Output) - General purpose input or output lines.
MICBIAS
16
Microphone Bias (Output) - Provides a low noise bias supply for an external microphone. Electrical
characteristics are specified in the DC Electrical Characteristics table.
MICIN_LMICIN_L+
MICIN_R+
MICIN_R-
17
18
19
20
Microphone Input Left/Right (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.
LINEIN_L+
LINEIN_CLINEIN_R+
21
22
23
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
VA_REF
VA
24
25
Analog Power (Input) - Positive power for the internal analog section. VA_REF is the return pin for the
VBIAS cap.
AGND
26
Analog Ground (Input) - Ground reference for the internal analog section.
VREF+
27
Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs.
VCOM
28
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VBIAS
29
Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs.
LINEOUT_L2LINEOUT_L2+
LINEOUT_R2+
LINEOUT_R2LINEOUT_L1LINEOUT_L1+
LINEOUT_R1+
LINEOUT_R1-
30
31
32
33
34
35
36
37
Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table
HPOUT_L
38
Analog Headphone Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table.
HPREF
39
Pseudo Diff. Headphone Reference (Input) - Ground reference for the headphone amplifiers.
HPOUT_R
40
Analog Headphone Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table.
VHP_FILT-
41
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump
that provides the negative rail for the headphone amplifier.
FLYN
42
Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s flying
capacitor.
FLYC
43
Charge Pump Cap Common Node (Output) - Common positive node for the step-down and inverting
charge pumps’ flying capacitor.
VHP_FILT+
44
Non-Inverting Charge Pump Filter Connection (Output) - Power supply from the step-down charge
pump that provides the positive rail for the headphone amplifier.
FLYP
45
Charge Pump Cap Positive Node (Output) - Positive node for the step-down charge pump’s flying
capacitor.
VA_HP
46
Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.
SPDIF_IN
47
S/PDIF Input (Input) - Input to internal S\PDIF Receiver.
SPDIF_OUT1
48
Thermal Pad
-
4
S/PDIF Output (Output) - Output from internal S/PDIF Transmitter.
HP Ground (Thermal Pad) - Ground reference for the internal headphone section.
DS880PB1
CS4207
2. TYPICAL CONNECTION DIAGRAMS
+5.0 V
+1.8 V
0.1 µF
0.1 µF
VD
VA
+5.0 V
0.1 µF
+
VA_REF
10 µF
HPOUT_L
VBIAS
VA_HP
+5.0 V
CS4207
VHP_FILT+
Left Headphone
33 Ω
0.1 µF
HPREF
Headphone Ground
HPOUT_R
Right Headphone
33 Ω
0.1 µF
VHP_FILT0.1 µF **10 µF **10 µF
LINEOUT_L1+
FLYP
LINEOUT_L1-
Differential to
Single-Ended
Output Filter
‡
Differential to
Single-Ended
Output Filter
‡
Differential to
Single-Ended
Output Filter
‡
Differential to
Single-Ended
Output Filter
‡
+Left Line Output 1
** 2.2 µF
FLYC
** 2.2 µF
FLYN
** Use low ESR
ceramic capacitors.
LINEOUT_R1+
LINEOUT_R1LINEOUT_L2+
BITCLK
LINEOUT_L2-
SYNC
HD Audio
Bus
LINEOUT_R2+
SDI
LINEOUT_R2-
SDO
RESET
+Right Line Output 1
+Left Line Output 2
+Right Line Output 2
* Capacitors must be C0G or equivalent
+1.5 V to +3.3 V
VL_HD
LINEIN_L+
0.1 µF
1 µF
Left Analog Input
*
1800 pF
1 µF
LINEIN_C+3.3 V
VL_IF
LINEIN_R+
0.1 µF
1 µF
Right Analog Input
*
1800 pF
GPIO2
GPIO3
SENSE_A
GPIO2
GPIO3
MICIN_L1 µF
SENSE_A
Differential Mic Left
MICIN_L+
1 µF
S/PDIF RX
SPDIF_IN
S/PDIF TX 1
SPDIF_OUT1
D-Mic In 2 / S/PDIF TX 2
DMIC_SDA2/
SPDIF_OUT2
Microphone Bias
MICBIAS
RL
0.47 µF
The value of R L is dictated by
the microphone cartridge.
RL
MICIN_R+
Differential Mic Right
1 µF
D-Mic In 1
DMIC_SDA1
D-Mic Clk
DMIC_SCL
MICIN_R1 µF
VCOM
VREF+
1 µF
10 µF
‡ Input and Output
filters are optional.
AGND
HP_GND(Thermal Pad)
Figure 1. Typical Connection Diagram - Desktop System
DS880PB1
5
CS4207
+3.3 V
+1.8 V
0.1 µF
0.1 µF
VD
VA
+3.3 V
0.1 µF
+
VA_REF
10 µF
HPOUT_L
VBIAS
VA_HP
+3.3 V
CS4207
VHP_FILT+
Left Headphone
33 Ω
0.1 µF
HPREF
Headphone Ground
HPOUT_R
Right Headphone
33 Ω
0.1 µF
VHP_FILT0.1 µF **10 µF **10 µF
LINEOUT_L1+
LINEOUT_L1FLYP
** 2.2 µF
FLYC
LINEOUT_R1+
FLYN
LINEOUT_R1-
** 2.2 µF
* *Use low ESR
ceramic capacitors.
LINEOUT_L2+
560 Ω
* 2200 pF
BITCLK
LINEOUT_L2-
SYNC
HD Audio
Bus
560 Ω
Speaker Driver
SDI
SDO
LINEOUT_R2+
560 Ω
* 2200 pF
RESET
LINEOUT_R2-
+1.5 V to +3.3 V
560 Ω
Speaker Driver
VL_HD
0.1 µF
* Capacitors must be C0G or equivalent
LINEIN_L+
1 µF
Left Analog Input
*
1800 pF
+3.3 V
VL_IF
1 µF
LINEIN_C-
0.1 µF
LINEIN_R+
1 µF
Right Analog Input
*
1800 pF
GPIO2
GPIO3
SENSE_A
GPIO2
GPIO3
SENSE_A
MICIN_LLeft Mic In
MICIN_L+
1 µF
S/PDIF RX
SPDIF_IN
S/PDIF TX 1
SPDIF_OUT1
D-Mic In 2 / S/PDIF TX 2
DMIC_SDA2/
SPDIF_OUT2
Microphone Bias
MICBIAS
RL
0.47 µF
The value of R L is dictated by
the microphone cartridge.
RL
MICIN_R+
Right Mic In
1 µF
MICIN_RD-Mic In 1
DMIC_SDA1
D-Mic Clk
DMIC_SCL
VCOM
VREF+
1 µF
10 µF
AGND
HP_GND(Thermal Pad)
Figure 2. Typical Connection Diagram - Portable System
6
DS880PB1
CS4207
3. PACKAGE DIMENSIONS
48LD QFN (6 X 6 mm BODY) PACKAGE DRAWING
D
D2
L
e
E
E2
1
b
BTM VIEW
TOP VIEW
A
A1
A3
SEATING
PLANE
SIDE VIEW
Notes:
1) Controlling dimensions are in mm.
2) Dimensioning and tolerancing conform to ASME Y14.5m-1994
3) Dimension b applies to the metallized terminal and is measured between 0.15mm
and 0.30mm from the terminal tip.
4) Reference JEDEC MO-229
DS880PB1
DIM
MIN
NOM
MAX
A
A1
A3
b
D
D2
E
E2
e
L
0.70
0.00
0.75
0.80
0.05
0.15
4.25
4.25
0.35
0.20 BSC
0.20
6.00 BSC
4.40
6.00 BSC
4.40
0.40 BSC
0.45
0.25
4.50
4.50
0.55
7
CS4207
4. ORDERING INFORMATION
Product
CS4207
CS4207
CDB4207
Description
Package Pb-Free
Low Power, 4-In/6-Out
HD Audio CODEC with 48L-QFN
Headphone Amp
Low Power, 4-In/6-Out
HD Audio CODEC with 48L-QFN
Headphone Amp
CS4207 Evaluation Board
Grade
Temp Range
Yes
Commercial -40°C to +85°C
Yes
Automotive -40°C to +105°C
-
-
Container
Order #
Rail
CS4207-CNZ/C1
Tape & Reel CS4207-CNZR/C1
Rail
CS4207-DNZ
Tape & Reel
CS4207-DNZR
-
CDB4207
-
5. REFERENCES
1. Intel Corporation, High Definition Audio Specification, Revision 1.0, April 15, 2004.
http://download.intel.com/standards/hdaudio/pdf/HDAudio_03.pdf
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
8
DS880PB1