TLV320AIC33 SLAS480 -- MAY 24, 2005 PRELIMINARY INFORMATION REV.17 Low Power Stereo Audio Codec for Portable Audio/Telephony FEATURES DESCRIPTION • STEREO AUDIO DAC • 103dB-A SIGNAL-TO-NOISE RATIO • 16/20/24/32-BIT DATA • SUPPORTS RATES FROM 8-kHz to 96-kHz • 3D/BASS/TREBLE/EQ/DE-EMPHASIS EFFECTS The TLV320AIC33 is a low power stereo audio codec with stereo headphone amplifier, as well as multiple inputs and outputs programmable in single-ended or fully-differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 15mW(TBD) from a 3.3V analog supply, making it ideal for portable battery-powered audio and telephony applications. • STEREO AUDIO ADC • 92dB-A SIGNAL-TO-NOISE RATIO • SUPPORTS RATES FROM 8-kHz TO 96-kHz • TEN AUDIO INPUT PINS • PROGRAMMABLE IN SINGLE-ENDED OR FULLY DIFFERENTIAL CONFIGURATIONS • TRI-STATE CAPABILITY FOR FLOATING INPUT CONFIGURATIONS • SEVEN AUDIO OUTPUT DRIVERS • STEREO 8-OHM 325mW/CHANNEL SPEAKER DRIVE CAPABILITY • STEREO FULLY-DIFFERENTIAL OR SINGLEENDED HEADPHONE DRIVERS • FULLY DIFFERENTIAL STEREO LINE OUTPUTS • FULLY DIFFERENTIAL MONO OUTPUT • LOW POWER: 14mW STEREO 48-kHz PLAYBACK WITH 3.3V ANALOG SUPPLY • PROGRAMMABLE INPUT/OUTPUT ANALOG GAINS • AUTOMATIC GAIN CONTROL (AGC) FOR RECORD • PROGRAMMABLE PLL FOR FLEXIBLE CLOCK GENERATION • CONTROL BUS SELECTABLE SPI OR I2C • AUDIO SERIAL DATA BUS SUPPORTS I2S, LEFT/RIGHT-JUSTIFIED, DSP, AND TDM MODES • ALTERNATE SERIAL PCM/I2S DATA BUS FOR EASY CONNECTION TO BLUETOOTH MODULE • EXTENSIVE MODULAR POWER CONTROL • POWER SUPPLIES: • ANALOG: 2.7V – 3.6V • DIGITAL CORE: 1.525V – 1.95V • DIGITAL I/O: 1.1V – 3.6V • PACKAGES: 5X5MM 80-BGA 7X7MM 48-QFN The TLV320AIC33 contains four high-power output drivers as well as three fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using ac-coupling capacitors, or stereo 16Ω headphones in a cap-less output configuration. In addition, pairs of drivers can be used to drive 8-Ω speakers in a BTL configuration at 325mW per channel. The stereo audio DAC supports sampling rates from 8-kHz to 96-kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48kHz rates. The stereo audio ADC supports sampling rates from 8-kHz to 96-kHz and is preceded by programmable gain amplifiers providing up to +59.5-dB analog gain for low-level microphone inputs. • PROGRAMMABLE MICROPHONE BIAS LEVEL • DIGITAL MICROPHONE INPUT SUPPORT The record path of the TLV320AIC33 contains integrated microphone bias, digitally controlled stereo microphone preamp, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs. The serial control bus supports SPI or I2C protocols, while the serial audio data bus is programmable for I2S, left/rightjustified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 2-MHz to 50-MHz, with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2MHz, and 19.68-MHz system clocks. The TLV320AIC33 operates from an analog supply of 2.7V – 3.6V, a digital core supply of 1.525V – 1.95V, and a digital I/O supply of 1.1V – 3.6V. The device is available in 5x5mm 80-ball u*jr BGA and 7x7mm 48-lead QFN. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appear at the end of this data sheet. Copyright © 2005, Texas Instruments Incorporated The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com 1 TLV320AIC33 MAY 24, 2005 PRELIMINARY INFORMATION REV.17 WCLK DIN DOUT BCLK AVDD_ADC AVSS_ADC AVDD_DAC AVSS_DAC DRVDD DRVSS DRVDD DRVSS DVDD DVSS IOVDD SIMPLIFIED BLOCK DIAGRAM Audio Serial Bus Voltage Supplies + HPL+ MIC2/LINE2L+ MIC2/LINE2L- MIC3/LINE3L MIC1/LINE1L+ MIC1/LINE1L- MIC1/LINE1R+ MIC1/LINE1R- VCM + PGA 0/+59.5dB 0.5dB steps + PGA 0/+59.5dB 0.5dB steps HPL-/HPLCOM + Volume Ctl & Effects ADC DAC L + Volume Ctl & Effects ADC HPR-/HPRCOM/ SPKFC VCM DAC R MIC3/LINE3R + MIC2/LINE2R+ MIC2/LINE2RBias/ Reference Audio Clock Generation + SPI / I2C Serial Control Bus HPR+ LINE_OUT_L+ LINE_OUT_L- SDA/GPIO SCL/GPIO MISO/GPIO MOSI/GPIO SCLK/I2C_ADR1 CSEL/I2C_ADR0 SELECT RESETB GPIO_2 GPIO_1 MCLK MICBIAS MICDET + LINE_OUT_R+ LINE_OUT_R- + MONO_OUT+ MONO_OUT- Figure 1. Simplified codec block diagram Copyright © 2004, Texas Instruments Incorporated The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com 2 TLV320AIC33 MAY 24, 2005 PRELIMINARY INFORMATION REV.17 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR BGA-80 ZQE QFN-48 RGZ OPERATING TEMPERATURE RANGE ORDERING NUMBER TRANSPORT MEDIA, QUANTITY -40C to 85C TLV320AIC33IZQE TLV320AIC33IZQER TLV320AIC33IRGZ TLV320AIC33IRGZR Trays??, xx Tape and Reel, 2000 Rails, 52 Tape and Reel, 2000 3 7 TLV320AIC33 PIN ASSIGNMENTS 1 12 J 13 48 H G F E D C B 37 24 36 A 1 25 48-lead QFN Package (Bottom view) 2 4 5 6 8 9 5x5mm 80-Ball BGA Package (Bottom View) (Not to scale) (Note: Shaded balls on BGA package are not connected to the die, but are electrically connected to each other.) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appear at the end of this data sheet. Copyright © 2004, Texas Instruments Incorporated The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com 3 TLV320AIC33 MAY 24, 2005 PRELIMINARY INFORMATION REV.17 PIN DESCRIPTION BGA BALL A2 A1 C2,D2 B1,C1 QFN PIN NUMBER 13 14 15 16,17 D1 E1 E2,F2 18 19 20,21 F1 G1 H1 J1 G2,H2 J2 J3 J4 J5 J6 J7 H8 PIN NAME DESCRIPTION MICBIAS MIC3R AVSS_ADC VDDA1 Microphone Bias Voltage Output MIC3 Input (Right or Multifunction) Analog ADC Ground Supply, 0V ADC Analog and Output Driver Voltage Supply, 2.7V – 3.6V HPLOUT HPLCOM DRVSS High Power Output Driver (Left Plus) High Power Output Driver (Left Minus or Multifunctional) Analog Output Driver Ground Supply, 0V 22 23 24 25 26 27 28 29 30 31 32 33 HPRCOM HPROUT VDDA1 AVDDA2 AVSS_DAC MONO_LOP MONO_LOM LEFT_LOP LEFT_LOM RIGHT_LOP RIGHT_LOM /RESET J8 34 GPIO2 J9 H9 G8 G9 F9 E9 F8 D9 E8 C9 B8 B9 A8 35 36 37 38 39 40 41 42 43 44 45 46 47 GPIO1 DVDD MCLK BCLK WCLK DIN DOUT DVSS SELECT IOVDD MFP0 MFP1 MFP2 A9 C8 D8 A7 A6 48 1 2 MFP3 SCL SDA NC LINE1LP High Power Output Driver (Right Minus or Multifunctional) High Power Output Driver (Right Plus) ADC Analog and Output Driver Voltage Supply, 2.7V – 3.6V Analog DAC Voltage Supply, 2.7V – 3.6V Analog DAC Ground Supply, 0V Mono Line Output (Plus) Mono Line Output (Minus) Left Line Output (Plus) Left Line Output (Minus) Right Line Output (Plus) Right Line Output (Minus) Reset General Purpose Input/Output #2 (Input/Output) / Digital Microphone Data Input / PLL Clock Input / Audio Serial Data Bus Bit Clock Input/Output General Purpose Input/Output #1 (Input/Output) / PLL/Clock Mux Output / Short Circuit Interrupt / AGC Noise Flag / Digital Microphone Clock / Audio Serial Data Bus Word Clock Input/Output Digital Core Voltage Supply, 1.525V – 1.95V Master Clock Input Audio Serial Data Bus Bit Clock (Input/Output) Audio Serial Data Bus Word Clock (Input/Output) Audio Serial Data Bus Data Input (Input) Audio Serial Data Bus Data Output (Output) Digital Core / I/O Ground Supply, 0V Select Pin (SPI vs I2C Control Mode) I/O Voltage Supply, 1.1V – 3.6V Multifunction pin #0 - SPI Chip Select / GPI / I2C Address Pin #0 Multifunction pin #1 - SPI Serial Clock / GPI / I2C Address Pin #1 Multifunction pin #2 - SPI MISO Slave Serial Data Output / GPO Multifunction pin #3 - SPI MOSI Slave Serial Data Input / GPI / Audio Serial Data Bus Data Input I2C Serial Clock / GPIO I2C Serial Data Input/Output / GPIO No Connect MIC1 or Line1 Analog Input (Left Plus or Multifunction) 3 The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. 4 The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com TLV320AIC33 MAY 6, 2005 PRELIMINARY INFORMATION REV.17 A5 B7 B6 A4 B5 B4 A3 B3 B2 4 5 6 7 8 9 10 11 12 LINE1LM LINE1RP LINE1RM LINE2LP LINE2LM LINE2RP LINE2RM MIC3L MICDET MIC1 or Line1 Analog Input (Left Minus or Multifunction) MIC1 or Line1 Analog Input (Right Plus or Multifunction) MIC1 or Line1 Analog Input (Right Minus or Multifunction) MIC2 or Line2 Analog Input (Left Plus or Multifunction) MIC2 or Line2 Analog Input (Left Minus or Multifunction) MIC2 or Line2 Analog Input (Right Plus or Multifunction) MIC2 or Line2 Analog Input (Right Minus or Multifunction) MIC3 Input (Left or Multifunction) Microphone Detect ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted (1) RATINGS -0.3V to 3.9V -0.3V to 3.9V -0.3V to 3.9V -0.3V to 2.5V -0.1V to 0.1V -0.3V to IOVDD+0.3V -0.3V to AVDD+0.3V -40°C to +85°C -65°C to +105°C +105°C (TJ Max – TA) / θJA TBD TBD TBD VDDA1 to VSS, VDDA2 to AVSS_DAC VDDA1 to DRVSS IOVDD to DVSS DVDD to DVSS VDDA2 to VDDA1 Digital Input Voltage to DVSS Analog Input Voltage to AVSS Operating temperature range Storage temperature range Junction temperature (TJ Max) BGA package Lead temperature Power dissipation θJA Thermal impedance Soldering vapor phase (60 sec) Infrared (15 sec) (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Analog supply voltage VDDA2, VDDA1(2) Digital core supply voltage DVDD(2) Digital I/O supply voltage IOVDD(2) Analog full-scale 0dB input voltage (VDDA2, VDDA1 = 3.3V) Stereo line output load resistance Stereo headphone output load resistance Digital output load capacitance Operating free-air temperature, TA MIN 2.7 1.525 1.1 10 TBD -40 NOM 3.3 1.8 1.8 0.707 MAX 3.6 1.95 3.6 16 10 +85 UNIT V V V VRMS kΩ Ω pF °C (2) Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to DVSS. The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com 5 TLV320AIC33 MAY 24, 2005 PRELIMINARY INFORMATION REV.17 ELECTRICAL CHARACTERISTICS At 25°C, VDDA1, VDDA2, IOVDD = 3.3V, DVDD = 1.8V, Fs=48-kHz, 24-bit audio data, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNITS AUDIO ADC Input signal level (0-dB) Single-ended input configuration 0.707 VRMS Fs=48-kHz, 0-dB PGA gain, Signal-to-noise ratio, A92 dB MIC1/LINE1 inputs selected and weighted(3)(4) AC-shorted together Fs=48-kHz, 1-kHz -60-dB full-scale Dynamic range, A-weighted(3)(4) 92 dB input applied at MIC1/LINE1 inputs, 0-dB PGA gain Fs=48-kHz, 1-kHz -1-dB full-scale Total harmonic distortion -80 dB input applied at MIC1/LINE1 inputs, 0-dB PGA gain 1-kHz, 100mVpp on AVDD, Power supply rejection ratio TBD dB DRVDD 1-kHz, -1-dB ADC channel separation TBD dB ADC programmable gain amplifier 1-kHz input tone, RSOURCE<50Ω maximum gain ADC programmable gain amplifier step size MIC1/LINE1 inputs, Input resistance Input Mix Attenuation = 0-dB Input capacitance MIC1/LINE1 inputs Input level control minimum attenuation setting Input level control maximum attenuation setting Input level control attenuation step size ADC DIGITAL DECIMATION Fs=48kHz FILTER FILTER GAIN FROM 0 TO 0.39FS Filter gain at 0.4125Fs Filter gain at 0.45Fs Filter gain at 0.5Fs Filter gain from 0.55Fs to 64Fs FILTER GROUP DELAY MICROPHONE BIAS 1 Bias voltage Current sourcing Output noise voltage AUDIO DAC Programmable settings 2.5V setting 2.5V setting Line output, Load = 10kΩ, 50pF The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. 6 +59.5 dB 0.5 dB 20 kΩ 10 pF 0 dB dB 12 1.5 dB ±0.1 dB -0.25 -3 -17.5 -75 17/Fs dB dB dB dB Sec 2.0 2.5 VDDA1 V 4 TBD mA nV/√Hz The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com TLV320AIC33 MAY 6, 2005 PRELIMINARY INFORMATION REV.17 0-dB full-scale output voltage Signal-to-noise ratio, Aweighted(5) Dynamic range, A-weighted Total harmonic distortion Power supply rejection ratio DAC channel separation (left to right) DAC Digital Interpolation Filter Passband Passband ripple Transition band Stopband Stopband attenuation Group delay Stereo Headphone Driver 0-dB full-scale output voltage Programmable Output Common Mode Voltage 0-dB gain to line outputs. DAC output common-mode setting = 1.35V, output level control gain = 0-dB Fs=48-kHz, 0-dB gain to line outputs, zero signal applied, referenced to full-scale input level Fs=48-kHz, 0-dB gain to line outputs, 1-kHz -60-dB signal applied Fs=48-kHz, 1-kHz -1-dB full-scale signal applied 1-kHz, 100mVpp on AVDD_DAC, AVDD_ADC, DRVDD1/2 1-kHz, 0-dB Fs = 48-kHz High-pass filter disabled High-pass filter disabled Power supply rejection ratio Mute attenuation Digital I/O 103 dB 103 dB -80 dB TBD dB TBD dB 0.45*Fs 65 21/Fs 0-dB gain to high power outputs. Output common-mode voltage setting = 1.35V 0.707 VRMS First option 1.35 V Second option Third option Fourth option 1.50 1.65 1.8 V V V 9 dB 1 dB 15 30 mW 95 dB TBD TBD dB TBD dB TBD dB TBD 0.45*Fs 0.55*Fs 0.55*Fs 7.5*Fs Pseudo-differential output configuration (5) RL = 32Ω RL = 16Ω Signal-to-noise ratio, Aweighted(6) Total harmonic distortion VRMS Hz dB Hz Hz dB Sec Maximum Programmable Output Level Control Gain Programmable Output Level Control Gain Step Size Maximum output power, PO 1.414 1-kHz output, PO = 10mW 1-kHz output, PO = 20mW 1-kHz, 100mVpp on AVDD_ADC, AVDD_DAC, DRVDD1/2 1-kHz output The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com 7 TLV320AIC33 MAY 24, 2005 PRELIMINARY INFORMATION REV.17 VIL Input low level IIL = +5-uA -0.3 VIH Input high level IIH = +5-uA 0.7 x IOVDD VOL Output low level IIH = 2 TTL loads VOH Output high level IOH = 2 TTL loads 0.3 x IOVDD V 0.1 x IOVDD 0.8 x IOVDD V V V Supply Current Fs = 48-kHz VDDA1 TBD Fs=48-kHz, PLL off, Stereo line playback VDDA2 TBD headphone drivers off DVDD TBD VDDA1 TBD Fs=48-kHz, PLL and Mono record VDDA2 TBD AGC off DVDD TBD VDDA1 TBD Fs=48-kHz, PLL and Stereo record VDDA2 TBD AGC off DVDD TBD VDDA1 Additional power TBD mA PLL VDDA2 consumed when PLL is TBD DVDD powered TBD VDDA1 LINE2LP/RP only routed TBD VDDA2 to single-ended TBD Headphone amplifier headphones, DAC and TBD DVDD PLL off, no signal applied VDDA1 All supply voltages TBD VDDA2 applied, all blocks TBD Power down programmed in lowest TBD DVDD power state (3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (4) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. (5) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35V, 0-dB output level control gain, 16-ohm single-ended load. (6) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to 20-kHz bandwidth. The product described herein is a prototype product. TI makes no warranty, either expressed, implied, or statutory, including any implied warranty or merchantability or fitness for a specific purpose, as to this product. 8 The information contined here concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TLV320AIC33IGQE PREVIEW VFBGA GQE 80 360 TBD Call TI Call TI TLV320AIC33IGQER PREVIEW VFBGA GQE 80 2500 TBD Call TI Call TI TLV320AIC33IRGZ PREVIEW QFN RGZ 48 250 TBD Call TI Call TI TLV320AIC33IRGZR PREVIEW QFN RGZ 48 2000 TBD Call TI Call TI TLV320AIC33IZQE PREVIEW BGA MI CROSTA R JUNI OR ZQE 80 360 TBD Call TI Call TI TLV320AIC33IZQER PREVIEW BGA MI CROSTA R JUNI OR ZQE 80 2500 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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