CS4353 3.3 V Stereo Audio DAC with 2 VRMS Line Output Features Description Multi-bit Delta-Sigma Modulator The CS4353 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a 3.3 V supply. 106 dB A-weighted Dynamic Range -93 dB THD+N Single-ended Ground Centered Analog Architecture – No DC-blocking Capacitors Required – Integrated Step-up/Inverting Charge Pump – Filtered Line-level Outputs – Selectable 1 or 2 VRMS Full-scale Output Low Clock-jitter Sensitivity Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit Resolution +3.3 V Charge Pump and Core Logic, +3.3 V Digital Core Logic and Charge Pump Supply (VCP) +3.3 V Analog Supply (VA) +3.3 V Power-On Reset Level Shifter Reset Hardware Control The CS4353 is available in a 24-pin QFN package in Commercial (-40°C to +85°C) grade. The CDB4353 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 25 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-component systems, and mixing consoles. Analog, and +0.9 to 3.3 V Interface Power Supplies Low Power Consumption 24-pin QFN, Lead-free Assembly Interface Supply (VL) +0.9 V to +3.3 V The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. Serial Audio Input Step-Up Inverting Hardware Control +VA_H -VA_H Ground-Centered, 2 Vrms Line Level Outputs Left Channel PCM Serial Audio Port Interpolation Filters Multibit Modulator DAC Pseudo Diff. Input Right Channel Auto Speed Mode Detect http://www.cirrus.com Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) MAY ‘11 DS803F3 CS4353 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DAC ANALOG CHARACTERISTICS .................................................................................................... 7 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 8 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ................................................... 9 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 4. APPLICATIONS ................................................................................................................................... 13 4.1.1 Ground-centered Outputs ...................................................................................................... 13 4.1.2 Full-scale Output Amplitude Control ...................................................................................... 13 4.1.3 Pseudo-differential Outputs ................................................................................................... 13 4.9.1 Power-up Sequences ............................................................................................................ 19 4.9.1.1 External RESET Power-up Sequence ....................................................................... 19 4.9.1.2 Internal Power-on Reset Power-up Sequence .......................................................... 19 4.9.2 Power-down Sequences ....................................................................................................... 19 4.9.2.1 External RESET Power-down Sequence .................................................................. 19 4.9.2.2 Internal Power-on Reset Power-down Sequence ...................................................... 19 4.10.1 Capacitor Placement ........................................................................................................... 20 5. DIGITAL FILTER RESPONSE PLOTS ......................................................................................... 21 6. PARAMETER DEFINITIONS ................................................................................................................ 23 7. PACKAGE DIMENSIONS .................................................................................................................... 24 8. ORDERING INFORMATION ............................................................................................................... 25 9. REVISION HISTORY ........................................................................................................................... 25 2 DS803F3 CS4353 LIST OF FIGURES Figure 1.Serial Input Timing ........................................................................................................................ 9 Figure 2.Power-on Reset Threshold Sequence ........................................................................................ 10 Figure 3.Typical Connection Diagram ....................................................................................................... 12 Figure 4.Stereo Pseudo-differential Output ............................................................................................... 13 Figure 5.I²S, up to 24-bit Data ................................................................................................................... 15 Figure 6.Left-justified up to 24-bit Data ..................................................................................................... 15 Figure 7.De-emphasis Curve, Fs = 44.1 kHz ............................................................................................ 16 Figure 8.Internal Power-on Reset Circuit .................................................................................................. 16 Figure 9.Initialization and Power-down Sequence Diagram ..................................................................... 18 Figure 10.Single-speed Stopband Rejection ............................................................................................. 21 Figure 11.Single-speed Transition Band ................................................................................................... 21 Figure 12.Single-speed Transition Band (detail) ....................................................................................... 21 Figure 13.Single-speed Passband Ripple ................................................................................................. 21 Figure 14.Double-speed Stopband Rejection ........................................................................................... 21 Figure 15.Double-speed Transition Band ................................................................................................. 21 Figure 16.Double-speed Transition Band (detail) ..................................................................................... 22 Figure 17.Double-speed Passband Ripple ............................................................................................... 22 Figure 18.Quad-speed Stopband Rejection .............................................................................................. 22 Figure 19.Quad-speed Transition Band .................................................................................................... 22 Figure 20.Quad-speed Transition Band (detail) ........................................................................................ 22 Figure 21.Quad-speed Passband Ripple .................................................................................................. 22 LIST OF TABLES Table 1. Digital I/O Pin Characteristics ..................................................................................................... 11 Table 2. CS4353 Operational Mode Auto-Detect ...................................................................................... 14 Table 3. Single-speed Mode Standard Frequencies ................................................................................. 14 Table 4. Double-speed Mode Standard Frequencies ............................................................................... 14 Table 5. Quad-speed Mode Standard Frequencies .................................................................................. 14 Table 6. Digital Interface Format ............................................................................................................... 15 DS803F3 3 CS4353 SDIN LRCK I²S/LJ DEM 1_2VRMS RESET 1. PIN DESCRIPTIONS 24 23 22 21 20 19 SCLK 1 18 VBIAS MCLK 2 17 VA VL 3 16 AGND 15 AOUTA 14 AOUT_REF 13 AOUTB Thermal Pad DGND 4 FLYP- 5 Top-Down (Through Package) View 24-Pin QFN Package Pin Name Pin # FLYN+ 10 11 12 VFILT- 9 FLYN- 8 CPGND 7 VFILT+ 6 FLYP+ VCP Pin Description SCLK 1 Serial Clock (Input) - Serial clock for the serial audio interface. MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VL 3 Serial Audio Interface Power (Input) - Positive power for the serial audio interface DGND 4 Digital Ground (Input) - Ground reference for the digital section. FLYP+ FLYP- 7 5 Step-up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the step-up charge pump’s flying capacitor. VCP 6 Charge Pump and Digital Core Logic Power (Input) - Positive power supply for the step-up and inverting charge pumps as well as the digital core logic sections. VFILT+ 8 Step-up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that provides the positive rail for the output amplifiers FLYN+ FLYN- 9 11 Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor. CPGND 10 Charge Pump Ground (Input) - Ground reference for the Charge Pump section. VFILT- 12 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. AOUTB AOUTA 13 15 Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table. AOUT_REF 14 Pseudo Diff. Analog Output Reference (Input) - Ground reference for the analog output amplifiers. This pin must be at the same nominal DC voltage as the AGND pin. AGND 16 Analog Ground (Input) - Ground reference for the low voltage analog section. 4 DS803F3 CS4353 VA 17 Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. RESET 19 Reset (Input) - Optional connection for an external reset control. The device enters a powered-down state when this pin is set low (GND) OR when the VCP supply falls below the Voff threshold (see See “Internal Power-on Reset Threshold Voltages” on page 10.). This pin should be set high (VL) during normal operation. 1_2VRMS 20 1 or 2 VRMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND) selects 1 VRMS, while setting it high (VL) selects 2 VRMS. DEM 21 De-emphasis (Input) - Selects the standard 50 s/15 s digital de-emphasis filter response for 44.1 kHz sample rates when enabled. I²S/LJ 22 Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND) selects I²S, while setting it high (VL) selects Left-Justified. LRCK 23 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SDIN 24 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Pad DS803F3 - Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections. 5 CS4353 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. Parameters Symbol Min Typ Max Units Charge Pump and Digital Core power (Note 1) Low Voltage Analog power (Note 1) Interface power Ambient Operating Temperature (Power Applied) VCP VA VL TA 3.13 3.13 0.85 -40 3.3 3.3 0.9 to 3.3 - 3.47 3.47 3.47 +85 V V V °C DC Power Supply Note: 1. VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the supply voltages applied to VCP and VA differ by more than 0.5 V. ABSOLUTE MAXIMUM RATINGS AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. Parameters Symbol Min Max Units Charge Pump and Digital Core Logic Power Low Voltage Analog Power Supply Voltage Difference Interface Power Input Current, Any Pin Except Supplies Digital Input Voltage Digital Interface Analog Input Voltage AOUT_REF Ambient Operating Temperature (Power Applied) Storage Temperature VCP VA |VCP - VA| VL Iin VIN-L VIN-A TA Tstg -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 3.63 3.63 0.5 3.63 ±10 VL+ 0.4 0.5 +125 +150 V V V V mA V V °C °C DC Power Supply WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS803F3 CS4353 DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND = CPGND = 0 V; VBIAS, VFILT+/-, and FLYP/N+/- capacitors as shown in Figure 3 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. 1_2VRMS = 0 Parameter Symbol Min 1_2VRMS = 1 Typ Max Min Typ Max Unit 94 91 - 100 97 92 89 - 100 97 - 106 103 98 95 - dB dB dB dB 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB - -93 -77 -37 -93 -75 -29 -87 -71 -31 - - -93 -83 -43 -93 -75 -35 -87 -77 -37 - dB dB dB dB dB dB (A-wt) - 100 - - 106 - dB (1 kHz) - 115 - - 115 - dB Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3, 4) Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted Total Harmonic Distortion + Noise 24-bit 16-bit Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Analog Output (Note 5) Full Scale AOUTx Output Voltage (Notes 4, 6, 7) 1.02 1.08 1.13 2.04 2.15 2.26 VRMS 2.89 3.05 3.20 5.78 6.09 6.40 Vpp - 575 - - 575 - A Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Output Offset - ±5 ±8 - ±5 ±8 mV Gain Drift - 100 - - 100 - ppm/°C ZOUT - 100 - - 100 - RL 5 - - 5 - - k CL - - 1000 - - 1000 pF AOR - 40 - - 40 - dB - - 0.2 - - 0.2 Vpp Max Current Draw from an AOUTx Pin IOUTmax Output Impedance AC-Load Resistance Load Capacitance AOUT_REF Rejection (Notes 8, 9) Analog Reference Input AOUT_REF Input Voltage (Note 10) Notes: 2. Measured at the output of the external LPF on AOUTx as shown in Figure 3 on page 12. 3. One LSB of triangular PDF dither is added to data. 4. Measured with the specified minimum AC-Load Resistance present on the AOUTx pins. 5. Measured between the AOUTx and AOUT_REF pins. 6. External impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 7. VPP is the controlling specification. VRMS specification valid for sine wave signals only. V ppNote that for sine wave signals: V RMS = --------2 2 8. Measured with AOUT_REF connected directly to ground. External impedance between AOUT_REF and ground will lower the AOUT_REF rejection. DS803F3 7 CS4353 9. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the test signal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Specification calculated by: AOR dB = 20 log 10 --------------------------------------------------------- AOUT_REF AOUT_REF – AOUTx 10. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. See Section 4.1.3 for more information. COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Parameter Single-Speed Mode - 48 kHz Passband (Note 11) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 13) (Relative to 1 kHz) to -0.01 dB corner to -3 dB corner (Note 12) Fs = 44.1 kHz Min Typ Max Unit 0 0 -0.01 0.547 102 - 9.4/Fs - .454 .499 +0.01 ±0.56/Fs 0 ±0.14 Fs Fs dB Fs dB s s s dB 0 0 -0.01 .583 80 - 4.6/Fs - .430 .499 0.01 ±0.03/Fs 0 Fs Fs dB Fs dB s s s 0 0 -0.01 .635 90 - 4.7/Fs .105 .490 0.01 - Fs Fs dB Fs dB s 9.00x10-5 9.74x10-6 - 5x104/Fs 0.01 1.34 - Fs Fs dB Deg s Double-Speed Mode - 96 kHz Passband (Note 11) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation (Note 12) Quad-Speed Mode - 192 kHz Passband (Note 11) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) (Note 12) High-Pass Filter Characteristics Passband (Note 11) to -0.05 dB corner to -3 dB corner Passband Ripple Phase Deviation @ 20 Hz Filter Settling Time (input signal goes to 95% of its final value) Notes: 11. Response is clock-dependent and will scale with Fs. 12. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 13. De-emphasis is available only in Single-Speed Mode. 14. Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 21. 8 DS803F3 CS4353 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters Symbol MCLK Frequency MCLK Duty Cycle Input Sample Rate (Auto selection) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs LRCK Duty Cycle Min Max Units 2.048 51.2 MHz 45 55 % 8 84 170 54 108 216 kHz kHz kHz 40 60 % SCLK Pulse Width Low tsclkl 20 - ns SCLK Pulse Width High tsclkh 20 - ns Single-Speed Mode 1 --------------------- 128 Fs - s Double-Speed Mode 1 ----------------- 64 Fs - s Quad-Speed Mode 1 ----------------- 64 Fs - s SCLK Period SCLK rising to LRCK edge delay tslrd 20 - ns SCLK rising to LRCK edge setup time tslrs 20 - ns SDIN valid to SCLK rising setup time tsdlrs 20 - ns SCLK rising to SDIN hold time tsdh 20 - ns LRCK t sclkh t slrs t slrd t sclkl SCLK t sdlrs t sdh SDATA Figure 1. Serial Input Timing DS803F3 9 CS4353 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Parameters 1.2 V <VL 3.3 V 0.9 V VL 1.2 V 1.2 V <VL 3.3 V 0.9 V VL 1.2 V High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Symbol Min Typ Max Units VIH VIH VIL VIL Iin 0.7xVL 0.9xVL - 8 0.3xVL 0.1xVL ±10 - V V V V A pF INTERNAL POWER-ON RESET THRESHOLD VOLTAGES Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Parameters Symbol Min Typ Max Units Internal Reset Asserted at Power-On Von1 - 1.00 - V Internal Reset Released at Power-On Von2 - 2.36 - V Internal Reset Asserted at Power-Off Voff - 2.22 - V VCP Voff Von2 Von1 DGND reset (internal) HI LO reset No Power undefined reset active DAC Ready reset active Figure 2. Power-on Reset Threshold Sequence 10 DS803F3 CS4353 DC ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; AGND = DGND = CPGND = 0 V; SDIN = 0; all voltages with respect to ground. Parameters Symbol Min Typ Max Units IVCP IVA IVL IPD - 36 2.4 0.1 65 127 1 60 60 43 3 0.2 152 - mA mA mA A mW mW dB dB - 3.3 6.6 6.6 6.6 2.1 - V V V V V Power Supplies Power Supply Current (Note 15) Normal Operation Power-Down, All Supplies (Note 16) Power Dissipation (All Supplies) Normal Operation, 1_2VRMS = 0 (Note 15) Power-Down (Note 16) Power Supply Rejection Ratio (Note 17) (1 kHz) (60 Hz) PSRR DC Output Voltages Pin Voltage FLYP+ to FLYPVFILT+ to GND (Note 18) FLYN+ to FLYNGND to VFILT- (Note 18) VA to VBIAS Notes: 15. Current consumption increases with increasing sample rate and increasing MCLK frequency. Typical values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Variance between speed modes is small. 16. Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputs have a weak pull-down (approximately 50 k) which is only present during reset. Opposing this pulldown will slightly increase the power-down current. 17. Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram in Section 3. 18. Typical voltage shown for “Initialization State”; see Section 4.8. Typical voltage may be up to 1.5 V lower during normal operation. 2.1 Digital I/O Pin Characteristics Input and output levels and associated power supply voltage are shown in Table 1. Logic levels should not exceed the corresponding power supply voltage. Pin Name RESET MCLK LRCK SCLK SDIN DEM I²S/LJ 1_2VRMS Power Supply VL I/O Input Input Input Input Input Input Input Input Driver - Receiver 0.9 V - 3.3 V, with Hysteresis 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V Table 1. Digital I/O Pin Characteristics DS803F3 11 CS4353 3. TYPICAL CONNECTION DIAGRAM +3.3 V 2.2 µF + 0.1 µF 0.1 µF + 2 1 Digital Audio Processor VA SCLK LRCK 24 SDIN 3 18 VFILT+ 8 0.1 µF FLYP+ + 7 FLYP- 5 AOUTA 15 AOUT_REF 14 VL Line Level Out Left & Right 562 2.2 nF 0.1 µF AOUTB 19 RESET 22 I²S/LJ Rext 13 562 FLYN+ 9 FLYN- 11 DEM VFILT- 12 10 4 + 22 µF AG N D G ND 0.1 µF D PG N D 1_2VRMS Note 1 Note 1: Values shown are for Fc = 130 kHz. Capacitors must be C0G or equivalent. 2.2 µF C 21 20 Note 2:Connect RESET to VL if internal power-on reset is used. Rext 2.2 nF Note 2 Hardware Control 2.2 µF 2.2 µF CS4353 +0.9 V to +3.3 V VBIAS MCLK 23 2.2 µF 17 VC P 6 16 Figure 3. Typical Connection Diagram 12 DS803F3 CS4353 4. APPLICATIONS 4.1 Line Outputs 4.1.1 Ground-centered Outputs An on-chip charge pump creates both positive and negative high-voltage supplies, which allows the fullscale output swing to be centered around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at lower supply voltages, and provides improved bandwidth frequency response. 4.1.2 Full-scale Output Amplitude Control The full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to VL, the full-scale output voltage at the AOUTx pins is approximately 2 VRMS. When the pin is connected to GND, the full-scale output voltage at the AOUTx pins is approximately 1 VRMS. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog Characteristics table for the complete specifications of the full-scale output voltage. 4.1.3 Pseudo-differential Outputs The CS4353 implements a pseudo-differential output stage. The AOUT_REF input is intended to be used as a pseudo-differential reference signal. This feature provides common mode noise rejection with singleended signals. Figure 4 shows a basic diagram outlining the internal implementation of the pseudo-differential output stage, including a recommended stereo pseudo-differential output topology. If pseudo-differential output functionality is not required, simply connect the AOUT_REF pin to ground next to the CS4353. If a split-ground design is used, the AOUT_REF pin should be connected to AGND. See the Absolute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. Internal Left DAC Signal AOUTA // Left Output (pseudo-differential traces) AOUT_REF // GND (pseudo-differential traces) AOUTB Internal Right DAC Signal // Right Output Psuedo-differential output improves common mode rejection, reducing external system noise Figure 4. Stereo Pseudo-differential Output DS803F3 13 CS4353 4.2 Sample Rate Range/Operational Mode Detect The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 2. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection; see Figure 9. Input Sample Rate (Fs) Mode 8 kHz - 54 kHz 84 kHz - 108 kHz 170 kHz - 216 kHz Single-Speed Mode Double-Speed Mode Quad-Speed Mode Table 2. CS4353 Operational Mode Auto-Detect 4.3 System Clocking The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5. Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and to “Switching Specifications - Serial Audio Interface” on page 9 for the maximum allowed clock frequencies. Sample Rate (kHz) 256x 384x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 MCLK (MHz) 512x 16.3840 22.5792 24.5760 768x 1024x 24.5760 33.8688 36.8640 32.7680 45.1584 49.1520 Table 3. Single-speed Mode Standard Frequencies Sample Rate (kHz) 128x 192x MCLK (MHz) 256x 384x 512x 88.2 96 11.2896 12.2880 16.9344 18.4320 22.5792 24.5760 33.8688 36.8640 45.1584 49.1520 Table 4. Double-speed Mode Standard Frequencies Sample Rate (kHz) 128x MCLK (MHz) 192x 256x 176.4 192 22.5792 24.5760 33.8688 36.8640 45.1584 49.1520 Table 5. Quad-speed Mode Standard Frequencies 14 DS803F3 CS4353 4.4 Digital Interface Format The device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in Table 6. The desired format is selected via the I²S/LJ pin. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in the Left-Justified format. For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com. Description I²S, up to 24-bit Data Left-Justified, up to 24-bit Data I²S/LJ 0 1 Figure 5 6 Table 6. Digital Interface Format Left C ha nnel LR C K Rig ht C ha nnel S C LK SDIN M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 5. I²S, up to 24-bit Data Left C ha nnel LR C K R ig ht C ha nnel S C LK SDIN MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 6. Left-justified up to 24-bit Data 4.5 Internal High-Pass Filter The device includes an internal digital high-pass filter. This filter prevents a constant digital offset from creating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see the Combined Interpolation & On-Chip Analog Filter Response table for filter specifications. DS803F3 15 CS4353 4.6 De-emphasis Control The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs. The de-emphasis error will increase for sample rates other than 44.1 kHz. When the DEM pin is connected to VL, the 44.1 kHz de-emphasis filter is activated. When the DEM pin is connected to GND, the de-emphasis filter is turned off. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 7. De-emphasis Curve, Fs = 44.1 kHz Note: 4.7 De-emphasis is only available in Single-Speed Mode. Internal Power-on Reset The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be connected to VL during power-up and power-down sequences if the external reset function is not needed. This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches defined thresholds (see “Internal Power-on Reset Threshold Voltages” on page 10). No external clocks are required for the POR circuit to function. VCP Power-On Reset Circuit DGND reset (internal) RESET (external) Figure 8. Internal Power-on Reset Circuit When power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Once the VCP supply reaches the secondary threshold, Von2, the POR circuit releases the internal reset. Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simultaneously with VCP. When power is removed and the VCP voltage reaches a defined threshold, Voff, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. 16 DS803F3 CS4353 4.8 Initialization When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA. The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alternatively, if no external reset control is required, the internal power-on reset can be used by tying the RESET pin to VL (see Section 4.7). Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charges the capacitors for both the positive and negative high-voltage supplies. Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to determine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference, VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. After this power-up state sequence is complete, normal operation begins and analog output is generated. If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RESET being set high to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device’s states and transition conditions. DS803F3 17 CS4353 USER: Apply Power Reset State Outputs Grounded USER: RESET Set Low or Remove MCLK USER: RESET Set High or RESET Tied High (if using POR) Power-Down State USER: Apply MCLK Initialization State USER: Apply LRCK and SCLK MCLK/LRCK Ratio Detection USER: Change MCLK/LRCK ratio Valid MCLK/LRCK Ratio Power-Up State Outputs Muted Normal Operation State Analog Output Generated Valid MCLK/LRCK Ratio USER: Change MCLK/LRCK ratio Mute State Figure 9. Initialization and Power-down Sequence Diagram 18 DS803F3 CS4353 4.9 Recommended Power-up and Power-down Sequences 4.9.1 Power-up Sequences 4.9.1.1 External RESET Power-up Sequence Follow the power-up sequence below if the external RESET pin is used: 1. Hold RESET low while the power supplies are turned on. The VA and VCP supplies should be applied prior to or simultaneously with the VL supply. If the VL supply is applied before the VA and VCP supplies, a DC offset will occur on the analog outputs. The offset level is bimodal: either approximately 0.7 V below the VL supply or approximately 50 mV. The first case can only occur if the VL supply is greater than approximately 1.2 V. Either offset level is removed when the VA and VCP supplies are applied. 2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as discussed in Section 4.3. 4. After the power supplies, configuration pins, and clock signals are stable, bring RESET high. The device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from AOUTx within 50 ms after RESET is set high. 4.9.1.2 Internal Power-on Reset Power-up Sequence Follow the power-up sequence below if the internal power-on reset is used: 1. Hold RESET high (connected to VL) while the power supplies are turned on. The VA and VCP supplies should be applied prior to or simultaneously with the VL supply. If the VL supply is applied before the VA and VCP supplies, a DC offset will occur on the analog outputs. The offset level is bimodal: either approximately 0.7 V below the VL supply or approximately 50 mV. The first case can only occur if the VL supply is greater than approximately 1.2 V. Either offset level is removed when the VA and VCP supplies are applied. The power-on reset circuitry will function as described in Section 4.7. 2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied. 4.9.2 Power-down Sequences 4.9.2.1 External RESET Power-down Sequence Follow the power-down sequence below if the external RESET pin is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. Bring RESET low. 3. Remove the power supply voltages. 4.9.2.2 Internal Power-on Reset Power-down Sequence Follow the power-down sequence below if the internal power-on reset is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. DS803F3 19 CS4353 2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin. 3. Remove the power supply voltages. Note: 4.10 A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 9. Grounding and Power Supply Arrangements As with any high-resolution converter, the CS4353 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 3 shows the recommended power arrangements, with VCP, VA, and VL connected to clean supplies. It is strongly recommended that a single ground plane be used, with the DGND, CPGND, and AGND pins all connected to this common plane. Should it be necessary to split the ground planes, the DGND and CPGND pins should be connected to the digital ground plane and the AGND pin should be connected to the analog ground plane. In this configuration, it is critical that the digital and analog ground planes be tied together with a low-impedance connection, ideally a strip of copper on the printed circuit board, at a single point near the CS4353. All signals, especially clocks, should be kept away from the VBIAS pin in order to avoid unwanted coupling into the DAC. 4.10.1 Capacitor Placement Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same PCB layer as the device. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. See DC Electrical Characteristics for the voltage present across pin pairs. This is useful for choosing appropriate capacitor voltage ratings and orientation if electrolytic capacitors are used. The CDB4353 evaluation board demonstrates the optimum layout and power supply arrangements. 20 DS803F3 CS4353 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 5. DIGITAL FILTER RESPONSE PLOTS −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 10. Single-speed Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 11. Single-speed Transition Band 0.02 0 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 0 Figure 12. Single-speed Transition Band (detail) 40 40 Amplitude (dB) Amplitude (dB) 20 60 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 60 80 80 100 100 120 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 Figure 14. Double-speed Stopband Rejection DS803F3 0.15 0 20 0.4 0.1 Figure 13. Single-speed Passband Ripple 0 120 0.05 1 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 15. Double-speed Transition Band 21 CS4353 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.02 0.55 0 Figure 16. Double-speed Transition Band (detail) 20 40 40 Amplitude (dB) Amplitude (dB) 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 60 60 80 80 100 100 120 0.2 0.1 Figure 17. Double-speed Passband Ripple 0 120 0.05 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.2 Figure 18. Quad-speed Stopband Rejection 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 19. Quad-speed Transition Band 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 Figure 20. Quad-speed Transition Band (detail) 22 0.55 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 21. Quad-speed Passband Ripple DS803F3 CS4353 6. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS803F3 23 CS4353 7. PACKAGE DIMENSIONS 24L QFN (4.00 mm BODY) PACKAGE DRAWING D e b PIN #1 CORNER 1.00 REF 1.00 REF PIN #1 IDENTIFIER LASER MARKING E E2 A1 A TOP VIEW DIM MIN A A1 b e D D2 E E2 L 0.00000 0.00787 0.01772 0.10433 0.10433 0.01181 D2 SIDE VIEW INCHES NOM MAX L BOTTOM VIEW MIN 0.03937 0.00197 0.00 0.00984 0.01181 0.20 0.01969 0.02165 0.45 0.15748 BSC 0.10630 0.10827 2.65 0.15748 BSC 0.10630 0.10827 2.65 0.01575 0.01969 0.30 Controlling Dimension is Millimeters MILLIMETERS NOM 0.25 0.50 4.00 BSC 2.70 4.00 BSC 2.70 0.40 NOTE MAX 1.00 0.05 0.30 0.55 2.75 2.75 0.50 1 1 1, 2 1 1 1 1 1 1 Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1994. 2. Dimensioning lead width applies to the metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. Parameter Junction to Ambient Thermal Impedance 24 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA JA - 68 28 - °C/Watt °C/Watt DS803F3 CS4353 8. ORDERING INFORMATION Product CS4353 Description Package Pb-Free 3.3 V Stereo Audio DAC 24-pin QFN YES with 2 VRMS Line Output CDB4353 CS4353 Evaluation Board - Grade Temp Range Commercial -40° to +85° C - - Container Rail Tape & Reel - Order # CS4353-CNZ CS4353-CNZR CDB4353 9. REVISION HISTORY Release PP1 PP2 F1 F2 F3 Changes – – – – – – – – – – – – – – – – – Updated interchannel isolation specification in the DAC Analog Characteristics specification table. Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface table. Updated power supply current and power dissipation specifications in the DC Electrical Characteristics table. Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table. Added “SDIN = 0” to the test conditions in the DC Electrical Characteristics table. Updated Section 4.9.1.1 on page 19. Updated output impedance specification in the DAC Analog Characteristics specification table. Removed Automotive Grade. Added Note 2 and reference to Note 4 in the Dynamic Performance section of the DAC Analog Characteristics table. Changed “additional” to “external” in Note 6 and 8 on page 7. Updated full scale output specification in the DAC Analog Characteristics table. Updated Von2 and Voff specifications in the Internal Power-on Reset Threshold Voltages table. Added HPF data to Combined Interpolation & On-Chip Analog Filter Response table. Added Section 4.5 Internal High-Pass Filter. FLYP and FLYN polarity indicators removed from Figure 3. Updated Note 3 to read “One LSB of triangular PDF dither is added to data.” Updated Step 1 in Section 4.9.1.1 and Section 4.9.1.2. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. 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