w WM8904-6201-CS36-M-REV1 Example Configurations DOC TYPE: EXAMPLE CONFIGURATIONS BOARD REFERENCE: WM8904-6201-CS36-M-REV1 BOARD TYPE: Customer Mini Board WOLFSON DEVICE(S): WM8904 DATE: August 2009 DOC REVISION: Rev 1.0 INTRODUCTION The WM8904-6201-CS36-M-REV1 Customer Mini Board is compatible with the 6201-EV1-REV2 customer evaluation board and together provide a complete hardware platform for evaluation of the WM8904. The WM8904 Customer Mini Board can also be used independently and connected directly to a processor board using flying field wires or appropriate headers. This document will cover both, but performance data will be based on the Wolfson system with 6201-EV1-REV2 mainboard. Configurations covered are listed below: • DAC to Headphone playback • IN1L/R to ADC Recording • IN1L+2L / IN1R+2R to ADC Recording (differential input) • IN3L/R to LINEOUTL/R (analogue bypass) • IN3L/R to LINEOUTL/R (digital loopback) This document should be used as a starting point for evaluation of WM8904 but it will not cover every possible configuration. Assumptions: 1. The user is familiar with the 6201-EV1-REV2 main board and that the board is correctly configured for the path of interest (see related documents below) 2. The user has control of the WM8904 register settings, for example by installing Wolfson WISCE software. Related documents: 1. WM8904 datasheet 2. WM8904-6201-CS36-M-REV1 Schematic and Layout.pdf 3. 6201-EV1-REV2 Schematic and Layout.pdf 4. WISCE Quick Start Guide.pdf WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews August 2009, Rev 1.0 Copyright ©2009 Wolfson Microelectronics plc WM8904-6201-CS36-M-REV1 Customer Information TABLE OF CONTENTS INTRODUCTION .............................................................................................................1 BOARD CONFIGURATION STAND-ALONE ..................................................................3 CONNECTION DIAGRAM ....................................................................................................... 3 I/O TABLE ............................................................................................................................... 4 SHORTING POINTS AND JUMPER LINKS TABLE ................................................................ 5 BOARD CONFIGURATION WITH 6201-EV1-REV2 MAIN BOARD ...............................6 DAC TO HEADPHONE PLAYBACK ........................................................................................ 6 IN1L/R TO ADC RECORDING ................................................................................................ 9 IN1L+2L / IN1R+2R TO ADC RECORDING (DIFFERENTIAL MIC INPUT)........................... 11 IN3L/R TO LINEOUTL/R (ANALOGUE BYPASS) ................................................................. 13 IN3L/R TO LINEOUTL/R (DIGITAL LOOPBACK) .................................................................. 16 APPLICATION SUPPORT ............................................................................................19 IMPORTANT NOTICE ...................................................................................................20 ADDRESS: ............................................................................................................................ 20 w Customer Information August 2009, Rev 1.0 2 WM8904-6201-CS36-M-REV1 Customer Information BOARD CONFIGURATION STAND-ALONE The WM8904 Customer Mini Board can be used a stand-alone module for direct connection to a processor board via flying leads or dedicated headers. This section will detail important considerations and provide all information required to do this without risking damage to the device. CONNECTION DIAGRAM Figure 1 below shows the connections required to power-up and control the WM8904 Customer Mini Board. Please refer to the Table 1 for further detail on external I/O connections. Figure 1 Stand-Alone Board Configuration w Customer Information August 2009, Rev 1.0 3 WM8904-6201-CS36-M-REV1 Customer Information I/O TABLE SIGNAL BOARD REFERENCE IMPORTANT NOTES Voltage Supplies AVDD = 1.71V to 2.0V AVDD H3: pin 8 CPVDD H1: pin 20 CPVDD = 1.71 to 2.0V DCVDD H4: pin 18 DCVDD = 0.95V to 1.98V DBVDD H4: pin 20 DBVDD = 1.42V to 3.6V MICVDD J5, TP10 MICVDD=1.71 to 3.6V , connected by default to AVDD, can also be supplied to pin 2 of J5 Ground DGND AGND CPGND Control Interface Common Ground Analogue and digital grounds must always be within 0.3V of each other H4: pin 12 H4: pin 14 Both control interface signals should swing between DGND and DBVDD H1: pin 4 Signal should swing between DGND and DBVDD SDA SCLK Master Clock MCLK Digital I/O and Audio Interface GPIO1/IRQ GPIO2 GPIO3 BCLK/GPIO4 DACDAT LRCLK ADCDAT Digital / Analogue Inputs IN3R IN2R IN1R/DMICDAT2 IN3L IN2L IN1L/DMICDAT1 MICBIAS H1: pin 10 H1: pin 6 H4: pin 16 H1: pin 12 H1: pin 14 H1: pin 16 H1: pin 18 Signals should swing between DGND and DBVDD H3: pin 20 H4: pin 2 H4: pin 4 H4: pin 6 H4: pin 8 H4: pin 10 H3: pin 18 Observe maximum input levels as per WM8904 datasheet Analogue microphone bias voltage output Analogue Outputs HPOUTR HPOUTL HPOUTFB H2: pin 12 H2: pin 16 H2: pin 14 Ground referenced headphone output LINOUTR LINOUTL LINOUTFB H2: pin 18 H3: pin 2 H2: pin 20 Ground referenced line output Charge Pump and VMID CPVOUTP CPVOUTN CPCA CPCB VMIDC J7: pin 2 J7: pin 1 J7: pin 4 J7: pin 3 TP6 HP reference pin, recommended to be connected to the common ground at headphone connector LINE reference pin, recommended to be connected to the common ground at line output connector. Charge Pump and VMIDC test points Table 1 I/O Configuration w Customer Information August 2009, Rev 1.0 4 WM8904-6201-CS36-M-REV1 Customer Information SHORTING POINTS AND JUMPER LINKS TABLE REFERENCE FUNCTION SP1 Short this pin to be able to use the onboard MIC connector. If shorted this links pin 1 of the MIC connector to LINPUT2 of the device J5 AVDD J6 DBVDD J7 CPVDD J8 DCVDD These jumpers link the relevant pins on the DUT to the different supply voltages. To supply different voltages disconnect the relevant jumper link and apply the chosen voltage directly to pin 2 of the relevant jumper. J9 HPOUTFB J10 LINEOUTFB These jumper links are set by default and connect the headphone and lineout reference to common ground. J2 MIC Supply Choose between MICBIAS and DBVDD for the MIC supply. Default is MICBIAS for analogue microphone. J3 MICVDD MICVDD by default is linked to AVDD (pin 1-2) alternatively it can be externally supplied to pin 2 (pin 3 is GND) Table 2 Shorting Points and Jumper Links Table w Customer Information August 2009, Rev 1.0 5 WM8904-6201-CS36-M-REV1 Customer Information BOARD CONFIGURATION WITH 6201-EV1-REV2 MAIN BOARD This section focuses on evaluation of the WM8904-6201-CS36-M-REV1 Customer Mini Board in combination with the 6201-EV1-REV2 main board. This system is the reference platform for measurement data contained in this document. Please note that only a limited number of usage modes will be covered. DAC TO HEADPHONE PLAYBACK The following section details the configuration for DAC to headphone playback through HPOUTL/R. For board configuration, please refer to Figure 3 BLOCK DIAGRAM DECIMATION FILTERS INTERPOLATION FILTERS DAC R DAC L BYPASS R BYPASS L CPVDD CPCB CPCA CPGND GPIO3 GPIO2 IRQ/GPIO1 MCLK DGND DBVDD DCVDD DACDAT LRCLK ADCDAT BCLK SDA SCLK AGND AVDD VMIDC Figure 2 Path Diagram DAC to HPOUTL/R w Customer Information August 2009, Rev 1.0 6 WM8904-6201-CS36-M-REV1 Customer Information BOARD CONFIGURATION Figure 3 Board Configuration DAC to HPOUTL/R REGISTER SETTINGS Register settings provided below are the typical sequence to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE 0x00 0x0000 0x6C 0x0100 WSEQ_ENA=1, WSEQ_WRITE_INDEX=0_0000 0x6F 0x0100 WSEQ_ABORT=0, WSEQ_START=1, WSEQ_START_INDEX=00_0000 0x14 0x845E TOCLK_RATE_DIV16=0, TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 (Required for MMCs: SGY, KRT see erratum CE000546) 0x39 0x0039 HPOUTL_MUTE=0, HPOUT_VU=0, HPOUTLZC=0, HPOUTL_VOL=11_1001 0x3A 0x00B9 HPOUTR_MUTE=0, HPOUT_VU=1, HPOUTRZC=0, HPOUTR_VOL=11_1001 0x21 0x0000 DAC_MONO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_UNMUTE_RAMP=0, DAC_OSR128=0, DAC_MUTE=0, DEEMPH=00 0x68 0x0005 CP_DYN_PWR=1 COMMENT SW Reset Table 3 Register Settings DAC to HPOUTL/R w Customer Information August 2009, Rev 1.0 7 WM8904-6201-CS36-M-REV1 Customer Information PERFORMANCE PLOT -30 -35 -40 -45 -50 -55 d B r -60 A -70 -65 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Red Blue Green Magenta Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left 22Hz-22kHz, A-Weighted, Left 22Hz-22kHz, A-Weighted, Right 22Hz-20kHz, AES17, Left 22Hz-20kHz, AES17, Right System AP2 Board: 6201-EV1-REV2 + WM8904-6201-CS36-M-REV1 Device Date Code: SGY Input Path: SPDIF_IN Input Signal: 997Hz; 0dBFS; 24-bit; 256fs (fs=48kHz) Output Path: HPOUT (32R load) Output Reference: 0dBrA = -0.497 dBV Supplies: AVDD=CPVDD=DCVDD=DBVDD=MICVDD=1.8V BW Filter: as stated Additional Filtering: as stated RMS or Averaging: Averaging Figure 4 Performance Plot DAC to HPOUTL/R w Customer Information August 2009, Rev 1.0 8 WM8904-6201-CS36-M-REV1 Customer Information IN1L/R TO ADC RECORDING The following section details the configuration for IN1L/R to ADC recording. For board configuration, please refer to Figure 6. BLOCK DIAGRAM DECIMATION FILTERS INTERPOLATION FILTERS DAC R DAC L BYPASS R BYPASS L CPVDD CPCB CPCA CPGND GPIO3 GPIO2 IRQ/GPIO1 MCLK DGND DBVDD DCVDD DACDAT LRCLK ADCDAT BCLK SDA SCLK AGND AVDD VMIDC Figure 5 Path Diagram IN1L/R to ADC BOARD CONFIGURATION Figure 6 Board Configuration IN1L/R to ADC w Customer Information August 2009, Rev 1.0 9 WM8904-6201-CS36-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE COMMENT 0x00 0x0000 SW Reset 0x04 0x0009 POBCTRL=0, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 0x05 0x0043 VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 0x14 0x845E TOCLK_RATE_DIV16=0, TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 (Required for MMCs: SGY, KRT see erratum CE000546) 0x0C 0x0003 INL_ENA=1, INR_ENA=1 0x12 0x0003 DACL_ENA=0, DACR_ENA=0, ADCL_ENA=1, ADCR_ENA=1 0x2C 0x0005 LINMUTE=0, LIN_VOL=0_0101 0x2D 0x0005 RINMUTE=0, RIN_VOL=0_0101 Table 4 Register Settings IN1L/R to ADC PERFROMANCE PLOT -76 -77 -78 -79 -80 -81 -82 d B F S -83 -84 -85 -86 -87 -88 -89 -90 -91 -92 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Red Blue Green Magenta Solid Solid Solid Solid 2 2 2 2 DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B Left Left Left Left 22Hz-20kHz, A-Weighted, Left 22Hz-20kHz, A-Weighted, Right 22Hz-22kHz, Left 22Hz-22kHz, Right Test System: AP2 Board: 6201-EV1-REV2 + WM8904-6201-CS36-REV1 Device Date Code: SGY Input Path: L/RINPUT1 Input Signal: 0.997kHz Output Path: S/PDIF_OUT Output Signal: 24 bit; 48kHz (256fs) Supplies: AVDD=CPVDD=DVCDD=DBVDD=MICVDD=1.8V BW Filtering: as stated Additional Filtering Type: as stated RMS or Averaging: RMS Figure 7 Performance Plot IN1L/R to ADC w Customer Information August 2009, Rev 1.0 10 WM8904-6201-CS36-M-REV1 Customer Information IN1L+2L / IN1R+2R TO ADC RECORDING (DIFFERENTIAL MIC INPUT) The following section details the configuration for recording from a differential microphone input (IN1L+R / IN1R+2R to ADC). For board configuration, please refer to Figure 6. BLOCK DIAGRAM DECIMATION FILTERS INTERPOLATION FILTERS DAC R DAC L BYPASS R BYPASS L CPVDD CPCB CPCA CPGND GPIO3 GPIO2 IRQ/GPIO1 MCLK DGND DBVDD DCVDD DACDAT LRCLK ADCDAT BCLK SDA SCLK AGND AVDD VMIDC Figure 8 Path Path Diagram IN1L+2L / IN1R+2R to ADC BOARD CONFIGURATION Figure 9 Board Configuration IN1L+2L / IN1R+2R to ADC w Customer Information August 2009, Rev 1.0 11 WM8904-6201-CS36-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are the typical sequence to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x04 0x0019 POBCTRL=1, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 0x05 0x0043 VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 0x14 0x845E TOCLK_RATE_DIV16=0, TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 (Required for MMCs: SGY, KRT see erratum CE000546) 0x0C 0x0003 INL_ENA=1, INR_ENA=1 0x12 0x0003 DACL_ENA=0, DACR_ENA=0, ADCL_ENA=1, ADCR_ENA=1 0x2C 0x001F LINMUTE=0, LIN_VOL=1_1111 0x2D 0x001F RINMUTE=0, RIN_VOL=1_1111 0x2E 0x0046 INL_CM_ENA=1, L_IP_SEL_N=00, L_IP_SEL_P=01, L_MODE=10 0x2F 0x0046 INR_CM_ENA=1, R_IP_SEL_N=00, R_IP_SEL_P=01, R_MODE=10 COMMENT Table 5 IN1L+2L / IN1R+2R to ADC (differential MIC input) PERFORMANCE PLOT -25 -30 -35 -40 -45 d B F S -50 -55 -60 -65 -70 -75 -80 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 3 1 3 Red Blue Green Magenta Solid Solid Solid Solid 2 2 2 2 DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B Left Left Left Left A-Weighted, Left A-Weighted, Right Left Right System AP2 Board: 6201-EV1-REV2 + WM8904-6201-CS36-M-REV1 Device Date Code: SGY Input Path: INPUT1-2 L/R Differential Input Input Signal: 997Hz Output Path: SPDIF_OUT Output Signal:24bit, 48kHz (256fs) Supplies: AVDD=CPVDD=DCVDD=DBVDD=MICVDD=1.8V BW Filter: 22Hz - 20kHz Additional Filtering: as stated RMS or Averagin: RMS Figure 10 Performance Plot IN1L+2L / IN1R+2R to ADC (differential MIC) w Customer Information August 2009, Rev 1.0 12 WM8904-6201-CS36-M-REV1 Customer Information IN3L/R TO LINEOUTL/R (ANALOGUE BYPASS) The following section details the configuration of an analogue bypass from IN3L/R to LINEOUTL/R. For board configuration, please refer to Figure 12. BLOCK DIAGRAM DECIMATION FILTERS INTERPOLATION FILTERS DAC R DAC L BYPASS R BYPASS L CPVDD CPCB CPCA CPGND GPIO3 GPIO2 IRQ/GPIO1 MCLK DGND DBVDD DCVDD DACDAT LRCLK ADCDAT BCLK SDA SCLK AGND AVDD VMIDC Figure 11 Path Diagram IN3L/R to LINEOUTL/R w Customer Information August 2009, Rev 1.0 13 WM8904-6201-CS36-M-REV1 Customer Information BOARD CONFIGURATION Left Audio Input USB Right Audio Input Audio (L/R) Line Output Figure 12 Board Configuration IN3L/R to LINEOUTL/R REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x04 0x0009 POBCTRL=0, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 0x05 0x0043 VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 0x0C 0x0003 INL_ENA=1, INR_ENA=1 0x0F 0x0003 LINEOUTL_PGA_ENA=1, LINEOUTR_PGA_ENA=1 0x2E 0x0024 INL_CM_ENA=0, L_IP_SEL_N=10, L_IP_SEL_P=01, L_MODE=00 0x2F 0x0024 INR_CM_ENA=0, R_IP_SEL_N=10, R_IP_SEL_P=01, R_MODE=00 0x2C 0x0005 LINMUTE=0, LIN_VOL=0_0101 0x2D 0x0005 RINMUTE=0, RIN_VOL=0_0101 0x3D 0x0003 HPL_BYP_ENA=0, HPR_BYP_ENA=0, LINEOUTL_BYP_ENA=1, LINEOUTR_BYP_ENA=1 0x5E 0x00FF LINEOUTL_RMV_SHORT=1, LINEOUTL_ENA_OUTP=1, LINEOUTL_ENA_DLY=1, LINEOUTL_ENA=1, LINEOUTR_RMV_SHORT=1, LINEOUTR_ENA_OUTP=1, LINEOUTR_ENA_DLY=1, LINEOUTR_ENA=1 0x62 0x0001 CP_ENA=1 COMMENT Table 6 Register Settings IN3L/R to LINEOUTL/R w Customer Information August 2009, Rev 1.0 14 WM8904-6201-CS36-M-REV1 Customer Information PERFROMANCE PLOT -10 -20 -30 -40 d B r A -50 -60 -70 -80 -90 -100 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Red Blue Green Magenta Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left 22Hz - 22kHz, A-Weighting, Left 22Hz - 22kHz, A-Weighting, Right 22Hz - 20kHz AES17, Left 22Hz - 20kHz AES17, Right System = AP2 Board: 6201-EV1-REV2 + WM8904-6201-CS36-REV1 Device Datecode: SGY Input Signal: 1kHz Reference Levels: 0dBrA = --0.860 dBV Supplies: AVDD=CPVDD=DCVDD=DBVDD=MICVDD=1.8V Input Signal Path: L/RINPUT3 Output Signal Path: L/ROUT (Lineout) BW Filtering: as stated Additional Filtering Type: as stated RMS or Averaging = Average Figure 13 Performance Plot (IN3L/R to LINEOUTL/R) w Customer Information August 2009, Rev 1.0 15 WM8904-6201-CS36-M-REV1 Customer Information IN3L/R TO LINEOUTL/R (DIGITAL LOOPBACK) The following section details the configuration for the digital loopback path. BLOCK DIAGRAM DECIMATION FILTERS INTERPOLATION FILTERS DAC R DAC L BYPASS R BYPASS L CPVDD CPCB CPCA CPGND GPIO3 GPIO2 IRQ/GPIO1 MCLK DGND DBVDD DCVDD DACDAT LRCLK ADCDAT BCLK SDA SCLK AGND AVDD VMIDC Figure 14 Path Diagram IN3L/R to LINEOUTL/R (digital loopback) BOARD CONFIGURATION The board configuration for this path is equivalent to the one used for the analogue bypass. See Figure 12 for reference. w Customer Information August 2009, Rev 1.0 16 WM8904-6201-CS36-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x04 0x0019 POBCTRL=1, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 0x05 0x0043 VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 0x14 0x845E TOCLK_RATE_DIV16=0, TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 (Required for MMCs: SGY, KRT see erratum CE000546) 0x0C 0x0003 INL_ENA=1, INR_ENA=1 0x0F 0x0003 LINEOUTL_PGA_ENA=1, LINEOUTR_PGA_ENA=1 0x12 0x000F DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 0x0150 DACL_DATINV=0, DACR_DATINV=0, DAC_BOOST=00, LOOPBACK=1, AIFADCL_SRC=0, AIFADCR_SRC=1, AIFDACL_SRC=0, AIFDACR_SRC=1, ADC_COMP=0, ADC_COMPMODE=0, DAC_COMP=0, DAC_COMPMODE=0 0x18 COMMENT 0x21 0x0000 DAC_MONO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_UNMUTE_RAMP=0, DAC_OSR128=0, DAC_MUTE=0, DEEMPH=00 0x2E 0x0024 INL_CM_ENA=0, L_IP_SEL_N=10, L_IP_SEL_P=01, L_MODE=00 0x2F 0x0024 INR_CM_ENA=0, R_IP_SEL_N=10, R_IP_SEL_P=01, R_MODE=00 0x2C 0x0005 LINMUTE=0, LIN_VOL=0_0101 0x2D 0x0005 RINMUTE=0, RIN_VOL=0_0101 0x5E 0x00FF LINEOUTL_RMV_SHORT=1, LINEOUTL_ENA_OUTP=1, LINEOUTL_ENA_DLY=1, LINEOUTL_ENA=1, LINEOUTR_RMV_SHORT=1, LINEOUTR_ENA_OUTP=1, LINEOUTR_ENA_DLY=1, LINEOUTR_ENA=1 0x68 0x0005 CP_DYN_PWR=1 0x62 0x0001 CP_ENA=1 Table 7 Register Settings IN3L/R to LINEOUTL/R (digital loopback) w Customer Information August 2009, Rev 1.0 17 WM8904-6201-CS36-M-REV1 Customer Information PERFORMANCE PLOT -20 -25 -30 -35 -40 -45 d B r A -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Red Blue Green Magenta Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left 22Hz - 22kHz, A-Weighting, Left 22Hz - 22kHz, A-Weighting, Right 22Hz-20kHz AES17, Left 22Hz-20kHz AES17, Right System = AP2 Board: 6201-EV1-REV2 + WM8904-6201-CS36-M-REV1 Device Datecode: SGY Input Signal: 1kHz Reference Levels: 0dBrA = -0.940 dBV Supplies: AVDD=CPVDD=DCVDD=DBVDD=MICVDD=1.8V Input Signal Path: L/RINPUT3 Output Signal Path: LINEOUTL/R BW Filtering: as stated Additional Filtering Type: as stated RMS or Averaging = Average Figure 15 Performance Plot IN3L/R to LINEOUTL/R (digital loopback) w Customer Information August 2009, Rev 1.0 18 WM8904-6201-CS36-M-REV1 Customer Information APPLICATION SUPPORT If you require more information or require technical support, please contact the Wolfson Microelectronics Applications group through the following channels: Email: Telephone Apps: Fax: Mail: [email protected] +44 (0) 131 272 7070 +44 (0) 131 272 7001 Applications Engineering at the address on the last page or contact your local Wolfson representative. Additional information may be made available on our web site at: http://www.wolfsonmicro.com w Customer Information August 2009, Rev 1.0 19 WM8904-6201-CS36-M-REV1 Customer Information IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 E-mail :: [email protected] w Customer Information August 2009, Rev 1.0 20