WOLFSON WM8912GEFL/V

WM8912
w
Ultra Low Power DAC with Headphone Driver
for Portable Audio Applications
DESCRIPTION
FEATURES
The WM8912 is a high performance ultra-low power stereo
DAC optimised for portable audio applications.
•
The device features stereo ground-referenced headphone
amplifiers using the Wolfson ‘Class-W’ amplifier techniques
- incorporating an innovative dual-mode charge pump
architecture - to optimise efficiency and power consumption
during playback. The ground-referenced outputs eliminate
headphone coupling capacitors. The outputs include
common mode feedback paths to reject ground noise.
Control sequences for audio path setup can be pre-loaded
and executed by an integrated control write sequencer to
reduce software driver development and minimise pops and
clicks via Wolfson’s SilentSwitch™ technology.
A dynamic range controller provides compression and level
control to support a wide range of portable recording
applications. Anti-clip and quick release features offer good
performance in the presence of loud impulsive noises.
ReTuneTM Mobile 5-band parametric equaliser with fully
programmable coefficients is integrated for optimization of
speaker characteristics.
Common audio sampling frequencies are supported from a
wide range of external clocks, either directly or generated
using the integrated FLL.
The WM8912 can operate directly from a single 1.8V
switched supply. For optimal power consumption, the digital
core can be operated from a 1.0V supply.
•
3.8mW quiescent power consumption for DAC to
headphone playback
DAC SNR 96dB typical, THD -86dB typical
•
Class W ground-referenced headphone driver
28mW per channel into 30Ω at <1% THD
32mW per channel into 15Ω at <1% THD
•
•
Dynamic range controller
ReTune™ Mobile parametric equalizer
•
Integrated control write sequencer for pop minimised startup and shutdown
Single register write for default start-up and shutdown
sequences
•
•
On-chip FLL provides all necessary clocks
•
DAC supports standard sample rates from 8kHz to 96kHz
•
32-pin QFN package (4x4mm, 0.4mm pitch)
APPLICATIONS
•
•
Portable multimedia players
Multimedia handsets
•
Handheld gaming
WOLFSON MICROELECTRONICS plc
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Production Data, September 2010, Rev 4.0
Copyright ©2010 Wolfson Microelectronics plc
WM8912
Production Data
BLOCK DIAGRAM
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TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1
FEATURES............................................................................................................. 1
APPLICATIONS ..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................. 2
TABLE OF CONTENTS ......................................................................................... 3
PIN CONFIGURATION ........................................................................................... 6
ORDERING INFORMATION .................................................................................. 6
PIN DESCRIPTION ................................................................................................ 7
ABSOLUTE MAXIMUM RATINGS ......................................................................... 8
RECOMMENDED OPERATING CONDITIONS ..................................................... 8
ELECTRICAL CHARACTERISTICS ...................................................................... 9
TERMINOLOGY ............................................................................................................ 9
COMMON TEST CONDITIONS .................................................................................... 9
OUTPUT SIGNAL PATH ............................................................................................. 10
CHARGE PUMP .......................................................................................................... 11
FLL .............................................................................................................................. 11
OTHER PARAMETERS .............................................................................................. 11
POWER CONSUMPTION .................................................................................... 12
COMMON TEST CONDITIONS .................................................................................. 12
POWER CONSUMPTION MEASUREMENTS ............................................................ 13
SIGNAL TIMING REQUIREMENTS ..................................................................... 14
COMMON TEST CONDITIONS .................................................................................. 14
MASTER CLOCK ........................................................................................................ 14
AUDIO INTERFACE TIMING ...................................................................................... 15
MASTER MODE ........................................................................................................................................................ 15
SLAVE MODE ........................................................................................................................................................... 16
CONTROL INTERFACE TIMING ................................................................................ 17
DIGITAL FILTER CHARACTERISTICS ............................................................... 18
DAC FILTER RESPONSES......................................................................................... 19
DE-EMPHASIS FILTER RESPONSES ........................................................................ 20
DEVICE DESCRIPTION ....................................................................................... 21
INTRODUCTION ......................................................................................................... 21
DYNAMIC RANGE CONTROL (DRC) ......................................................................... 22
COMPRESSION/LIMITING CAPABILITIES ............................................................................................................... 22
GAIN LIMITS ............................................................................................................................................................. 24
DYNAMIC CHARACTERISTICS ................................................................................................................................ 24
ANTI-CLIP CONTROL ............................................................................................................................................... 25
QUICK RELEASE CONTROL .................................................................................................................................... 26
GAIN SMOOTHING ................................................................................................................................................... 26
INITIALISATION ........................................................................................................................................................ 27
TM
RETUNE
MOBILE PARAMETRIC EQUALIZER (EQ) .............................................. 28
DEFAULT MODE (5-BAND PARAMETRIC EQ) ........................................................................................................ 28
TM
RETUNE MOBILE MODE ....................................................................................................................................... 29
EQ FILTER CHARACTERISTICS .............................................................................................................................. 29
DIGITAL MIXING ......................................................................................................... 31
DAC INTERFACE ROUTING AND CONTROL .......................................................................................................... 31
DAC INTERFACE VOLUME BOOST ......................................................................................................................... 31
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DIGITAL-TO-ANALOGUE CONVERTER (DAC) ......................................................... 32
DAC DIGITAL VOLUME CONTROL .......................................................................................................................... 32
DAC SOFT MUTE AND SOFT UN-MUTE.................................................................................................................. 34
DAC MONO MIX ........................................................................................................................................................ 35
DAC DE-EMPHASIS .................................................................................................................................................. 35
DAC SLOPING STOPBAND FILTER ......................................................................................................................... 36
DAC OVERSAMPLING RATIO (OSR) ....................................................................................................................... 36
OUTPUT SIGNAL PATH ............................................................................................. 37
OUTPUT SIGNAL PATHS ENABLE .......................................................................................................................... 38
HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE ........................................................................................ 38
OUTPUT VOLUME CONTROL .................................................................................................................................. 41
ANALOGUE OUTPUTS............................................................................................... 44
HEADPHONE OUTPUTS – HPOUTL AND HPOUTR ................................................................................................ 44
LINE OUTPUTS – LINEOUTL AND LINEOUTR ........................................................................................................ 44
EXTERNAL COMPONENTS FOR GROUND REFERENCED OUTPUTS.................................................................. 45
REFERENCE VOLTAGES AND MASTER BIAS ......................................................... 46
CHARGE PUMP .......................................................................................................... 46
DC SERVO .................................................................................................................. 48
DC SERVO ENABLE AND START-UP ...................................................................................................................... 48
DC SERVO ACTIVE MODES .................................................................................................................................... 51
DC SERVO READBACK............................................................................................................................................ 53
DIGITAL AUDIO INTERFACE ..................................................................................... 53
MASTER AND SLAVE MODE OPERATION.............................................................................................................. 53
OPERATION WITH TDM ........................................................................................................................................... 54
BCLK FREQUENCY .................................................................................................................................................. 55
AUDIO DATA FORMATS (NORMAL MODE) ............................................................................................................. 55
AUDIO DATA FORMATS (TDM MODE) .................................................................................................................... 57
DIGITAL AUDIO INTERFACE CONTROL ................................................................... 59
AUDIO INTERFACE OUTPUT TRI-STATE ............................................................................................................... 59
BCLK AND LRCLK CONTROL .................................................................................................................................. 60
COMPANDING .......................................................................................................................................................... 61
DIGITAL PULL-UP AND PULL-DOWN ...................................................................................................................... 63
CLOCKING AND SAMPLE RATES ............................................................................. 64
SYSCLK CONTROL .................................................................................................................................................. 65
CONTROL INTERFACE CLOCKING ......................................................................................................................... 66
CLOCKING CONFIGURATION ................................................................................................................................. 66
DAC CLOCK CONTROL ............................................................................................................................................ 67
OPCLK CONTROL .................................................................................................................................................... 67
TOCLK CONTROL .................................................................................................................................................... 68
DAC OPERATION AT 88.2K / 96K ............................................................................................................................ 69
FREQUENCY LOCKED LOOP (FLL) .......................................................................... 70
FREE-RUNNING FLL CLOCK ................................................................................................................................... 73
EXAMPLE FLL CALCULATION ................................................................................................................................. 74
GPIO OUTPUTS FROM FLL ..................................................................................................................................... 75
EXAMPLE FLL SETTINGS ........................................................................................................................................ 75
GENERAL PURPOSE INPUT/OUTPUT (GPIO).......................................................... 76
IRQ/GPIO1 ................................................................................................................................................................ 76
BCLK/GPIO4 ............................................................................................................................................................. 77
INTERRUPTS ............................................................................................................. 78
CONTROL INTERFACE .............................................................................................. 80
CONTROL WRITE SEQUENCER ............................................................................... 83
INITIATING A SEQUENCE ........................................................................................................................................ 83
PROGRAMMING A SEQUENCE ............................................................................................................................... 84
DEFAULT SEQUENCES ........................................................................................................................................... 86
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WM8912
START-UP SEQUENCE ............................................................................................................................................ 87
SHUTDOWN SEQUENCE ......................................................................................................................................... 88
POWER-ON RESET ................................................................................................... 90
QUICK START-UP AND SHUTDOWN ........................................................................ 91
QUICK START-UP (DEFAULT SEQUENCE) ............................................................................................................ 91
FAST START-UP FROM STANDBY .......................................................................................................................... 92
QUICK SHUTDOWN (DEFAULT SEQUENCE) ......................................................................................................... 93
SOFTWARE RESET AND CHIP ID ............................................................................. 93
REGISTER MAP................................................................................................... 94
REGISTER BITS BY ADDRESS ................................................................................. 97
APPLICATIONS INFORMATION ....................................................................... 126
RECOMMENDED EXTERNAL COMPONENTS ........................................................ 126
PACKAGE DIMENSIONS .................................................................................. 127
IMPORTANT NOTICE ........................................................................................ 128
ADDRESS .......................................................................................................... 128
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PIN CONFIGURATION
The WM8912 is supplied in a 32-pin QFN package.
ORDERING INFORMATION
DEVICE
WM8912GEFL/V
TEMPERATURE
RANGE
-40°C to +85°C
PACKAGE
MOISTURE
SENSITIVITY
LEVEL
PEAK
SOLDERING
TEMPERATURE
32-lead QFN
MSL3
260°C
MSL3
260°C
(4x4x0.4mm, lead-free)
WM8912GEFL/RV
-40°C to +85°C
32-lead QFN
(4x4x0.4mm, lead-free, tape and reel)
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
NAME
QFN-32
TYPE
DESCRIPTION
IRQ/GPIO1
1
Digital Input / Output
GPIO1 / Interrupt
SCLK
2
Digital Input
Control interface clock input
SDA
3
Digital Input / Output
Control interface data input / output
DBVDD
4
Supply
Digital buffer supply (powers audio interface and control
interface)
DGND
5
Supply
Digital ground (return path for DCVDD and DBVDD)
DCVDD
6
Supply
Digital core supply
CPVDD
7
Supply
Charge pump power supply
CPCA
8
Analogue Input
Charge pump flyback capacitor pin
CPGND
9
Supply
Charge pump ground
CPCB
10
Analogue Input
Charge pump flyback capacitor pin
CPVOUTP
11
Analogue Output
Charge pump positive supply decoupling (powers
HPOUTL/R, LINEOUTL/R)
CPVOUTN
12
Analogue Output
Charge pump negative supply decoupling (powers
HPOUTL/R, LINEOUTL/R)
HPOUTL
13
Analogue Output
Left headphone output (line or headphone output)
HPOUTFB
14
Analogue Output
Headphone output ground loop noise rejection feedback
HPOUTR
15
Analogue Output
Right headphone output (line or headphone output)
LINEOUTL
16
Analogue Output
Left line output 1 (line output)
LINEOUTFB
17
Analogue Output
Line output ground loop noise rejection feedback
LINEOUTR
18
Analogue Output
Right line output 1 (line output)
DNC
19
n/a
Do Not Connect
DNC
20
n/a
Do Not Connect
VMIDC
21
Analogue Output
Midrail voltage decoupling capacitor
AGND
22
Supply
Analogue power return
AVDD
23
Supply
Analogue power supply
DNC
24
n/a
Do Not Connect
DNC
25
n/a
Do Not Connect
DNC
26
n/a
Do Not Connect
27
n/a
Do Not Connect
Master clock for DAC
DNC
MCLK
28
Digital Input
BCLK/GPIO4
29
Digital Input / Output
Audio interface bit clock / GPIO4
LRCLK
30
Digital Input / Output
Audio interface left / right clock
DNC
31
n/a
Do Not Connect
DACDAT
32
Digital Input
DAC digital audio data
GND_PADDLE
33
Die Paddle
Note:
It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
MIN
MAX
AVDD, DCVDD
CONDITION
-0.3V
+2.5V
DBVDD,
-0.3V
+4.5V
CPVDD
-0.3V
+2.2V
(CPVDD + 0.3V) * -1
CPVDD + 0.3V
Voltage range digital inputs
DGND -0.3V
DBVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
HPOUTL, HPOUTR, LINEOUTL, LINEOUTR
Temperature range, TA
-40°C
+85°C
Storage temperature after soldering
-65°C
+150°C
Notes:
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
All digital and analogue supplies are completely independent from each other; there is no restriction on power supply
sequencing.
3.
HPOUTL, HPOUTR, LINEOUTL, LINEOUTR are outputs, and should not normally become connected to DC levels.
However, if the limits above are exceeded, then damage to the WM8912 may occur.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Digital supply range (Core)
DCVDD
0.95
1.0
1.98
V
Digital supply range (Buffer)
DBVDD
1.42
1.8
3.6
V
AVDD
1.71
1.8
2.0
V
CPVDD
1.71
1.8
2.0
V
-40
+25
+85
°C
Analogue supplies range
Charge pump supply range
Ground
Operating Temperature (ambient)
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DGND, AGND, CPGND
TA
0
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ELECTRICAL CHARACTERISTICS
TERMINOLOGY
1.
Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output
noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ratio is also called idle channel
noise. (No Auto-zero or Automute function is employed).
2.
Total Harmonic Distortion (dB) – THD is the difference in level between a 1kHz full scale sinewave output signal and
the first seven harmonics of the output signal. The amplitude of the fundamental frequency of the output signal is
compared to the RMS value of the next seven harmonics and expressed as a ratio.
3.
Total Harmonic Distortion + Noise (dB) – THD+N is the difference in level between a 1kHz full scale sine wave output
signal and all noise and distortion products in the audio band. The amplitude of the fundamental reference frequency
of the output signal is compared to the RMS value of all other noise and distortion products and expressed as a ratio.
4.
Channel Separation (dB) – is a measure of the coupling between left and right channels. A full scale signal is applied
to the left channel only, the right channel amplitude is measured. Then a full scale signal is applied to the right
channel only and the left channel amplitude is measured. The worst case channel separation is quoted as a ratio.
5.
Channel Level Matching (dB) – measures the difference in gain between the left and the right channels.
6.
Power Supply Rejection Ratio (dB) – PSRR is a measure of ripple attenuation between the power supply pin and an
output path. With the signal path idle, a small signal sine wave is summed onto the power supply rail, The amplitude
of the sine wave is measured at the output port and expressed as a ratio.
7.
All performance measurements carried out with 20kHz AES17 low pass filter for distortion measurements, and an
A-weighted filter for noise measurement. Failure to use such a filter will result in higher THD and lower SNR and
Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band
noise; although it is not audible it may affect dynamic specification values.
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
•
DCVDD = 1.0V
•
DBVDD = 1.8V
•
AVDD = CPVDD =1.8V
•
Ambient temperature = +25°C
•
Audio signal: 1kHz sine wave, sampled at 48kHz with 24-bit data resolution
•
SYSCLK_SRC = 0 (system clock comes direct from MCLK, not from FLL).
Additional, specific test conditions are given within the relevant sections below.
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OUTPUT SIGNAL PATH
Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 15Ω load
Test conditions: HPOUTL_VOL = HPOUTR_VOL = 111001b (0dB)
PARAMETER
Output Power (per Channel)
SYMBOL
TEST CONDITIONS
Po
1% THD
RLoad= 30Ω
28
0.92
-0.76
mW
Vrms
dBV
1% THD
RLoad= 15Ω
32
0.69
-3.19
mW
Vrms
dBV
DC Offset
Signal to Noise Ratio
Total Harmonic Distortion + Noise
DC servo enabled,
calibration complete.
-1.5
SNR
A-weighted
90
THD+N
RL=30Ω; Po=2mW
Channel Separation
Channel Level Matching
Power Supply Rejection Ratio
MIN
PSRR
TYP
MAX
+1.5
96
UNIT
mV
dB
-91
RL=30Ω; Po=20mW
-84
RL=15Ω; Po=2mW
-87
RL=15Ω; Po=20mW
-85
1kHz signal, 0dBFS
100
10kHz signal, 0dBFS
90
1kHz signal, 0dBFS
+/-1
217Hz, 100mVpk-pk
75
1kHz, 100mV pk-pk
70
-80
dB
dB
dB
dB
Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR pins with 10kΩ / 50pF load
Test conditions: LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Full Scale Output Signal Level
DAC 0dBFS output at
0dB volume
DC offset
DC servo enabled.
Calibration complete.
-1.5
SNR
A-weighted
90
THD+N
10kΩ load
-85
1kHz signal, 0dBFS
100
10kHz signal, 0dBFS
90
Signal to Noise Ratio
Total Harmonic Distortion + Noise
Channel Separation
Channel Level Matching
Power Supply Rejection Ratio
PSRR
MAX
1.0
0
2.83
+1.5
96
1kHz signal, 0dBFS
+/-1
217Hz, 100mVpk-pk
62
1kHz, 100mV pk-pk
62
UNIT
Vrms
dBV
Vpk-pk
mV
dB
-70
dB
dB
dB
dB
Output PGAs (HP, LINE)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum PGA gain setting
-57
dB
Maximum PGA gain setting
6
dB
PGA Gain Step Size
1
PGA gain accuracy
+6dB to -40dB
-1.5
PGA gain accuracy
-40dB to -57dB
-1
Mute attenuation
w
dB
+1.5
dB
+1
dB
HPOUTL/R
85
dB
LINEOUTL/R
85
dB
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CHARGE PUMP
PARAMETER
TEST CONDITIONS
MIN
TYP
Start-up Time
MAX
UNIT
μs
260
CPCA
Normal mode
CPVDD
V
Low power mode
CPVDD/2
V
CPCB
Normal mode
-CPVDD
V
Low power mode
-CPVDD/2
V
External component requirements
To achieve specified headphone output power and performance
Flyback Capacitor
(between CPCA and CPCB)
at 2V
1
2.2
μF
CPVOUTN Capacitor
at 2V
2
2.2
μF
CPVOUTP Capacitor
at 2V
2
2.2
μF
FLL
PARAMETER
Input Frequency
SYMBOL
TEST CONDITIONS
MIN
FREF
FLL_CLK_REF_DIV = 00
0.032
13.5
MHz
FLL_CLK_REF_DIV = 01
0.064
27
MHz
Lock time
TYP
MAX
UNIT
2
ms
VMID enabled
100
μs
Reference supplied
initially
+/-10
%
No reference provided
+/-30
%
Free-running mode start-up time
Free-running mode frequency accuracy
OTHER PARAMETERS
VMID Reference
PARAMETER
TEST CONDITIONS
Midrail Reference Voltage (VMID pin)
Charge up time (from fully discharged
to +5% or -10% of VMID)
MIN
TYP
MAX
-3%
AVDD/2
+3%
External capacitor
4.7μF
UNIT
V
μs
890
Digital Inputs / Outputs
PARAMETER
SYMBOL
TEST CONDITIONS
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOH = +1mA
Output LOW Level
VOL
IOL = -1mA
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MIN
TYP
MAX
UNIT
0.3×DBVDD
V
0.1×DBVDD
V
0.7×DBVDD
V
0.9×DBVDD
V
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POWER CONSUMPTION
The WM8912 power consumption is dependent on many parameters. Most significantly, it depends
on supply voltages, sample rates, mode of operation, and output loading.
The power consumption on each supply rail varies approximately with the square of the voltage.
Power consumption is greater at fast sample rates than at slower ones. When the digital audio
interface is operating in Master mode, the DBVDD current is significantly greater than in Slave mode.
(Note also that power savings can be made by using MCLK as the BCLK source in Slave mode.) The
output load conditions (impedance, capacitance and inductance) can also impact significantly on the
device power consumption.
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
•
•
•
•
•
Ambient temperature = +25°C
Audio signal = quiescent (zero amplitude)
Sample rate = 48kHz
MCLK = 12.288MHz
Audio interface mode = Slave (LRCLK_DIR=0, BCLK_DIR=0)
•
SYSCLK_SRC = 0 (system clock comes direct from MCLK, not from FLL)
Additional, variant test conditions are quoted within the relevant sections below. Where applicable,
power dissipated in the headphone or line loads is included.
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POWER CONSUMPTION MEASUREMENTS
Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 30Ω load.
Test conditions:
VMID_RES = 01 (for normal operation)
CP_DYN_PWR = 1 (Class-W, Charge pump controlled by real-time audio level)
Variant test conditions
AVDD
DCVDD
DBVDD
CPVDD
TOTAL
V
mA
V
mA
V
mA
V
mA
mW
48kHz sample rate
1.80
1.69
1.00
0.76
1.80
0.00
1.80
0.31
4.38
8kHz sample rate
1.80
1.69
1.00
0.18
1.80
0.00
1.80
0.31
3.80
48kHz, Po = 0.1mW/channel
1kHz sine wave 0dBFS
HPOUT_VOL= -25dB
DAC_VOL= 0dB
1.80
1.71
1.00
0.77
1.80
0.00
1.80
1.99
7.45
48kHz, Po = 1mW/channel
1kHz sine wave 0dBFS
HPOUT_VOL= -15dB
DAC_VOL= 0dB
1.80
1.73
1.00
0.77
1.80
0.00
1.80
5.61
13.99
48kHz sample rate, Master mode,
FLL enabled, MCLK input frequency =
13MHz
1.80
1.82
1.00
1.05
1.80
0.73
1.80
0.30
6.18
48kHz sample rate, Master mode,
FLL enabled, MCLK input frequency =
32.768kHz
1.80
1.83
1.00
0.94
1.80
0.76
1.80
0.29
6.14
Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR or HPOUTL+HPOUTR pins with 10kΩ / 50pF load
Test conditions :
VMID_RES = 01 (for normal operation)
CP_DYN_PWR = 1 (Class-W, Charge pump controlled by real-time audio level)
Variant test conditions
AVDD
DCVDD
DBVDD
CPVDD
TOTAL
V
mA
V
mA
V
mA
V
mA
mW
48kHz sample rate
1.8
1.67
1
0.76
1.8
0.00
1.8
0.36
4.43
8kHz sample rate
1.8
1.67
1
0.18
1.8
0.00
1.8
0.36
3.86
48kHz, Po = 0dBFS 1kHz sine wave
1.8
1.78
1
0.77
1.8
0.00
1.8
2.27
8.09
Off
Note: DC servo calibration is retained in this state as long as DCVDD is supplied. This allows fast, pop suppressed start-up from
the off state.
Variant test conditions
AVDD
DCVDD
DBVDD
CPVDD
TOTAL
V
mA
V
mA
V
mA
V
mA
mW
Off (default settings)
No Clocks applied
1.8
0.01
1
0.00
1.8
0.00
1.8
0.01
0.04
Off (default settings)
DACDAT, MCLK, BCLK, and LRCLK
applied
1.8
0.01
1
0.02
1.8
0.00
1.8
0.01
0.06
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SIGNAL TIMING REQUIREMENTS
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
•
•
•
•
Ambient temperature = +25°C
DCVDD = 1.0V
DBVDD = AVDD = CPVDD = 1.8V
DGND = AGND = CPGND = 0V
Additional, specific test conditions are given within the relevant sections below.
MASTER CLOCK
tMCLKY
MCLK
tMCLKL
tMCLKH
Figure 1 Master Clock Timing
Master Clock Timing
PARAMETER
MCLK cycle time
MCLK duty cycle
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SYMBOL
TEST CONDITIONS
MIN
TMCLKY
MCLK_DIV=1
40
ns
MCLK_DIV=0
80
ns
TMCLKDS
60:40
TYP
MAX
UNIT
40:60
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AUDIO INTERFACE TIMING
MASTER MODE
BCLK
(output)
LRCLK
(output)
tDL
DACDAT
(input)
tDST
tDHT
Figure 2 Audio Interface Timing – Master Mode
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25oC, Master Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing - Master Mode
LRCLK propagation delay from BCLK falling edge
tDL
DACDAT setup time to BCLK rising edge
tDST
20
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
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20
ns
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SLAVE MODE
tBCY
BCLK
(input)
LRCLK
(input)
tBCH
tBCL
tLRH
DACDAT
(input)
tDS
tLRSU
tDH
Figure 3 Audio Interface Timing – Slave Mode
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25oC, Slave Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing - Slave Mode
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRCLK set-up time to BCLK rising edge
tLRSU
20
ns
LRCLK hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ns
DACDAT set-up time to BCLK rising edge
tDS
20
ns
Note: BCLK period must always be greater than or equal to MCLK period.
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CONTROL INTERFACE TIMING
Figure 4 Control Interface Timing
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
SCLK Frequency
TYP
MAX
UNIT
400
kHz
SCLK Low Pulse-Width
t1
1300
ns
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDA, SCLK Rise Time
t6
SDA, SCLK Fall Time
t7
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
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ns
300
ns
300
ns
900
ns
5
ns
600
0
ns
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
+/- 0.05dB
0
TYP
MAX
UNIT
DAC Normal Filter
Passband
-6dB
Passband Ripple
0.454 fs
0.5 fs
0.454 fs
Stopband
+/- 0.03
dB
0.546 fs
Stopband Attenuation
F > 0.546 fs
-50
dB
DAC Sloping Stopband Filter
Passband
+/- 0.03dB
0
0.25 fs
+/- 1dB
0.25 fs
0.454 fs
-6dB
Passband Ripple
0.5 fs
0.25 fs
Stopband 1
+/- 0.03
0.546 fs
Stopband 1 Attenuation
f > 0.546 fs
Stopband 2
-60
0.7 fs
Stopband 2 Attenuation
f > 0.7 fs
Stopband 3
dB
0.7 fs
dB
1.4 fs
-85
dB
1.4 fs
Stopband 3 Attenuation
F > 1.4 fs
-55
dB
DAC FILTERS
Mode
Group Delay
Normal
16.5 / fs
Sloping Stopband
18 / fs
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
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DAC FILTER RESPONSES
MAGNITUDE(dB)
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
-0.005
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.5
Frequency (fs)
Figure 5 DAC Digital Filter Frequency Response; (Normal
Mode); Sample Rate > 24kHz
Figure 6 DAC Digital Filter Ripple (Normal Mode)
MAGNITUDE(dB)
0.05
0
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
Frequency (fs)
Figure 7 DAC Digital Filter Frequency Response; (Sloping
Stopband Mode); Sample Rate <= 24kHz
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Figure 8 DAC Digital Filter Ripple (Sloping Stopband
Mode)
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DE-EMPHASIS FILTER RESPONSES
MAGNITUDE(dB)
MAGNITUDE(dB)
0.3
0
-1
0
5000
10000
15000
20000
-2
0.25
0.2
-3
0.15
-4
0.1
-5
0.05
-6
0
-7
-0.05
-8
-9
-0.1
-10
-0.15
0
2000
4000
6000
Frequency (Hz)
10000
12000
14000
16000
18000
Frequency (Hz)
Figure 9 De-Emphasis Digital Filter Response (32kHz)
Figure 10 De-Emphasis Error (32kHz)
MAGNITUDE(dB)
MAGNITUDE(dB)
0
-1
8000
0.2
0
5000
10000
15000
20000
25000
0.15
-2
-3
0.1
-4
0.05
-5
-6
0
-7
0
-8
5000
10000
15000
20000
25000
-0.05
-9
-0.1
-10
Frequency (Hz)
Frequency (Hz)
Figure 11 De-Emphasis Digital Filter Response (44.1kHz)
Figure 12 De-Emphasis Error (44.1kHz)
MAGNITUDE(dB)
MAGNITUDE(dB)
0.15
0
0
5000
10000
15000
20000
25000
30000
-2
0.1
-4
0.05
-6
0
-8
-0.05
-10
-0.1
0
5000
10000
15000
20000
25000
30000
-0.15
-12
Frequency (Hz)
Figure 13 De-Emphasis Digital Filter Response (48kHz)
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Frequency (Hz)
Figure 14 De-Emphasis Error (48kHz)
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DEVICE DESCRIPTION
INTRODUCTION
The WM8912 is a high performance ultra-low power stereo DAC optimised for portable audio
applications. Powerful digital signal processing (DSP) makes it ideal for small portable devices.
Two stereo pairs of ground-referenced Class-W outputs are provided, suitable for driving a stereo
headphone and stereo line load simultaneously. The ground-referenced outputs are powered from an
integrated Charge Pump, enabling high quality, power efficient outputs without requirement for DC
blocking capacitors. A DC Servo circuit is available for DC offset correction, thereby suppressing
pops and further reducing power consumption. Ground loop feedback is provided on the headphone
outputs and on the line outputs, providing rejection of noise on the ground connections. All outputs
use Wolfson SilentSwitch™ technology for pop and click suppression.
The stereo DACs are of hi-fi quality, using a 24-bit low-order oversampling architecture to deliver
optimum performance. A flexible clocking arrangement supports all commonly used DAC sample
rates, either directly from an external MCLK or with the use of the integrated Frequency Locked Loop
(FLL) for additional flexibility. DAC soft mute and un-mute is available for pop-free music playback.
The integrated Dynamic Range Controller (DRC) and ReTuneTM Mobile 5-band parametric equaliser
(EQ) provide further processing capability of the digital audio paths. The DRC provides compression
and signal level control to improve the handling of unpredictable signal levels. ‘Anti-clip’ and ‘quick
release’ algorithms improve intelligibility in the presence of transients and impulsive noises. The EQ
provides the capability to tailor the audio path according to the frequency characteristics of an
earpiece or loudspeaker, and/or according to user preferences.
The WM8912 has a highly flexible digital audio interface, supporting a number of protocols, including
I2S, DSP, MSB-first left/right justified, and can operate in master or slave modes. PCM operation is
supported in the DSP mode. A-law and μ-law companding are also supported. Time division
multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same
bus, saving space and power.
The system clock (SYSCLK) provides clocking for the DACs, DSP core, digital audio interface and
other circuits. SYSCLK can be derived directly from the MCLK pin or via the integrated FLL,
providing flexibility to support a wide range of clocking schemes. Typical portable system MCLK
frequencies and commonly used sample rates from 8kHz to 48kHz are all supported. The clocking
circuits are configured automatically from the sample rate and from the MCLK / SYSCLK ratio.
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference
sources and frequencies. The FLL can accept a wide range of reference frequencies, which may be
high frequency (e.g. 13MHz) or low frequency (eg. 32.768kHz). The FLL is tolerant of jitter and may
be used to generate a stable SYSCLK from a less stable input signal. The integrated FLL can be
used as a free-running oscillator, enabling autonomous clocking of the Headphone Charge Pump
and DC Servo if required.
The WM8912 uses a standard 2-wire control interface, providing full software control of all features,
together with device register readback. An integrated Control Write Sequencer enables automatic
scheduling of control sequences; commonly-used signal configurations may be selected using readyprogrammed sequences, including time-optimised control of the WM8912 pop suppression features.
It is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.
Unused circuitry can be disabled under software control, in order to save power; low leakage currents
enable extended standby/off time in portable battery-powered applications.
Two GPIO pins may be configured for miscellaneous input/output functions such as
button/accessory detect inputs, or for clock, system status, or programmable logic level output for
control of additional external circuitry. Interrupt logic, status readback and de-bouncing options are
supported within this functionality.
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DYNAMIC RANGE CONTROL (DRC)
The dynamic range controller (DRC) is a circuit which can be enabled in the digital DAC playback
path. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is
unknown or varies over a wide range, e.g. when recording from microphones built into a handheld
system. The DRC can apply Compression and Automatic Level Control to the signal path. It
incorporates ‘anti-clip’ and ‘quick release’ features for handling transients in order to improve
intelligibility in the presence of loud impulsive noises.
The DRC is enabled in the digital DAC playback path by setting DRC_ENA and DRC_DAC_PATH,
as shown in Table 1. Both bits must be set for DRC operation.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
DRC Control 0
15
DRC_ENA
0
DRC enable
0 = disabled
1 = enabled
14
DRC_DAC_PAT
H
0
DRC path select
0 = Reserved
1 = DAC path
Table 1 DRC Enable
COMPRESSION/LIMITING CAPABILITIES
The DRC supports two different compression regions, separated by a “knee” at input amplitude T.
For signals above the knee, the compression slope DRC_HI_COMP applies; for signals below the
knee, the compression slope DRC_LO_COMP applies.
The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is nearconstant) is illustrated in Figure 15.
DRC Output Amplitude (dB)
(Y0)
“knee”
DRC_KNEE_OP
P
COM
_HI_
DRC
P
OM
_C
O
L
C_
DR
DRC_KNEE_IP
0dB
DRC Input Amplitude (dB)
Figure 15 DRC Compression Characteristic
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The slope of the DRC response is determined by register fields DRC_HI_COMP and
DRC_LO_COMP respectively. A slope of 1 indicates constant gain in this region. A slope less than 1
represents compression (i.e. a change in input amplitude produces only a smaller change in output
amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of
input amplitudes; this is infinite compression.
The “knee” in Figure 15 is determined by register fields DRC_KNEE_IP and DRC_KNEE_OP.
Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from
the other parameters, using the equation.
The DRC Compression parameters are defined in Table 2.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R43 (2Bh)
DRC Control 3
10:5
DRC_KNEE_IP
[5:0]
00_0000
Input signal at the Compressor
'knee'.
000000 = 0dB
000001 = -0.75dB
000010 = -1.5dB
… (-0.75dB steps)
111100 = -45dB
111101 to 111111 = Reserved
4:0
DRC_KNEE_OP
[4:0]
0_0000
Output signal at the Compressor
'knee'.
00000 = 0dB
00001 = -0.75dB
00010 = -1.5dB
… (-0.75dB steps)
11110 = -22.5dB
11111 = Reserved
5:3
DRC_HI_COMP
[2:0]
000
Compressor slope (upper region)
000 = 1 (no compression)
001 = 1/2
010 = 1/4
011 = 1/8
100 = 1/16
101 = 0
110 to 111 = Reserved
2:0
DRC_LO_COMP
[2:0]
000
Compressor slope (lower region)
000 = 1 (no compression)
001 = 1/2
010 = 1/4
011 = 1/8
100 = 0
101 to 111 = Reserved
R42 (2Ah)
DRC Control 2
DESCRIPTION
Table 2 DRC Compression Control
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GAIN LIMITS
The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and
DRC_MAXGAIN. These limits can be used to alter the DRC response from that illustrated in Figure
15. If the range between maximum and minimum gain is reduced, then the extent of the dynamic
range control is reduced. The maximum gain prevents quiet signals (or silence) from being
excessively amplified.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R41 (29h)
DRC Control 1
3:2
DRC_MINGAIN [1:0]
10
Minimum gain the DRC can use
to attenuate audio signals
00 = 0dB (default)
01 = -6dB
10 = -12dB
11 = -18dB
1:0
DRC_MAXGAIN
[1:0]
00
Maximum gain the DRC can use
to boost audio signals
00 = 12dB
01 = 18dB (default)
10 = 24dB
11 = 36dB
DESCRIPTION
Table 3 DRC Gain Limits
DYNAMIC CHARACTERISTICS
The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note
that the DRC responds to the average (RMS) signal amplitude over a period of time.
DRC_ATK determines how quickly the DRC gain decreases when the signal amplitude is high.
DRC_DCY determines how quickly the DRC gain increases when the signal amplitude is low.
These register fields are described in Table 4. Note that the register defaults are suitable for general
purpose microphone use.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R41 (29h)
DRC Control 1
15:12
DRC_ATK [3:0]
0011
DESCRIPTION
Gain attack rate (seconds/6dB)
0000 = Reserved
0001 = 182μs
0010 = 363μs
0011 = 726μs (default)
0100 = 1.45ms
0101 = 2.9ms
0110 = 5.8ms
0111 = 11.6ms
1000 = 23.2ms
1001 = 46.4ms
1010 = 92.8ms
1011-1111 = Reserved
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
11:8
DRC_DCY [3:0]
0010
DESCRIPTION
Gain decay rate (seconds/6dB)
0000 = 186ms
0001 = 372ms
0010 = 743ms (default)
0011 = 1.49s
0100 = 2.97s
0101 = 5.94s
0110 = 11.89s
0111 = 23.78s
1000 = 47.56s
1001-1111 = Reserved
Table 4 DRC Attack and Decay Rates
Note:
For detailed information about DRC attack and decay rates, please see Wolfson application note
WAN0247.
ANTI-CLIP CONTROL
The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very
quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal
clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip
feature is enabled using the DRC_ANTICLIP bit.
Note that the feed-forward processing increases the latency in the input signal path. For low-latency
applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce
the effectiveness of the anti-clip feature. The latency is determined by the DRC_FF_DELAY bit. If
necessary, the latency can be minimised by disabling the anti-clip feature altogether.
The DRC Anti-Clip control bits are described in Table 5.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
DRC Control 0
5
DRC_FF_DELAY
1
Feed-forward delay for anti-clip
feature
0 = 5 samples
1 = 9 samples
Time delay can be calculated as
5/fs or 9/ fs, where fs is the sample
rate.
1
DRC_ANTICLIP
1
Anti-clip enable
0 = disabled
1 = enabled
Table 5 DRC Anti-Clip Control
Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent
signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be
prevented by reducing the analogue signal gain or by adjusting the source signal.
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QUICK RELEASE CONTROL
The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the
intended source signal. For example, in handheld microphone recording, transient signal peaks
sometimes occur due to user handling, key presses or accidental tapping against the microphone.
The Quick Release feature ensures that these transients do not cause the intended signal to be
masked by the longer time constants of DRC_DCY.
The Quick-Release feature is enabled by setting the DRC_QR bit. When this bit is enabled, the DRC
measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a
transient peak that may not be related to the intended source signal. If the crest factor exceeds the
level set by DRC_QR_THR, then the normal decay rate (DRC_DCY) is ignored and a faster decay
rate (DRC _QR_DCY) is used instead.
The DRC Quick-Release control bits are described in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
DRC Control 0
2
DRC_QR
1
Quick release enable
0 = disabled
1 = enabled
R41 (29h)
DRC Control 1
7:6
DRC_QR_THR
[1:0]
01
Quick release crest factor threshold
00 = 12dB
01 = 18dB (default)
10 = 24dB
11 = 30dB
5:4
DRC_QR_DCY
[1:0]
00
Quick release decay rate
(seconds/6dB)
00 = 0.725ms (default)
01 = 1.45ms
10 = 5.8ms
11 = Reserved
Table 6 DRC Quick-Release Control
GAIN SMOOTHING
The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of
hysteresis is also used to control the DRC gain. This improves the handling of very low frequency
input signals whose period is close to the DRC attack/decay time. DRC Gain Smoothing is enabled
by default and it is recommended to use the default register settings.
The extent of the gain smoothing filter may be adjusted or disabled using the control fields described
in Table 7.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
DRC Control 0
12:11
DRC_GS_HYST
_LVL [1:0]
00
Gain smoothing hysteresis
threshold
00 = Low
01 = Medium (recommended)
10 = High
11 = Reserved
3
DRC_GS_ENA
1
Gain smoothing enable
0 = disabled
1 = enabled
0
DRC_GS_HYST
1
Gain smoothing hysteresis enable
0 = disabled
1 = enabled
Table 7 DRC Gain Smoothing
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INITIALISATION
When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN
register field. The default setting is 0dB, but values from -3dB to +6dB are available, as described in
Table 8.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R40 (28h)
DRC Control 0
10:6
DRC_STARTUP_
GAIN [4:0]
00110
DESCRIPTION
Initial gain at DRC start-up
00000 = -3dB
00001 = -2.5dB
00010 = -2dB
00011 = -1.5dB
00100 = -1dB
00101 = -0.5dB
00110 = 0dB (default)
00111 = 0.5dB
01000 = 1dB
01001 = 1.5dB
01010 = 2dB
01011 = 2.5dB
01100 = 3dB
01101 = 3.5dB
01110 = 4dB
01111 = 4.5dB
10000 = 5dB
10001 = 5.5dB
10010 = 6dB
10011 to 11111 = Reserved
Table 8 DRC Initialisation
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RETUNE
TM
Production Data
MOBILE PARAMETRIC EQUALIZER (EQ)
The ReTuneTM Mobile Parametric Equaliser is a circuit that can be enabled in the DAC path. The
function of the EQ is to adjust the frequency characteristic of the output to compensate for unwanted
frequency characteristics in the loudspeaker (or other output transducer). It can also be used to tailor
the response according to user preferences, for example to accentuate or attenuate specific
frequency bands to emulate different sound profiles or environments such as concert hall, rock etc.
The EQ is enabled using the EQ_ENA bit as shown in Table 9.
REGISTER
ADDRESS
R134 (86h)
EQ1
BIT
0
LABEL
DEFAULT
EQ_ENA
0
DESCRIPTION
EQ enable
0 = EQ disabled
1 = EQ enabled
Table 9 ReTuneTM Mobile Parametric EQ Enable
The EQ can be configured to operate in two modes - “Default” mode or “ReTuneTM Mobile” mode.
DEFAULT MODE (5-BAND PARAMETRIC EQ)
In default mode, the cut-off / centre frequencies are fixed as per Table 10. The filter bandwidths are
also fixed in default mode. The gain of the individual bands (-12dB to +12dB) can be controlled as
described in Table 11.
Note that the cut-off / centre frequencies noted in Table 10 are applicable to a DAC Sample Rate of
48kHz. When using other sample rates, these frequencies will be scaled in proportion to the selected
sample rate.
EQ BAND
CUT-OFF/CENTRE
FREQUENCY
1
100 Hz
2
300 Hz
3
875 Hz
4
2400 Hz
5
6900 Hz
Table 10 EQ Band Cut-off / Centre Frequencies
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R135 (87h)
EQ2
4:0
EQ_B1_GAIN [4:0]
01100b
(0dB)
EQ Band 1 Gain
(see Table 12 for gain range)
R136 (88h)
EQ3
4:0
EQ_B2_GAIN [4:0]
01100b
(0dB)
EQ Band 2 Gain
(see Table 12 for gain range)
R137 (89h)
EQ4
4:0
EQ_B3_GAIN [4:0]
01100b
(0dB)
EQ Band 3 Gain
(see Table 12 for gain range)
R138 (8Ah)
EQ5
4:0
EQ_B4_GAIN [4:0]
01100b
(0dB)
EQ Band 4 Gain
(see Table 12 for gain range)
R139 (8Bh)
EQ6
4:0
EQ_B5_GAIN [4:0]
01100b
(0dB)
EQ Band 5 Gain
(see Table 12 for gain range)
Table 11 EQ Band Gain Control
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EQ GAIN SETTING
GAIN (DB)
00000
-12
00001
-11
00010
-10
00011
-9
00100
-8
00101
-7
00110
-6
00111
-5
01000
-4
01001
-3
01010
-2
01011
-1
01100
0
01101
+1
01110
+2
01111
+3
10000
+4
10001
+5
10010
+6
10011
+7
10100
+8
10101
+9
10110
+10
10111
+11
11000
+12
11001 to 11111
Reserved
Table 12 EQ Gain Control
RETUNE
TM
MOBILE MODE
TM
ReTune Mobile mode provides a comprehensive facility for the user to define the cut-off/centre
frequencies and filter bandwidth for each EQ band, in addition to the gain controls already described.
This enables the EQ to be accurately customised for a specific transducer characteristic or desired
sound profile.
The EQ enable and EQ gain controls are the same as defined for the default mode. The additional
coefficients used in ReTuneTM Mobile mode are held in registers R140 to R157. These coefficients
are derived using tools provided in Wolfson’s WISCE™ evaluation board control software.
Please contact your local Wolfson representative for more details.
EQ FILTER CHARACTERISTICS
The filter characteristics for each frequency band are shown in Figure 16 to Figure 20. These figures
show the frequency response for all available gain settings, using default cut-off/centre frequencies
and bandwidth.
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15
15
10
10
5
5
Gain (dB)
Gain (dB)
WM8912
0
0
-5
-5
-10
-10
-15
-15
1
10
100
1000
10000
100000
1
10
Frequency (Hz)
1000
10000
100000
Frequency (Hz)
Figure 16 EQ Band 1 – Low Freq Shelf Filter Response
Figure 17 EQ Band 2 – Peak Filter Response
15
15
10
10
5
5
Gain (dB)
Gain (dB)
100
0
0
-5
-5
-10
-10
-15
-15
1
10
100
1000
10000
100000
Frequency (Hz)
1
10
100
1000
10000
100000
Frequency (Hz)
Figure 18 EQ Band 3 – Peak Filter Response
Figure 19 EQ Band 4 – Peak Filter Response
15
10
Gain (dB)
5
0
-5
-10
-15
1
10
100
1000
10000
100000
Frequency (Hz)
Figure 20 EQ Band 5 – High Freq Shelf Filter Response
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DIGITAL MIXING
The digital DAC data can be controlled in various ways to support a range of different usage modes.
Data from either of the digital audio interface channels can be routed to either the left or the right
DAC. The DACs can be configured as a mono mix of the two audio channels. See "Digital Audio
Interface Control" for more information on the audio interface.
The WM8912 provides a Dynamic Range Control (DRC) feature, which can apply compression and
gain adjustment in the digital domain to the DAC signal path. This is effective in controlling signal
levels under conditions where input amplitude is unknown or varies over a wide range. See “Dynamic
Range Control (DRC)” for further details.
The W8912 also incorporates the ReTuneTM Mobile 5-band parametric equaliser with fully
programmable coefficients for optimization of speaker characteristics or for tailoring the response
according to user preferences. See “ReTuneTM Mobile Parametric Equalizer (EQ)” for further details.
DAC INTERFACE ROUTING AND CONTROL
The input data source for each DAC can be changed under software control using register bits
AIFDACL_SRC and AIFDACR_SRC. The polarity of each DAC input may also be modified using
register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 13.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
Audio
Interface 0
12
DACL_DATINV
0
Left DAC Invert
0 = Left DAC output not inverted
1 = Left DAC output inverted
11
DACR_DATINV
0
Right DAC Invert
0 = Right DAC output not inverted
1 = Right DAC output inverted
5
AIFDACL_SRC
0
Left DAC Data Source Select
0 = Left DAC outputs left interface data
1 = Left DAC outputs right interface data
4
AIFDACR_SRC
1
Right DAC Data Source Select
0 = Right DAC outputs left interface data
1 = Right DAC outputs right interface
data
Table 13 DAC Routing and Control
DAC INTERFACE VOLUME BOOST
A digital gain function is available at the audio interface to boost the DAC volume when a small
signal is received on DACDAT. This is controlled using register bits DAC_BOOST [1:0]. To prevent
clipping at the DAC input, this function should not be used when the boosted DAC data is expected
to be greater than 0dBFS.
The digital interface volume is controlled as shown in Table 14.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R24 (18h)
Audio
Interface 0
10:9
DAC_BOOST
[1:0]
00
DESCRIPTION
DAC Input Volume Boost
00 = 0dB
01 = +6dB (Input data must not
exceed -6dBFS)
10 = +12dB (Input data must not
exceed -12dBFS)
11 = +18dB (Input data must not
exceed -18dBFS)
Table 14 DAC Interface Volume Boost
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DIGITAL-TO-ANALOGUE CONVERTER (DAC)
The WM8912 DACs receive digital input data from the DACDAT pin. The digital audio data is
converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The
bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue
audio signals. The Wolfson SmartDAC™ architecture offers reduced power consumption, whilst also
delivering a reduction in high frequency noise and sensitivity to clock jitter. It also uses a Dynamic
Element Matching technique for high linearity and low distortion.
The analogue outputs from the DACs are sent directly to the output PGAs (see “Output Signal
Path”).
The DACs are enabled by the DACL_ENA and DACR_ENA register bits.
REGISTER
ADDRESS
R18 (12h)
Power
Management
6
BIT
LABEL
DEFAULT
DESCRIPTION
3
DACL_ENA
0
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
2
DACR_ENA
0
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
Table 15 DAC Enable Control
DAC DIGITAL VOLUME CONTROL
The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in
0.375dB steps. The level of attenuation for an eight-bit code is detailed in Table 17.
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the
DACL_VOL or DACR_VOL control data is loaded into the respective control register, but does not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to DAC_VU. This makes it possible to update the gain of both channels simultaneously.
REGISTER
ADDRESS
R30 (1Eh)
DAC Digital
Volume Left
R31 (1Fh)
DAC Digital
Volume Right
BIT
LABEL
DEFAULT
DESCRIPTION
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit causes left
and right DAC volume to be
updated simultaneously
7:0
DACL_VOL [7:0]
1100_0000
(0dB)
Left DAC Digital Volume
00h = Mute
01h = -71.625dB
02h = -71.250dB
… (0.375dB steps)
C0h to FFh = 0dB
(See Table 17 for volume range)
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit causes left
and right DAC volume to be
updated simultaneously
7:0
DACR_VOL [7:0]
1100_0000
(0dB)
Right DAC Digital Volume
00h = Mute
01h = -71.625dB
02h = -71.250dB
… (0.375dB steps)
C0h to FFh = 0dB
(See Table 17 for volume range)
Table 16 DAC Digital Volume Control
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DACL_VOL or
DACL_VOL or
DACL_VOL or
DACL_VOL or
DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
MUTE
-71.625
-71.250
-70.875
-70.500
-70.125
-69.750
-69.375
-69.000
-68.625
-68.250
-67.875
-67.500
-67.125
-66.750
-66.375
-66.000
-65.625
-65.250
-64.875
-64.500
-64.125
-63.750
-63.375
-63.000
-62.625
-62.250
-61.875
-61.500
-61.125
-60.750
-60.375
-60.000
-59.625
-59.250
-58.875
-58.500
-58.125
-57.750
-57.375
-57.000
-56.625
-56.250
-55.875
-55.500
-55.125
-54.750
-54.375
-54.000
-53.625
-53.250
-52.875
-52.500
-52.125
-51.750
-51.375
-51.000
-50.625
-50.250
-49.875
-49.500
-49.125
-48.750
-48.375
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
-48.000
-47.625
-47.250
-46.875
-46.500
-46.125
-45.750
-45.375
-45.000
-44.625
-44.250
-43.875
-43.500
-43.125
-42.750
-42.375
-42.000
-41.625
-41.250
-40.875
-40.500
-40.125
-39.750
-39.375
-39.000
-38.625
-38.250
-37.875
-37.500
-37.125
-36.750
-36.375
-36.000
-35.625
-35.250
-34.875
-34.500
-34.125
-33.750
-33.375
-33.000
-32.625
-32.250
-31.875
-31.500
-31.125
-30.750
-30.375
-30.000
-29.625
-29.250
-28.875
-28.500
-28.125
-27.750
-27.375
-27.000
-26.625
-26.250
-25.875
-25.500
-25.125
-24.750
-24.375
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
-24.000
-23.625
-23.250
-22.875
-22.500
-22.125
-21.750
-21.375
-21.000
-20.625
-20.250
-19.875
-19.500
-19.125
-18.750
-18.375
-18.000
-17.625
-17.250
-16.875
-16.500
-16.125
-15.750
-15.375
-15.000
-14.625
-14.250
-13.875
-13.500
-13.125
-12.750
-12.375
-12.000
-11.625
-11.250
-10.875
-10.500
-10.125
-9.750
-9.375
-9.000
-8.625
-8.250
-7.875
-7.500
-7.125
-6.750
-6.375
-6.000
-5.625
-5.250
-4.875
-4.500
-4.125
-3.750
-3.375
-3.000
-2.625
-2.250
-1.875
-1.500
-1.125
-0.750
-0.375
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
Table 17 DAC Digital Volume Range
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DAC SOFT MUTE AND SOFT UN-MUTE
The WM8912 has a soft mute function. When enabled, this gradually attenuates the volume of the
DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital
gain setting, or return instantly to the digital gain setting, depending on the DAC_UNMUTE_RAMP
register bit.
To mute the DAC, this function must be enabled by setting DAC_MUTE to 1.
Soft Mute Mode would typically be enabled (DAC_UNMUTE_RAMP = 1) when using DAC_MUTE
during playback of audio data so that when DAC_MUTE is subsequently disabled, the sudden
volume increase will not create pop noise by jumping immediately to the previous volume level (e.g.
resuming playback after pausing during a track).
Soft Mute Mode would typically be disabled (DAC_UNMUTE_RAMP = 0) when un-muting at the start
of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of
a new track, or resuming playback after pausing between tracks).
DAC muting and un-muting using volume control bits
DACL_VOL and DACR_VOL.
DAC muting and un-muting using the DAC_MUTE bit.
If soft Mute Mode is not enabled (DAC_UNMUTE_RAMP = 0):
Setting the DAC_MUTE bit causes the volume to ramp down
at a rate controlled by DAC_MUTERATE.
Clearing the DAC_MUTE bit causes the volume to return to
the un-muted level immediately.
DAC muting and un-muting using the DAC_MUTE bit.
If soft Mute Mode is enabled (DAC_UNMUTE_RAMP = 1):
Setting the DAC_MUTE bit causes the volume to ramp down.
Clearing the DAC_MUTE bit causes the volume to ramp up to
the un-muted level at a rate controlled by DAC_MUTERATE.
Figure 21 DAC Mute Control
The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit.
Ramp rates of fs/32 and fs/2 can be selected, as shown in Table 18. The ramp rate determines the
rate at which the volume is increased or decreased. The actual ramp time depends on the extent of
the difference between the muted and un-muted volume settings.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R33 (21h)
DAC Digital 1
10
DAC_MUTERA
TE
0
DAC Soft Mute Ramp Rate
0 = Fast ramp (fs/2, maximum ramp
time is 10.7ms at fs=48k)
1 = Slow ramp (fs/32, maximum ramp
time is 171ms at fs=48k)
9
DAC_UNMUTE
_RAMP
0
DAC Soft Mute Mode
0 = Disabling soft-mute
(DAC_MUTE=0) will cause the DAC
volume to change immediately to
DACL_VOL and DACR_VOL settings
1 = Disabling soft-mute
(DAC_MUTE=0) will cause the DAC
volume to ramp up gradually to the
DACL_VOL and DACR_VOL settings
3
DAC_MUTE
DAC Soft Mute Control
0 = DAC Un-mute
1 = DAC Mute
1
Table 18 DAC Soft-Mute Control
DAC MONO MIX
A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will
be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically
applied to the mono mix.
The mono mix is only supported when one or other DAC is disabled. When the mono mix is selected,
then the mono mix is output on the enabled DAC only; there is no output from the disabled DAC. If
DACL_ENA and DACR_ENA are both set, then stereo operation applies.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R33 (21h)
DAC Digital 1
12
DAC_MONO
0
DESCRIPTION
DAC Mono Mix
0 = Stereo
1 = Mono (Mono mix output on
enabled DAC)
Table 19 DAC Mono Mix
DAC DE-EMPHASIS
Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD
with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of
48kHz, 44.1kHz and 32kHz. See “Digital Filter Characteristics” for details of de-emphasis filter
characteristics.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R33 (21h)
DAC Digital 1
2:1
DEEMPH [1:0]
00
DESCRIPTION
DAC De-Emphasis Control
00 = No de-emphasis
01 = 32kHz sample rate
10 = 44.1kHz sample rate
11 = 48kHz sample rate
Table 20 DAC De-Emphasis Control
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DAC SLOPING STOPBAND FILTER
Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at
lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband
filter type is selected (DAC_SB_FILT=1) to reduce out-of-band noise which can be audible at low
DAC sample rates. See “Digital Filter Characteristics” for details of DAC filter characteristics.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R33 (21h)
DAC Digital 1
11
DAC_SB_FILT
0
DESCRIPTION
Selects DAC filter characteristics
0 = Normal mode
1 = Sloping stopband mode
Table 21 DAC Sloping Stopband Filter
DAC OVERSAMPLING RATIO (OSR)
The DAC oversampling rate is programmable to allow power consumption versus audio performance
trade-offs. The default oversampling rate is low for reduced power consumption; using the higher
OSR setting improves the DAC signal-to-noise performance.
REGISTER
ADDRESS
R33 (21h)
DAC Digital 1
BIT
LABEL
DEFAULT
DESCRIPTION
6
DAC_OSR128
0
DAC Oversample Rate Select
0 = Low power (normal OSR)
1 = High performance (double OSR)
Table 22 DAC Oversampling Control
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OUTPUT SIGNAL PATH
The outputs HPOUTL and LINEOUTL are derived from the Left DAC output, whilst the outputs
HPOUTR and LINEOUTR are derived from the Right DAC output, as illustrated in Figure 22.
A feedback path for common mode noise rejection is provided at HPOUTFB and LINEOUTFB for the
Headphone and Line outputs respectively. This pin must be connected to ground for normal
operation.
Each analogue output can be separately enabled; independent volume control is also provided for
each output. The signal paths and associated control registers are illustrated in Figure 22.
Figure 22 Output Signal Path and Control Registers
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OUTPUT SIGNAL PATHS ENABLE
The output PGAs for each analogue output pin can be enabled and disabled using the register bits
described in Table 23.
Note that the Headphone Outputs and Line Outputs are also controlled by fields located within
Register R90 and R94, which provide suppression of pops & clicks when enabling and disabling
these signal paths. These registers are described in the following “Headphone / Line Output Signal
Paths Enable” section.
Under recommended usage conditions, all the control bits associated with enabling the Headphone
Outputs and the Line Outputs will be configured by scheduling the default Start-Up and Shutdown
sequences as described in the “Control Write Sequencer” section. In these cases, the user does not
need to set the register fields in R14, R15, R90 and R94 directly.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R14 (0Eh)
Power
Management 2
1
HPL_PGA_ENA
0
Left Headphone Output Enable
0 = disabled
1 = enabled
0
HPR_PGA_ENA
0
Right Headphone Output Enable
0 = disabled
1 = enabled
1
LINEOUTL_PGA_
ENA
0
Left Line Output Enable
0 = disabled
1 = enabled
0
LINEOUTR_PGA
_ENA
0
Right Line Output Enable
0 = disabled
1 = enabled
R15 (0Fh)
Power
Management 3
DESCRIPTION
Table 23 Output Signal Paths Enable
Note that, to enable the output PGAs and multiplexers, the reference voltage VMID and the bias
current must also be enabled. See “Reference Voltages and Master Bias” for details of the
associated controls VMID_RES and BIAS_ENA.
HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE
The output paths can be actively discharged to AGND through internal resistors if desired. This is
desirable at start-up in order to achieve a known output stage condition prior to enabling the VMID
reference voltage. This is also desirable in shutdown to prevent the external connections from being
affected by the internal circuits. The ground-referenced Headphone outputs and Line outputs are
shorted to AGND by default; the short circuit is removed on each of these paths by setting the
applicable fields HPL_RMV_SHORT, HPR_RMV_SHORT, LINEOUTL_RMV_SHORT or
LINEOUTR_RMV_SHORT.
The ground-referenced Headphone output and Line output drivers are designed to suppress pops
and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance
with a defined sequence in start-up and shutdown to achieve the pop suppression. It is also
necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see
“DC Servo”). Table 24 and Table 25 describe the recommended sequences for enabling and
disabling these output drivers.
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SEQUENCE
HEADPHONE ENABLE
LINEOUT ENABLE
Step 1
HPL_ENA = 1
HPR_ENA = 1
LINEOUTL_ENA = 1
LINEOUTR_ENA = 1
Step 2
HPL_ENA_DLY = 1
HPR_ENA_DLY = 1
LINEOUTL_ENA_DLY = 1
LINEOUTR_ENA_DLY = 1
DC offset correction
DC offset correction
Step 4
HPL_ENA_OUTP = 1
HPR_ENA_OUTP = 1
LINEOUTL_ENA_OUTP = 1
LINEOUTR_ENA_OUTP = 1
Step 5
HPL_RMV_SHORT = 1
HPR_RMV_SHORT = 1
LINEOUTL_RMV_SHORT = 1
LINEOUTR_RMV_SHORT = 1
Step 3
Table 24 Headphone / Line Output Enable Sequence
SEQUENCE
HEADPHONE DISABLE
LINEOUT DISABLE
Step 1
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
Step 2
HPL_ENA = 0
HPL_ENA_DLY = 0
HPL_ENA_OUTP = 0
HPR_ENA = 0
HPR_ENA_DLY = 0
HPR_ENA_OUTP = 0
LINEOUTL_ENA = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA_OUTP = 0
LINEOUTR_ENA = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA_OUTP = 0
Table 25 Headphone / Line Output Disable Sequence
The register bits relating to pop suppression control are defined in Table 26 below.
REGISTER
ADDRESS
R90 (5Ah)
Analogue
HP 0
w
BIT
LABEL
DEFAULT
DESCRIPTION
7
HPL_RMV_SHOR
T
0
Removes HPL short
0 = HPL short enabled
1 = HPL short removed
For normal operation, this bit should
be set as the final step of the HPL
Enable sequence.
6
HPL_ENA_OUTP
0
Enables HPL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
5
HPL_ENA_DLY
0
Enables HPL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPL_ENA.
4
HPL_ENA
0
Enables HPL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPL
Enable sequence.
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REGISTER
ADDRESS
R94 (5Eh)
Analogue
Lineout 0
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BIT
LABEL
DEFAULT
DESCRIPTION
3
HPR_RMV_SHO
RT
0
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
For normal operation, this bit should
be set as the final step of the HPR
Enable sequence.
2
HPR_ENA_OUTP
0
Enables HPR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
1
HPR_ENA_DLY
0
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPR_ENA.
0
HPR_ENA
0
Enables HPR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPR
Enable sequence.
7
LINEOUTL_RMV
_SHORT
0
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTL Enable sequence.
6
LINEOUTL_ENA_
OUTP
0
Enables LINEOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
5
LINEOUTL_ENA_
DLY
0
Enables LINEOUTL intermediate
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTL_ENA.
4
LINEOUTL_ENA
0
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTL Enable sequence.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
3
LINEOUTR_RMV
_SHORT
0
Removes LINEOUTR short
0 = LINEOUTR short enabled
1 = LINEOUTR short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTR Enable sequence.
2
LINEOUTR_ENA
_OUTP
0
Enables LINEOUTR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
1
LINEOUTR_ENA
_DLY
0
Enables LINEOUTR intermediate
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTR_ENA.
0
LINEOUTR_ENA
0
Enables LINEOUTR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTR Enable sequence.
Table 26 Headphone / Line Output Pop Suppression Control
OUTPUT VOLUME CONTROL
Each analogue output can be independently controlled using the registers described in Table 27 (for
Headphone outputs) and Table 28 (for Line outputs). See also the “Analogue Outputs” section for
details of these output pins, including recommended external components.
The volume and mute status of each analogue output can be controlled individually using the register
bits described in Table 27 and Table 28.
To prevent “zipper noise” when a volume adjustment is made, a zero-cross function is provided on all
output paths. When this function is enabled, volume updates will not take place until a zero-crossing
is detected. In the event of a long period without zero-crossings, a timeout will apply. The timeout
must be enabled by setting the TOCLK_ENA bit, as defined in “Clocking and Sample Rates”.
The volume update bits control the loading of the output driver volume data. For example, when
HPOUT_VU is set to 0, the headphone volume data can be loaded into the respective control
register, but will not actually change the gain setting. The Left and Right headphone volume settings
are updated when a 1 is written to HPOUT_VU. This makes it possible to update the gain of a
Left/Right pair of output paths simultaneously.
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REGISTER
ADDRESS
R57 (39h)
Analogue
OUT1 Left
R58 (3Ah)
Analogue
OUT1 Right
BIT
LABEL
DEFAULT
DESCRIPTION
8
HPOUTL_MUTE
0
Left Headphone Output Mute
0 = Un-mute
1 = Mute
7
HPOUT_VU
0
Headphone Output Volume Update
Writing a 1 to this bit will update
HPOUTL and HPOUTR volumes
simultaneously.
6
HPOUTLZC
0
Left Headphone Output Zero Cross
Enable
0 = disabled
1 = enabled
5:0
HPOUTL_VOL
[5:0]
10_1101
Left Headphone Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
8
HPOUTR_MUTE
0
Right Headphone Output Mute
0 = Un-mute
1 = Mute
7
HPOUT_VU
0
Headphone Output Volume Update
Writing a 1 to this bit will update
HPOUTL and HPOUTR volumes
simultaneously.
6
HPOUTRZC
0
Right Headphone Output Zero
Cross Enable
0 = disabled
1 = enabled
5:0
HPOUTR_VOL
[5:0]
10_1101
Right Headphone Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Table 27 Volume Control for HPOUTL and HPOUTR
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REGISTER
ADDRESS
R59 (3Bh)
Analogue
OUT2 Left
R60 (3Ch)
Analogue
OUT2 Right
BIT
LABEL
DEFAULT
DESCRIPTION
8
LINEOUTL_MUTE
0
Left Line Output Mute
0 = Un-mute
1 = Mute
7
LINEOUT_VU
0
Line Output Volume Update
Writing a 1 to this bit will update
LINEOUTL and LINEOUTR volumes
simultaneously.
6
LINEOUTLZC
0
Left Line Output Zero Cross Enable
0 = disabled
1 = enabled
5:0
LINEOUTL_VOL
[5:0]
11_1001
8
LINEOUTR_MUT
E
0
7
LINEOUT_VU
0
Line Output Volume Update
Writing a 1 to this bit will update
LINEOUTL and LINEOUTR volumes
simultaneously.
6
LINEOUTRZC
0
Right Line Output Zero Cross
Enable
0 = disabled
1 = enabled
5:0
LINEOUTR_VOL
[5:0]
11_1001
Left Line Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Right Line Output Mute
0 = Un-mute
1 = Mute
Right Line Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Table 28 Volume Control for LINEOUTL and LINEOUTR
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ANALOGUE OUTPUTS
The WM8912 has four analogue output pins:
•
Headphone outputs, HPOUTL and HPOUTR, with feedback HPOUTFB
•
Line outputs, LINEOUTL and LINEOUTR, with feedback LINEOUTFB
The output signal paths and associated control registers are illustrated in Figure 22.
HEADPHONE OUTPUTS – HPOUTL AND HPOUTR
The headphone outputs are designed to drive 16Ω or 32Ω headphones. These outputs are groundreferenced, i.e. no series capacitor is required between the pins and the headphone load. They are
powered by an on-chip charge pump (see “Charge Pump” section). Signal volume at the headphone
outputs is controlled as shown in Table 27.
The ground-referenced outputs incorporates a common mode, or ground loop, feedback path which
provides rejection of system-related ground noise. The return path for the HPOUTL and HPOUTR
outputs is via HPOUTFB. This pin must be connected to ground for normal operation of the
headphone output. No register configuration is required.
LINE OUTPUTS – LINEOUTL AND LINEOUTR
The line outputs are identical to the headphone outputs in design. They are ground-referenced and
powered by the on-chip charge pump. Signal volume at the line outputs is controlled as shown in
Table 28.
Note that these outputs are intended for driving line loads, as the charge pump powering both the
Headphone and Line outputs can only provide sufficient power to drive one set of headphones at any
given time.
The ground-referenced outputs incorporates a common mode, or ground loop, feedback path which
provides rejection of system-related ground noise. The return path for the LINEOUTL and
LINEOUTR outputs is via LINEOUTFB. This pin must be connected to ground for normal operation of
the line output. No register configuration is required.
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EXTERNAL COMPONENTS FOR GROUND REFERENCED OUTPUTS
It is recommended to connect a zobel network to the ground-referenced outputs HPOUTL, HPOUTR,
LINEOUTL and LINEOUTR in order to ensure best audio performance in all applications. The
components of the zobel network have the effect of dampening high frequency oscillations or
instabilities that can arise outside the audio band under certain conditions. Possible sources of these
instabilities include the inductive load of a headphone coil or an active load in the form of an external
line amplifier. The capacitance of lengthy cables or PCB tracks can also lead to amplifier instability.
The zobel network should comprise of a 20Ω resistor and 100nF capacitor in series with each other,
as illustrated in Figure 23.
Note that the zobel network is recommended for best audio quality and amplifier stability in all cases.
Figure 23 Zobel Network Components for HPOUTL, HPOUTR, LINEOUTL and LINEOUTR
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REFERENCE VOLTAGES AND MASTER BIAS
This section describes the analogue reference voltage and bias current controls. Note that, under the
recommended usage conditions of the WM8912, these features will be configured by scheduling the
default Start-Up and Shutdown sequences as described in the “Control Write Sequencer” section. In
these cases, the user does not need to set these register fields directly.
The analogue circuits in the WM8912 require a mid-rail analogue reference voltage, VMID. This
reference is generated from AVDD via a programmable resistor chain.
VMID is enabled by setting the VMID_ENA register bit. The programmable resistor chain is
configured by VMID_RES [1:0], and can be used to optimise the reference for normal operation, low
power standby or for fast start-up as described in Table 29. For normal operation, the VMID_RES
field should be set to 01.
The analogue circuits in the WM8912 require a bias current. The normal bias current is enabled by
setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
VMID
Control (0)
2:1
VMID_RES
[1:0]
00
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal operation)
10 = 2 x 250k divider (for low power standby)
11 = 2 x 5k divider (for fast start-up)
0
VMID_ENA
0
Enable VMID master bias current source
0 = Disabled
1 = Enabled
0
BIAS_ENA
0
Enables the Normal bias current generator
(for all analogue functions)
0 = Disabled
1 = Enabled
R4 (04h)
Bias Control
(0)
Table 29 Reference Voltages and Master Bias Enable
CHARGE PUMP
The WM8912 incorporates a dual-mode Charge Pump which generates the supply rails for the
headphone and line output drivers, HPOUTL, HPOUTR, and LINEOUTL and LINEOUTR. The
Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and
CPVOUTN according to the selected mode of operation. The Charge Pump connections are
illustrated in Figure 24 (see the “Electrical Characteristics” section for external component values).
An input decoupling capacitor may also be required at CPVDD, depending upon the system
configuration.
Figure 24 Charge Pump External Connections
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The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts
the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to
optimise the power consumption according to the operating conditions. This can take two forms,
which are selected using the CP_DYN_PWR register bit.
•
Register control (CP_DYN_PWR = 0)
•
Dynamic control (CP_DYN_PWR = 1)
Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL
register settings are used to control the charge pump mode of operation.
Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of
operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised
in real time.
Under the recommended usage conditions of the WM8912, the Charge Pump will be enabled by
running the default headphone Start-Up sequence as described in the “Control Write Sequencer”
section. (Similarly, it will be disabled by running the Shutdown sequence.) In these cases, the user
does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register
control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.
Note that the charge pump clock is derived from internal clock SYSCLK; this may derived from
MCLK directly or else using the FLL output, as determined by the SYSCLK_SRC bit. Under normal
circumstances an external clock signal must be present for the charge pump to function. However,
the FLL has a free-running mode that does not require an external clock but will generate an internal
clock suitable for running the charge pump. The clock division from SYSCLK is handled transparently
by the WM8912 without user intervention, as long as SYSCLK and sample rates are set correctly.
Refer to the “Clocking and Sample Rates” section for more detail on the FLL and clocking
configuration.
The Charge Pump control fields are described in Table 30.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R98 (62h)
Charge
Pump 0
0
CP_ENA
0
Enable charge-pump digits
0 = disable
1 = enable
R104 (68h)
Class W (0)
0
CP_DYN_PWR
0
Enable dynamic charge pump power
control
0 = Charge pump controlled by
volume register settings (Class G)
1 = Charge pump controlled by realtime audio level (Class W)
Class W is recommended for lowest
power consumption
Table 30 Charge Pump Control
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DC SERVO
The WM8912 provides four DC servo circuits, two on the headphone outputs HPOUTL and HPOUTR
and two on the line outputs LINEOUTL and LINEOUTR, to remove DC offset from these groundreferenced outputs. When enabled, the DC servos ensure that the DC level of these outputs remains
within 1mV of ground. Removal of the DC offset is important because any deviation from GND at the
output pin will cause current to flow through the load under quiescent conditions, resulting in
increased power consumption. Additionally, the presence of DC offsets can result in audible pops
and clicks at power up and power down.
The recommended usage of the DC Servo is initialised by scheduling the default Start-Up sequence
as described in the “Control Write Sequencer” section. The default Start-Up sequence executes a
series of DC offset corrections, after which the measured offset correction is maintained on the
headphone output channels. If a different usage is required, e.g. if a periodic DC offset correction is
required, then the default Start-Up sequence may be modified according to specific requirements.
The relevant control fields are described in the following paragraphs and are defined in Table 31.
DC SERVO ENABLE AND START-UP
The DC Servo circuits are enabled on HPOUTL and HPOUTR by setting DCS_ENA_CHAN_0 and
DCS_ENA_CHAN_1 respectively. Similarly, the DC Servo circuits are enabled on LINEOUTL and
LINEOUTR by setting DCS_ENA_CHAN_2 and DCS_ENA_CHAN_3 respectively When the DC
Servo is enabled, the DC offset correction can be commanded in a number of different ways,
including single-shot and periodically recurring events.
Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and
applies the necessary correction to the associated output; (‘n’ = 3 for LINEOUTR channel, 2 for
LINEOUTL channel, 1 for HPOUTR channel, 0 for HPOUTL channel). On completion, the output will
be within 1mV of AGND. This is the DC Servo mode selected by the default Start-Up sequence.
Completion of the DC offset correction triggered in this way is indicated by the
DCS_STARTUP_COMPLETE field, as described in Table 31. Typically, this operation takes 86ms
per channel.
Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value
contained in the DCS_DAC_WR_VAL_n fields in Registers R73 to R76. This mode is useful if the
required offset correction has already been determined and stored; it is faster than the
DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the
DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as
described in Table 31. Typically, this operation takes 2ms per channel.
When using either of the DC Servo options above, the status of the DC offset correction process is
indicated by the DCS_CAL_COMPLETE field; this is the logical OR of the
DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields.
The DC Servo control fields associated with start-up operation are described in Table 31. It is
important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC
Servo operation should be commanded as part of a control sequence which includes muting and
shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence.
REGISTER
ADDRESS
R68 (44h)
DC Servo 1
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BIT
LABEL
DEFAULT
DESCRIPTION
7
DCS_TRIG_STAR
TUP_3
0
Writing 1 to this bit selects Start-Up
DC Servo mode for LINEOUTR.
In readback, a value of 1 indicates
that the DC Servo Start-Up correction
is in progress.
6
DCS_TRIG_STAR
TUP_2
0
Writing 1 to this bit selects Start-Up
DC Servo mode for LINEOUTL.
In readback, a value of 1 indicates
that the DC Servo Start-Up correction
is in progress.
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REGISTER
ADDRESS
R67 (43h)
DC Servo 0
R73 (49h)
DC Servo 6
BIT
LABEL
DEFAULT
DESCRIPTION
5
DCS_TRIG_STAR
TUP_1
0
Writing 1 to this bit selects Start-Up
DC Servo mode for HPOUTR.
In readback, a value of 1 indicates
that the DC Servo Start-Up correction
is in progress.
4
DCS_TRIG_STAR
TUP_0
0
Writing 1 to this bit selects Start-Up
DC Servo mode for HPOUTL.
In readback, a value of 1 indicates
that the DC Servo Start-Up correction
is in progress.
3
DCS_TRIG_DAC_
WR_3
0
Writing 1 to this bit selects DAC Write
DC Servo mode for LINEOUTR.
In readback, a value of 1 indicates
that the DC Servo DAC Write
correction is in progress.
2
DCS_TRIG_DAC_
WR_2
0
Writing 1 to this bit selects DAC Write
DC Servo mode for LINEOUTL.
In readback, a value of 1 indicates
that the DC Servo DAC Write
correction is in progress.
1
DCS_TRIG_DAC_
WR_1
0
Writing 1 to this bit selects DAC Write
DC Servo mode for HPOUTR.
In readback, a value of 1 indicates
that the DC Servo DAC Write
correction is in progress.
0
DCS_TRIG_DAC_
WR_0
0
Writing 1 to this bit selects DAC Write
DC Servo mode for HPOUTL.
In readback, a value of 1 indicates
that the DC Servo DAC Write
correction is in progress.
3
DCS_ENA_CHAN
_3
0
DC Servo enable for LINEOUTR
0 = disabled
1 = enabled
2
DCS_ENA_CHAN
_2
0
DC Servo enable for LINEOUTL
0 = disabled
1 = enabled
1
DCS_ENA_CHAN
_1
0
DC Servo enable for HPOUTR
0 = disabled
1 = enabled
0
DCS_ENA_CHAN
_0
0
DC Servo enable for HPOUTL
0 = disabled
1 = enabled
7:0
DCS_DAC_WR_V
AL_3 [7:0]
0000 0000
DC Offset value for LINEOUTR in
DAC Write DC Servo mode in two's
complement format.
In readback, the current DC offset
value is returned in two's complement
format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R74 (4Ah)
DC Servo 7
7:0
DCS_DAC_WR_V
AL_2 [7:0]
0000 0000
DESCRIPTION
DC Offset value for LINEOUTL in
DAC Write DC Servo mode in two's
complement format.
In readback, the current DC offset
value is returned in two's complement
format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
R75 (4Bh)
DC Servo 8
7:0
DCS_DAC_WR_V
AL1 [7:0]
0000 0000
DC Offset value for HPOUTR in DAC
Write DC Servo mode in two's
complement format.
In readback, the current DC offset
value is returned in two's complement
format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
R76 (4Ch)
DC Servo 9
7:0
DCS_DAC_WR_V
AL0 [7:0]
0000 0000
DC Offset value for HPOUTL in DAC
Write DC Servo mode in two's
complement format.
In readback, the current DC offset
value is returned in two's complement
format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
R77 (4Dh)
DC Servo
Readback 0
11:8
DCS_CAL_COMP
LETE [3:0]
0000
DC Servo Complete status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = DAC Write or Start-Up DC Servo
mode not completed.
1 = DAC Write or Start-Up DC Servo
mode complete.
7:4
DCS_DAC_WR_
COMPLETE [3:0]
0000
DC Servo DAC Write status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = DAC Write DC Servo mode not
completed.
1 = DAC Write DC Servo mode
complete.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
3:0
DCS_STARTUP_
COMPLETE [3:0]
0000
DESCRIPTION
DC Servo Start-Up status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = Start-Up DC Servo mode not
completed..
1 = Start-Up DC Servo mode
complete.
Table 31 DC Servo Enable and Start-Up Modes
DC SERVO ACTIVE MODES
The DC Servo modes described above are suitable for initialising the DC offset correction circuit on
the Line and Headphone outputs as part of a controlled start-up sequence which is executed before
the signal path is fully enabled. Additional modes are available for use whilst the signal path is active;
these modes may be of benefit following a large change in signal gain, which can lead to a change in
DC offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by
changes in parameters such as device temperature.
The DC Servo circuit is enabled on HPOUTR and HPOUTL by setting DCS_ENA_CHAN_1 and
DCS_ENA_CHAN_0 respectively, as described earlier in Table 31. Similarly, the DC Servo circuit is
enabled on LINEOUTR and LINEOUTL by setting DCS_ENA_CHAN_3 and DCS_ENA_CHAN_2
respectively.
Writing a logic 1 to DCS_TRIG_SINGLE_n initiates a single DC offset measurement and adjustment
to the associated output; (‘n’ = 3 for LINEOUTR channel, 2 for LINEOUTL channel, 1 for HPOUTR
channel, 0 for HPOUTL channel). This will adjust the DC offset correction on the selected channel by
no more than 1LSB (0.25mV).
Setting DCS_TIMER_PERIOD_01 or DCS_TIMER_PERIOD_23 to a non-zero value will cause a
single DC offset measurement and adjustment to be scheduled on a periodic basis. Periodic rates
ranging from every 0.52s to in excess of 2 hours can be selected.
Writing a logic 1 to DCS_TRIG_SERIES_n initiates a series of DC offset measurements and applies
the necessary correction to the associated output. The number of DC Servo operations performed is
determined by DCS_SERIES_NO_01 or DCS_SERIES_NO_23. A maximum of 128 operations may
be selected, though a much lower value will be sufficient in most applications.
The DC Servo control fields associated with active modes (suitable for use on a signal path that is in
active use) are described in Table 32.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R68 (44h)
DC Servo 1
15
DCS_TRIG_SING
LE_3
0
Writing 1 to this bit selects a single DC
offset correction for LINEOUTR.
In readback, a value of 1 indicates that
the DC Servo single correction is in
progress.
14
DCS_TRIG_SING
LE_2
0
Writing 1 to this bit selects a single DC
offset correction for LINEOUTL.
In readback, a value of 1 indicates that
the DC Servo single correction is in
progress.
13
DCS_TRIG_SING
LE_1
0
Writing 1 to this bit selects a single DC
offset correction for HPOUTR.
In readback, a value of 1 indicates that
the DC Servo single correction is in
progress.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
12
DCS_TRIG_SING
LE_0
0
Writing 1 to this bit selects a single DC
offset correction for HPOUTL.
In readback, a value of 1 indicates that
the DC Servo single correction is in
progress.
11
DCS_TRIG_SERI
ES_3
0
Writing 1 to this bit selects a series of
DC offset corrections for LINEOUTR.
In readback, a value of 1 indicates that
the DC Servo DAC Write correction is
in progress.
10
DCS_TRIG_SERI
ES_2
0
Writing 1 to this bit selects a series of
DC offset corrections for LINEOUTL.
In readback, a value of 1 indicates that
the DC Servo DAC Write correction is
in progress.
9
DCS_TRIG_SERI
ES_1
0
Writing 1 to this bit selects a series of
DC offset corrections for HPOUTR.
In readback, a value of 1 indicates that
the DC Servo DAC Write correction is
in progress.
8
DCS_TRIG_SERI
ES_0
0
Writing 1 to this bit selects a series of
DC offset corrections for HPOUTL.
In readback, a value of 1 indicates that
the DC Servo DAC Write correction is
in progress.
6:0
DCS_SERIES_N
O_23 [6:0]
010_1010
Number of DC Servo updates to
perform in a series event for
LINEOUTL/LINEOUTR.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
R72 (48h)
DC Servo 5
6:0
DCS_SERIES_N
O_01 [6:0]
010 1010
Number of DC Servo updates to
perform in a series event for
HPOUTL/HPOUTR.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
R69 (45h)
DC Servo 2
11:8
DCS_TIMER_PE
RIOD_23 [3:0]
1010
Time between periodic updates for
LINEOUTL/LINEOUTR. Time is
calculated as 0.256s x (2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
3:0
DCS_TIMER_PE
RIOD_01 [3:0]
1010
Time between periodic updates for
HPOUTL/HPOUTR. Time is calculated
as 0.256s x (2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
R71 (47h)
DC Servo 4
Table 32 DC Servo Active Modes
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DC SERVO READBACK
The current DC offset value for each Line and Headphone output channel can be read in two’s
complement format from the DCS_DAC_WR_VAL_n [7:0] bit fields in Registers R73, R74, R75 and
R76. Note that these values may form the basis of settings that are subsequently used by the DC
Servo in DAC Write mode.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data to the WM8912. The digital audio interface
uses three pins:
•
DACDAT: DAC data input
•
LRCLK: Left/Right data alignment clock
•
BCLK: Bit clock, for synchronisation
The clock signals BCLK and LRCLK can be outputs when the WM8912 operates as a master, or
inputs when it is a slave (see “Master and Slave Mode Operation”, below).
Four different audio data formats are supported:
•
Left justified
•
Right justified
•
I2S
•
DSP mode
All four of these modes are MSB first. They are described in “Audio Data Formats (Normal Mode)”,
below. Refer to the “Signal Timing Requirements” section for timing information.
Time Division Multiplexing (TDM) is available in all four data format modes. The WM8912 can be
programmed to receive data in one of two time slots.
PCM operation is supported using the DSP mode.
MASTER AND SLAVE MODE OPERATION
The WM8912 digital audio interface can operate in master or slave mode, as shown in Figure 25 and
Figure 26.
Figure 25 Master Mode
Figure 26 Slave Mode
In master mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV.
In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE.
The BCLK input to this divider may be internal or external, allowing mixed master and slave modes.
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The direction of these signals and the clock frequencies are controlled as described in the “Digital
Audio Interface Control” section.
BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation
- see “Digital Audio Interface Control”.
OPERATION WITH TDM
Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same
bus. The WM8912 supports TDM in master and slave modes for all data formats and word lengths.
TDM is enabled and configured using register bits defined in the “Digital Audio Interface Control”
section.
Figure 27 TDM with WM8912 as Master
Figure 28 TDM with other DAC as Master
Figure 29 TDM with Processor as Master
Note: The WM8912 is a 24-bit device. If the user operates the WM8912 in 32-bit mode then the 8
LSBs will be ignored on the DAC input. It is recommended to add a pull-down resistor to the
DACDAT line in TDM mode in this case.
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BCLK FREQUENCY
The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide
and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable
and repeatable position relative to each other and relative to the data for a given combination of DAC
sample rate and BCLK_DIV settings.
BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample
Rates” section for more information.
AUDIO DATA FORMATS (NORMAL MODE)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 30 Right Justified Audio Interface (assuming n-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 31 Left Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
1 BCLK
DACDAT
1
MSB
2
1 BCLK
3
n-2
Input Word Length (WL)
n-1
n
1
2
3
n-2
n-1
n
LSB
Figure 32 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 33 and Figure
34. In device slave mode, Figure 35 and Figure 36, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
Figure 33 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 34 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
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Figure 35 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
Figure 36 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)
PCM operation is supported in DSP interface mode. Mono PCM data received by the WM8912 will
be treated as Left Channel data. This data may be routed to the Left/Right DACs as described in the
“Digital Mixing” section.
AUDIO DATA FORMATS (TDM MODE)
TDM is supported in master and slave mode and is enabled by the AIFDAC_TDM register bit. All
audio interface data formats support time division multiplexing (TDM) for DAC data.
Two time slots are available (Slot 0 and Slot 1), selected by the AIFDAC_TDM_CHAN register bit.
When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to
be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as
shown in Figure 37 to Figure 41.
Figure 37 TDM in Right-Justified Mode
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Figure 38 TDM in Left-Justified Mode
Figure 39 TDM in I2S Mode
1/fs
LRCLK
Falling edge can occur anywhere in this area
1 BCLK
1 BCLK
BCLK
DACDAT
SLOT 0 LEFT
SLOT 0 RIGHT
SLOT 1 LEFT
SLOT 1 RIGHT
Figure 40 TDM in DSP Mode A
Figure 41 TDM in DSP Mode B
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DIGITAL AUDIO INTERFACE CONTROL
The register bits controlling audio data format, word length, left/right channel data source and TDM
are summarised in Table 33.
REGISTER
ADDRESS
R24 (18h)
Audio
Interface 0
R25 (19h)
Audio
Interface 1
BIT
LABEL
DEFAULT
DESCRIPTION
5
AIFDACL_SR
C
0
Left DAC Data Source Select
0 = Left DAC outputs left channel data
1 = Left DAC outputs right channel data
4
AIFDACR_SR
C
1
Right DAC Data Source Select
0 = Right DAC outputs left channel data
1 = Right DAC outputs right channel data
13
AIFDAC_TDM
0
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
12
AIFDAC_TDM
_CHAN
0
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
7
AIF_BCLK_IN
V
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
4
AIF_LRCLK_I
NV
0
LRC Polarity / DSP Mode A-B select.
Right, left and I2S modes – LRC polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
3:2
AIF_WL [1:0]
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
1:0
AIF_FMT [1:0]
10
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Table 33 Digital Audio Interface Data Control
AUDIO INTERFACE OUTPUT TRI-STATE
Register bit AIF_TRIS can be used to tri-state the audio interface pins as described in Table 34. All
digital audio interface pins will be tri-stated by this function, regardless of the state of other registers
which control these pin configurations.
REGISTER
ADDRESS
R25 (19h)
Audio
Interface 1
BIT
LABEL
DEFAULT
8
AIF_TRIS
0
DESCRIPTION
Audio Interface Tristate
0 = Audio interface pins operate normally
1 = Tristate all audio interface pins
Table 34 Digital Audio Interface Tri-State Control
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BCLK AND LRCLK CONTROL
The audio interface can be programmed to operate in master mode or slave mode using the
BCLK_DIR and LRCLK_DIR register bits. In master mode, the BCLK and LRCLK signals are
generated by the WM8912 when either of the DACs is enabled. In slave mode, the BCLK and
LRCLK clock outputs are disabled by default to allow another digital audio interface to drive these
pins.
It is also possible to force the BCLK or LRCLK signals to be output using BCLK_DIR and
LRCLK_DIR, allowing mixed master and slave modes. The BCLK_DIR and LRCLK_DIR fields are
defined in Table 35.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
Audio
Interface 1
6
BCLK_DIR
0
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
R26 (1Ah)
Audio
Interface 2
4:0
BCLK_DIV
[4:0]
0_0100
BCLK Frequency (Master Mode)
00000 = SYSCLK
00001 = SYSCLK / 1.5
00010 = SYSCLK / 2
00011 = SYSCLK / 3
00100 = SYSCLK / 4
00101 = SYSCLK / 5
00110 = SYSCLK / 5.5
00111 = SYSCLK / 6
01000 = SYSCLK / 8 (default)
01001 = SYSCLK / 10
01010 = SYSCLK / 11
01011 = SYSCLK / 12
01100 = SYSCLK / 16
01101 = SYSCLK / 20
01110 = SYSCLK / 22
01111 = SYSCLK / 24
10000 = SYSCLK / 25
10001 = SYSCLK / 30
10010 = SYSCLK / 32
10011 = SYSCLK / 44
10100 = SYSCLK / 48
R27 (1Bh)
Audio
Interface 3
11
LRCLK_DIR
0
10:0
LRCLK_RATE
[10:0]
000_0100
_0000
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
LRC Rate (Master Mode)
LRC clock output = BCLK / LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
Table 35 Digital Audio Interface Clock Control
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COMPANDING
The WM8912 supports A-law and μ-law companding on the digital receive (DAC) path as shown in
Table 36.
REGISTER
ADDRESS
R24 (18h)
Audio
Interface 0
BIT
LABEL
DEFAULT
DESCRIPTION
1
DAC_COMP
0
DAC Companding Enable
0 = disabled
1 = enabled
0
DAC_COMPMODE
0
DAC Companding Type
0 = μ-law
1 = A-law
Table 36 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
μ-law (where μ=255 for the U.S. and Japan):
F(x) = ln( 1 + μ|x|) / ln( 1 + μ)
-1 ≤ x ≤ 1
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA)
1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of
data.
Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
8-bit mode is selected whenever DAC_COMP=1. The use of 8-bit data allows samples to be passed
using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B, 8-bit data words may
be transferred consecutively every 8 BCLK cycles.
8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 when
DAC_COMP=0.
BIT7
BIT [6:4]
BIT [3:0]
SIGN
EXPONENT
MANTISSA
Table 37 8-bit Companded Word Composition
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u-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalised Input
Figure 42 μ-Law Companding
A-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.2
0.4
0.6
0.8
1
Normalised Input
Figure 43 A-Law Companding
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DIGITAL PULL-UP AND PULL-DOWN
The WM8912 provides integrated pull-up and pull-down resistors on each of the MCLK, DACDAT,
LRCLK and BCLK pins. This provides a flexible capability for interfacing with other devices. Each of
the pull-up and pull-down resistors can be configured independently using the register bits described
in Table 38.
REGISTER
ADDRESS
R126 (7Eh)
Digital Pulls
BIT
LABEL
DEFAULT
DESCRIPTION
7
MCLK_PU
0
MCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
6
MCLK_PD
0
MCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
5
DACDAT_PU
0
DACDAT pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
4
DACDAT_PD
0
DACDAT pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
3
LRCLK_PU
0
LRCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
2
LRCLK_PD
0
LRCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
1
BCLK_PU
0
BCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
0
BCLK_PD
0
BCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
Table 38 Digital Audio Interface Pull-Up and Pull-Down Control
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CLOCKING AND SAMPLE RATES
The internal clocks for the WM8912 are all derived from a common internal clock source, SYSCLK.
This clock is the reference for the DACs, DSP core functions, digital audio interface, DC servo
control and other internal functions.
SYSCLK can either be derived directly from MCLK, or may be generated from a Frequency Locked
Loop (FLL) using MCLK, BCLK or LRCLK as a reference. Many commonly-used audio sample rates
can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a
wide range of MCLK frequencies. To avoid audible glitches, all clock configurations must be set up
before enabling playback. The FLL can be used to generate a free-running clock in the absence of
an external reference source; see “Frequency Locked Loop” for further details.
The WM8912 supports automatic clocking configuration. The programmable dividers associated with
the DACs, DSP core functions and DC servo are configured automatically, with values determined
from the CLK_SYS_RATE and SAMPLE_RATE fields. The user must also configure the OPCLK (if
required), the TOCLK (if required) and the Digital Audio Interface.
Oversample rates of 64fs or 128fs are supported (based on a 48kHz sample rate).
A 256kHz clock, supporting a number of internal functions, is derived from SYSCLK.
The DC servo control is clocked from SYSCLK.
A GPIO Clock, OPCLK, can be derived from SYSCLK and output on a GPIO pin to provide clocking
to other devices. This clock is enabled by OPCLK_ENA and controlled by OPCLK_DIV.
A slow clock, TOCLK, is used to de-bounce the button/accessory detect inputs, and to set the
timeout period for volume updates when zero-cross detect is used. This clock is enabled by
TOCLK_ENA and controlled by TOCLK_RATE, TOCLK_RATE_X4 and TOCLK_RATE_DIV16.
In master mode, BCLK is derived from SYSCLK via a programmable divider set by BCLK_DIV. In
master mode, the LRCLK is derived from BCLK via a programmable divider LRCLK_RATE. The
LRCLK can be derived from an internal or external BCLK source, allowing mixed master/slave
operation.
The control registers associated with Clocking and Sample Rates are shown in Table 39 to Table 43.
The overall clocking scheme for the WM8912 is illustrated in Figure 44.
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Figure 44 Clocking Scheme
SYSCLK CONTROL
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the
selected MCLK source or the FLL output. The MCLK source can be inverted or non-inverted, as
selected by the MCLK_INV bit. The selected source may also be adjusted by the MCLK_DIV divider
to generate SYSCLK. These register fields are described in Table 39. See “Frequency Locked Loop
(FLL)” for more details of the Frequency Locked Loop clock generator.
The SYSCLK signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when
reconfiguring clock sources. It is not recommended to change SYSCLK_SRC while the
CLK_SYS_ENA bit is set.
The following operating frequency limits must be observed when configuring SYSCLK. Failure to
observe these limits will result in degraded noise performance and/or incorrect DAC functionality.

SYSCLK ≥ 3MHz

If DAC_OSR128 = 1 then SYSCLK ≥ 6MHz

If DAC_MONO = 1, then SYSCLK ≥ 64 x fs

If DAC_MONO = 0, then SYSCLK ≥ 128 x fs
Note that DAC Mono mode (DAC_MONO = 1) is only valid when one or other DAC is disabled. If
both DACs are enabled, then the minimum SYSCLK for clocking the DACs is 128 x fs.
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The SYSCLK control register fields are defined in Table 39.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R22 (16h)
Clock Rates
2
15
MCLK_INV
0
MCLK Invert
0 = MCLK not inverted
1 = MCLK inverted
14
SYSCLK_SRC
0
SYSCLK Source Select
0 = MCLK
1 = FLL output
2
CLK_SYS_ENA
0
System Clock enable
0 = Disabled
1 = Enabled
0
MCLK_DIV
0
Enables divide by 2 on MCLK
0 = SYSCLK = MCLK
1 = SYSCLK = MCLK / 2
R20 (14h)
Clock Rates
0
DESCRIPTION
Table 39 MCLK and SYSCLK Control
CONTROL INTERFACE CLOCKING
Register map access is possible with or without a Master Clock (MCLK). However, if CLK_SYS_ENA
has been set to 1, then a Master Clock must be present for control register Read/Write operations. If
CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. (Note that
read/write access to register R22, containing CLK_SYS_ENA, is always possible.)
If it cannot be assured that MCLK is present when accessing the register map, then it is required to
set CLK_SYS_ENA = 0 to ensure correct operation.
Note that MCLK is always required when using HPOUTL, HPOUTR, LINEOUTL or LINEOUTR.
CLOCKING CONFIGURATION
The WM8912 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The
Automatic Clocking Configuration simplifies the configuration of the clock dividers in the WM8912 by
deriving most of the required parameters from a minimum number of user registers.
The SAMPLE_RATE field selects the sample rate, fs, of the DAC.
The CLK_SYS_RATE fields must be set according to the ratio of SYSCLK to fs. When these fields
are set correctly, the Sample Rate Decoder circuit automatically determines the clocking
configuration for all other circuits within the WM8912.
A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit; in
48kHz sample mode, the DAC_OSR128 feature results in 128x oversampling. Audio performance is
improved, but power consumption is also increased.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R33 (21h)
DAC Digital
1
6
DAC_OSR128
0
R21 (15h)
Clock Rates
1
13:10
CLK_SYS_RAT
E [3:0]
0011
Selects the SYSCLK / fs ratio
0000 = 64
0001 = 128
0010 = 192
0011 = 256
0100 = 384
0101 = 512
0110 = 768
0111 = 1024
1000 = 1408
1001 = 1536
2:0
SAMPLE_RATE
[2:0]
101
Selects the Sample Rate (fs)
000 = 8kHz
001 = 11.025kHz, 12kHz
010 = 16kHz
011 = 22.05kHz, 24kHz
100 = 32kHz
101 = 44.1kHz, 48kHz
110 to 111 = Reserved
DAC Oversample Rate Select
0 = Low power (normal OSR)
1 = High performance (double OSR)
Table 40 Automatic Clocking Configuration Control
DAC CLOCK CONTROL
The clocking of the DAC circuits is derived from CLK_DSP, which is enabled by CLK_DSP_ENA.
CLK_DSP is generated from SYSCLK which is separately enabled, using the register bit
CLK_SYS_ENA.
Note that higher performance DAC operation can be achieved by increasing the DAC oversample
rate - see Table 40.
REGISTER
ADDRESS
R22 (16h)
Clock Rates 2
BIT
LABEL
DEFAULT
1
CLK_DSP_ENA
0
DESCRIPTION
DSP Clock enable
0 = Disabled
1 = Enabled
Table 41 ADC / DAC Clock Control
OPCLK CONTROL
A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled
by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.
This output of this clock is also dependent upon the GPIO register settings described under “General
Purpose Input/Output (GPIO)”.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R22 (16h)
Clock Rates 2
3
OPCLK_ENA
0
GPIO Clock Output Enable
0 = disabled
1 = enabled
11:8
OPCLK_DIV [3:0]
0000
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
R26 (1Ah)
Audio
Interface 2
DESCRIPTION
Table 42 OPCLK Control
TOCLK CONTROL
A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input debouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,
and its frequency is controlled by TOCLK_RATE and TOCLK_RATE_X4, as described in Table 43.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R22 (16h)
Clock Rates 2
12
TOCLK_RATE
0
TOCLK Rate Divider (/2)
0=f/2
1=f/1
0
TOCLK_ENA
0
Zero Cross timeout enable
0 = Disabled
1 = Enabled
14
TOCLK_RATE_
DIV16
0
TOCLK Rate Divider (/16)
0=f/1
1 = f / 16
13
TOCLK_RATE_
X4
0
TOCLK Rate Multiplier
0=fx1
1=fx4
R20 (14h)
Clock Rates 0
DESCRIPTION
Table 43 TOCLK Control
A list of possible TOCLK rates is provided in Table 44.
TOCLK
TOCLK_RATE
TOCLK_RATE_X4
TOCLK_RATE_DIV16
FREQ
(Hz)
PERIOD
(ms)
1
1
0
1000
1
0
1
0
500
2
1
0
0
250
4
0
0
0
125
8
1
1
1
62.5
16
0
1
1
31.25
32
1
0
1
15.625
64
0
0
1
7.8125
128
Table 44 TOCLK Rates
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DAC OPERATION AT 88.2K / 96K
The WM8912 supports DAC operation at 88.2kHz and 96kHz sample rates. This section details
specific conditions applicable to these operating modes.
For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 45. DAC operation at these sample rates is achieved by setting the
SAMPLE_RATE field to half the required sample rate (eg. select 48kHz for 96kHz mode).
For DAC operation at 88.2kHz or 96kHz sample rates, the DAC_OSR128 register must be set to 0.
TM
ReTune Mobile can not be used during 88.2kHz or 96kHz operation, so EQ_ENA must be set to 0.
The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the
“Signal Timing Requirements” section.
SAMPLE RATE
REGISTER CONFIGURATION
CLOCKING RATIO
88.2kHz
SAMPLE_RATE = 101
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
SYSCLK = 128 x fs
96kHz
SAMPLE_RATE = 101
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
SYSCLK = 128 x fs
Table 45 DAC Operation at 88.2kHz and 96kHz Sample Rates
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FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference
sources and frequencies. The FLL can use either MCLK, BCLK or LRCLK as its reference, which
may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is
tolerant of jitter and may be used to generate a stable SYSCLK from a less stable input signal. The
FLL characteristics are summarised in “Electrical Characteristics”.
Note that the FLL can be used to generate a free-running clock in the absence of an external
reference source. This is described in the “Free-Running FLL Clock” section below.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency FREF, it is
recommended the FLL be reset by setting FLL_ENA to 0.
The FLL_CLK_REF_SRC field allows MCLK, BCLK or LRCLK to be selected as the input reference
clock.
The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK, BCLK or
LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For
best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only
the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should
be set to the recommended value quoted in Table 48.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRACN_ENA.
It is recommended that FLL_FRACN_ENA is enabled at all times. Power consumption in the FLL is
reduced in integer mode; however, the performance may also be reduced, with increased noise or
jitter on the output.
If low power consumption is required, then FLL settings must be chosen when N.K is an integer (ie.
FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRACN_ENA = 0.
For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode
must be enabled by setting FLL_FRACN_ENA = 1. The FLL settings must be adjusted, if necessary,
to produce a non-integer value of N.K.
The FLL output frequency is generated according to the following equation:
FOUT = (FVCO / FLL_OUTDIV)
The FLL operating frequency, FVCO is set according to the following equation:
FVCO = (FREF x N.K x FLL_FRATIO)
See Table 48 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
FREF is the input frequency, as determined by FLL_CLK_REF_DIV.
FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.
Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed
across the full range of device operating temperatures.
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In order to follow the above requirements for FVCO, the value of FLL_OUTDIV should be selected
according to the desired output FOUT. The divider, FLL_OUTDIV, must be set so that FVCO is in the
range 90-100MHz. The available divisions are integers from 4 to 64. Some typical settings of
FLL_OUTDIV are noted in Table 46.
OUTPUT FREQUENCY FOUT
FLL_OUTDIV
2.8125 MHz - 3.125 MHz
011111 (divide by 32)
3.75 MHz - 4.1667 MHz
011000 (divide by 24)
5.625 MHz - 6.25 MHz
001111 (divide by 16)
11.25 MHz - 12.5 MHz
000111 (divide by 8)
18 MHz - 20 MHz
000100 (divide by 5)
22.5 MHz - 25 MHz
000011 (divide by 4)
Table 46 Selection of FLL_OUTDIV
The value of FLL_FRATIO should be selected as described in Table 47.
REFERENCE FREQUENCY FREF
1MHz - 13.5MHz
FLL_FRATIO
0h (divide by 1)
256kHz - 1MHz
1h (divide by 2)
128kHz - 256kHz
2h (divide by 4)
64kHz - 128kHz
3h (divide by 8)
Less than 64kHz
4h (divide by 16)
Table 47 Selection of FLL_FRATIO
In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be
calculated, as given by the following equation:
FVCO = (FOUT x FLL_OUTDIV)
The value of FLL_N and FLL_K can then be determined as follows:
N.K = FVCO / (FLL_FRATIO x FREF)
See Table 48 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable.
In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.
This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if
desired, the value of this field may be calculated by multiplying K by 216 and treating FLL_K as an
integer value, as illustrated in the following example:
If N.K = 8.192, then K = 0.192
Multiplying K by 216 gives 0.192 x 65536 = 12582.912 (decimal)
Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)
For best performance, FLL Fractional Mode should always be used. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order to obtain a
non-integer value of N.K. Care must always be taken to ensure that the FLL operating frequency,
FVCO, is within its recommended limits of 90-100 MHz.
The register fields that control the FLL are described in Table 48. Example settings for a variety of
reference frequencies and output frequencies are shown in Table 50.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R116 (74h)
FLL Control 1
2
FLL_FRACN_E
NA
0
DESCRIPTION
FLL Fractional enable
0 = Integer Mode
1 = Fractional Mode
Fractional Mode
(FLL_FRACN_ENA=1) is
recommended in all cases
1
FLL_OSC_ENA
0
FLL Oscillator enable
0 = Disabled
1 = Enabled
FLL_OSC_ENA must be enabled
before enabling FLL_ENA.
Note that this field is required for freerunning FLL modes only.
0
FLL_ENA
0
FLL Enable
0 = Disabled
1 = Enabled
FLL_OSC_ENA must be enabled
before enabling FLL_ENA.
R117 (75h)
FLL Control 2
13:8
FLL_OUTDIV
[5:0]
00_0000
6:4
FLL_CTRL_RAT
E [2:0]
000
FLL FOUT clock divider
00_0000 = Reserved
00_0001 = Reserved
00_0010 = Reserved
00_0011 = 4
00_0100 = 5
00_0101 = 6
…
11_1110 = 63
11_1111 = 64
(FOUT = FVCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = FVCO / 1 (Recommended
value)
001 = FVCO / 2
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that these are not
changed from default.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
2:0
FLL_FRATIO
[2:0]
111
DESCRIPTION
FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
R118 (76h)
FLL Control 3
15:0
FLL_K [15:0]
0000h
Fractional multiply for FREF
(MSB = 0.5)
R119 (77h)
FLL Control 4
14:5
FLL_N [9:0]
177h
Integer multiply for FREF
(LSB = 1)
3:0
FLL_GAIN [3:0]
0h
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not
changed from default.
R120 (78h)
FLL Control 5
4:3
FLL_CLK_REF_
DIV [1:0]
00
FLL Clock Reference Divider
00 = MCLK / 1
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must
be divided down to <=13.5MHz.
For lower power operation, the
reference clock can be divided down
further if desired.
1:0
FLL_CLK_REF_
SRC [1:0]
00
FLL Clock source
00 = MCLK
01 = BCLK
10 = LRCLK
11 = Reserved
Table 48 FLL Register Map
FREE-RUNNING FLL CLOCK
The FLL can generate a clock signal even when no external reference is available. However, it
should be noted that the accuracy of this clock is reduced, and a reference source should always be
used where possible. Note that, in free-running mode, the FLL is not sufficiently accurate for hi-fi
DAC applications. However, the free-running mode is suitable for clocking most other functions,
including the Write Sequencer, Charge Pump, DC Servo and Class W output driver.
If an accurate reference clock is available at FLL start-up, then the FLL should be configured as
described above. The FLL will continue to generate a stable output clock after the reference input is
stopped or disconnected.
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If no reference clock is available at the time of starting up the FLL, then an internal clock frequency
of approximately 12MHz can be generated by enabling the FLL Analogue Oscillator using the
FLL_OSC_ENA register bit, and setting FOUT clock divider to divide by 8 (FLL_OUTDIV = 07h), as
defined in Table 48. Under recommended operating conditions, the FLL output may be forced to
approximately 12MHz by then enabling the FLL_FRC_NCO bit and setting FLL_FRC_NCO_VAL to
19h (see Table 49). The resultant SYSCLK delivers the required clock frequencies for the Class W
output driver, DC Servo, Charge Pump and other functions. Note that the value of
FLL_FRC_NCO_VAL may be adjusted to control FOUT, but care should be taken to maintain the
correct relationship between SYSCLK and the aforementioned functional blocks.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R248 (F8h)
FLL NCO Test 1
5:0
FLL_FRC_NCO
_VAL [5:0]
01_1001
FLL Forced oscillator value
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for
free-running FLL modes only)
R247 (F7h)
FLL NCO Test 0
0
FLL_FRC_NCO
0
FLL Forced control select
0 = Normal
1 = FLL oscillator controlled by
FLL_FRC_NCO_VAL
(Note that this field is required for
free-running FLL modes only)
Table 49 FLL Free-Running Mode
In both cases described above, the FLL must be selected as the SYSCLK source by setting
SYSCLK_SRC (see Table 39). Note that, in the absence of any reference clock, the FLL output is
subject to a very wide tolerance. See “Electrical Characteristics” for details of the FLL accuracy.
EXAMPLE FLL CALCULATION
To generate 12.288 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):
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•
Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:
FLL_CLK_REF_DIV = 00 (divide by 1)
•
Set FLL_CTRL_RATE to the recommended setting:
FLL_CTRL_RATE = 000 (divide by 1)
•
Sett FLL_GAIN to the recommended setting:
FLL_GAIN = 0000 (multiply by 1)
•
Set FLL_OUTDIV for the required output frequency as shown in Table 46:FOUT = 12.288 MHz, therefore FLL_OUTDIV = 07h (divide by 8)
•
Set FLL_FRATIO for the given reference frequency as shown in Table 47:
FREF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)
•
Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:FVCO = 12.288 x 8 = 98.304MHz
•
Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):
N.K = 98.304 / (1 x 12) = 8.192
•
Determine FLL_N and FLL_K from the integer and fractional portions of N.K:FLL_N is 8. FLL_K is 0.192
•
Confirm that N.K is a fractional quantity and set FLL_FRACN_ENA:
N.K is fractional. Set FLL_FRACN_ENA = 1.
Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be
selected in order to produce a fractional value of N.K.
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GPIO OUTPUTS FROM FLL
The WM8912 has an internal signal which indicates whether the FLL Lock has been achieved. The
FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt
event - see “Interrupts”.
The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See
“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL
Lock signal.
The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the
FLL Clock may be output even if the FLL is not selected as the WM8912 SYSCLK source. The
clocking configuration is illustrated in Figure 44. See “General Purpose Input/Output (GPIO)” for
details of how to configure a GPIO pin to output the FLL Clock.
EXAMPLE FLL SETTINGS
Table 50 provides example FLL settings for generating common SYSCLK frequencies from a variety
of low and high frequency reference inputs.
FREF
FOUT
FLL_CLK_
REF_DIV
FVCO
FLL_N
FLL_K
FLL_
FRATIO
FLL_
OUTDIV
FLL_
FRACN
_ENA
32.768
kHz
12.288
MHz
Divide by 1
(0h)
98.304
MHz
187
(0BBh)
0.5
(8000h)
16
(4h)
8
(7h)
1
32.768
kHz
11.288576
MHz
Divide by 1
(0h)
90.308608
MHz
344
(158h)
0.5
(8000h)
8
(3h)
8
(7h)
1
32.768
kHz
11.2896
MHz
Divide by 1
(0h)
90.3168
MHz
344
(158h)
0.53125
(8800h)
8
(3h)
8
(7h)
1
48
kHz
12.288
MHz
Divide by 1
(0h)
98.304
MHz
256
(100h)
0
(0000h)
8
(3h)
8
(7h)
0
12.000
MHz
12.288
MHz
Divide by 1
(0h)
98.3040
MHz
8
(008h)
0.192
(3127h)
1
(0h)
8
(7h)
1
12.000
MHz
11.289597
MHz
Divide by 1
(0h)
90.3168
MHz
7
(007h)
0.526398
(86C2h)
1
(0h)
8
(7h)
1
12.288
MHz
12.288
MHz
Divide by 1
(0h)
98.304
MHz
8
(008h)
0
(0000h)
1
(0h)
8
(7h)
0
12.288
MHz
11.2896
MHz
Divide by 1
(0h)
90.3168
MHz
7
(007h)
0.35
(599Ah)
1
(0h)
8
(7h)
1
13.000
MHz
12.287990
MHz
Divide by 1
(0h)
98.3040
MHz
7
(007h)
0.56184
(8FD5h)
1
(0h)
8
(7h)
1
13.000
MHz
11.289606
MHz
Divide by 1
(0h)
90.3168
MHz
6
(006h)
0.94745
(F28Ch)
1
(0h)
8
(7h)
1
19.200
MHz
12.287988
MHz
Divide by 2
(1h)
98.3039
MHz
5
(005h)
0.119995
(1EB8h)
1
(0h)
8
(7h)
1
19.200
MHz
11.289588
MHz
Divide by 2
(1h)
90.3168
MHz
4
(004h)
0.703995
(B439h)
1
(0h)
8
(7h)
1
Table 50 Example FLL Settings
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GENERAL PURPOSE INPUT/OUTPUT (GPIO)
The WM8912 provides two multi-function pins which can be configured to provide a number of
different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins
are:
•
IRQ/GPIO1
•
BCLK/GPIO4
Each general purpose I/O pin can be configured to be a GPIO input or configured as one of a
number of output functions. Signal de-bouncing can be selected on GPIO input pins for use with
jack/button detect applications. Table 51 lists the functions that are available on each of the GPIO
pins.
GPIO PIN FUNCTION
GPIO PINS
IRQ / GPIO1
BCLK / GPIO4
GPIO input
(including jack/button detect)
Yes
Yes
GPIO output
Yes
Yes
BCLK
No
Yes
Interrupt (IRQ)
Yes
Yes
FLL Lock output
Yes
Yes
FLL Clock output
Yes
Yes
Table 51 GPIO Functions
IRQ/GPIO1
The IRQ/GPIO1 pin is configured using the register bits described in Table 52. By default, this pin is
IRQ output with pull-down resistor enabled.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R121 (79h)
GPIO
Control 1
5
GPIO1_PU
0
GPIO1 pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
4
GPIO1_PD
1
GPIO1 pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
3:0
GPIO1_SEL [3:0]
0100
GPIO1 Function Select
0000 = GPIO input
0001 = Clock output
(f=SYSCLK/OPCLKDIV)
0010 = Logic '0' output
0011 = Logic '1' output
0100 = IRQ output (default)
0101 = FLL Lock output
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = FLL Clock output
1010 to 1111 = Reserved
Table 52 IRQ/GPIO1 Control
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BCLK/GPIO4
The BCLK/GPIO4 pin is configured using the register bits described in Table 53. By default, this pin
provides the BCLK function associated with the Digital Audio Interface. The BCLK function can
operate in slave mode (BCLK input) or in master mode (BCLK output), depending on the BCLK_DIR
register bit as described in the “Digital Audio Interface” section.
It is possible to configure the BCLK/GPIO4 pin to provide various GPIO functions; in this case, the
BCLK function is provided using the MCLK pin. Note that the BCLK function is always in slave mode
(BCLK input) in this mode.
To select the GPIO4 functions, it is required to set BCLK_DIR = 0 (see Table 35) and to set
GPIO_BCLK_MODE_ENA = 1 (see Table 53 below). In this configuration, the MCLK input is used as
the bit-clock (BCLK) for the Digital Audio Interface.
When the BCLK/GPIO4 pin is configured as GPIO4, then the pin function is determined by the
GPIO_BCLK_SEL register field.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R124 (7Ch)
GPIO
7
GPIO_BCLK_MODE_
ENA
0
Selects BCLK/GPIO4 pin function
0 = BCLK/GPIO4 is used as BCLK
1 = BCLK/GPIO4 is used as GPIO.
MCLK provides the BCLK in the AIF
in this mode.
3:0
GPIO_BCLK_SEL
[3:0]
0000
Control 4
BCLK/GPIO4 function select:
0000 = GPIO input (default)
0001 = Clock output
(f=SYSCLK/OPCLKDIV)
0010 = Logic '0' output
0011 = Logic '1' output
0100 = IRQ output
0101 = FLL Lock output
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = FLL Clock output
1010 to 1111 = Reserved
Table 53 BCLK/GPIO4 Control
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INTERRUPTS
The Interrupt Controller has multiple inputs; these include the GPIO input pins and other internal
signals. Any combination of these inputs can be used to trigger an Interrupt Output (IRQ) event.
WM8912 interrupt events may be triggered in response to external GPIO inputs, FLL Lock status or
Write Sequencer status. Note that the GPIO inputs are only supported as interrupt events when the
respective pin is configured as a GPIO input.
There is an Interrupt Status field associated with each of the IRQ inputs. These are contained in the
Interrupt Status Register (R127), as described in Table 54. The status of the IRQ inputs can be read
from this register at any time, or in response to the Interrupt Output being signalled via a GPIO pin.
Individual mask bits can select or deselect different functions from the Interrupt controller. These are
listed within the Interrupt Status Mask register (R128), as described in Table 54. Note that the
Interrupt Status fields remain valid, even when masked, but the masked bits will not cause the
Interrupt (IRQ) output to be asserted.
The Interrupt (IRQ) output represents the logical ‘OR’ of all unmasked IRQ inputs. The bits within the
Interrupt Status register (R127) are latching fields and, once set, are not reset until a ‘1’ is written to
the respective register bit in the Interrupt Status Register. The Interrupt (IRQ) output is not reset until
each of the unmasked IRQ inputs has been reset.
Each of the IRQ inputs can be individually inverted in the Interrupt function, enabling either active
high or active low behaviour on each IRQ input. The polarity inversion is controlled using the bits
contained in the Interrupt Polarity register (R129).
Each of the IRQ inputs can be debounced to ensure that spikes and transient glitches do not assert
the Interrupt Output. This is selected using the bits contained in the Interrupt Debounce Register
(R130).
The WM8912 Interrupt Controller circuit is illustrated in Figure 45. The associated control fields are
described in Table 54.
Figure 45 Interrupt Controller
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R127 (7Fh)
Interrupt
Status
10
IRQ
0
Logical OR of all other interrupt
flags
9
GPIO_BCLK_EINT
0
GPIO4 interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
8
WSEQ_EINT
0
Write Sequence interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written.
Note that the read value of
WSEQ_EINT is not valid whilst
the Write Sequencer is Busy
5
GPIO1_EINT
0
GPIO1 interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
2
FLL_LOCK_EINT
0
FLL Lock interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
9
IM_GPIO_BCLK_EI
NT
1
GPIO4 interrupt mask
0 = do not mask interrupt
1 = mask interrupt
8
IM_WSEQ_EINT
1
Write sequencer interrupt mask
0 = do not mask interrupt
1 = mask interrupt
5
IM_GPIO1_EINT
1
GPIO1 interrupt mask
0 = do not mask interrupt
1 = mask interrupt
2
IM_FLL_LOCK_EIN
T
1
FLL Lock interrupt mask
0 = do not mask interrupt
1 = mask interrupt
9
GPIO_BCLK_EINT_
POL
0
GPIO4 interrupt polarity
0 = active high
1 = active low
8
WSEQ_EINT_POL
0
Write Sequencer interrupt polarity
0 = active high (interrupt is
triggered when WSEQ is busy)
1 = active low (interrupt is
triggered when WSEQ is idle)
5
GPIO1_EINT_POL
0
GPIO1 interrupt polarity
0 = active high
1 = active low
2
FLL_LOCK_EINT_P
OL
0
FLL Lock interrupt polarity
0 = active high (interrupt is
triggered when FLL Lock is
reached)
1 = active low (interrupt is
triggered when FLL is not locked)
9
GPIO_BCLK_EINT_
DB
0
GPIO4 interrupt debounce
0 = disabled
1 = enabled
R128 (80h)
Interrupt
Status Mask
R129 (81h)
Interrupt
Polarity
R130 (82h)
Interrupt
Debounce
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8
WSEQ_EINT_DB
0
Write Sequencer interrupt
debounce enable
0 = disabled
1 = enabled
5
GPIO1_EINT_DB
0
GPIO1 input debounce
0 = disabled
1 = enabled
2
FLL_LOCK_EINT_D
B
0
FLL Lock debounce
0 = disabled
1 = enabled
Table 54 Interrupt Control
CONTROL INTERFACE
The WM8912 is controlled by writing to registers through a 2-wire serial control interface. Readback
is available for all registers, including Chip ID, power management status and GPIO status.
Note that, if it cannot be assured that MCLK is present when accessing the register map, then it is
required to set CLK_SYS_ENA = 0 to ensure correct operation. See “Clocking and Sample Rates”
for details of CLK_SYS_ENA.
The WM8912 is a slave device on the control interface; SCLK is a clock input, while SDA is a bidirectional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same
interface, the WM8912 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An
external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by
the master.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 8-bit device ID (this is not the same as the 8-bit address of each register in the WM8912).
The WM8912 device ID is 0011 0100 (34h). The LSB of the device ID is the Read/Write bit; this bit is
set to logic 1 for “Read” and logic 0 for “Write”.
The WM8912 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDA while SCLK remains high. This indicates that a device ID, register
address and data will follow. The WM8912 responds to the start condition and shifts in the next eight
bits on SDA (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches
the device ID of the WM8912, then the WM8912 responds by pulling SDA low on the next clock
pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only
mode, the WM8912 returns to the idle condition and waits for a new start condition and valid
address.
If the device ID matches the device ID of the WM8912, the data transfer continues as described
below. The controller indicates the end of data transfer with a low to high transition on SDA while
SCLK remains high. After receiving a complete address and data sequence the WM8912 returns to
the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns
to the idle condition.
The WM8912 supports the following read and write operations:
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•
•
•
Single write
Single read
Multiple write using auto-increment
•
Multiple read using auto-increment
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The sequence of signals associated with a single register write operation is illustrated in Figure 46.
Figure 46 Control Interface Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 47.
SCLK
SDA
D7
START
D1
device ID
R/W
(Write)
A7
ACK
A1
A0
register address
D6
ACK
Rpt
START
D0
device ID
R/W
B15
(Read)
ACK
B9
B8
data bits B15 – B8
B7
ACK
B1
data bits B15 – B8
B0
ACK
STOP
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
Figure 47 Control Interface Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 55.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM8912
register map faster than is possible with single register operations.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
¯A¯
Not Acknowledge (SDA High)
P
R/W
¯¯
Stop Condition
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM8912
[Grey field]
Data flow from WM8912 to bus master
Table 55 Control Interface Terminology
Figure 48 Single Register Write to Specified Address
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Figure 49 Single Register Read from Specified Address
Figure 50 Multiple Register Write to Specified Address using Auto-increment
Figure 51 Multiple Register Read from Specified Address using Auto-increment
Figure 52 Multiple Register Read from Last Address using Auto-increment
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CONTROL WRITE SEQUENCER
The Control Write Sequencer is a programmable unit that forms part of the WM8912 control interface
logic. It provides the ability to perform a sequence of register write operations with the minimum of
demands on the host processor - the sequence may be initiated by a single operation from the host
processor and then left to execute independently.
Default sequences for Start-Up and Shutdown are provided (see “Default Sequences” section). It is
recommended that these default sequences are used unless changes become necessary.
When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The
host processor informs the sequencer of the start index of the required sequence within the
sequencer’s memory. At each step of the sequence, the contents of the selected register fields are
read from the sequencer’s memory and copied into the WM8912 control registers. This continues
sequentially through the sequencer’s memory until an “End of Sequence” bit is encountered; at this
point, the sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the
write sequence is important, a programmable delay can be set for specific steps within the sequence.
Note that the Control Write Sequencer’s internal clock is derived from the internal clock SYSCLK. An
external MCLK signal must be present when using the Control Write Sequencer, and SYSCLK must
be enabled by setting CLK_SYS_ENA (see “Clocking and Sample Rates”). The clock division from
MCLK is handled transparently by the WM8912 without user intervention, as long as MCLK and
sample rates are set correctly.
INITIATING A SEQUENCE
The Register fields associated with running the Control Write Sequencer are described in Table 56.
The Write Sequencer Clock is enabled by setting the WSEQ_ENA bit. Note that the operation of the
Control Write Sequencer also requires the internal clock SYSCLK to be enabled via the
CLK_SYS_ENA (see “Clocking and Sample Rates”).
The start index of the required sequence must be written to the WSEQ_START_INDEX field. Setting
the WSEQ_START bit initiates the sequencer at the given start index.
The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.
The current status of the Write Sequencer can be read using two further register fields - when the
WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the
Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal
read/write operations to the Control Registers cannot be supported. (The Write Sequencer registers
and the Software Reset register can still be accessed when the Sequencer is busy.) The index of the
current step in the Write Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an
indicator of the sequencer’s progress. On completion of a sequence, this field holds the index of the
last step within the last commanded sequence.
When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_EINT flag in
Register R127 (see Table 54 within the “Interrupts” section). This flag can be used to generate an
Interrupt Event on completion of the sequence. Note that the WSEQ_EINT flag is asserted to
indicate that the Write Sequencer is NOT Busy.
REGISTER
ADDRESS
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BIT
LABEL
DEFAULT
DESCRIPTION
R108 (6Ch)
Write
Sequencer 0
8
WSEQ_ENA
0
Write Sequencer Enable.
0 = Disabled
1 = Enabled
R111 (6Fh)
Write
Sequencer 3
9
WSEQ_ABORT
0
Writing a 1 to this bit aborts the
current sequence and returns
control of the device back to the
serial control interface.
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REGISTER
ADDRESS
R112 (70h)
Write
Sequencer 4
BIT
LABEL
DEFAULT
DESCRIPTION
8
WSEQ_START
0
Writing a 1 to this bit starts the write
sequencer at the memory location
indicated by the
WSEQ_START_INDEX field. The
sequence continues until it reaches
an “End of sequence” flag. At the
end of the sequence, this bit will be
reset by the Write Sequencer.
5:0
WSEQ_START_
INDEX [5:0]
00_0000
Sequence Start Index. This is the
memory location of the first
command in the selected sequence.
0 to 31 = RAM addresses
32 to 48 = ROM addresses
49 to 63 = Reserved
9:4
WSEQ_CURRE
NT_INDEX [5:0]
00_0000
Sequence Current Index (read only):
This is the location of the most
recently accessed command in the
write sequencer memory.
0
WSEQ_BUSY
0
Sequencer Busy flag (read only):
0 = Sequencer idle
1 = Sequencer busy
Note: it is not possible to write to
control registers via the control
interface while the Sequencer is
Busy.
Table 56 Write Sequencer Control - Initiating a Sequence
PROGRAMMING A SEQUENCE
A sequence consists of write operations to data bits (or groups of bits) within the control registers.
The register fields associated with programming the Control Write Sequencer are described in Table
57.
For each step of the sequence being programmed, the Sequencer Index must be written to the
WSEQ_WRITE_INDEX field. The values 0 to 31 correspond to all the available RAM addresses
within the Write Sequencer memory. (Note that memory addresses 32 to 48 also exist, but these are
ROM addresses, which are not programmable.)
Having set the Index as described above, Register R109 must be written to (containing the Control
Register Address, the Start Bit Position and the Field Width applicable to this step of the sequence).
Also, Register R110 must be written to (containing the Register Data, the End of Sequence flag and
the Delay time required after this step is executed). After writing to these two registers, the next step
in the sequence may be programmed by updating WSEQ_WRITE_INDEX and repeating the
procedure.
WSEQ_ADDR is an 8-bit field containing the Control Register Address in which the data should be
written.
WSEQ_DATA_START is a 4-bit field which identifies the LSB position within the selected Control
Register to which the data should be written. Setting WSEQ_DATA_START = 0100 will cause 1-bit
data to be written to bit 4. With this setting, 4-bit data would be written to bits 7:4 and so on.
WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This
enables selected portions of a Control Register to be updated without any concern for other bits
within the same register, eliminating the need for read-modify-write procedures. Values of 0 to 7
correspond to data widths of 1 to 8 respectively. For example, setting WSEQ_DATA_WIDTH = 010
will cause a 3-bit data block to be written. Note that the maximum value of this field corresponds to
an 8-bit data block; writing to register fields greater than 8 bits wide must be performed using two
separate operations of the Control Write Sequencer.
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WSEQ_DATA is an 8-bit field which contains the data to be written to the selected Control Register.
The WSEQ_DATA_WIDTH field determines how many of these bits are written to the selected
register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTH) are
ignored.
WSEQ_DELAY is a 4-bit field which controls the waiting time between the current step and the next
step in the sequence. The total delay time per step (including execution) is given by:
T = k × (2
WSEQ_DELAY
+ 8)
where k = 62.5μs (under recommended operating conditions)
This gives a useful range of execution/delay times from 562μs up to 2.048s per step.
WSEQ_EOS is a 1-bit field which indicates the End of Sequence. If this bit is set, then the Control
Write Sequencer will automatically stop after this step has been executed.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R108 (6Ch)
Write
Sequencer
0
4:0
WSEQ_WRITE_
INDEX [4:0]
0_0000
Sequence Write Index. This is the
memory location to which any updates
to R109 and R110 will be copied.
0 to 31 = RAM addresses
R109 (6Dh)
Write
Sequencer
1
14:12
WSEQ_DATA_
WIDTH [2:0]
000
Width of the data block written in this
sequence step.
000 = 1 bit
001 = 2 bits
010 = 3 bits
011 = 4 bits
100 = 5 bits
101 = 6 bits
110 = 7 bits
111 = 8 bits
11:8
WSEQ_DATA_
START [3:0]
0000
Bit position of the LSB of the data
block written in this sequence step.
0000 = Bit 0
…
1111 = Bit 15
7:0
WSEQ_ADDR
[7:0]
0000_000
0
Control Register Address to be written
to in this sequence step.
14
WSEQ_EOS
0
End of Sequence flag. This bit
indicates whether the Control Write
Sequencer should stop after executing
this step.
0 = Not end of sequence
1 = End of sequence (Stop the
sequencer after this step).
11:8
WSEQ_DELAY
[3:0]
0000
7:0
WSEQ_DATA
[7:0]
0000_000
0
R110 (6Eh)
Write
Sequencer
2
Time delay after executing this step.
Total delay time per step (including
execution)=
62.5μs × (2^WSEQ_DELAY + 8)
Data to be written in this sequence
step. When the data width is less than
8 bits, then one or more of the MSBs
of WSEQ_DATA are ignored. It is
recommended that unused bits be set
to 0.
Table 57 Write Sequencer Control - Programming a Sequence
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Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to
write a value of 0 to bit 0 of Register R255 (FFh). This is effectively a write to a non-existent register
location. This can be used in order to create placeholders ready for easy adaptation of the sequence.
For example, a sequence could be defined to power-up a mono signal path from DACL to
headphone, with a ‘dummy’ write included to leave space for easy modification to a stereo signal
path configuration. Dummy writes can also be used in order to implement additional time delays
between register writes. Dummy writes are included in the default start-up sequence – see Table 59.
In summary, the Control Register to be written is set by the WSEQ_ADDR field. The data bits that
are written are determined by a combination of WSEQ_DATA_START, WSEQ_DATA_WIDTH and
WSEQ_DATA. This is illustrated below for an example case of writing to the VMID_RES field within
Register R5 (05h).
Figure 53 Control Write Sequencer Example
In this example, the Start Position is bit 01 (WSEQ_DATA_START = 0001b) and the Data width is 2
bits (WSEQ_DATA_WIDTH = 0001b). With these settings, the Control Write Sequencer would
updated the Control Register R5 [2:1] with the contents of WSEQ_DATA [1:0].
DEFAULT SEQUENCES
When the WM8912 is powered up, two Control Write Sequences are available through default
settings in both RAM and ROM memory locations. The purpose of these sequences, and the register
write required to initiate them, is summarised in Table 58. A single register write will initiate the
sequence in both cases.
WSEQ START
INDEX
WSEQ FINISH
INDEX
PURPOSE
TO INITIATE
0 (00h)
22 (16h)
Start-Up sequence
Write 0100h to
Register R111 (6Fh)
25 (19h)
39 (27h)
Shutdown sequence
Write 0119h to
Register R111 (6Fh)
Table 58 Write Sequencer Default Sequences
Note on Shutdown sequence: The instruction at Index Address 25 (19h) shorts the outputs
LINEOUTL and LINEOUTR. If the Line outputs are not in use at the time the sequence is run, then
the sequence could, instead, be started at Index Address 26.
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Index addresses 0 to 24 may be programmed to users’ own settings at any time, as described in
“Programming a Sequence”. Users’ own settings remain in memory and are not affected by software
resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is
powered down.
START-UP SEQUENCE
The Start-up sequence is initiated by writing 0100h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in
Table 59.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately
300ms to run.
Note that, for fast startup, step 18 may be overwritten with dummy data in order to achieve startup
within 50ms (see “Quick Start-Up and Shutdown”).
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
0 (00h)
R4 (04h)
5 bits
Bit 0
1Ah
0h
0b
BIAS_ENA = 0
(delay = 0.5625ms)
1 (01h)
R5 (05h)
8 bits
Bit 0
47h
6h
0b
VMID_RES [1:0] = 11b
VMID_ENA = 1
(delay = 4.5ms)
2 (02h)
R5 (05h)
2 bits
Bit 1
01h
0h
0b
VMID_RES [1:0] = 01b
(delay = 0.5625ms)
3 (03h)
R4 (04h)
1 bit
Bit 0
01h
0h
0b
BIAS_ENA = 1
(delay = 0.5625ms)
4 (04h)
R14 (0Eh)
2 bits
Bit 0
03h
0h
0b
HPL_PGA_ENA = 1
HPR_PGA_ENA = 1
(delay = 0.5625ms)
5 (05h)
R15 (0Fh)
2 bits
Bit 0
03h
0h
0b
LINEOUTL_PGA_ENA = 1
LINEOUTR_PGA_ENA = 1
(delay = 0.5625ms)
6 (06h)
R22 (16h)
1 bit
Bit 1
01h
0h
0b
CLK_DSP_ENA = 1
(delay = 0.5625ms)
7 (07h)
R18 (12h)
2 bits
Bit 2
03h
5h
0b
DACL_ENA = 1
DACR_ENA = 1
(delay = 2.5ms)
8 (08h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5625ms)
9 (09h)
R4 (04h)
1 bit
Bit 4
00h
0h
0b
(delay = 0.5625ms)
10 (0Ah)
R98 (62h)
1 bit
Bit 0
01h
6h
0b
CP_ENA = 1
(delay = 4.5ms)
11 (0Bh)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5625ms)
12 (0Ch)
R90 (5Ah)
8 bits
Bit 0
11h
0h
0b
HPL_ENA = 1
HPR_ENA = 1
(delay = 0.5625ms)
13 (0Dh)
R94 (5Eh)
8 bits
Bit 0
11h
0h
0b
LINEOUTL_ENA = 1
LINEOUTR_ENA = 1
(delay = 0.5625ms)
14 (0Eh)
R90 (5Ah)
8 bits
Bit 0
33h
0h
0b
HPL_ENA_DLY = 1
HPR_ENA_DLY = 1
(delay = 0.5625ms)
15 (0Fh)
R94 (5Eh)
8 bits
Bit 0
33h
0h
0b
LINEOUTL_ENA_DLY = 1
LINEOUTR_ENA_DLY = 1
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WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
16 (10h)
R67 (43h)
4 bits
Bit 0
0Fh
Ch
0b
DCS_ENA_CHAN_0 = 1
DCS_ENA_CHAN_1 = 1
DCS_ENA_CHAN_2 = 1
DCS_ENA_CHAN_3 = 1
(delay = 0.5625ms)
17 (11h)
R68 (44h)
8 bits
Bit 0
F0h
0h
0b
DCS_TRIG_STARTUP_0 = 1
DCS_TRIG_STARTUP_1 = 1
DCS_TRIG_STARTUP_2 = 1
DCS_TRIG_STARTUP_3 = 1
(delay = 256.5ms)
18 (12h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5625ms)
19 (13h)
R90 (5Ah)
8 bits
Bit 0
77h
0h
0b
HPL_ENA_OUTP = 1
HPR_ENA_OUTP = 1
(delay = 0.5625ms)
20 (14h)
R94 (5Eh)
8 bits
Bit 0
77h
0h
0b
LINEOUTL_ENA_OUTP = 1
LINEOUTR_ENA_OUTP = 1
(delay = 0.5625ms)
21 (15h)
R90 (5Ah)
8 bits
Bit 0
FFh
0h
0b
HPL_RMV_SHORT = 1
HPR_RMV_SHORT = 1
(delay = 0.5625ms)
22 (16h)
R94 (5Eh)
8 bits
Bit 0
FFh
0h
1b
LINEOUTL_RMV_SHORT = 1
LINEOUTR_RMV_SHORT = 1
End of Sequence
23 (17h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Spare
24 (18h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Spare
(delay = 0.5625ms)
Table 59 Start-up Sequence
SHUTDOWN SEQUENCE
The Shutdown sequence is initiated by writing 0119h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in
Table 60.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately
350ms to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
25 (19h)
R94 (5Eh)
8 bits
Bit 0
77h
0h
0b
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
(delay = 0.5625ms)
26 (1Ah)
R90 (5Ah)
8 bits
Bit 0
77h
0h
0b
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
(delay = 0.5625ms)
27 (1Bh)
R90 (5Ah)
8 bits
Bit 0
00h
0h
0b
HPL_ENA_OUTP = 0
HPL_ENA_DLY = 0
HPL_ENA = 0
HPR_ENA_OUTP = 0
HPR_ENA_DLY = 0
HPR_ENA = 0
(delay = 0.5625ms)
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WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
28 (1Ch)
R94 (5Eh)
8 bits
Bit 0
00h
0h
0b
LINEOUTL_ENA_OUTP = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA = 0
LINEOUTR_ENA_OUTP = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA = 0
(delay = 0.5625ms)
29 (1Dh)
R67 (43h)
4 bits
Bit 0
00h
0h
0b
DCS_ENA_CHAN_0 = 0
DCS_ENA_CHAN_1 = 0
DCS_ENA_CHAN_2 = 0
DCS_ENA_CHAN_3 = 0
(delay = 0.5625ms)
30 (1Eh)
R98 (62h)
1 bit
Bit 0
00h
0h
0b
CP_ENA = 0
(delay = 0.5625ms)
31 (1Fh)
R18 (12h)
2 bits
Bit 2
00h
0h
0b
DACL_ENA = 0
DACR_ENA = 0
(delay = 0.5625ms)
32 (20h)
R22 (16h)
1 bit
Bit 1
00h
0h
0b
CLK_DSP_ENA = 0
(delay = 0.5625ms)
33 (21h)
R14 (0Eh)
2 bits
Bit 0
00h
0h
0b
HPL_PGA_ENA = 0
HPR_PGA_ENA = 0
(delay = 0.5625ms)
34 (22h)
R15 (0Fh)
2 bits
Bit 0
00h
0h
0b
LINEOUTL_PGA_ENA = 0
LINEOUTR_PGA_ENA = 0
(delay = 0.5625ms)
35 (23h)
R4 (04h)
1 bit
Bit 0
00h
0h
0b
BIAS_ENA = 0
(delay = 0.5625ms)
36 (24h)
R5 (05h)
1 bit
Bit 0
00h
Ch
0b
VMID_ENA = 0
(delay = 256.5ms)
37 (25h)
R5 (05h)
1 bit
Bit 0
00h
9h
0b
VMID_ENA = 0
(delay = 32.5ms)
38 (26h)
R5 (05h)
8 bits
Bit 0
00h
0h
0b
VMID_RES [1:0] = 00
VMID_ENA = 0
(delay = 0.5625ms)
39 (27h)
R4 (04h)
2 bits
Bit 0
00h
0h
1b
BIAS_ENA = 0
End of Sequence
Table 60 Shutdown Sequence
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POWER-ON RESET
The WM8912 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital
logic into a default state after power up. The POR circuit is powered from AVDD and monitors
DCVDD. The internal POR
¯ ¯ ¯ signal is asserted low when AVDD and DCVDD are below minimum
thresholds.
The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 54 and Figure 55.
AVDD
Vpora
Vpora_off
0V
DCVDD
Vpord_on
0V
HI
Internal POR
LO
POR active
Device ready
POR active
POR undefined
Figure 54 Power On Reset Timing - AVDD Enabled First
Figure 55 Power On Reset Timing - DCVDD Enabled First
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The POR
¯ ¯ ¯ signal is undefined until AVDD has exceeded the minimum threshold, Vpora Once this
threshold has been exceeded, POR
¯ ¯ ¯ is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once AVDD and DCVDD have reached their respective
power on thresholds, POR
¯ ¯ ¯ is released high, all registers are in their default state, and writes to the
control interface may take place.
Note that a minimum power-on reset period, TPOR, applies even if AVDD and DCVDD have zero rise
time. (This specification is guaranteed by design rather than test.)
On power down, POR
¯ ¯ ¯ is asserted low when any of AVDD or DCVDD falls below their respective
power-down thresholds.
Typical Power-On Reset parameters for the WM8912 are defined in Table 61.
SYMBOL
TYP
UNIT
AVDD threshold below which POR is undefined
0.25
V
Vpora_on
Power-On threshold (AVDD)
1.15
V
Vpora_off
Power-Off threshold (AVDD)
1.12
V
Vpord_on
Power-On threshold (DCVDD)
0.57
V
Power-Off threshold (DCVDD)
0.55
V
Minimum Power-On Reset period
9.5
μs
Vpora
Vpord_off
TPOR
DESCRIPTION
Table 61 Typical Power-On Reset Parameters
Notes:
1.
If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below Vpora_off or Vpord_off) then the chip does not reset and resumes normal
operation when the voltage is back to the recommended level again.
2.
The chip enters reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This
may be important if the supply is turned on and off frequently by a power management system.
3.
The minimum Tpor period is maintained even if DCVDD and AVDD have zero rise time. This
specification is guaranteed by design rather than test.
QUICK START-UP AND SHUTDOWN
The WM8912 has the capability to perform a quick start-up and shutdown with a minimum number of
register operations. This is achieved using the Control Write Sequencer, which is configured with
default start-up settings that set up the device for DAC playback via Headphone and Line output.
Assuming a 12.288MHz external clock, the start-up sequence configures the device for 48kHz
playback mode.
The default start-up sequence requires three register write operations. The default shutdown
sequence requires just a single register write. The minimum procedure for executing the quick startup and shutdown sequences is described below. See “Control Write Sequencer” for more details.
After the default start-up sequence has been performed, the DC offset correction values will be held
in memory, provided that power is maintained and a software reset is not performed. Fast start-up
using the stored values of DC offset correction is also possible, as described below.
QUICK START-UP (DEFAULT SEQUENCE)
An external clock must be applied to MCLK. Assuming 12.288MHz input clock, the start-up sequence
will take approximately 300ms to complete.
The following register operations will initiate the quick start-up sequence.
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WM8912
Production Data
REGISTER
ADDRESS
VALUE
DESCRIPTION
R108 (6Ch)
Write Sequencer 0
0100h
WSEQ_ENA = 1
WSEQ_WRITE_INDEX = 0_0000
R111 (6Fh)
Write Sequencer 3
0100h
WSEQ_ABORT = 0
WSEQ_START = 1
WSEQ_START_INDEX = 0_0000
R33 (21h)
DAC Digital 1
0000h
DAC_MONO = 0
DAC_SB_FILT = 0
DAC_MUTERATE = 0
DAC_UNMUTE_RAMP = 0
DAC_OSR128 = 0
DAC_MUTE = 0
DEEMPH = 00
Table 62 Quick Start-up Control
The WSEQ_BUSY bit (in Register R112, see Table 56) will be set to 1 while the sequence runs.
When this bit returns to 0, the device has been set up and is ready for DAC playback operation.
FAST START-UP FROM STANDBY
The default start-up sequence runs the DC Servo to remove DC offsets from the outputs. The offset
for this path selection is then stored in memory. Provided that power is maintained to the chip, and a
software reset is not performed, then the DC offset correction will be held in memory on the
WM8912. This allows the DC Servo calibrations to be omitted from the start-up sequence if the offset
correction has already been performed. By omitting this part of the start-up sequence, a fast start-up
time of less than 50ms can be achieved.
The register write sequence described in Table 63 replaces the default DC Servo operation with
dummy operations, allowing a fast start-up to be achieved, assuming the device is initially in a
standby condition with DC offset correction previously performed.
Note that, if power is removed from the WM8912 or if a software reset is performed, then the default
sequence will be restored, and the DC offset correction will be necessary on the output paths once
more.
REGISTER
ADDRESS
VALUE
DESCRIPTION
R108 (6Ch)
Write Sequencer 0
0111h
WSEQ_ENA = 1
WSEQ_WRITE_INDEX = 1_0001
R109 (6Dh)
Write Sequencer 1
00FFh
WSEQ_DATA_WIDTH = 000
WSEQ_DATA_START = 0000
WSEQ_ADDR = 1111_1111
R110 (6Eh)
Write Sequencer 2
0000h
WSEQ_EOS = 0
WSEQ_DELAY = 0000
WSEQ_DATA = 0000_0000
R111 (6Fh)
Write Sequencer 3
0100h
WSEQ_ABORT = 0
WSEQ_START = 1
WSEQ_START_INDEX = 00_0000
R33 (21h)
DAC Digital 1
0000h
DAC_MONO = 0
DAC_SB_FILT = 0
DAC_MUTERATE = 0
DAC_UNMUTE_RAMP = 0
DAC_OSR128 = 0
DAC_MUTE = 0
DEEMPH = 00
Table 63 Fast Start-up from Standby Control
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WM8912
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The WSEQ_BUSY bit (in Register R112, see Table 56) will be set to 1 while the sequence runs.
When this bit returns to 0, the device has been set up and is ready for DAC playback operation.
QUICK SHUTDOWN (DEFAULT SEQUENCE)
The default shutdown sequences assumes the initial device conditions are as configured by the
default start-up sequence. Assuming 12.288MHz input clock, the shutdown sequence will take
approximately 350ms to complete.
The following register operation will initiate the default shutdown sequence.
REGISTER
ADDRESS
VALUE
R111 (6Fh)
Write Sequencer 3
0119h
DESCRIPTION
WSEQ_ABORT = 0
WSEQ_START = 1
WSEQ_START_INDEX = 19h
Table 64 Quick Shutdown Control
The WSEQ_BUSY bit (in Register R112, see Table 56) will be set to 1 while the sequence runs.
When this bit returns to 0, the system clock can be disabled (CLK_SYS_ENA=0) and MCLK can be
stopped.
SOFTWARE RESET AND CHIP ID
A Software Reset can be commanded by writing to Register R0. This is a read-only register field and
the contents will not be affected by writing to this Register.
The Chip ID can be read back from Register R0.
REGISTER
ADDRESS
R0 (00h)
SW Reset
and ID
BIT
LABEL
DEFAULT
DESCRIPTION
15:0
SW_RST_DE
V_ID1 [15:0]
8904h
Writing to this register resets all
registers to their default state.
Reading from this register will indicate
Device ID 8904h.
Table 65 Software Reset and Chip ID
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PD, Rev 4.0, September 2010
93
w
43
44
45
47
48
68
69
71
72
39
57
3C
2B
43
67
2A
42
60
29
41
3A
28
40
3B
21
33
58
1F
31
59
1E
18
24
30
16
22
1B
15
21
27
14
20
19
12
18
1A
0F
15
26
0E
14
25
04
05
5
00
0
4
Hex Addr
Dec Addr
Name
DC Servo 5
DC Servo 4
DC Servo 2
DC Servo 1
DC Servo 0
Analogue OUT2 Right
Analogue OUT2 Left
Analogue OUT1 Right
Analogue OUT1 Left
DRC 3
DRC 2
DRC 1
DRC 0
DAC Digital 1
DAC Digital Volume Right
DAC Digital Volume Left
Audio Interface 3
Audio Interface 2
Audio Interface 1
Audio Interface 0
Clock Rates 2
Clock Rates 1
Clock Rates 0
Power Management 6
Power Management 3
Power Management 2
VMID Control 0
Bias Control 0
SW Reset and ID
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIFDAC_TDM
DRC_ATK[3:0]
DRC_DAC_PATH
0
0
0
0
0
0
0
SYSCLK_SRC
0
TOCLK_RATE_DI TOCLK_RATE_X
V16
4
0
0
0
0
0
14
1
0
0
0
0
0
11
DAC_SB_FILT
0
0
LRCLK_DIR
0
DACR_DATINV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_GS_HYST_LVL[1:0]
DAC_MONO
0
0
0
0
AIFDAC_TDM_CHAN
DACL_DATINV
TOCLK_RATE
CLK_SYS_RATE[3:0]
0
0
0
0
0
0
12
8
0
0
0
0
0
0
0
0
0
0
DRC_DCY[3:0]
0
0
0
0
0
0
0
DAC_VU
DAC_VU
AIF_TRIS
0
0
0
0
0
0
0
0
LINEOUTR_MUTE
LINEOUTL_MUTE
HPOUTR_MUTE
HPOUTL_MUTE
DAC_OSR128
1
BCLK_DIR
1
0
0
1
0
0
0
0
0
6
0
0
LINEOUT_VU
LINEOUT_VU
HPOUT_VU
HPOUT_VU
0
LINEOUTRZC
LINEOUTLZC
HPOUTRZC
HPOUTLZC
0
DRC_QR_THR[1:0]
0
1
DRC_KNEE_IP[5:0]
0
0
0
AIF_BCLK_INV
DRC_STARTUP_GAIN[4:0]
DAC_MUTERAT DAC_UNMUTE_
E
RAMP
0
0
OPCLK_DIV[3:0]
0
0
0
0
0
0
0
DAC_BOOST[1:0]
0
7
SW_RST_DEV_ID1[15:0]
0
0
0
0
0
0
0
0
9
0
0
1
0
0
0
0
0
10
0
0
0
0
DRC_QR
DRC_GS_HYST
DRC_MAXGAIN[1:0]
DRC_ANTICLIP
DRC_LO_COMP[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DCS_TIMER_PERIOD_23[3:0]
0
0
0
0
0
0
0
0
1010_1010_1010_1010
1010_1010_1010_1010
DCS_SERIES_NO_01[6:0]
1010_1010_1010_1010
DCS_SERIES_NO_23[6:0]
DCS_TIMER_PERIOD_01[3:0]
PPPP_PPPP_PPPP_PPPP
0000_0000_0000_0000
0000_0000_P011_1001
LINEOUTR_VOL[5:0]
DCS_ENA_CHAN DCS_ENA_CHAN DCS_ENA_CHAN DCS_ENA_CHAN
_3
_2
_1
_0
0000_0000_P010_1101
0000_0000_P011_1001
HPOUTR_VOL[5:0]
LINEOUTL_VOL[5:0]
0000_0000_P010_1101
0000_0000_0000_0000
0000_0000_0000_0000
0011_0010_0100_1000
0000_0001_1010_1111
0000_0000_0000_1000
HPOUTL_VOL[5:0]
DRC_KNEE_OP[4:0]
DRC_MINGAIN[1:0]
DRC_GS_ENA
DAC_MUTE
0000_000P_1100_0000
0
0000_0000_0100_0000
0000_0000_1110_0100
0000_0000_0000_1010
0000_0000_0000_0000
0000_0000_0101_0000
DAC_COMPMOD
E
0000_1100_0000_0101
1000_1100_0101_1110
0000_0000_0000_0000
TOCLK_ENA
MCLK_DIV
AIF_FMT[1:0]
DAC_COMP
CLK_DSP_ENA
SAMPLE_RATE[2:0]
1
0
DACR_VOL[7:0]
DRC_HI_COMP[2:0]
0
0000_0000_0001_1000
0000_0000_0000_0000
0000_0000_0000_0000
DEEMPH[1:0]
BCLK_DIV[4:0]
AIF_WL[1:0]
0
CLK_SYS_ENA
1
Bin Default
1000_1001_0000_0100
0000_0000_0000_0000
VMID_ENA
BIAS_ENA
0
HPR_PGA_ENA
HPL_PGA_ENA
0
1
LINEOUTL_PGA_ LINEOUTR_PGA
ENA
_ENA
VMID_RES[1:0]
DACR_ENA
0
0
0
2
0000_000P_1100_0000
0
OPCLK_ENA
0
1
DACL_ENA
0
0
0
1
3
DACL_VOL[7:0]
AIF_LRCLK_INV
AIFDACR_SRC
0
0
1
0
0
0
0
1
4
DRC_QR_DCY[1:0]
DRC_FF_DELAY
0
LRCLK_RATE[10:0]
1
0
AIFDACL_SRC
0
0
0
0
0
0
0
0
5
DCS_TRIG_SING DCS_TRIG_SING DCS_TRIG_SING DCS_TRIG_SING DCS_TRIG_SERI DCS_TRIG_SERI DCS_TRIG_SERI DCS_TRIG_SERI DCS_TRIG_STA DCS_TRIG_STA DCS_TRIG_STA DCS_TRIG_STA DCS_TRIG_DAC DCS_TRIG_DAC DCS_TRIG_DAC DCS_TRIG_DAC
LE_3
LE_2
LE_1
LE_0
ES_3
ES_2
ES_1
ES_0
RTUP_3
RTUP_2
RTUP_1
RTUP_0
_WR_3
_WR_2
_WR_1
_WR_0
0
0
0
0
0
0
0
DRC_ENA
0
0
0
0
0
0
0
MCLK_INV
0
1
0
0
0
0
0
15
WM8912
Production Data
REGISTER MAP
PD, Rev 4.0, September 2010
94
w
80
81
82
86
129
130
134
78
120
128
77
119
7F
76
7E
75
117
118
127
74
116
126
70
112
79
6F
111
7C
6E
110
124
6D
109
121
6C
5E
94
108
Charge Pump 0
5A
90
62
4D
77
68
4C
76
98
4B
75
104
Analogue Lineout 0
4A
74
Name
49
73
EQ1
Interrupt Debounce
Interrupt Polarity
Interrupt Status Mask
Interrupt Status
Digital Pulls
GPIO Control 4
GPIO Control 1
FLL Control 5
FLL Control 4
FLL Control 3
FLL Control 2
FLL Control 1
Write Sequencer 4
Write Sequencer 3
Write Sequencer 2
Write Sequencer 1
Write Sequencer 0
Class W 0
Analogue HP 0
DC Servo Readback 0
DC Servo 9
DC Servo 8
DC Servo 7
DC Servo 6
Hex Addr
Dec Addr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
WSEQ_DATA_WIDTH[2:0]
WSEQ_EOS
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
9
0
0
0
0
0
0
IRQ
0
0
0
0
0
0
0
GPIO_BCLK_EIN
WSEQ_EINT_DB
T_DB
0
1
0
GPIO_BCLK_EIN WSEQ_EINT_PO
T_POL
L
0
0
0
0
1
0
MCLK_PD
0
MCLK_PU
0
0
0
0
GPIO_BCLK_MO
DE_ENA
0
0
0
IM_GPIO_BCLK_
IM_WSEQ_EINT
EINT
0
WSEQ_EINT
0
0
0
0
WSEQ_CURRENT_INDEX[5:0]
FLL_K[15:0]
0
0
0
0
0
GPIO_BCLK_EIN
T
FLL_N[9:0]
0
WSEQ_ABORT
0
0
0
WSEQ_WRITE_INDEX[4:0]
1
0
0
0
0
1
0
0
DACDAT_PD
0
GPIO1_PD
IM_GPIO1_EINT
GPIO1_EINT_DB
0
0
0
0
0
0
CP_ENA
WSEQ_BUSY
CP_DYN_PWR
0
0
0
1
0
LRCLK_PU
GPIO1_SEL[3:0]
0
FLL_LOCK_EINT
_POL
0
0
0
1
IM_FLL_LOCK_E
INT
FLL_LOCK_EINT
_DB
0
BCLK_PU
FLL_LOCK_EINT
LRCLK_PD
FLL_ENA
EQ_ENA
0
0
1
0
BCLK_PD
FLL_CLK_REF_SRC[1:0]
GPIO_BCLK_SEL[3:0]
1
FLL_FRATIO[2:0]
FLL_OSC_ENA
FLL_GAIN[3:0]
FLL_FRACN_ENA
0
WSEQ_START_INDEX[5:0]
FLL_CLK_REF_DIV[1:0]
0
0
GPIO1_EINT_PO
L
GPIO1_EINT
DACDAT_PU
0
GPIO1_PU
0
FLL_CTRL_RATE[2:0]
0
0
0
0000_0000_0000_0000
0000_0000_0000_0100
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
1111_1111_1111_1111
XXXX_XPPP_PPPP_PPPP
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0001_0100
0000_0000_0000_0100
0010_1110_1110_0000
0000_0000_0000_0000
0000_0000_0000_0111
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0
WSEQ_START
0
0
0
0000_0000_0000_0000
0
0
0
WSEQ_DATA[7:0]
0
0
0
0000_0000_0000_0000
0000_0000_0000_0000
LINEOUTR_RMV LINEOUTR_ENA LINEOUTR_ENA
LINEOUTL_RMV LINEOUTL_ENA_ LINEOUTL_ENA_
LINEOUTR_ENA
LINEOUTL_ENA
_SHORT
_OUTP
_DLY
_SHORT
OUTP
DLY
0000_0000_0000_0000
HPR_ENA
HPR_RMV_SHO
HPR_ENA_OUTP HPR_ENA_DLY
RT
HPL_ENA
0000_0000_0000_0000
HPL_RMV_SHO
HPL_ENA_OUTP HPL_ENA_DLY
RT
0000_0000_0000_0000
Bin Default
DCS_DAC_WR_VAL_0[7:0]
0
0000_0000_0000_0000
1
DCS_DAC_WR_VAL_2[7:0]
2
DCS_DAC_WR_VAL_1[7:0]
3
0000_0000_0000_0000
4
DCS_DAC_WR_VAL_3[7:0]
WSEQ_ADDR[7:0]
WSEQ_ENA
0
0
0
0
5
DCS_STARTUP_COMPLETE[3:0]
6
DCS_DAC_WR_COMPLETE[3:0]
7
WSEQ_DELAY[3:0]
0
0
0
0
0
0
0
0
0
8
WSEQ_DATA_START[3:0]
0
0
0
0
0
DCS_CAL_COMPLETE[3:0]
0
0
0
0
10
FLL_OUTDIV[5:0]
0
0
0
0
0
0
0
0
0
0
0
0
11
Production Data
WM8912
PD, Rev 4.0, September 2010
95
Hex Addr
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
F7
F8
Dec Addr
135
136
137
138
139
140
141
142
w
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
247
248
FLL NCO Test 1
FLL NCO Test 0
EQ24
EQ23
EQ22
EQ21
EQ20
EQ19
EQ18
EQ17
EQ16
EQ15
EQ14
EQ13
EQ12
EQ11
EQ10
EQ9
EQ8
EQ7
EQ6
EQ5
EQ4
EQ3
EQ2
Name
0
0
0
0
0
0
0
15
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
10
0
0
0
0
0
0
0
9
0
0
0
0
0
0
0
8
0000_0111_1010_1101
0001_0001_0000_0011
0000_0101_0110_0100
0000_0101_0101_1001
0100_0000_0000_0000
EQ_B4_PG[15:0]
EQ_B5_A[15:0]
EQ_B5_B[15:0]
EQ_B5_PG[15:0]
FLL_FRC_NCO_VAL[5:0]
1111_1000_0010_1001
EQ_B4_C[15:0]
0
0001_0110_1000_1110
EQ_B4_B[15:0]
0
0000_0101_0101_1000
EQ_B4_A[15:0]
0000_0000_0001_1001
0000_0000_0000_0000
0000_1010_0101_0100
EQ_B3_PG[15:0]
FLL_FRC_NCO
1111_0011_0111_0011
EQ_B3_C[15:0]
0
0001_1100_0101_1000
EQ_B3_B[15:0]
0
0000_0001_1100_0101
EQ_B3_A[15:0]
0
0000_1011_0111_0101
EQ_B2_PG[15:0]
0
1111_0001_0100_0101
EQ_B2_C[15:0]
0
0001_1110_1011_0101
0000_0000_0000_1100
EQ_B2_B[15:0]
0000_0000_0000_1100
EQ_B5_GAIN[4:0]
0000_0000_1101_1000
0000_0000_0000_1100
EQ_B4_GAIN[4:0]
EQ_B2_A[15:0]
0000_0000_0000_1100
Bin Default
EQ_B3_GAIN[4:0]
0
EQ_B2_GAIN[4:0]
1
0000_0000_0000_1100
2
EQ_B1_GAIN[4:0]
0000_0100_0000_0000
0
3
EQ_B1_PG[15:0]
0
4
0000_1111_1100_1010
0
0
0
0
0
5
EQ_B1_B[15:0]
0
0
0
0
0
6
EQ_B1_A[15:0]
0
0
0
0
0
7
WM8912
Production Data
PD, Rev 4.0, September 2010
96
WM8912
Production Data
REGISTER BITS BY ADDRESS
REGISTER
ADDRESS
BIT
R0 (00h)
SW Reset
and ID
15:0
LABEL
DEFAULT
DESCRIPTION
REFER TO
SW_RST_DEV 1000_1001 Writing to this register resets all registers to their
_ID1 [15:0]
_0000_010 default state.
0
Reading from this register will indicate Device ID
8904h.
Register 00h SW Reset and ID
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R4 (04h)
Bias Control
0
0
BIAS_ENA
0
DESCRIPTION
REFER TO
Enables the Normal bias current generator (for all
analogue functions)
0 = Disabled
1 = Enabled
Register 04h Bias Control 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
VMID
Control 0
2:1
VMID_RES
[1:0]
00
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal operation)
10 = 2 x 250k divider (for low power standby)
11 = 2 x 5k divider (for fast start-up)
0
VMID_ENA
0
Enable VMID master bias current source
0 = Disabled
1 = Enabled
REFER TO
Register 05h VMID Control 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R14 (0Eh)
Power
Managemen
t2
1
HPL_PGA_EN
A
0
Left Headphone Output Enable
0 = disabled
1 = enabled
0
HPR_PGA_EN
A
0
Right Headphone Output Enable
0 = disabled
1 = enabled
REFER TO
Register 0Eh Power Management 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R15 (0Fh)
Power
Managemen
t3
1
LINEOUTL_PG
A_ENA
0
Left Line Output Enable
0 = disabled
1 = enabled
0
LINEOUTR_P
GA_ENA
0
Right Line Output Enable
0 = disabled
1 = enabled
REFER TO
Register 0Fh Power Management 3
w
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R18 (12h)
Power
Managemen
t6
3
DACL_ENA
0
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
2
DACR_ENA
0
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
Register 12h Power Management 6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R20 (14h)
Clock Rates
0
14
TOCLK_RATE
_DIV16
0
TOCLK Rate Divider (/16)
0=f/1
1 = f / 16
13
TOCLK_RATE
_X4
0
TOCLK Rate Multiplier
0=fx1
1=fx4
0
MCLK_DIV
0
Enables divide by 2 on MCLK
0 = SYSCLK = MCLK
1 = SYSCLK = MCLK / 2
Register 14h Clock Rates 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R21 (15h)
Clock Rates
1
13:10
CLK_SYS_RA
TE [3:0]
0011
Selects the SYSCLK / fs ratio
0000 = 64
0001 = 128
0010 = 192
0011 = 256
0100 = 384
0101 = 512
0110 = 768
0111 = 1024
1000 = 1408
1001 = 1536
2:0
SAMPLE_RAT
E [2:0]
101
Selects the Sample Rate (fs)
000 = 8kHz
001 = 11.025kHz, 12kHz
010 = 16kHz
011 = 22.05kHz, 24kHz
100 = 32kHz
101 = 44.1kHz, 48kHz
110 to 111 = Reserved
REFER TO
Register 15h Clock Rates 1
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R22 (16h)
Clock Rates
2
15
MCLK_INV
0
MCLK Invert
0 = MCLK not inverted
1 = MCLK inverted
14
SYSCLK_SRC
0
SYSCLK Source Select
0 = MCLK
1 = FLL output
12
TOCLK_RATE
0
TOCLK Rate Divider (/2)
0=f/2
1=f/1
3
OPCLK_ENA
0
GPIO Clock Output Enable
0 = disabled
1 = enabled
2
CLK_SYS_EN
A
0
System Clock enable
0 = Disabled
1 = Enabled
1
CLK_DSP_EN
A
0
DSP Clock enable
0 = Disabled
1 = Enabled
0
TOCLK_ENA
0
Zero Cross timeout enable
0 = Disabled
1 = Enabled
REFER TO
Register 16h Clock Rates 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R24 (18h)
Audio
Interface 0
12
DACL_DATINV
0
Left DAC Invert
0 = Left DAC output not inverted
1 = Left DAC output inverted
11
DACR_DATIN
V
0
Right DAC Invert
0 = Right DAC output not inverted
1 = Right DAC output inverted
10:9
DAC_BOOST
[1:0]
00
DAC Digital Input Volume Boost
00 = 0dB
01 = +6dB (Input data must not exceed -6dBFS)
10 = +12dB (Input data must not exceed -12dBFS)
11 = +18dB (Input data must not exceed -18dBFS)
5
AIFDACL_SRC
0
Left DAC Data Source Select
0 = Left DAC outputs left channel data
1 = Left DAC outputs right channel data
4
AIFDACR_SR
C
1
Right DAC Data Source Select
0 = Right DAC outputs left channel data
1 = Right DAC outputs right channel data
1
DAC_COMP
0
DAC Companding Enable
0 = disabled
1 = enabled
0
DAC_COMPM
ODE
0
DAC Companding Type
0 = μ-law
1 = A-law
Register 18h Audio Interface 0
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
Audio
Interface 1
13
AIFDAC_TDM
0
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
12
AIFDAC_TDM_
CHAN
0
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
8
AIF_TRIS
0
Audio Interface Tristate
0 = Audio interface pins operate normally
1 = Tristate all audio interface pins
7
AIF_BCLK_INV
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
6
BCLK_DIR
0
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
4
AIF_LRCLK_IN
V
0
LRC Polarity / DSP Mode A-B select.
REFER TO
Right, left and I2S modes – LRC polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising edge after
LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after
LRC rising edge (mode B)
3:2
AIF_WL [1:0]
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
1:0
AIF_FMT [1:0]
10
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Register 19h Audio Interface 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R26 (1Ah)
Audio
Interface 2
11:8
OPCLK_DIV
[3:0]
0000
w
DESCRIPTION
REFER TO
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
PD, Rev 4.0, September 2010
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
4:0
BCLK_DIV
[4:0]
0_0100
DESCRIPTION
REFER TO
BCLK Frequency (Master Mode)
00000 = SYSCLK
00001 = SYSCLK / 1.5
00010 = SYSCLK / 2
00011 = SYSCLK / 3
00100 = SYSCLK / 4
00101 = SYSCLK / 5
00110 = SYSCLK / 5.5
00111 = SYSCLK / 6
01000 = SYSCLK / 8 (default)
01001 = SYSCLK / 10
01010 = SYSCLK / 11
01011 = SYSCLK / 12
01100 = SYSCLK / 16
01101 = SYSCLK / 20
01110 = SYSCLK / 22
01111 = SYSCLK / 24
10000 = SYSCLK / 25
10001 = SYSCLK / 30
10010 = SYSCLK / 32
10011 = SYSCLK / 44
10100 = SYSCLK / 48
Register 1Ah Audio Interface 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R27 (1Bh)
Audio
Interface 3
11
LRCLK_DIR
0
10:0
LRCLK_RATE
[10:0]
DESCRIPTION
REFER TO
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
000_0100_ LRC Rate (Master Mode)
0000
LRC clock output = BCLK / LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
Register 1Bh Audio Interface 3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R30 (1Eh)
DAC Digital
Volume Left
8
DAC_VU
0
DAC Volume Update
Writing a 1 to this bit causes left and right DAC volume
to be updated simultaneously
7:0
DACL_VOL
[7:0]
1100_0000 Left DAC Digital Volume
00h = Mute
01h = -71.625dB
02h = -71.250dB
… (0.375dB steps)
C0h to FFh = 0dB
Register 1Eh DAC Digital Volume Left
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R31 (1Fh)
DAC Digital
Volume
Right
8
DAC_VU
0
DAC Volume Update
Writing a 1 to this bit causes left and right DAC volume
to be updated simultaneously
7:0
DACR_VOL
[7:0]
1100_0000 Right DAC Digital Volume
00h = Mute
01h = -71.625dB
02h = -71.250dB
… (0.375dB steps)
C0h to FFh = 0dB
Register 1Fh DAC Digital Volume Right
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R33 (21h)
DAC Digital
1
12
DAC_MONO
0
DAC Mono Mix
0 = Stereo
1 = Mono (Mono mix output on enabled DAC)
11
DAC_SB_FILT
0
Selects DAC filter characteristics
0 = Normal mode
1 = Sloping stopband mode
10
DAC_MUTERA
TE
0
DAC Soft Mute Ramp Rate
0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at
fs=48k)
1 = Slow ramp (fs/32, maximum ramp time is 171ms at
fs=48k)
9
DAC_UNMUTE
_RAMP
0
DAC Soft Mute Mode
0 = Disabling soft-mute (DAC_MUTE=0) will cause the
DAC volume to change immediately to DACL_VOL and
DACR_VOL settings
1 = Disabling soft-mute (DAC_MUTE=0) will cause the
DAC volume to ramp up gradually to the DACL_VOL
and DACR_VOL settings
6
DAC_OSR128
0
DAC Oversample Rate Select
0 = Low power (normal OSR)
1 = High performance (double OSR)
3
DAC_MUTE
1
DAC Soft Mute Control
0 = DAC Un-mute
1 = DAC Mute
2:1
DEEMPH [1:0]
00
DAC De-Emphasis Control
00 = No de-emphasis
01 = 32kHz sample rate
10 = 44.1kHz sample rate
11 = 48kHz sample rate
Register 21h DAC Digital 1
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R40 (28h)
DRC 0
15
DRC_ENA
0
DRC enable
1 = enabled
0 = disabled
14
DRC_DAC_PA
TH
0
DRC path select
0 = Reserved
1 = DAC path
12:11
DRC_GS_HYS
T_LVL [1:0]
00
Gain smoothing hysteresis threshold
00 = Low
01 = Medium (recommended)
10 = High
11 = Reserved
10:6
DRC_STARTU
P_GAIN [4:0]
0_0110
5
DRC_FF_DEL
AY
1
Feed-forward delay for anti-clip feature
0 = 5 samples
1 = 9 samples
Time delay can be calculated as 5/fs or 9/ fs, where fs
is the sample rate.
3
DRC_GS_ENA
1
Gain smoothing enable
0 = disabled
1 = enabled
2
DRC_QR
1
Quick release enable
0 = disabled
1 = enabled
1
DRC_ANTICLI
P
1
Anti-clip enable
0 = disabled
1 = enabled
0
DRC_GS_HYS
T
1
Gain smoothing hysteresis enable
0 = disabled
1 = enabled
Initial gain at DRC startup
00000 = -3dB
00001 = -2.5dB
00010 = -2dB
00011 = -1.5dB
00100 = -1dB
00101 = -0.5dB
00110 = 0dB (default)
00111 = 0.5dB
01000 = 1dB
01001 = 1.5dB
01010 = 2dB
01011 = 2.5dB
01100 = 3dB
01101 = 3.5dB
01110 = 4dB
01111 = 4.5dB
10000 = 5dB
10001 = 5.5dB
10010 = 6dB
10011 to 11111 = Reserved
Register 28h DRC 0
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Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R41 (29h)
DRC 1
15:12
DRC_ATK [3:0]
0011
Gain attack rate (seconds/6dB)
0000 = instantaneous
0001 = 363us
0010 = 726us
0011 = 1.45ms (default)
0100 = 2.9ms
0101 = 5.8ms
0110 = 11.6ms
0111 = 23.2ms
1000 = 46.4ms
1001 = 92.8ms
1010 = 185.6ms
1011-1111 = Reserved
11:8
DRC_DCY
[3:0]
0010
Gain decay rate (seconds/6dB)
0000 = 186ms
0001 = 372ms
0010 = 743ms (default)
0011 = 1.49s
0100 = 2.97s
0101 = 5.94s
0110 = 11.89s
0111 = 23.78s
1000 = 47.56s
1001-1111 = Reserved
7:6
DRC_QR_THR
[1:0]
01
Quick release crest factor threshold
00 = 12dB
01 = 18dB (default)
10 = 24dB
11 = 30dB
5:4
DRC_QR_DCY
[1:0]
00
Quick release decay rate (seconds/6dB)
00 = 0.725ms (default)
01 = 1.45ms
10 = 5.8ms
11 = Reserved
3:2
DRC_MINGAIN
[1:0]
10
Minimum gain the DRC can use to attenuate audio
signals
00 = 0dB (default)
01 = -6dB
10 = -12dB
11 = -18dB
1:0
DRC_MAXGAI
N [1:0]
00
Maximum gain the DRC can use to boost audio signals
00 = 12dB
01 = 18dB (default)
10 = 24dB
11 = 36dB
Register 29h DRC 1
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R42 (2Ah)
DRC 2
5:3
DRC_HI_COM
P [2:0]
000
Compressor slope R0
000 = 1 (no compression)
001 = 1/2
010 = 1/4
011 = 1/8
100 = 1/16
101 = 0
110 = Reserved
111 = Reserved
2:0
DRC_LO_COM
P [2:0]
000
Compressor slope R1
000 = 1 (no compression)
001 = 1/2
010 = 1/4
011 = 1/8
100 = 0
101 = Reserved
11X = Reserved
REFER TO
Register 2Ah DRC 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R43 (2Bh)
DRC 3
10:5
DRC_KNEE_IP
[5:0]
00_0000
Compressor threshold T (dB)
000000 = 0dB
000001 = -0.75dB
000010 = -1.5dB
… (-0.75dB steps)
111100 = -45dB
111101 = Reserved
11111X = Reserved
4:0
DRC_KNEE_O
P [4:0]
0_0000
Compressor amplitude at threshold YT (dB)
00000 = 0dB
00001 = -0.75dB
00010 = -1.5dB
… (-0.75dB steps)
11110 = -22.5dB
11111 = Reserved
REFER TO
Register 2Bh DRC 3
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R57 (39h)
Analogue
OUT1 Left
8
HPOUTL_MUT
E
0
Left Headphone Output Mute
0 = Un-mute
1 = Mute
7
HPOUT_VU
0
Headphone Output Volume Update
Writing a 1 to this bit will update HPOUTL and
HPOUTR volumes simultaneously.
6
HPOUTLZC
0
Left Headphone Output Zero Cross Enable
0 = disabled
1 = enabled
5:0
HPOUTL_VOL
[5:0]
10_1101
Left Headphone Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Register 39h Analogue OUT1 Left
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R58 (3Ah)
Analogue
OUT1 Right
8
HPOUTR_MUT
E
0
Right Headphone Output Mute
0 = Un-mute
1 = Mute
7
HPOUT_VU
0
Headphone Output Volume Update
Writing a 1 to this bit will update HPOUTL and
HPOUTR volumes simultaneously.
6
HPOUTRZC
0
Right Headphone Output Zero Cross Enable
0 = disabled
1 = enabled
5:0
HPOUTR_VOL
[5:0]
10_1101
Right Headphone Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Register 3Ah Analogue OUT1 Right
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R59 (3Bh)
Analogue
OUT2 Left
8
LINEOUTL_MU
TE
0
Left Line Output Mute
0 = Un-mute
1 = Mute
7
LINEOUT_VU
0
Line Output Volume Update
Writing a 1 to this bit will update LINEOUTL and
LINEOUTR volumes simultaneously.
6
LINEOUTLZC
0
Left Line Output Zero Cross Enable
0 = disabled
1 = enabled
5:0
LINEOUTL_VO
L [5:0]
11_1001
Left Line Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Register 3Bh Analogue OUT2 Left
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R60 (3Ch)
Analogue
OUT2 Right
8
LINEOUTR_M
UTE
0
Right Line Output Mute
0 = Un-mute
1 = Mute
7
LINEOUT_VU
0
Line Output Volume Update
Writing a 1 to this bit will update LINEOUTL and
LINEOUTR volumes simultaneously.
6
LINEOUTRZC
0
Right Line Output Zero Cross Enable
0 = disabled
1 = enabled
5:0
LINEOUTR_V
OL [5:0]
11_1001
Right Line Output Volume
000000 = -57dB
000001 = -56dB
(… 1dB steps)
111001 = 0dB
(… 1dB steps)
111110 = +5dB
111111 = +6dB
Register 3Ch Analogue OUT2 Right
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R67 (43h)
DC Servo 0
3
DCS_ENA_CH
AN_3
0
DC Servo enable for LINEOUTR
0 = disabled
1 = enabled
2
DCS_ENA_CH
AN_2
0
DC Servo enable for LINEOUTL
0 = disabled
1 = enabled
1
DCS_ENA_CH
AN_1
0
DC Servo enable for HPOUTR
0 = disabled
1 = enabled
0
DCS_ENA_CH
AN_0
0
DC Servo enable for HPOUTL
0 = disabled
1 = enabled
REFER TO
Register 43h DC Servo 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R68 (44h)
DC Servo 1
15
DCS_TRIG_SI
NGLE_3
0
Writing 1 to this bit selects a single DC offset correction
for LINEOUTR.
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
14
DCS_TRIG_SI
NGLE_2
0
Writing 1 to this bit selects a single DC offset correction
for LINEOUTL.
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
13
DCS_TRIG_SI
NGLE_1
0
Writing 1 to this bit selects a single DC offset correction
for HPOUTR.
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
12
DCS_TRIG_SI
NGLE_0
0
Writing 1 to this bit selects a single DC offset correction
for HPOUTL.
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
11
DCS_TRIG_SE
RIES_3
0
Writing 1 to this bit selects a series of DC offset
corrections for LINEOUTR.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
10
DCS_TRIG_SE
RIES_2
0
Writing 1 to this bit selects a series of DC offset
corrections for LINEOUTL.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
9
DCS_TRIG_SE
RIES_1
0
Writing 1 to this bit selects a series of DC offset
corrections for HPOUTR.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
8
DCS_TRIG_SE
RIES_0
0
Writing 1 to this bit selects a series of DC offset
corrections for HPOUTL.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
7
DCS_TRIG_ST
ARTUP_3
0
Writing 1 to this bit selects Start-Up DC Servo mode for
LINEOUTR.
In readback, a value of 1 indicates that the DC Servo
Start-Up correction is in progress.
6
DCS_TRIG_ST
ARTUP_2
0
Writing 1 to this bit selects Start-Up DC Servo mode for
LINEOUTL.
In readback, a value of 1 indicates that the DC Servo
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
5
DCS_TRIG_ST
ARTUP_1
0
Writing 1 to this bit selects Start-Up DC Servo mode for
HPOUTR.
In readback, a value of 1 indicates that the DC Servo
Start-Up correction is in progress.
4
DCS_TRIG_ST
ARTUP_0
0
Writing 1 to this bit selects Start-Up DC Servo mode for
HPOUTL.
In readback, a value of 1 indicates that the DC Servo
Start-Up correction is in progress.
3
DCS_TRIG_DA
C_WR_3
0
Writing 1 to this bit selects DAC Write DC Servo mode
for LINEOUTR.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
2
DCS_TRIG_DA
C_WR_2
0
Writing 1 to this bit selects DAC Write DC Servo mode
for LINEOUTL.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
1
DCS_TRIG_DA
C_WR_1
0
Writing 1 to this bit selects DAC Write DC Servo mode
for HPOUTR.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
0
DCS_TRIG_DA
C_WR_0
0
Writing 1 to this bit selects DAC Write DC Servo mode
for HPOUTL.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
Start-Up correction is in progress.
Register 44h DC Servo 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R69 (45h)
DC Servo 2
11:8
DCS_TIMER_P
ERIOD_23
[3:0]
1010
Time between periodic updates for
LINEOUTL/LINEOUTR. Time is calculated as 0.256s x
(2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
3:0
DCS_TIMER_P
ERIOD_01
[3:0]
1010
Time between periodic updates for HPOUTL/HPOUTR.
Time is calculated as 0.256s x (2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
DESCRIPTION
Register 45h DC Servo 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R71 (47h)
DC Servo 4
6:0
DCS_SERIES_
NO_23 [6:0]
010_1010
REFER TO
Number of DC Servo updates to perform in a series
event for LINEOUTL/LINEOUTR.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
Register 47h DC Servo 4
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Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R72 (48h)
DC Servo 5
6:0
DCS_SERIES_
NO_01 [6:0]
010_1010
DESCRIPTION
REFER TO
Number of DC Servo updates to perform in a series
event for HPOUTL/HPOUTR.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
Register 48h DC Servo 5
REGISTER
ADDRESS
BIT
LABEL
R73 (49h)
DC Servo 6
7:0
DCS_DAC_W
R_VAL_3 [7:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 DC Offset value for LINEOUTR in DAC Write DC Servo
mode in two's complement format.
In readback, the current DC offset value is returned in
two's complement format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
Register 49h DC Servo 6
REGISTER
ADDRESS
BIT
LABEL
R74 (4Ah)
DC Servo 7
7:0
DCS_DAC_W
R_VAL_2 [7:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 DC Offset value for LINEOUTL in DAC Write DC Servo
mode in two's complement format.
In readback, the current DC offset value is returned in
two's complement format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
Register 4Ah DC Servo 7
REGISTER
ADDRESS
BIT
LABEL
R75 (4Bh)
DC Servo 8
7:0
DCS_DAC_W
R_VAL_1 [7:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 DC Offset value for HPOUTR in DAC Write DC Servo
mode in two's complement format.
In readback, the current DC offset value is returned in
two's complement format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
Register 4Bh DC Servo 8
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REGISTER
ADDRESS
BIT
LABEL
R76 (4Ch)
DC Servo 9
7:0
DCS_DAC_W
R_VAL_0 [7:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 DC Offset value for HPOUTL in DAC Write DC Servo
mode in two's complement format.
In readback, the current DC offset value is returned in
two's complement format.
Two’s complement format:
LSB is 0.25mV.
Range is +/-32mV
Register 4Ch DC Servo 9
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R77 (4Dh)
DC Servo
Readback 0
11:8
DCS_CAL_CO
MPLETE [3:0]
0000
DESCRIPTION
REFER TO
DC Servo Complete status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = DAC Write or Start-Up DC Servo mode not
completed.
1 = DAC Write or Start-Up DC Servo mode complete.
7:4
DCS_DAC_W
R_COMPLETE
[3:0]
0000
DC Servo DAC Write status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = DAC Write DC Servo mode not completed.
1 = DAC Write DC Servo mode complete.
3:0
DCS_STARTU
P_COMPLETE
[3:0]
0000
DC Servo Start-Up status
[3] - LINEOUTR
[2] - LINEOUTL
[1] - HPOUTR
[0] - HPOUTL
0 = Start-Up DC Servo mode not completed..
1 = Start-Up DC Servo mode complete.
Register 4Dh DC Servo Readback 0
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R90 (5Ah)
Analogue
HP 0
7
HPL_RMV_SH
ORT
0
Removes HPOUTL short
0 = HPOUTL short enabled
1 = HPOUTL short removed
For normal operation, this bit should be set as the final
step of the HPL Enable sequence.
6
HPL_ENA_OU
TP
0
Enables HPOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the DC offset cancellation has been scheduled.
5
HPL_ENA_DL
Y
0
Enables HPOUTL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the output signal path has been configured, and before
DC offset cancellation is scheduled. This bit should be
set with at least 20us delay after HPL_ENA.
4
HPL_ENA
0
Enables HPOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first
step of the HPL Enable sequence.
3
HPR_RMV_SH
ORT
0
Removes HPOUTR short
0 = HPOUTR short enabled
1 = HPOUTR short removed
For normal operation, this bit should be set as the final
step of the HPR Enable sequence.
2
HPR_ENA_OU
TP
0
Enables HPOUTR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the DC offset cancellation has been scheduled.
1
HPR_ENA_DL
Y
0
Enables HPOUTR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the output signal path has been configured, and before
DC offset cancellation is scheduled. This bit should be
set with at least 20us delay after HPR_ENA.
0
HPR_ENA
0
Enables HPOUTR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first
step of the HPR Enable sequence.
Register 5Ah Analogue HP 0
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R94 (5Eh)
Analogue
Lineout 0
7
LINEOUTL_RM
V_SHORT
0
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should be set as the final
step of the LINEOUTL Enable sequence.
6
LINEOUTL_EN
A_OUTP
0
Enables LINEOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the DC offset cancellation has been scheduled.
5
LINEOUTL_EN
A_DLY
0
Enables LINEOUTL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the output signal path has been configured, and before
DC offset cancellation is scheduled. This bit should be
set with at least 20us delay after LINEOUTL_ENA.
4
LINEOUTL_EN
A
0
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first
step of the LINEOUTL Enable sequence.
3
LINEOUTR_R
MV_SHORT
0
Removes LINEOUTR short
0 = LINEOUTR short enabled
1 = LINEOUTR short removed
For normal operation, this bit should be set as the final
step of the LINEOUTR Enable sequence.
2
LINEOUTR_EN
A_OUTP
0
Enables LINEOUTR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the DC offset cancellation has been scheduled.
1
LINEOUTR_EN
A_DLY
0
Enables LINEOUTR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after
the output signal path has been configured, and before
DC offset cancellation is scheduled. This bit should be
set with at least 20us delay after LINEOUTR_ENA.
0
LINEOUTR_EN
A
0
Enables LINEOUTR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first
step of the LINEOUTR Enable sequence.
Register 5Eh Analogue Lineout 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R98 (62h)
Charge
Pump 0
0
CP_ENA
0
DESCRIPTION
REFER TO
Enable charge-pump digits
0 = disable
1 = enable
Register 62h Charge Pump 0
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R104 (68h)
Class W 0
0
CP_DYN_PWR
0
Enable dynamic charge pump power control
0 = Charge pump controlled by volume register settings
(Class G)
1 = Charge pump controlled by real-time audio level
(Class W)
Class W is recommended for lowest power
consumption.
Register 68h Class W 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R108 (6Ch)
Write
Sequencer 0
8
WSEQ_ENA
0
4:0
WSEQ_WRITE
_INDEX [4:0]
0_0000
DESCRIPTION
REFER TO
Write Sequencer Enable.
0 = Disabled
1 = Enabled
Sequence Write Index. This is the memory location to
which any updates to R109 and R110 will be copied.
0 to 31 = RAM addresses
Register 6Ch Write Sequencer 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R109 (6Dh)
Write
Sequencer 1
14:12
WSEQ_DATA_
WIDTH [2:0]
000
Width of the data block written in this sequence step.
000 = 1 bit
001 = 2 bits
010 = 3 bits
011 = 4 bits
100 = 5 bits
101 = 6 bits
110 = 7 bits
111 = 8 bits
11:8
WSEQ_DATA_
START [3:0]
0000
Bit position of the LSB of the data block written in this
sequence step.
0000 = Bit 0
…
1111 = Bit 15
7:0
WSEQ_ADDR
[7:0]
0000_0000 Control Register Address to be written to in this
sequence step.
Register 6Dh Write Sequencer 1
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R110 (6Eh)
Write
Sequencer 2
14
WSEQ_EOS
0
11:8
WSEQ_DELAY
[3:0]
0000
7:0
WSEQ_DATA
[7:0]
DESCRIPTION
REFER TO
End of Sequence flag. This bit indicates whether the
Control Write Sequencer should stop after executing
this step.
0 = Not end of sequence
1 = End of sequence (Stop the sequencer after this
step).
Time delay after executing this step.
Total delay time per step (including execution)=
62.5μs × (2^WSEQ_DELAY + 8)
0000_0000 Data to be written in this sequence step. When the data
width is less than 8 bits, then one or more of the MSBs
of WSEQ_DATA are ignored. It is recommended that
unused bits be set to 0.
Register 6Eh Write Sequencer 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R111 (6Fh)
Write
Sequencer 3
9
WSEQ_ABOR
T
0
Writing a 1 to this bit aborts the current sequence and
returns control of the device back to the serial control
interface.
8
WSEQ_START
0
Writing a 1 to this bit starts the write sequencer at the
memory location indicated by the
WSEQ_START_INDEX field. The sequence continues
until it reaches an “End of sequence” flag. At the end of
the sequence, this bit will be reset by the Write
Sequencer.
5:0
WSEQ_START
_INDEX [5:0]
00_0000
Sequence Start Index. This is the memory location of
the first command in the selected sequence.
0 to 31 = RAM addresses
32 to 48 = ROM addresses
49 to 63 = Reserved
Register 6Fh Write Sequencer 3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R112 (70h)
Write
Sequencer 4
9:4
WSEQ_CURR
ENT_INDEX
[5:0]
00_0000
0
WSEQ_BUSY
0
DESCRIPTION
REFER TO
Sequence Current Index (read only):
This is the location of the most recently accessed
command in the write sequencer memory.
Sequencer Busy flag (read only):
0 = Sequencer idle
1 = Sequencer busy
Note: it is not possible to write to control registers via
the control interface while the Sequencer is Busy.
Register 70h Write Sequencer 4
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R116 (74h)
FLL Control
1
2
FLL_FRACN_E
NA
0
DESCRIPTION
REFER TO
FLL Fractional enable
0 = Integer Mode
1 = Fractional Mode
Fractional Mode (FLL_FRACN_ENA=1) is
recommended in all cases
1
FLL_OSC_EN
A
0
FLL Oscillator enable
0 = Disabled
1 = Enabled
FLL_OSC_ENA must be enabled before enabling
FLL_ENA.
Note that this field is required for free-running FLL
modes only.
0
FLL_ENA
0
FLL Enable
0 = Disabled
1 = Enabled
FLL_OSC_ENA must be enabled before enabling
FLL_ENA.
Register 74h FLL Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R117 (75h)
FLL Control
2
13:8
FLL_OUTDIV
[5:0]
00_0000
6:4
FLL_CTRL_RA
TE [2:0]
000
DESCRIPTION
REFER TO
FLL FOUT clock divider
00_0000 = Reserved
00_0001 = Reserved
00_0010 = Reserved
00_0011 = 4
00_0100 = 5
00_0101 = 6
…
11_1110 = 63
11_1111 = 64
(FOUT = FVCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that these are not changed from
default.
2:0
FLL_FRATIO
[2:0]
w
111
FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
Register 75h FLL Control 2
REGISTER
ADDRESS
BIT
LABEL
R118 (76h)
FLL Control
3
15:0
FLL_K [15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 Fractional multiply for FREF
_0000_000 (MSB = 0.5)
0
Register 76h FLL Control 3
REGISTER
ADDRESS
BIT
LABEL
R119 (77h)
FLL Control
4
14:5
FLL_N [9:0]
3:0
FLL_GAIN [3:0]
DEFAULT
DESCRIPTION
REFER TO
01_0111_0 Integer multiply for FREF
111
(LSB = 1)
0000
FLL Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not changed from
default.
Register 77h FLL Control 4
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R120 (78h)
FLL Control
5
4:3
FLL_CLK_REF
_DIV [1:0]
00
DESCRIPTION
REFER TO
FLL Clock Reference Divider
00 = MCLK / 1
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
1:0
FLL_CLK_REF
_SRC [1:0]
00
FLL Clock source
00 = MCLK
01 = BCLK
10 = LRCLK
11 = Reserved
Register 78h FLL Control 5
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R121 (79h)
GPIO
Control 1
5
GPIO1_PU
0
GPIO1 pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
4
GPIO1_PD
1
GPIO1 pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
3:0
GPIO1_SEL
[3:0]
0100
REFER TO
GPIO1 Function Select
0000 = GPIO input
0001 = Clock output (f=SYSCLK/OPCLKDIV)
0010 = Logic '0' output
0011 = Logic '1' output
0100 = IRQ output (default)
0101 = FLL Lock output
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = FLL Clock output
1010 to 1111 = Reserved
Register 79h GPIO Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R124 (7Ch)
GPIO
Control 4
7
GPIO_BCLK_
MODE_ENA
0
Selects BCLK/GPIO4 pin function
0 = BCLK/GPIO4 is used as BCLK
1 = BCLK/GPIO4 is used as GPIO. MCLK provides the
BCLK in the AIF in this mode.
3:0
GPIO_BCLK_S
EL [3:0]
0000
BCLK/GPIO4 function select:
0000 = GPIO input (default)
0001 = Clock output (f=SYSCLK/OPCLKDIV)
0010 = Logic '0' output
0011 = Logic '1' output
0100 = IRQ output
0101 = FLL Lock output
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = FLL Clock output
1010 to 1111 = Reserved
Register 7Ch GPIO Control 4
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R126 (7Eh)
Digital Pulls
7
MCLK_PU
0
MCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
6
MCLK_PD
0
MCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
5
DACDAT_PU
0
DACDAT pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
4
DACDAT_PD
0
DACDAT pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
3
LRCLK_PU
0
LRCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
2
LRCLK_PD
0
LRCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
1
BCLK_PU
0
BCLK pull-up resistor enable
0 = pull-up disabled
1 = pull-up enabled
0
BCLK_PD
0
BCLK pull-down resistor enable
0 = pull-down disabled
1 = pull-down enabled
LABEL
DEFAULT
REFER TO
Register 7Eh Digital Pulls
REGISTER
ADDRESS
BIT
DESCRIPTION
REFER TO
R127 (7Fh)
Interrupt
Status
10
IRQ
0
Logical OR of all other interrupt flags
9
GPIO_BCLK_E
INT
0
GPIO4 interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
8
WSEQ_EINT
0
Write Sequence interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written.
Note that the read value of WSEQ_EINT is not valid
whilst the Write Sequencer is Busy
5
GPIO1_EINT
0
GPIO1 interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
2
FLL_LOCK_EI
NT
0
FLL Lock interrupt
0 = interrupt not set
1 = interrupt is set
Cleared when a ‘1’ is written
Register 7Fh Interrupt Status
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R128 (80h)
Interrupt
Status Mask
9
IM_GPIO_BCL
K_EINT
1
GPIO4 interrupt mask
0 = do not mask interrupt
1 = mask interrupt
8
IM_WSEQ_EIN
T
1
Write sequencer interrupt mask
0 = do not mask interrupt
1 = mask interrupt
5
IM_GPIO1_EIN
T
1
GPIO1 interrupt mask
0 = do not mask interrupt
1 = mask interrupt
2
IM_FLL_LOCK
_EINT
1
FLL Lock interrupt mask
0 = do not mask interrupt
1 = mask interrupt
REFER TO
Register 80h Interrupt Status Mask
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R129 (81h)
Interrupt
Polarity
9
GPIO_BCLK_E
INT_POL
0
GPIO4 interrupt polarity
0 = active high
1 = active low
8
WSEQ_EINT_
POL
0
Write Sequencer interrupt polarity
0 = active high (interrupt is triggered when WSEQ is
busy)
1 = active low (interrupt is triggered when WSEQ is
idle)
5
GPIO1_EINT_
POL
0
GPIO1 interrupt polarity
0 = active high
1 = active low
2
FLL_LOCK_EI
NT_POL
0
FLL Lock interrupt polarity
0 = active high (interrupt is triggered when FLL Lock is
reached)
1 = active low (interrupt is triggered when FLL is not
locked)
DESCRIPTION
Register 81h Interrupt Polarity
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R130 (82h)
Interrupt
Debounce
9
GPIO_BCLK_E
INT_DB
0
GPIO4 interrupt debounce
0 = disabled
1 = enabled
8
WSEQ_EINT_
DB
0
Write Sequencer interrupt debounce enable
0 = disabled
1 = enabled
5
GPIO1_EINT_
DB
0
GPIO1 input debounce
0 = disabled
1 = enabled
2
FLL_LOCK_EI
NT_DB
0
FLL Lock debounce
0 = disabled
1 = enabled
REFER TO
Register 82h Interrupt Debounce
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R134 (86h)
EQ1
0
EQ_ENA
0
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
EQ enable
0 = EQ disabled
1 = EQ enabled
Register 86h EQ1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R135 (87h)
EQ2
4:0
EQ_B1_GAIN
[4:0]
0_1100
Gain for EQ band 1
00000 = -12dB
00001 = -11dB
(… 1dB steps)
01100 = 0dB
(… 1dB steps)
11000 = +12dB
11001 to 11111 = reserved
Register 87h EQ2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R136 (88h)
EQ3
4:0
EQ_B2_GAIN
[4:0]
0_1100
DESCRIPTION
REFER TO
Gain for EQ band 2
00000 = -12dB
00001 = -11dB
(… 1dB steps)
01100 = 0dB
(… 1dB steps)
11000 = +12dB
11001 to 11111 = reserved
Register 88h EQ3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R137 (89h)
EQ4
4:0
EQ_B3_GAIN
[4:0]
0_1100
DESCRIPTION
REFER TO
Gain for EQ band 3
00000 = -12dB
00001 = -11dB
(… 1dB steps)
01100 = 0dB
(… 1dB steps)
11000 = +12dB
11001 to 11111 = reserved
Register 89h EQ4
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R138 (8Ah)
EQ5
4:0
EQ_B4_GAIN
[4:0]
0_1100
DESCRIPTION
REFER TO
Gain for EQ band 4
00000 = -12dB
00001 = -11dB
(… 1dB steps)
01100 = 0dB
(… 1dB steps)
11000 = +12dB
11001 to 11111 = reserved
Register 8Ah EQ5
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R139 (8Bh)
EQ6
4:0
EQ_B5_GAIN
[4:0]
0_1100
DEFAULT
DESCRIPTION
REFER TO
Gain for EQ band5
00000 = -12dB
00001 = -11dB
(… 1dB steps)
01100 = 0dB
(… 1dB steps)
11000 = +12dB
11001 to 11111 = reserved
Register 8Bh EQ6
REGISTER
ADDRESS
BIT
LABEL
R140 (8Ch)
EQ7
15:0
EQ_B1_A
[15:0]
DESCRIPTION
REFER TO
0000_1111 EQ Band 1 Coefficient A
_1100_101
0
Register 8Ch EQ7
REGISTER
ADDRESS
BIT
LABEL
R141 (8Dh)
EQ8
15:0
EQ_B1_B
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0100 EQ Band 1 Coefficient B
_0000_000
0
Register 8Dh EQ8
REGISTER
ADDRESS
BIT
LABEL
R142 (8Eh)
EQ9
15:0
EQ_B1_PG
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0000 EQ Band 1 Coefficient PG
_1101_100
0
Register 8Eh EQ9
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REGISTER
ADDRESS
BIT
LABEL
R143 (8Fh)
EQ10
15:0
EQ_B2_A
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0001_1110 EQ Band 2 Coefficient A
_1011_010
1
Register 8Fh EQ10
REGISTER
ADDRESS
BIT
LABEL
R144 (90h)
EQ11
15:0
EQ_B2_B
[15:0]
DEFAULT
DESCRIPTION
REFER TO
1111_0001 EQ Band 2 Coefficient B
_0100_010
1
Register 90h EQ11
REGISTER
ADDRESS
BIT
LABEL
R145 (91h)
EQ12
15:0
EQ_B2_C
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_1011 EQ Band 2 Coefficient C
_0111_010
1
Register 91h EQ12
REGISTER
ADDRESS
BIT
LABEL
R146 (92h)
EQ13
15:0
EQ_B2_PG
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0001 EQ Band 2 Coefficient PG
_1100_010
1
Register 92h EQ13
REGISTER
ADDRESS
BIT
LABEL
R147 (93h)
EQ14
15:0
EQ_B3_A
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0001_1100 EQ Band 3 Coefficient A
_0101_100
0
Register 93h EQ14
REGISTER
ADDRESS
BIT
LABEL
R148 (94h)
EQ15
15:0
EQ_B3_B
[15:0]
DEFAULT
DESCRIPTION
REFER TO
1111_0011 EQ Band 3 Coefficient B
_0111_001
1
Register 94h EQ15
REGISTER
ADDRESS
BIT
LABEL
R149 (95h)
EQ16
15:0
EQ_B3_C
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_1010 EQ Band 3 Coefficient C
_0101_010
0
Register 95h EQ16
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REGISTER
ADDRESS
BIT
LABEL
R150 (96h)
EQ17
15:0
EQ_B3_PG
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0101 EQ Band 3 Coefficient PG
_0101_100
0
Register 96h EQ17
REGISTER
ADDRESS
BIT
LABEL
R151 (97h)
EQ18
15:0
EQ_B4_A
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0001_0110 EQ Band 4 Coefficient A
_1000_111
0
Register 97h EQ18
REGISTER
ADDRESS
BIT
LABEL
R152 (98h)
EQ19
15:0
EQ_B4_B
[15:0]
DEFAULT
DESCRIPTION
REFER TO
1111_1000 EQ Band 4 Coefficient B
_0010_100
1
Register 98h EQ19
REGISTER
ADDRESS
BIT
LABEL
R153 (99h)
EQ20
15:0
EQ_B4_C
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0111 EQ Band 4 Coefficient C
_1010_110
1
Register 99h EQ20
REGISTER
ADDRESS
BIT
LABEL
R154 (9Ah)
EQ21
15:0
EQ_B4_PG
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0001_0001 EQ Band 4 Coefficient PG
_0000_001
1
Register 9Ah EQ21
REGISTER
ADDRESS
BIT
LABEL
R155 (9Bh)
EQ22
15:0
EQ_B5_A
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0101 EQ Band 5 Coefficient A
_0110_010
0
Register 9Bh EQ22
REGISTER
ADDRESS
BIT
LABEL
R156 (9Ch)
EQ23
15:0
EQ_B5_B
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0000_0101 EQ Band 1 Coefficient B
_0101_100
1
Register 9Ch EQ23
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WM8912
Production Data
REGISTER
ADDRESS
BIT
LABEL
R157 (9Dh)
EQ24
15:0
EQ_B5_PG
[15:0]
DEFAULT
DESCRIPTION
REFER TO
0100_0000 EQ Band 5 Coefficient PG
_0000_000
0
Register 9Dh EQ24
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R247 (F7h)
FLL NCO
Test 0
0
FLL_FRC_NC
O
0
DESCRIPTION
REFER TO
FLL Forced control select
0 = Normal
1 = FLL oscillator controlled by FLL_FRC_NCO_VAL
(Note that this field is required for free-running FLL
modes only)
Register F7h FLL NCO Test 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R248 (F8h)
FLL NCO
Test 1
5:0
FLL_FRC_NC
O_VAL [5:0]
01_1001
DESCRIPTION
REFER TO
FLL Forced oscillator value
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for free-running FLL
modes only)
Register F8h FLL NCO Test 1
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 56 Recommended External Components
Notes:
1. Decoupling Capacitors
X5R ceramic capacitor is recommended for capacitors C7, C8, C13, C14, C15, C17 and C18.
The positioning of C7 is very important - this should be as close to the WM8912 as possible.
Capacitors C17 and C18 should also be positioned as close to the WM8912 as possible.
2.
Charge Pump Capacitors
Specific recommendations for C12, C17 and C18 are provided in Table 66. Note that two different recommendations are
provided for C17 and C18; either of these components is suitable, depending upon size requirements and availability.
The positioning of C12 is very important - this should be as close to the WM8912 as possible.
It is important to select a suitable capacitor type for the Charge Pump. Note that the capacitance may vary with DC voltage;
care is required to ensure that required capacitance is achieved at the applicable operating voltage, as specified in Table 66.
The capacitor datasheet should be consulted for this information.
COMPONENT
REQUIRED
CAPACITANCE
VALUE
C12 (CPCA-CPCB)
≥ 1μF at 2VDC
C17 (CPVOUTP)
C18 (CPVOUTN)
≥ 2μF at 2VDC
PART NUMBER
VOLTAGE
TYPE
SIZE
2.2μF
Kemet C0402C225M9PAC
6.3v
X5R
0402
2.2μF
MuRata GRM188R61A225KE34D
10v
X5R
0603
4.7μF
MuRata GRM155R60J475M_EIA
6.3v
X5R
0402
Table 66 Charge Pump Capacitors
3.
ZOBEL NETWORKS
The Zobel network shown in Figure 56 is required on HPOUTL, HPOUTR, LINEOUTL and LINEOUTR whenever that output is
enabled. Stability of these ground-referenced outputs across all process corners cannot be guaranteed without the Zobel
network components. (Note that, if any ground-referenced output pin is not required, the zobel network components can be
omitted from the output pin, and the pin can be left floating.) The Zobel network requirement is detailed further in the
applications note WAN_0212 “Class W Headphone Impedance Compensation”.
Zobel networks (C9, C10, C11, C16, R3, R4, R5, R6) should be positioned reasonably close to the WM8912.
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Production Data
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.75 mm BODY, 0.40 mm LEAD PITCH
DM067.A
D
D2
32
25
L
1
24
4
EXPOSED
GROUND 6
PADDLE
A
INDEX AREA
(D/2 X E/2)
E2
17
E
8
16
2X
15
9
b
B
e
1
bbb M C A B
2X
aaa C
aaa C
TOP VIEW
BOTTOM VIEW
ccc C
A3
A
0.08 C
C
SEATING PLANE
5
A1
SIDE VIEW
DETAIL 1
A3
G
b
Exposed lead
DETAIL 1
2.65
Dimensions (mm)
NOM
MAX
NOTE
0.75
0.8
0.035
0.05
0.203 REF
0.2
0.25
1
4.00 BSC
2.7
2.75
2
4.00 BSC
2.7
2.75
2
0.35
0.40 BSC
0.5
0.40
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
L
aaa
bbb
ccc
REF:
MIN
0.70
0
0.15
2.65
0.45
Tolerances of Form and Position
0.05
0.10
0.10
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.25 mm FROM TERMINAL TIP.
2. ALL DIMENSIONS ARE IN MILLIMETRES.
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
5. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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