CDB4228A Evaluation Board for CS4228A Features Description l Demonstrates The CDB4228A evaluation board is an excellent means for quickly evaluating the CS4228A 2 in, 6 out, 24-bit, 96kHz capable CODEC. Evaluation requires an analog signal source and analyzer, a digital signal source and analyzer, a PC compatible computer for control, and a power supply. recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF & EIAJ340 compatible digital audio l CS8404 transmits AES/EBU, S/PDIF & EIAJ340 compatible digital audio l PC software provides easy to use board and device control l Interfaces for external serial audio I/O and microprocessor control System timing can be supplied by the CS8414 digital audio receiver I.C., or an onboard oscillator. Control is provided by PC software. The evaluation board may also be configured to accept external timing, data, and control signals for operation in a user application during system development. ORDERING INFORMATION CDB4228A Evaluation Board PC Control Port CS8414 Digital Audio Receiver CS8404 Digital Audio Transmitter Digital Audio Port External Control Port PLD SCK SDA/CDIN CDOUT CS MCLK LRCLK Analog Outputs SCLK SDIN1 SDIN2 SDIN3 SDOUT CS4228A Analog Inputs Oscillator Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved) OCT ’00 DS511DB1 1 CDB4228A TABLE OF CONTENTS 1. CDB4228A SYSTEM OVERVIEW .................................................................. 4 2. CS4228A CODEC ........................................................................................... 4 3. BOARD CONTROL ........................................................................................ 4 3.1 Graphical User Interface ...................................................................... 4 3.2 External Control Interface .................................................................... 4 4. DIGITAL AUDIO I/O ........................................................................................ 4 4.1 Receiver ............................................................................................... 4 4.2 Transmitter ........................................................................................... 4 4.3 Digital Audio Port ................................................................................. 5 4.4 Master Clock ........................................................................................ 5 4.5 Serial Data Format ............................................................................... 5 5. ANALOG INPUT ............................................................................................. 5 6. ANALOG OUTPUT ......................................................................................... 5 7. EXTERNAL CONTROL MODE ...................................................................... 5 7.1 Serial Mode .......................................................................................... 6 7.2 MCLK Multiplexer ................................................................................ 6 7.3 Transmitter Clock Divider .................................................................... 6 8. POWER SUPPLY CIRCUITRY ....................................................................... 6 9. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 6 10. BILL OF MATERIALS .............................................................................. 31 LIST OF FIGURES Figure 1. CDB4228A Top Level Schematic ......................................................... 9 Figure 2. Analog Input Filter .............................................................................. 10 Figure 3. External Control ................................................................................. 11 Figure 4. Digital Audio Port ............................................................................... 12 Figure 5. Analog Output Filter 1 ........................................................................ 13 Figure 6. Analog Output Filter 2 ........................................................................ 14 Figure 7. Analog Output Filter 3 ........................................................................ 15 Figure 8. Analog Output Filter 4 ........................................................................ 16 Figure 9. Analog Output Filter 5 ........................................................................ 17 Figure 10.Analog Output Filter 6 ........................................................................ 18 Figure 11.Low Cost Analog Output Filter ........................................................... 19 Figure 12.Control Port Interface ......................................................................... 20 Figure 13.Programmable Logic .......................................................................... 21 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales/cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS511DB1 CDB4228A Figure 14.Power Supply ..................................................................................... 22 Figure 15.Master Clock Circuit ........................................................................... 23 Figure 16.CS8414 Digital Audio Receiver .......................................................... 24 Figure 17.CS8404 Digital Audio Transmitter ...................................................... 25 Figure 18.Silkscreen Top ................................................................................... 26 Figure 19.Top Side ............................................................................................. 27 Figure 20.Level 2 Ground Plane ........................................................................ 28 Figure 21.Level 3 ............................................................................................... 29 Figure 22.Bottom Side ....................................................................................... 30 LIST OF TABLES Table 1. Board Level Serial Mode Settings ............................................................. 6 Table 2. System Connections ................................................................................. 7 Table 3. MCLK Multiplexer Settings ........................................................................ 7 Table 4. CDB4228A Jumper and Switch Settings ................................................... 8 Table 5. Transmitter Clock Divider Settings ............................................................ 8 Table 6. Bill of Materials ........................................................................................ 31 DS511DB1 3 CDB4228A 1. CDB4228A SYSTEM OVERVIEW 4. DIGITAL AUDIO I/O The CDB4228A evaluation board is an excellent means of quickly evaluating the CS4228A. Input and output analog interfaces are provided as well as a CS8414 digital interface receiver and CS8404 digital interface transmitter that provide an easy interface to digital audio test equipment. The evaluation board also allows the user to interface external systems’ digital audio clocks and data through the digital audio port (DAP) 20-pin header. An external two wire or SPI control interface is also provided through a 10-pin header for easy system development using the evaluation board. 4.1 The CDB4228A schematic has been partitioned into 17 schematics shown in Figures 1 through 17. Each partitioned schematic is represented in the top level schematic shown in Figure 1. 2. CS4228A CODEC A complete description of the CS4228A CODEC is included in the CS4228A data sheet. 3. BOARD CONTROL 3.1 Graphical User Interface The CDB4228A is shipped with Windows based graphical user interface (GUI) software for interfacing with the CS4228A control port via a PC parallel port connected to the DB25 connector, J15. Parallel port control is selected by placing the CONTROL switch S2 in the PP position. The software can be used to communicate with the CS4228A in two wire or SPI mode by selecting the MODE switch S4. Further documentation for the software is available on the distribution diskette in the plain text format file, README.TXT. 3.2 External Control Interface The evaluation board can also be controlled via a external host such as a microcontroller connected to the EXTRNL CONTROL port JP9 by placing the CONTROL switch S2 in the EXTRNL position. For more information, see section 7. 4 Receiver Digital-to-Analog (DAC) performance can be quickly tested by connecting a S/PDIF audio source to the CS8414 receiver. The S/PDIF input can be either optical or coax, see Figure 16. However, both inputs cannot be driven simultaneously. The interface for the CS8414 includes a serial bit clock, serial data, left-right clock (FSYNC), and a 256 Fs master clock. The bit clock and left-right clock signals are bidirectional, and as a pair can be selected to supply these signals to the system, or can be selected as inputs from the CS4228A or DAP. The receiver data output can be simultaneously connected to the SDIN1, SDIN2, and SDIN3 inputs on the CS4228A. The receiver can be powered down to prevent asynchronous clock interference by depressing all three rocker switches to the OFF position on the RX PWR DIP switch S1. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 data sheet. 4.2 Transmitter The analog-to-digital converter performance can be quickly evaluated by connecting an analog generator to the left and right inputs, and connecting the S/PDIF optical or coaxial output to audio test equipment. The CS8404 digital interface transmitter is connected to the CODEC serial data output SDOUT, and the system bit clock, left-right clock and master clock as shown in Figure 17. The transmitter and CS4228A share several serial modes, but not all modes of each device are supported. SMODE 4 and 5 will not work properly with the transmitter: The data will be right-shifted by 8 bits. The transmitter must always be supplied a 128 Fs master clock, which is supplied by clock dividers within the PLD. The clock divider source is the same as that selected for the CS4228A MCLK. The DS511DB1 CDB4228A PLD can support division ratios of 1, 2, 3, and 4 to support MCLK frequencies of 128, 256, 384, and 512 Fs respectively. The proper division ratio can be selected in the GUI in PP mode, or S5 in EXTRNL mode. 4.3 Digital Audio Port The digital audio port (DAP) provides an interface to the CODEC serial audio clocks and data. The DAP can be used to interface to external compressed audio decoder systems such as the CS492x or CS49300 families of digital signal processors for ease in evaluating complete audio system solutions. MCLK, LRCLK, and SCLK are bidirectional signals. The direction of these signals can be controlled by the GUI in PP mode, or S5 switches in EXTRNL mode. The direction of SCLK and LRCLK is always selected as a pair. 4.4 Master Clock Master clock (MCLK) for the evaluation board can come from one of three sources: the on-board CS8414 receiver, the on-board oscillator, or an external source via the DAP port. One of the three sources is selected by multiplexer U2 which is controlled via the GUI in PP mode or the S5 switches in EXTRNL mode. The on-board oscillator provided with the board is 12.288 MHz for evaluation at 256 Fs at a 48kHz sample rate, or 128 Fs at a 96kHz sample rate. The oscillator is socketed for easy replacement and can be powered down with header JP1 to prevent asynchronous clock interference when the S/PDIF receiver is being used. The MCLK multiplexer adds a small amount of clock jitter to the MCLK signal, which has a very slight effect on converter performance. The system can be evaluated without the buffer by installing a 3x2 pin header in JP2, and removing R3. A 2-socket shorting jumper is then installed in JP2 to select the system MCLK source. Refer to Figure 15. DS511DB1 4.5 Serial Data Format The serial data format for the evaluation board is set by the GUI in PP mode or by S5 switches in EXTRNL mode. Not all serial modes of each device are supported. SMODE 4 and 5 are not supported by the transmitter. Two serial formats are common to all three devices; I2S, 16 to 24 bits/sample, and right justified, 16 bits/sample. Each of the three SDIN inputs to the CS4228A comes from a multiplexer within the PLD and can be individually sourced from the CS8414 receiver or from the DAP. The multiplexer can be disabled and jumpers JP3-JP5 can be used to select the source. 5. ANALOG INPUT Analog inputs to the CDB4228A are single ended, with a full scale of 2V RMS (5.66V p-p). The inputs are AC coupled, then converted to a differential signal with a 2.3V common mode voltage derived from the 5V supply. The differential signal is then antialiased with a passive filter, Fc = 200 kHz, before being sent to the ADC as shown in Figure 2. 6. ANALOG OUTPUT The analog outputs from the DACs are buffered with a 2-pole active butterworth filter, Fc = 50 kHz. The filter has a DC gain of 1.56V/V for a 2V RMS full scale output. For a lower cost alternative, the outputs can be filtered with a single pole passive filter with Fc = 50 kHz and RL > 10k ohms as shown in Figure 11. The outputs also have a mute circuit that is controlled by the MUTEC pin on the CS4228A. 7. EXTERNAL CONTROL MODE The CDB4228A system can be controlled without using a PC by connecting a host controller to the EXTRNL CTRL port. All board functions set by the parallel port are available to the user on the 10 position DIP switch, S5. There are three parameters on S5; board level serial mode, MCLK multiplexing, and S/PDIF transmitter clock divider control. On S5, an open switch denotes a one for that bit position. 5 CDB4228A 7.1 Serial Mode The SMODE[4..0] switches on S5 set the serial mode and the LRCLK/SCLK direction of all other devices in the system except the CS4228A. The devices controlled by SMODE include the CS8414, the CS8404, and the DAP. SMODE settings on S5 are only active when in EXTRNL mode. The SMODE mapping is shown in Table 1. Care must be taken when setting up SMODE so that the LRCLK/SCLK direction corresponds with the CS4228A master/slave setting to avoid bus contention. The CS4228A serial port master/slave mode is set in the Serial Port Mode register 0x0D. 7.2 MCLK Multiplexer The board level MCLK source is controlled by the MCLK-SEL[2..0] switches on S5 when in EXTRNL mode. The multiplexer settings are shown in Table 3. The MCLK source should be the CS8414 whenever the S/PDIF data source is used. 7.3 Transmitter Clock Divider The TX_MCLK[1..0] switches on S5 control the clock divider for the CS8404 S/PDIF transmitter when in EXTRNL mode. The transmitter must be supplied a 128 Fs MCLK which is sourced from the SMODE [4..0] Board Level Serial Mode CS4228A MCLK multiplexer. The clock divider ratios are shown in Table 5. 8. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by four binding posts (+5V, GND, +12V, -12V). The +5V input supplies power to the analog and digital +5 Volt circuitry and to a 3.3V voltage regulator. There is a power supply header for selecting either 5V or 3.3V supplies to the CS4228A VL pin. A second header selects the interface voltage for the programmable logic device that supplies the control port interface. The VL setting should always be equal or greater than the PLD PWR to prevent noise due to charge injection. 9. GROUNDING AND POWER SUPPLY DECOUPLING The CS4228A requires careful attention to power supply and grounding arrangements to optimize performance. The decoupling capacitors are located as close to the CS4228A as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise. CS8414 MODE CS8404 MODE DAP CLK MODE CS8414 M[3..0] CS8404 M[2..0] Output Input Input 2 4 0 I2S, TX Master, 64Fs SCLK only 1 I2S, CODEC Master Input Input Input 3 4 2 I2S, DAP Master Input Input Output 3 4 3 Right Justified, TX Master, 16 bits Output Input Input 5 5 4 Right Justified, CODEC master Input OFF Input 15 4 5 Right Justified, DAP master Input OFF Output 15 4 6 Left Justified, CODEC master Input OFF Input 15 1 7 Left Justified, DAP master Input OFF Output 15 1 8 Left Justified, test mode Output Input Input 0 1 9 Left Justified, test mode Input Output Input 1 0 I2S, CODEC master Input Input Input 3 4 10 - 31 Table 1. Board Level Serial Mode Settings 6 DS511DB1 CDB4228A CONNECTOR INPUT/OUTPUT SIGNAL PRESENT +5V Input + 5 Volt power +12V, -12V Input + 12/-12V Volt power for the op-amps GND Input Ground connection from power supply J9, SPDIF IN Input Digital audio interface input via coax U9, SPDIF IN Input Digital audio interface input via optical LEFT Input Analog audio input, 2V RMS (5.65Vp-p) full scale RIGHT Input Analog audio input, 2V RMS (5.65Vp-p) full scale DAC1 - DAC6 Output Analog audio output, 2V RMS (5.65Vp-p) full scale J7, SPDIF OUT Output Digital audio interface output via coax U5, SPDIF OUT Output Digital audio interface output via optical Parallel Port Input/Output Parallel connection to PC for two wire® or SPI control port signals EXT CTRL Input/Output I/O for two wire® or SPI control port signals DAP Input/Output I/O for serial audio clocks and data PGM Input/Output Programming header for PLD Table 2. System Connections MCLK-SEL [2..0] MCLK Source DAP MCLK DIR 0 Oscillator OFF 1 Oscillator Output 2 S/PDIF Receiver OFF 3 S/PDIF Receiver Output 4 DAP Input 5 None OFF 6 None OFF 7 None OFF Table 3. MCLK Multiplexer Settings DS511DB1 7 CDB4228A JUMPER PURPOSE POSITION VD Selects the supply voltage for the CS4228A digital core. 3.3V* 5V VL Selects the supply voltage for the CS4228A logic interface pins 3.3V 5V* RX PWR Selects the supply voltage for the Altera PLD I/O pins. 3.3V 5V* OSC PWR Connects power to the oscillator ON* OFF S1 Connects power and clocks to the CS8414 ON* OFF S2 Selects control port interface S3 Selects the CS4228A SDIN1,2,3 source in EXTRNL control mode SPDIF* DAP S4 Selects the control port data format Two wire* SPI Two wire control format SPI control format S5 Selects serial mode and DAP clock directions in EXTRNL control mode. CLOSED* OPEN See external control mode section for more information. JP2 Optional pin header select for MCLK PP* EXTRNL FUNCTION SELECTED Power and LRCLK and SCLK are connected Power, LRCLK, and SCLK are disconnected Parallel port control enabled. EXTRNL CTRL header enabled CS8414 data is routed to SDIN1,2,3 SDIN1,2,3 source is the DAP OSC MCLK source is onboard oscillator. SPDIF MCLK MCLK source is CS8414 receiver MUX MCLK MCLK source is multiplexer Notes: *Default setting from factory Table 4. CDB4228A Jumper and Switch Settings TX-MCLK [1..0] MCLK Division Ratio System MCLK Rate 0 1:1 128 *1 1:2 256 2 1:3 384 3 1:4 512 Table 5. Transmitter Clock Divider Settings 8 DS511DB1 DS511DB1 SPDIF Out SPDIF In TX_MCLK SCLK LRCLK SDOUT MCLK SCLK LRCLK SDIN 2 J1 PHONO JACK RA 1 M[2..0] RESETn TX_U TX_C TX_CBL A/D Input AINL OUTLOUTL+ OUTROUTR+ GND AINR J2 PHONO JACK RA 1 AINLAINL+ AINRAINR+ MCLK SCLK FSYNC SDOUT M[3..0] RXPWR RX_C RX_U RX_CBL RX_ERF RX_VERF TX_M[2..0] MRESETn TX_U TX_C TX_CBL SPDIF TX SPDIF_SDOUT DAP_SDIN1 1 3 2 4 AOUT1 SDIN1 IN MUTE HEADER 2X2 Out1 JP4 SPDIF_SDOUT DAP_SDIN2 Output Buffer2 1 3 2 4 AOUT2 SDIN2 HEADER 2X2 SPDIF RX A/D Input Output Buffer1 JP3 SPDIF_MCLK SCLK LRCLK SPDIF_SDOUT RX_M[3..0] RXPWR RX_C RX_U RX_CBL RX_ERF RX_VERF IN MUTE JP5 2 SPDIF_SDOUT DAP_SDIN3 Out2 1 3 2 4 SDIN3 Output Buffer3 AOUT3 HEADER 2X2 GND IN MUTE Out3 U3 VL +3.3V JP6 VD VCC 1 3 +5V R5 R6 R7 2 4 10k 3.16k 10k HEADER 2X2 VLOGIC SEL +3.3V VD VCC +5V CLKIN SCLK LRCLK SDIN1 SDIN2 SDIN3 SDOUT TP3 TP5 TP7 TP9 TP11 TP12 TP14 10 5 6 3 2 1 4 150 150 150 150 150 150 SCL SDA/CDIN AD0/CS TP16 TP18 TP20 11 12 13 MRESETn MUTEC TP23 TP25 JP11 1 3 R98 R99 R100 R101 R102 R103 2 4 TP26 + C7 HEADER 2X2 10uf C9 47nf VD SEL 14 15 9 8 7 CLKIN SCLK LRCLK SDIN1 SDIN2 SDIN3 SDOUT SCL/CCLK SDA/CDIN AD0/CS RESET MUTEC VL VD DGND 16 AINR+ 17 AINR20 AINL+ 19 AINLFILT AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 Output Buffer4 AINR+ AINRAINL+ AINL- 18 FILT 23 24 25 26 27 28 AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 TP4 TP6 TP8 TP10 AOUT4 IN MUTE Out4 TP13 + C5 TP15 TP17 TP19 TP21 TP22 TP24 10uf GND Output Buffer5 C6 47nf AOUT5 GND IN MUTE Out5 VA AGND 21 22 VA TP27 Output Buffer6 AOUT6 + C8 C12 47nf CS4228A-KS C13 47nf 10uf MUTE IN MUTE Out6 GND GND Control Switches X_CTRL SDIN_CTRL CTRL_MODE SDOUT MODE_CTRL[9..0] X_CTRL SDIN_CTRL CTRL_MODE SDOUT_LOAD MODE_CTRL[9..0] CONTROL J3 TERMINAL BLUE +12V RESETn D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn Parallel Port J4 TERMINAL BLACK GND 1 J5 TERMINAL GREEN D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn TX_CBL TX_C TX_U RX_CBL RX_C RX_U RXPWR RX_VERF RX_ERF MRESETn -12V D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn TX_CBL TX_C TX_U RX_CBL RX_C RX_U RXPWR RX_VERF RX_ERF MRESETn Power 1 +12VBUS GND -12VBUS +5VBUS +12VBUS GND -12VBUS +5VBUS PPRESETn X_RESETn MRESETn MUTEC MUTE PPRESETn X_RESETn MRESETn MUTEC MUTE Reference Clock Programmable Logic Host Interface PPRESETn 1 SCL SDA/CDOUT CDIN AD0/CS SCLK LRCLK SDIN[3..1] DAP_SDIN[3..1] SPDIF_SDOUT SDIN_CTRL TX_M[2..0] RX_M[3..0] DAP_CTRL REFCLK_CTRL[3..0] X_CTRL CTRL_MODE CLKIN TX_MCLK MODE_CTRL[9..0] SCL SDA/CDIN MUTEC AD0/CS SCLK LRCLK SDIN[3..1] DAP_SDIN[3..1] SPDIF_SDOUT SDIN_CTRL SPDIF_MCLK DAP_MCLK REFCLK_CTRL[3..0] TX_M[2..0] RX_M[3..0] DAP_CTRL REFCLK_CTRL[3..0] REFCLK CLKIN R104 75 GND DAP_MCLK SCLK LRCLK SDOUT DAP_CTRL X_CTRL CTRL_MODE CLKIN TX_MCLK MODE_CTRL[9..0] SPDIF_MCLK DAP_MCLK REFCLK_CTRL[3..0] RefClk SDIN1 SDIN2 SDIN3 Digital Audio Port (DAP)/External Control DAP_SDIN[3..1] MCLK DAP_SDIN[3..1] SCLK SDA/CDIN LRCLK X_SDA SCL DAP_SDOUT X_SCL AD0/CS X_AD0/CS X_RESETn DAP_CTRL X_RESETn MUTEC MUTEC DAP PLD Power J6 TERMINAL RED +5V 1 9 CDB4228A Figure 1. CDB4228A Top Level Schematic CDB4228A C80 100pf R75 OUTL- R76 4.99k -12V R77 10k C83 4 8 + + 3 - 2 C82 2.2nf 47nf GND R79 10k U14A 1 U14B 6 5 + R78 10k - C84 10uf AINL 150 C81 100pf R80 7 MC33078 OUTL+ MC33078 150 C85 47nf +12V TP86 GND R81 10k VA + C86 +12V C88 47nf GND R82 8.25k C87 47nf 10uf GND GND 8 U15B MC33078 + C89 10uf 3 2 5 + 6 - R84 + 1 4 AINR R85 10k GND C90 U15A MC33078 47nf GND R83 7 OUTR+ 150 10k R86 10k -12V C91 2.2nf C92 R87 4.99k 100pf R88 OUTR- C93 100pf 150 Figure 2. Analog Input Filter 10 DS511DB1 VCC 2 2 VCC 2 DS511DB1 VCC D3 GREEN LED D4 GREEN LED D5 GREEN LED I2C PPORT SPDIF R42 374 R43 R44 374 374 X_CT RL SDIN_CTRL 2 1 3 4 6 1 3 CONTROL PORT MODE SELECT SPI/2wire CONTROL SOURCE XTERNAL/PPORTn S3 SW SPDT GND GND GND VCC 1 S2 SW SPDT S4 SW DPDT 3 5 2 CTRL_MO DE 2 R41 33k 1 1 1 SDOUT_LOAD SERIAL CONTROL DAP/SPDIFn GND VCC VCC 1 2 3 4 5 6 7 8 9 10 RP10 10k RPACK9 VCC R96 10k MODE_CTRL[9..0] L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 SMODE4 SMODE3 SMODE2 SMODE1 SMODE0 MCLK_SEL2 MCLK_SEL1 MCLK_SEL0 TX_MCLK_RATE1 TX_MCLK_RATE0 20 19 18 17 16 15 14 13 12 11 MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR 0 ON S6 SW DIP10 GND Figure 3. External Control 11 CDB4228A 1 2 3 4 5 6 7 8 9 10 1 12 VCC C76 47nf C77 47nf C78 47nf C79 47nf GND U12 R105 75 GND JP8 TP82 1 3 5 7 9 11 13 15 17 19 18 17 16 15 14 13 12 11 2 4 6 8 10 12 14 16 18 20 TP83 MC LK R66 R68 33 33 TP84 X_DAP_SDOUT X_DAP_SDIN1 X_DAP_SDIN2 X_DAP_SDIN3 B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 G DIR 2 3 4 5 6 7 8 9 R67 R69 33 33 SCLK LRCLK 19 1 DAP_CTRL 74HC245AW M GND TP85 HEADER 10X2 GND Digital Audio Port (DAP) U13 DAP_SDIN[3..1] DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 R70 R71 R72 R73 2 3 4 5 6 7 8 9 33 33 33 33 19 1 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 X_DAP_SDIN1 X_DAP_SDIN2 X_DAP_SDIN3 DAP_SDOUT G DIR 74HC245AW M GND VCC R74 10k JP9 2 4 6 8 10 X_SD A X_SC L X_AD0/CS X_RES ETn MUTEC HEADER 5X2 XTERNAL CONTROL GND DS511DB1 Figure 4. Digital Audio Port CDB4228A 1 3 5 7 9 DS511DB1 C38 1nf TP65 +12V C39 47nf GND C40 + 2 - U7A 1 R15 MC330 78 604 J8 PHONO JACK RA 1 R16 100k 10uf 4 C41 1nf 3 + IN 2 R14 3.16k 8 R13 3.16k C42 47nf GND GND 3 GND -12V Q1 2SC3326 2 MU TE R19 R17 C117 3.16k 47nf 1 R18 GND 1.78k GND GND 3.16k GND C43 100pf Figure 5. Analog Output Filter 1 CDB4228A 13 14 TP77 C52 1nf C53 IN C54 1nf 5 + 6 - U7B 7 R29 MC330 78 604 J10 PHONO JACK RA 1 R30 100k 10uf 2 R28 3.16k + R27 3.16k GND GND GND R32 1.78k Q2 2SC3326 2 MU TE 3.16k 1 GND 3 R31 C118 47nf C55 R33 3.16k GND 100pf GND Figure 6. Analog Output Filter 2 CDB4228A DS511DB1 DS511DB1 C56 1nf TP78 +12V C57 47nf GND C58 2 - R36 MC330 78 604 J11 PHONO JACK RA 1 R37 100k 10uf 4 C59 1nf + U10A 1 + IN 3 2 R35 3.16k 8 R34 3.16k C60 47nf GND GND 3 GND -12V Q3 2SC3326 2 MUT E R40 1 R39 GND 1.78k GND C119 47nf R38 3.16k GND 3.16k C61 GND 100pf Figure 7. Analog Output Filter 3 CDB4228A 15 16 C62 1nf C63 IN C64 1nf 5 + 6 - U10B 7 R47 MC330 78 604 J12 PHONO JACK RA 1 R48 100k 10uf 2 R46 3.16k + R45 3.16k TP79 GND GND R49 R50 3.16k 1.78k 3 GND Q4 2SC3326 2 MUT E 1 GND C120 47nf C65 R51 3.16k GND 100pf GND Figure 8. Analog Output Filter 4 CDB4228A DS511DB1 DS511DB1 C66 1nf TP80 +12V C67 47nf GND C68 + 2 - U11A 1 R54 MC3307 8 604 J13 PHONO JACK RA 1 R55 100k 10uf 4 C69 1nf 3 + IN 2 R53 3.16k 8 R52 3.16k C70 47nf GND GND 3 GND -12V Q5 2SC3326 2 MUT E R58 1 R57 GND 1.78k GND C121 47nf R56 3.16k GND 3.16k GND C71 100pf 17 CDB4228A Figure 9. Analog Output Filter 5 18 C72 1nf C73 IN C74 1nf 5 + 6 - U11B 7 R61 MC3307 8 604 J14 PHONO JACK RA 1 R62 100k 10uf 2 R60 3.16k + R59 3.16k TP81 GND GND R63 3 GND R64 Q6 2SC3326 2 MUT E GND 1 1.78k 3.16k C75 C122 47nf R65 3.16k GND GND 100pf Figure 10. Analog Output Filter 6 CDB4228A DS511DB1 DS511DB1 + R3 10k From DAC R1 100K C1 10uF Mute R2 100k To Amp C2 3.3nF Mute Control 19 CDB4228A Figure 11. Low Cost Analog Output Filter 20 RP4 1k RPACK9 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 RP5 1k RPACK9 VCC TP87 VCC RP6 PP_D0 PP_D1 PP_D2 PP_D3 PP_D4 PP_D5 PP_D6 PP_D7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D[7..0] D0 D1 D2 D3 D4 D5 D6 D7 RP7 PP_nSTROBE nAUTOFEED nINIT nSELECTIN 1 2 3 4 5 6 7 8 TP89 TP91 TP93 TP95 4.7k RPACK8 16 15 14 13 12 11 10 9 STROBEn A0 A1 TP88 TP90 TP92 TP94 TP96 A[1..0] 4.7k RPACK8 RP8 1k RPACK9 PP_D4 VCC PP_D5 PP_D6 PP_D7 PP_nACK nBUSY RP9 ACKn TP97 TP99 TP101 nBUSY PE SELEC T nERROR PE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 22 RPACK8 PP_nACK STATUS STATUS STATUS STATUS 0 1 2 3 TP98 TP100 TP102 STATUS[3..0] SELEC T GND DS511DB1 Figure 12. Control Port Interface CDB4228A J15 DB25M_R A RESET n 1 2 3 4 5 6 7 8 9 10 PP_nSTROBE nAUTOFEED PP_D0 nERROR PP_D1 nINIT PP_D2 nSELECTIN PP_D3 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DS511DB1 RP3 1k RPACK9 MODE_CTRL[9..0] 1 2 3 4 5 6 7 8 9 10 MODE_CTRL0 MODE_CTRL1 MODE_CTRL2 MODE_CTRL3 MODE_CTRL4 MODE_CTRL5 MODE_CTRL6 MODE_CTRL7 MODE_CTRL8 MODE_CTRL9 JP7 VCC TCK TDO TMS 1 3 5 7 9 TDI 2 4 6 8 10 VCC HEADER 5X2 GND U6 MODE_CTRL6 MODE_CTRL7 MODE_CTRL8 MODE_CTRL9 D0 STATUS3 D1 A0 D2 A1 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A[1..0] A0 A1 ACKn STATUS0 STATUS1 STATUS2 STATUS[3..0] TP51 TP53 STATUS0 STATUS1 STATUS2 STATUS3 CTRL_MODE X_CTRL SDIN_CTRL TP56 R EFCLK_CTRL[3..0] RX_VERF RX_ERF REFCLK_CTRL0 REFCLK_CTRL1 REFCLK_CTRL2 REFCLK_CTRL3 TP55 TP58 SPDIF_ERRORn RESET_LED TP61 SDIN1 SDIN2 SDIN3 SPDIF_SDOUT REFCLK_CTRL0 REFCLK_CTRL1 REFCLK_CTRL2 REFCLK_CTRL3 TP64 SDIN[3..1] SDIN1 SDIN2 SDIN3 VD VCC DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 1 3 +5V 39 91 3 18 34 51 66 82 VCC JP10 +3.3V DAP_SDIN[3..1] 2 4 HEADER 2X2 PLD PWR SEL SPDIF_SDOUT 1 2 5 6 7 8 9 10 12 13 14 16 17 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 40 41 42 44 45 46 47 48 49 50 SPDIF_SDOUT TDI TMS TCK TDO IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38 IO39 IO40 IO41 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO58 IO59 IO60 IO61 IO62 IO63 IO64 IO65 IO66 IO67 IO68 IO69 IO70 IO71 IO72 IO73 IO74 IO75 IO76 VCCINT1 VCCINT2 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 4 15 62 73 52 53 54 55 56 57 58 60 61 63 64 65 67 68 69 70 71 72 75 76 77 78 79 80 81 83 84 85 92 93 94 96 97 98 99 100 TDI TMS TCK TDO TP43 CDIN AD0/CS SDA/CDOUT SCL HALFSCLK TP47 TP48 SCLK LRCLK TP49 TP50 RX_C RX_U RX_CBL RX_M3 RX_M2 RX_M0 RX_M1 MODE_CTRL0 MODE_CTRL1 MODE_CTRL2 TX_M[2..0] TX_M0 TX_M1 TX_M2 RX_M[3..0] TX_C TX_U TX_CBL TX_M0 TX_M1 TX_M2 MODE_CTRL3 RX_M0 RX_M1 RX_M2 RX_M3 TP60 MODE_CTRL4 MODE_CTRL5 DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 DAP_CTRL TX_MCLK VCC GNDINT1 GNDINT2 GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 38 86 11 26 43 59 74 95 R11 374 VCC R12 374 D1 RED LED EPM7128STC100-15 2 D[7..0] GCLK1 GCLRn OE1 OE2/GCLK2 2 87 89 88 90 STROBEn MRESETn RXPWR CLKIN GND D2 RED LED C27 47nf C28 47nf C29 47nf C30 47nf C31 47nf C32 47nf SPDIF_ERRORn 1 + C20 10uf 1 RESET_LED + C19 10uf GND VCC 10uf C34 47nf C35 47nf GND Figure 13. Programmable Logic 21 CDB4228A + C33 22 Analog Supply Voltage +12V TP105 R89 1k L3 2 2 +12VBUS + C94 D11 P6KE13A C100 47nf C101 47nf C109 47nf C103 47nf 22uf D6 GREEN LED + C95 + C96 + C97 + C98 + C99 10uf 10uf 10uf 10uf 10uf + C104 + C105 + C106 + C107 + C108 TP106 TP107 TP108 1 D12 P6KE13A 2 2 1 13V + C102 13V 10uf R90 1k L4 1 GND 22uf 10uf 10uf 10uf 10uf D7 GREEN LED 1 -12VBUS Analog Supply Voltage -12V TP109 VA +5V Analog Supply Voltage TP115 L5 + C110 22uf C111 47nf GND 5V Digital Supply Voltage VCC VD TP110 TP111 TP112 U16 LT1086CT-3.3 L6 3 VIN VOUT 3.3V Digital Supply Voltage TP114 ADJ +5VBUS TP103 2 R91 + C112 374 22uf 1 2 C115 47nf R92 121 1 D8 GND GREEN LED 1 6.8V + C114 47nf C113 22uf 2 D13 P6KE6.8A R93 500 POT 1 2 GND + C116 R94 0 3 22uf GND GND GND GND TP104 D9 1N4148 2 1 X_RESETn VL MRESETn D10 1N4148 2 1 PPRESETn MRESETn 2 VCC RESETn GND 5 1 MUTEC D15 1N4148 2 1 3 2 TP116 2 Q8 MUN2211T1 3 3 MUTE R97 10k 1 DS1233-10 1 GND DS511DB1 GND GND -12V Figure 14. Power Supply CDB4228A MUTEC U17 4 3 R95 0 Q7 MUN2111T1 VCC S5 PTS645TL50 1 2 D14 1N4148 2 1 DS511DB1 OFF VCC 3 2 1 JP1 HDR3X1 ON OSC U1 1 7 NC GND +5V CLKOUT 14 C1 47nf 8 C2 47nf 12.2880 MHZ GND GND GND R1 OSC TP1 TP2 33 U2A 74AC125SC 3 JP2 OSC SPDIF_MCLK MUX_ MCLK 1 2 REFCLK_CTRL3 2 4 6 1 3 5 REFCLK REFCLK HEADER 3X2 REFCLK SELECT U2B 74AC125SC SPDIF_MCLK 5 R2 R3 33 0 6 4 SPDIF_MCLK REFCLK_CTRL2 U2C 74AC125SC DAP_MCLK 9 8 10 DAP_MCLK R106 75 REFCLK_CTRL1 R4 33 U2D 74AC125SC GND 12 REFCLK 13 11 REFCLK_CTRL0 REFCLK_CTRL[3..0] C3 47nf GND C4 47nf GND Figure 15. Master Clock Circuit 23 CDB4228A VCC 24 RXPWR L1 U8 22 C44 47nf C48 C45 47nf R21 21 68nf NPO GND VCC OUT M[3..0] 16 13 M3 M2 M1 M0 3 GND 17 18 24 23 C50 1 9 C51 FILT VERF ERF CBL U C C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2 C46 47nf 8 C47 47nf 10 SEL CS12/FCK M3 M2 M1 M0 RXP RXN MCK SCK FSYNC SDATA 28 25 15 14 1 6 5 4 3 2 27 19 12 11 26 RX_CB L RX_U RX_C TP70 TP71 TP72 TP73 TP75 TP76 TP74 MCL K S1 R22 R23 R24 R25 CS8414-CS 47nf TP66 TP67 TP68 RX_VERF RX_ERF GND 33 33 33 33 1 2 3 6 5 4 VCC SCLK FSYNC SW DIP-3 PWR DOWN SDOUT 2 6 5 4 2 CASE2 CASE1 GND2 GND1 47nf J9 PHONO JACK RA 1 DGND R20 10k 7 GND TP69 C49 47nf AGND 470 L2 47uH U9 TORX 173 VD+ GND 20 VCC VA+ R26 75 1% GND GND Figure 16. CS8414 Digital Audio Receiver CDB4228A DS511DB1 DS511DB1 RP1 1 10k RPACK9 RP2 1 10k RPACK9 VCC 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 GND TRNPT/FC1 nPRO V C/SBF U nC9/nC15 EM0/nC9 TP28 TP30 TP32 TP34 TP36 TP38 TP39 TP40 nC7/nC3 nC1/FC0 nC6/nC2 EM1/nC8 TP29 TP31 TP33 TP35 TP37 GND VCC VCC U4 C16 47nf 18 nMRE SET 16 VD+ GND GND RESET n MCL K SCLK LRCLK SDIN MCL K SCLK LRCLK 5 6 7 8 RST TRNPT/FC1 C7/C3 PRO C1/FC0 C6/C2 C9/C15 EM1/C8 EM0/C9 M2 M1 M0 MCK SCK FSYNC SDATA TX_C TX_U 9 10 11 TRNPT/FC1 nC7/nC3 nPRO nC1/FC0 nC6/nC2 nC9/nC15 EM1/nC8 EM0/nC9 23 22 21 M2 M1 M0 M[2..0] VCC C17 47nf U5 TO TX173 3 R8 CBL/SBC V C/SBF U 24 1 2 3 4 12 13 14 V C/SBF U TXP TXN 15 2 TX_C BL GND 8.25k 20 4 VCC R IN 17 CS8404A-CS R9 374 2 3 4 1 6 J7 PHONO JACK RA 1 1 C18 1% 5 GND GND GND Figure 17. CS8404 Digital Audio Transmitter T1 67129600 25 CDB4228A R10 93.1 1% 2 47nf CASE1 CASE2 C15 47nf GND TP41 5 6 19 CDB4228A Figure 18. Silkscreen Top 26 DS511DB1 CDB4228A Figure 19. Top Side DS511DB1 27 CDB4228A Figure 20. Level 2 Ground Plane 28 DS511DB1 CDB4228A Figure 21. Level 3 DS511DB1 29 CDB4228A Figure 22. Bottom Side 30 DS511DB1 DS511DB1 10. BILL OF MATERIALS Item 1 Qnty 55 Value 47nf Mfg KEMET Mfg P/N Description C1206C473K5R CAP, CERAMIC, 47NF, 50V, 10%, X7R, AC 1206 10uf PANASONIC ECEV1CS100SR CAP, ELECT, 10UF, 16V, 20%, AL, SM_A CSP_ELEC_130SQ 1nf KEMET 100pf KEMET 1 Reference C1,C2,C3,C4,C6,C9,C12, C13,C15,C16,C17,C18,C27, C28,C29,C30,C31,C32,C34, C35,C39,C42,C44,C45,C46, C47,C49,C50,C51,C57,C60, C67,C70,C76,C77,C78,C79, C83,C85,C87,C88,C90,C100, C101,C103,C109,C111,C114, C115,C117,C118,C119,C120, C121,C122 C5,C7,C8,C19,C20,C33,C40, C53,C58,C63,C68,C73,C84, C86,C89,C95,C96,C97,C98, C99,C104,C105,C106,C107,C108 C38,C41,C52,C54,C56,C59, C62,C64,C66,C69,C72,C74 C43,C55,C61,C65,C71,C75, C80,C81,C92,C93 C48 2 25 3 12 4 10 5 68nf KEMET 6 2 C82,C91 2.2nf KEMET 7 6 C94,C102,C110,C112,C113,C116 22uf CAP, CERAMIC, 1NF, 100V, 5%, NPO, 1206 CAP, CERAMIC, 100PF, 100V, 5%, NPO, 1206 CAP, CERAMIC, 68NF, 50V, 10%, X7R, 1206 CAP, CERAMIC, 2.2NF, 50V, 5%, NPO, 1206 CAP, ELECT, 22UF, 25V, 20%, AL, SM_D CSP_ELEC_260SQ 8 2 D2,D1 PANASONIC LITEON C1206C102J1G AC C1206C101J1G AC C1206C683K5R AC C1206C222J1G AC ECEV1EA220SP LT1139 LED, RED, DIFF, T1 LED_T-1 9 6 D3,D4,D5,D6,D7,D8 LITEON LT1142 LED, GREEN, DIFF, T1 LED_T-1 10 11 4 2 D9,D10,D14,D15 D11,D12 1N4148 P6KE13A DIODE, SWITCHING, DO35 DIODE, ZENER, 13V, DO7 DO35 DO7 12 1 D13 P6KE6.8A DIODE, ZENER, 6.8V, DO7 DO7 13 1 JP1 LITEON MOTOROLA MOTOROLA SAMTEC HEADER, MALE, 3X1 HDR3X1 14 1 JP2 HEADER, MALE, 3X2 HDR3X2 15 6 JP3,JP4,JP5,JP6,JP10,JP11 TSW-103-07-GS TSW-103-07-GD TSW-102-07-GD HEADER, MALE, 2X2 HDR2X2 RED LED GREEN LED 1N4148 P6KE13 A P6KE6.8 A HDR3X1 Table 6. Bill of Materials CSN_1206 CSN_1206 CSN_1206 CSN_1206 31 CDB4228A HEADE SAMTEC R 3X2 HEADE SAMTEC R 2X2 PCB Footprint CSN_1206 32 2 JP7,JP9 17 1 JP8 18 10 J1,J2,J7,J8,J9,J10,J11, J12,J13,J14 19 1 J3 20 1 J4 21 1 J5 22 1 J6 23 1 J15 24 5 L1,L3,L4,L5,L6 25 1 L2 26 6 Q1,Q2,Q3,Q4,Q5,Q6 27 1 Q7 28 1 Q8 29 3 RP1,RP2,RP10 30 4 RP3,RP4,RP5,RP8 31 2 RP7,RP6 32 1 RP9 33 15 R1,R2,R4,R22,R23,R24,R25, R66,R67,R68,R69,R70,R71, R72,R73 HEADE R 5X2 HEADE R 10X2 PHONO JACK RA TERMINAL BLUE TERMINAL BLACK TERMINAL GREEN TERMINAL RED DB25M_ RA ELDR25 SAMTEC TSW-105-07-GD SAMTEC TSW-110-07-GD A/D ELECT ARJ2018 HEADER, MALE, 5X2 HDR5X2 HEADER, MALE, 10X2 HDR10X2 PHONO JACK, RA, GOLD CON_RCA_RA E.F.JOHNS 111-0110-001 ON BINDING POST, BLUE, BPOST CON-BINDPOST E.F.JOHNS 111-0103-001 ON BINDING POST, BLACK, BPOST CON-BINDPOST E.F.JOHNS 111-0104-001 ON BINDING POST, GREEN, BPOST CON-BINDPOST E.F.JOHNS 111-0102-001 ON BINDING POST, RED, BPOST CON-BINDPOST DB25-PL-24 CONNECTOR, DB25, MALE, RA CON_DB25M_RA EXC-ELDR25 FERRITE, RADIAL, RADIAL200 EXC-ELDR25 8230-60 INDUCTOR, 47UH, SHIELDED, IND500 IND500 2SC3326 BJT, NPN, MUTE, SC59 SC59 MUN2111T1 BJT, PNP, 10K INTERNAL BIAS, SC59 SC59 MUN2211T1 BJT, NPN, 10K INTERNAL BIAS, SC59 SC59 4610X-101-103 RES, R-PACK9, 10K, 1/8W, 2%, SIP10 SIP10 4610X-101-102 RES, RPACK9, 1K, 1/8W, 2%, SIP10 SIP10 4816P-T01-472 RES, RPACK8, 4.7K, 1/8W, 2%, SOM16 SO16-220 4816P-T01-220 RES, RPACK8, 22, 1/8W, 2%, SOM16 SO16-220 ERJ-8GEYJ330 RES, THICK FILM, 33, 1/8W, 5%, 1206 RES_1206 ADAM TECH PANASONIC 47uH J.W. MILLER 2SC332 TOSHIBA 6 MUN211 MOTOR1T1 OLA MUN221 MOTOR1T1 OLA 10k BOURNS RPACK9 1k BOURNS RPACK9 4.7k BOURNS RPACK8 22 BOURNS RPACK8 33 PANASONIC Table 6. Bill of Materials CDB4228A DS511DB1 16 DS511DB1 34 35 3 13 36 25 37 38 7 R9,R11,R12,R42,R43,R44,R91 374 39 1 R10 93.1 40 6 R15,R29,R36,R47,R54,R61 604 41 6 R16,R30,R37,R48,R55,R62 100k 42 6 R19,R32,R40,R50,R58,R64 1.78k 43 1 R21 470 44 4 R26,R104,R105,R106 75 45 1 R41 33k 46 10 150 47 2 R75,R80,R83,R88,R98,R99, R100,R101,R102,R103 R76,R87 48 2 R89,R90 1k 49 1 R92 121 50 1 R93 51 1 S1 52 2 S3,S2 53 1 S4 500 3296Y-501 POT SW DIP- GRAYHILL 76SB03 3 SW C&K TS01CBE SPDT SW AUGUAT TSS21NGPC DPDT 3.16k 8.25k 4.99k YAGEO PANASONIC PANASONIC ERJ-8GEYJ000 ERJ-8ENF1002 RES, 0 OHM JUMPER, 1/8W, 1206 RES, THICK FILM, 10K, 1/8W, 1%, 1206 RES_1206 RES_1206 ERJ-8ENF3161 RES, THICK FILM, 3.16K, 1/8W, 1%, 1206 RES_1206 PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC BOURNS ERJ-8ENF8251 RES_1206 ERJ-8ENF3740 RES, THICK FILM, 8.25K, 1/8W, 1%, 1206 RES, THICK FILM, 374, 1/8W, 1%, 1206 RES_1206 ERJ-8ENF93R1 RES, THICK FILM, 93.1, 1/8W 1%, 1206 RES_1206 ERJ-8ENF6040 RES, THICK FILM, 604, 1/8W, 1%, 1206 RES_1206 ERJ-8GEYJ104 RES, THICK FILM, 100K, 1/8W, 5%, 1206 RES_1206 ERJ-8ENF1781 ERJ-8GEYJ470 RES, THICK FILM, 1.78K, 1/8W, 1%, 1206 RES, THICK FILM, 470, 1/8W, 5%, 1206 RES_1206 ERJ-8ENF75R0 RES, THICK FILM, 75, 1/8W, 1%, 1206 RES_1206 ERJ-8GEYJ333 RES, THICK FILM, 33K, 1/8W, 5%, 1206 RES_1206 ERJ-8ENF1500 RES, THICK FILM, 150, 1/8W, 1%, 1206 RES_1206 ERJ-8ENF4991 RES_1206 ERJ-8GEYJ102 RES, THICK FILM, 4.99K, 1/8W, 1%, 1206 RES, THICK FILM, 1K, 1/8W, 5%, 1206 RES_1206 ERJ-8ENF1210 RES, THICK FILM, 121, 1/8W, 1%, 1206 RES_1206 POTENTIOMETER, 25T, TOP ADJ, 500, 3296Y SWITCH, DIP, 3 POS, ROCKER, DIP6 POT_BRNS_3296Y SWITCH, SLIDE, SPDT SW_CK_TS01CBE SWITCH, SLIDE, DPDT SW_AGT_TSS21NG PC Table 6. Bill of Materials RES_1206 SW-DIP3 33 CDB4228A 0 10k 2 R3,R94,R95 R5,R7,R20,R74,R77,R78, R79,R81,R84,R85,R86,R96,R97 R6,R13,R14,R17,R18,R27, R28,R31,R33,R34,R35,R38, R39,R45,R46,R49,R51,R52, R53,R56,R57,R59,R60,R63,R65 R8,R82 34 1 55 1 56 106 57 1 58 1 59 1 60 1 61 1 62 1 63 1 64 5 S5 PTS645 C&K TL50 S6 SW GRAYHILL DIP10 TP1,TP2,TP3,TP4,TP5,TP6,TP7, TEST TP8,TP9,TP10,TP11,TP12,TP13, POINT TP14,TP15,TP16,TP17,TP18, TP19,TP20,TP21,TP22,TP23, TP24,TP25,TP26,TP27,TP28, TP29,TP30,TP31,TP32,TP33, TP34,TP35,TP36,TP37,TP38, TP39,TP40,TP41,TP43,TP47, TP48,TP49,TP50,TP51,TP53, TP55,TP56,TP58,TP60,TP61, TP64,TP65,TP66,TP67,TP68, TP69,TP70,TP71,TP72,TP73, TP74,TP75,TP76,TP77,TP78, TP79,TP80,TP81,TP82,TP83, TP84,TP85,TP86,TP87,TP88, TP89,TP90,TP91,TP92,TP93, TP94,TP95,TP96,TP97,TP98, TP99,TP100,TP101,TP102, TP103,TP104,TP105,TP106, TP107,TP108,TP109,TP110, TP111,TP112,TP113,TP114, TP115,TP116 T1 6712960 SCHOTT 0 U1 12.2880 CAL MHZ CRYSTAL U2 74AC12 FAIR5SC CHILD U3 CS4228 CRYSTAL A-KS U4 CS8404 CRYSTAL A-CS U5 TOTX17 TOSHIBA 3 U6 EPM712 ALTERA 8STC10 0-15 U7,U10,U11,U14,U15 MC3307 MOTOR8 OLA PTS645TL50 76SB10 SWITCH, 6MM TACT W/ ESD PIN, SW-MOM-C&K 130GF, DPST SWITCH, DIP, 10 POS, ROCKER, DIP20 SW-DIP10 - TEST POINT, PAD60R40 TESTPOINT 67129600 XFMR, PULSE, TH XFR_SC67129600 CX21AF12.2880MHZ 74AC125SC IC, OSCILLATOR, 12.2880MHZ, 50PPM, OSC-FULL OSC14 IC, TRISTATE BUFFER, QUAD, SO14 SO14-150 CS4228D-KS IC, CODEC, SSOP28 SSOP28-209 CS8404A-CS IC, SPDIF TX, SOIC24 SO24-300 TOTX173 IC, OPTICAL TXMTR TOTX173 EPM7128STC10 IC, CPLD, 128MC, 15NS, TQFP100 0-15 QFP100_14X14 MC33078D SO8-150 Table 6. Bill of Materials IC, OPAMP, DUAL, SO8 CDB4228A DS511DB1 54 DS511DB1 65 1 U8 66 1 U9 67 2 U13,U12 68 1 U16 69 1 U17 100 101 4 6 U1 - 102 6 - 103 104 105 106 4 4 3 2 J3,4,5,6 JP6, 10, 11 J15 107 2 J15 CS8414CS TORX17 3 74HC24 5AWM LT1086 CT-3.3 DS123310 CRYSTAL CS8414-CS IC, SPDIF RX, SOIC28 SO28-300 TOSHIBA TORX173 IC, OPTICAL RX TORX173 FAIRCHILD LINEAR MM74HC245AW IC, TRANCEIVER, HEX, SOW20 M LT1086CT-3.3 IC, VOLTAGE REG, POSITIVE, 3.3V, TO220 DS1233-10 IC, POWER SUPPLY MONITOR, TO92 DALLAS AUGUAT Keystone/DK MCMASTER CARR MOLEX 8134-HC-5P2 8401K-ND SO20-300 TO-220AB TO-92 SOCKET, PIN, POP-IN, SM 1/2" X 4-40 HEX STANDOFF 91773A108/PAN 4-40 3/8" MACHINE SCREW, PAN 4CR6SZ 15-29-1025 SHUNT, OPEN END Connect wire, 20GA, Stranded, 2" shorting jumper, 22GA, solid MACHINE SCREW, 6-32 x 1/2", PAN HEAD NUT, #6 Table 6. Bill of Materials CDB4228A 35