MIP7965 64-bit Superscaler Microprocessor

Standard Products
MIP 7965
64-Bit Superscaler Microprocessor
October 01, 2010
www.aeroflex.com/Avionics
FEATURES
❑
Upscreened PMC-Sierra RM7965
❑
Military and Industrial Grades Available
❑
CPU core with MIPS64™ compatible Instruction Set Architecture that features:
- 668 & 750 MHz
- Dual-issue superscalar 7-stage pipeline
- 16-KB, 4-way set associative L1 Instruction cache
- 16-KB, 4-way set associative L1 Data cache
- 256-KB, 4-way set associative L2 cache with industry best 5-cycle access latency
- Error Checking and Correcting (ECC) on L2 cache
- Fast Packet Cache™ to assist processing of packet data
- 8K-entry branch prediction table
- Fully associative 64-entry TLB with dual pages
- High performance Floating Point unit (IEEE 754)
- Fixed-point DSP instructions such as Multiply/Add, Multiply/Subtract and 3 Operand Multiply
❑
High-performance system interface:
- Multiple outstanding reads with out of order return
- 1600 MB/s peak throughput
- Multiplexed address/data bus (SysAD) supports 3.3V I/logic
- Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 10, 11, 12, 13, 14, 15, 16, 17
❑
Integrated on-chip EJTAG controller
❑
64-entry dynamic Trace Buffer for use in real-time trace and debug
❑
Two 32-bit virtually addressed Watch registers
❑
Integrated performance counters:
– Contains 2 independent 32-bit counters
– Counts over 30 processor events including mispredicted branches
– Enables full characterization and analysis of application software
❑
MIP7965 is available in a 256-TBGA package (27x27 mm):
– MIP7965 (256-TBGA) is pin compatible with RM7065C and RM7065A TBGA products.
– MIP7965 (208-lead CQFP, cavity-up package (F17)) is pin compatible with the ACT7000ASC
– MIP7965 (208-lead CQFP, inverted footprint (F24)), is pin compatible and with the same pin rotation
as the commercial PMC-Sierra RM5261A
NOTE: *MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra
SCD7965 Rev H
BLOCK DIAGRAM
SCD7965 Rev H 10/01/10
2
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INTRODUCTION
The MIP7965 comprise a new family of high-performance 64-bit microprocessors. This product is optimized for performance with
features including a seven-stage dual-issue pipeline, tightly coupled L1 and L2 caches, and sophisticated branch prediction for
maintaining pipeline efficiency.
A 200 MHz 64-bit multiplexed system address and data bus (SysAD) enables a high-bandwidth I/O interface to a variety of system
controllers providing connectivity to a wide range of networking peripherals. All products also contain vectored and prioritized
interrupt controllers for versatile interrupt configurations.
On-chip EJTAG debug modules ensure smooth and easy debugging for both hardware and software by allowing single-step and state
examination. The inclusion of a pipeline-rate branch instruction trace buffer facilitates debugging under operating conditions.
The MIP7965 is available in a 256-TBGA and 208-lead CQFP package. The 256-TBGA package is pin compatible with previous
RM7065x devices. The RM7965 products offer a cost advantage by eliminating the L3 cache controller functionality available with the
RM7900.
For additional Detail Information regarding the operation of the PMC-Sierra see the latest PMC-Sierra datasheet for the RM79xx
Family Microprocessors Data Sheet (doc. # PMC-2030581), Issue No. 11: September, 2006
SCD7965 Rev H 10/01/10
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PIN DESCRIPTIONS
The following is a list of control, data, clock, interrupt, and miscellaneous pins of MIP7965.
System Interface
PIN NAME
TYPE
DESCRIPTION
ExtRqst*
Input
External request
Signals that the external agent is submitting an external request.
Release*
Output
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on the bus and a valid
command or data identifier on the SysCmd bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
PRqst*
Output
Processor Request
When asserted this signal requests that control of the system interface be returned to the
processor.
PAck*
Input
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the processor that it has been
granted control of the system interface.
RspSwap*
Input
Response Swap
RspSwap* is used by the external agent to signal the processor when it is about to return a
memory reference out of order; i.e., of two outstanding memory references, the data for the
second reference is being returned ahead of the data for the first reference. In order that the
processor will have time to switch the address to the tertiary cache, this signal must be asserted
a minimum of two cycles prior to the data itself being presented. Note that this signal works as
a toggle; i.e., for each cycle that it is held asserted the order of return is reversed. By default,
anytime the processor issues a second read it is assumed that the reads will be returned in
order; i.e., no action is required if the reads are indeed returned in order.
RdType
Output
SysAD[63:0]
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
SysADC[7:0]
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
SysCmd[8:0]
Input/Output
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.
SysCmdP
Input/Output
System Command/Data Identifier Bus Parity
For the RM79xx, unused on input and zero on output.
SCD7965 Rev H 10/01/10
Release interface
Signals that the processor is releasing the system interface to slave state
Read Type
During the address cycle of a read request, RdType indicates whether the read request is an
instruction read or a data read.
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Clock/Control Interface
PIN NAME
TYPE
DESCRIPTION
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All output timings are relative
to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the
factor selected during boot initialization.
TYPE
DESCRIPTION
VccInt
Input
Power supply for core.
VccIO
Input
Power supply for I/O.
VccP
Input
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter
circuit. Note: Not applicable for the F17, F24 QFPs which incorporates the filter components
except for the 10µF capacitor. See "PLL Analog Power Filtering" section herein.
VccJ
Input
Power supply used for JTAG.
Vss
Input
Ground Return.
VssP
Input
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
Note: Not applicable for the F17, F24 QFPs which incorporates the filter components except
for the 10µF capacitor. See "PLL Analog Power Filtering" section herein.
PIN NAME
TYPE
DESCRIPTION
INT[9:0]*
Input
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register..
PIN NAME
TYPE
DESCRIPTION
JTDI/DBDI
Input
JTAG/EJTAG data in
JTAG/EJTAG serial data in.
JTCK/DBCK
Input
JTAG/EJTAG clock input
JTAG/EJTAG serial clock input.
JTDO/DBDO
Output
JTMS/DBMS
Input
JTAG/EJTAG command
JTAG/EJTAG command signal, signals that the incoming serial data is command data.
JTRST*/DBRST*
Input
JTAG/EJTAG reset.
JTAGSEL
Input
JTAG/EJTAG select Selects
JTAG when JTAGSEL=1; selects EJTAG when JTAGSEL=0
Power Supply
PIN NAME
Interrupt Interface
JTAG Interface
SCD7965 Rev H 10/01/10
JTAG/EJTAG data out
JTAG/EJTAG serial data out.
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Initialization Interface
PIN NAME
TYPE
DESCRIPTION
BigEndian
Input
Big Endian / Little Endian Control
Allows the system to change the processor addressing
VccOK
Input
Vcc is OK
When asserted, this signal indicates to the MIP7965 that the VccInt power supply has been
above the recommended value for more than 100 milliseconds and will remain stable. The
assertion of VccOK initiates the reading of the boot-time mode control serial stream.
ColdReset*
Input
Cold Reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted
synchronously with SysClock.
Reset*
Input
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or
asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be
de-asserted synchronously with SysClock.
ModeClock
Output
Modein
Input
SCD7965 Rev H 10/01/10
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and
fifty six.
Boot Mode Data In
Serial boot-mode data input.
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ABSOLUTE MAXIMUM RATINGS 1
SYMBOL
RATING
RANGE
UNITS
VTERM
Terminal Voltage with respect to Vss
-0.5 2 to +3.9
V
Tc
Operating Temperature
I = Commercial
R = Commercial
Class H = Extended, Screened
-40 to +85
-55 to +110
-55 to +110
•C
•C
•C
TSTG
Storage Temperature
-55 to +125
•C
IIN
DC Input Current
±20
mA
IOUT
DC Output Current 4
±20
mA
Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +3.95 Volts.
3. When VIN < 0V or VIN > VccIO.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 seconds.
RECOMMENDED OPERATING CONDITIONS
GRADE
CPU
SPEED
TEMP
(CASE)
Vss
VccInt
VccIO
VccP
VccJ
Commercial
(I)
750
MHz
-40°C to+85°C
0V
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
668
MHz
Commercial
(R)
750
MHz
-55°C to
+110°C
0V
668
MHz
Extended
Screened
(Class H)
668
MHz
-55°C to
+110°C
0V
Notes
1. VccIO should not exceed VccInt by greater than 2.5 V during the power-up sequence.
2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the
RM79xx User Manual.
4. VccP must be connected to VccInt through a passive filter circuit. See RM79xx User Manual for recommended circuit. Not applicable
for the F17, F24 QFP and Interposer evaluation board devices which incorporates the filter components except for the 10µF capacitor.
SCD7965 Rev H 10/01/10
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DC ELECTRICAL CHARACTERISTICS
VccIO = 3.15V to 3.45V
PARAMETER
MINIMUM
MAXIMUM
CONDITIONS
VOL
-
0.2V
|IOUT | = 100µA
VOH
VccIO - 0.2V
-
VOL
-
0.4V
VOH
2.4V
-
VIL
-0.3V
0.8V
VIH
2.0V
VccIO + 0.3V
IIN
-
±15µA
±15µA
|IOUT | = 2mA
VIN = 0
VIN = VccIO
POWER CONSUMPTION
CPU SPEED
PARAMETER
VCCINT
Power
(mWatts)
750MHz
(COMM)
668MHz
(COMM)
750MHz
(MIL)
668MHz
(MIL)
MAX
MAX
MAX
MAX
3000
3000
3000
3000
Maximum with no FPU operation 2
5000
4500
5000
4500
Maximum worst case instruction mix
5000
4500
5000
4500
CONDITIONS
Standby 5
Active 4
Notes:
1. Worst case supply voltage (maximum VccInt) with worst case temperature (maximum TCASE).
2. Dhrystone 2.1 instruction mix.
3. I/O supply power is application dependant, but typically <20% of VccInt.
4. IccInt active test limit set to 2.3 Amps during a stable program loop for measurement consistency.
5. IccInt standby test limit set to 1.2 Amps at 1.30 V and TCASE = 115°C.
SCD7965 Rev H 10/01/10
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AC CHARACTERISTICS
CAPACITIVE LOAD DERATION
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
Mode
CLD
Load Derate
-
2
ns/25pF
LVTTL
CLOCK PARAMETERS
BUS SPEED
PARAMETER
SYMBOL
TEST CONDITIONS
LVTTL
UNITS
MIN
MAX
SysClock High
tSCHigh
Transition < 2ns
3
-
ns
SysClock Low
tSCLow
Transition < 2ns
3
-
ns
33.3
100
MHz
tSCP
10
30
ns
Clock Jitter for SysClock
tJitterIn
-
±150
ps
SysClock Rise Time
tSCRise
-
2
ns
SysClock Fall Time
tSCFall
-
2
ns
ModeClock Period
tModeCKP
-
256
tSCP
JTAG Clock Period
tJTAGCKP
4
-
tSCP
SysClock Frequency1
SysClock Period
Notes:
1. Operation of the MIP7965 is only guaranteed with the Phase Loop enabled.
SYSTEM INTERFACE PARAMETERS
BUS SPEED
PARAMETER1
SYM
Data Output 2
tDO
TEST CONDITIONS
LVTTL I/O
UNITS
MIN
MAX
LVTTL (VccIO = 3.3V): mode[15:14] = 10 (fastest) 4,5,6
0.75
4.5
ns
LVTTL (VccIO = 3.3V): mode[15:14] = 01 (slowest)4,5,6
0.75
5.5
ns
Data Setup3
tDS5
tRISE = See above table
2.5
-
ns
Data Hold3
tDH
tFALL= See above table
1.0
-
ns
Notes
1. In LVTTL mode, timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O, and from 0.48 x VccIO
of clock to 0.48 x VccIO of signal for 2.5V I/O.
2. Capacitive load for all LVTTL maximum output timings is 50 pF. Minimum output timings are for theoretical no load conditions.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode [15:14] = 10 is tested and guaranteed.
SCD7965 Rev H 10/01/10
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TIMING DIAGRAMS
CLOCK TIMING
SysClock
tHigh
tRise
tLow
tFall
±tJitterin
SYSTEM INTERFACE TIMING
(SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
INPUT TIMING
SysClock
tDH
tDS
Data
Data
OUTPUT TIMING
SysClock
tDOmax
tDOmin
Data
SCD7965 Rev H 10/01/10
Data
10
Data
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THERMAL INFORMATION
This product is designed to operate over a wide temperature range when used with a heat sink.
Ambient
Device Compact Model 256-TBGA 2,3
Θ SA
θJC (°C/W)
0.43
θJB (°C/W)
2.92
ΘCS
θJA (°C/W)
15.85
Case
Heat Sink
ΘJC
Device Compact
Model
Junction
ΘJB
Board
Device Compact Model 208-Lead CQFP F17 and F24 2
θJC (°C/W)
1.28
Junction
ΘJC
Device Compact
Model
Case
Operating power is dissipated in any package (watts) offered at worst case power supply
Power at 750 MHz
VccInt = 1.3 V, VccIO = 3.3 V
5.0W
Power at 668 MHz
VccInt = 1.3 V, VccIO = 3.3 V
4.5W
Notes
1. Short-term is understood as the definition stated in Telcordia Generic Requirements GR-63-Core.
2. θJC, the junction-to-case thermal resistance, θJB, the junction-to-board thermal resistance are obtained from Package vendor.
3. θSA is the thermal resistance of the heat sink to ambient. θCS is the thermal resistance of the heat sink attached material.
SCD7965 Rev H 10/01/10
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PLL ANALOG POWER FILTERING
The MIP7965 includes extra PLL Analog Power Filtering circuitry designed to provide low noise, temperature stable filtering for
the VccP and VssP signals. The included circuitry consists of several passive components located at the closest possible point to
the MIP7965 die and is configured as shown below.
5.1 Ω
VccP
64
.01
µF
1000
pF
RM7965
Die
5.1 Ω
VssP
65
MIP7965 INCLUDING PLL FILTER CIRCUIT
Additional board level PPL filtering is also required. The recommended configuration is shown in below.
VccInt
64
VccP
65
VssP
10
µF
VssInt
RECOMMENDED BOARD LEVEL PLL FILTER CIRCUIT FOR THE MIP7965
SCD7965 Rev H 10/01/10
12
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MIP7965 256-TBGA PACKAGE OUTLINE
SCD7965 Rev H 10/01/10
13
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MIP7965 256-TBGA ALPHANUMERICAL PINOUT
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
A1
VccIO
B19
VccIO
D17
VccIO
J3
VccInt
A2
Vss
B20
Vss
D18
Do Not Connect
J4
VccIO
A3
Vss
C1
Vss
D19
Vss
J17
VccIO
A4
Do Not Connect
C2
Vss
D20
Do Not Connect
J18
SysAD54
A5
SysAD35
C3
VccIO
E1
SysAD5
J19
SysAD22
A6
Vss
C4
Do Not Connect
E2
Do Not Connect
J20
Vss
A7
SysAD33
C5
Do Not Connect
E3
VccInt
K1
SysAD41
A8
SysAD32
C6
Do Not Connect
E4
VccIO
K2
SysAD10
A9
Vss
C7
SysAD34
E17
VccIO
K3
SysAD42
A10
SysADC1
C8
VccInt
E18
Do Not Connect
K4
SysAD11
A11
Do Not Connect
C9
SysAD0
E19
Do Not Connect
K17
SysAD53
A12
Vss
C10
SysADC4
E20
SysAD59
K18
SysAD21
A13
SysADC2
C11
SysADC7
F1
Vss
K19
SysAD52
A14
SysAD62
C12
VccInt
F2
SysAD36
K20
SysAD20
A15
Vss
C13
SysAD31
F3
SysAD4
L1
SysAD43
A16
SysAD60
C14
SysAD61
F4
VccInt
L2
SysAD44
A17
Do Not Connect
C15
VccInt
F17
VccInt
L3
SysAD12
A18
Vss
C16
Do Not Connect
F18
SysAD27
L4
VccInt
A19
Vss
C17
Do Not Connect
F19
SysAD58
L17
VccInt
A20
VccIO
C18
VccIO
F20
Vss
L18
SysAD51
B1
Vss
C19
Vss
G1
SysAD38
L19
SysAD19
B2
VccIO
C20
Vss
G2
SysAD6
L20
SysAD50
B3
Vss
D1
Do Not Connect
G3
SysAD37
M1
Vss
B4
Vss
D2
Vss
G4
VccInt
M2
SysAD13
B5
Do Not Connect
D3
Do Not Connect
G17
VccInt
M3
SysAD45
B6
SysAD3
D4
VccIO
G18
SysAD26
M4
VccIO
B7
SysAD2
D5
VccIO
G19
SysAD57
M17
VccIO
B8
SysAD1
D6
Do Not Connect
G20
SysAD25
M18
SysAD18
B9
SysADC5
D7
VccInt
H1
SysAD7
M19
SysAD49
B10
SysADC0
D8
VccInt
H2
SysAD39
M20
Vss
B11
SysADC3
D9
VccIO
H3
SysAD40
N1
SysAD14
B12
SysADC6
D10
VccInt
H4
SysAD8
N2
SysAD46
B13
Do Not Connect
D11
VccInt
H17
SysAD24
N3
VccInt
B14
SysAD30
D12
VccIO
H18
SysAD56
N4
SysAD47
B15
SysAD29
D13
SysAD63
H19
SysAD55
N17
VccInt
B16
Do Not Connect
D14
VccInt
H20
SysAD23
N18
SysAD48
B17
Vss
D15
SysAD28
J1
Vss
N19
SysAD16
B18
Vss
D16
VccIO
J2
SysAD9
N20
SysAD17
SCD7965 Rev H 10/01/10
14
PIN
FUNCTION
Aeroflex Plainview
MIP7965 256-TBGA ALPHANUMERICAL PINOUT CON’T
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
P1
SysAD15
U15
INT3*
W13
SysCmd5
P2
RspSwap*
U16
VccIO
W14
SysCmdP
P3
PAck*
U17
VccIO
W15
VccInt
P4
VccInt
U18
INT6*
W16
INT1*
P17
ColdReset*
U19
Vss
W17
Vss
P18
VccOK
U20
INT7*
W18
Vss
P19
BigEndian
V1
Vss
W19
VccIO
P20
Reset*
V2
Vss
W20
Vss
R1
Vss
V3
VccIO
Y1
VccIO
R2
Do Not Connect
V4
RDType
Y2
Vss
R3
JTDI
V5
RdRdy*
Y3
Vss
R4
JTCK
V6
VccP
Y4
ModeIn
R17
VccInt
V7
Do Not Connect
Y5
ValidOut*
R18
ExtRqst*
V8
VccInt
Y6
Vss
R19
NMI*
V9
Do Not Connect
Y7
VccP
R20
Vss
V10
Do Not Connect
Y8
Do Not Connect
T1
PRqst*
V11
VccInt
Y9
Vss
T2
JTDO
V12
SysCmd3
Y10
Do Not Connect
T3
VccIO
V13
SysCmd6
Y11
SysCmd0
T4
JTRST*
V14
VccInt
Y12
Vss
T17
VccIO
V15
INT2*
Y13
SysCmd4
T18
VccInt
V16
INT5*
Y14
SysCmd8
T19
INT9*
V17
INT4*
Y15
Vss
T20
INT8*
V18
VccIO
Y16
VccJ
U1
ModeClock
V19
Vss
Y17
INT0*
U2
Vss
V20
Vss
Y18
Vss
U3
JTMS
W1
Vss
Y19
Vss
U4
VccIO
W2
VccIO
Y20
VccIO
U5
JTAGSEL
W3
VSS
U6
ValidIn*
W4
Vss
U7
VssP
W5
WrRdy*
U8
VccInt
W6
Release*
U9
VccIO
W7
SysClock
U10
VccInt
W8
VccInt
U11
VccInt
W9
Do Not Connect
U12
VccIO
W10
Do Not Connect
U13
SysCmd7
W11
SysCmd1
U14
VccInt
W12
SysCmd2
SCD7965 Rev H 10/01/10
15
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MIP7965 "F17" – CQFP 208 LEADS PACKAGE OUTLINE
1.131 (28.727) SQ
1.109 (28.169) SQ
53
104
52
.0236 (.51)
.0158 (.49)
105
Lid
.010R REF
.010R REF
.015 (.381)
.009 (.229)
.130 (3.302)
MAX
1.009 (25.63)
.9998 (25.37)
51 Spaces at .0197
(51 Spaces at .50)
0°±5°
.090 (2.286) REF
.010 (.253)
.007 (.178)
.050 (1.27)
.030 (.762)
Detail "A"
1
Pin 1 Chamfer
156
208
157
.960 (24.384) SQ
REF
Detail "A"
.055 (1.397)
REF
.005 (.127)
.008 (.202)
1.331 (33.807)
1.269 (32.233)
Units: Inches (Millimeters)
.115 (2.921)
MAX
.055 (1.397)
.045 (1.143)
Note: Pin rotation is opposite of PMC-Sierra PQUAD due to cavity-up construction.
MIP7965 "F24" – Inverted QFP 208 LEADS PACKAGE OUTLINE
1.131 (28.727) SQ
1.109 (28.169) SQ
156
105
157
.0236 (.51)
.0158 (.49)
104
.055 (1.397)
REF
.012R REF
.012R REF
1.009 (25.63)
.9998 (25.37)
51 Spaces at .0197
(51 Spaces at .50)
.055 (1.397)
.045 (1.143)
.115 (2.921)
MAX
0°±5°
Lid
.010 (.253)
.007 (.178)
.090 (2.286) REF
208
Pin 1 Chamfer
.055 (1.397)
.035 (.889)
53
1
52
Detail "A"
.139 (3.531)
MAX
Detail "A"
.005 (.127)
.008 (.202)
Units: Inches (Millimeters)
.960 (24.384) REF
.015 (.381)
.009 (.229)
1.331 (33.807)
1.291 (32.791)
Note: Pin rotation is Identical to PMC-Sierra PQUAD due to cavity-down construction.
SCD7965 Rev H 10/01/10
16
Aeroflex Plainview
MIP7965 208-LEAD CQFP PINOUTS – "F17" & "F24"
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
FUNCTION
VccIO
Do Not Connect
Do Not Connect
VccIO
Vss
SysAD4
SysAD36
SysAD5
SysAD37
VccInt
Vss
SysAD6
SysAD38
VccIO
Vss
SysAD7
SysAD39
SysAD8
SysAD40
VccInt
Vss
SysAD9
SysAD41
VccIO
Vss
SysAD10
SysAD42
SysAD11
SysAD43
VccInt
Vss
SysAD12
SysAD44
VccIO
Vss
SysAD13
SysAD45
SysAD14
SysAD46
VccInt
Vss
SysAD15
SysAD47
VccIO
Vss
ModeClock
JTDO
JTDI
JTCK
JTMS
VccIO
Vss
SCD7965 Rev H 10/01/10
PIN #
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
FUNCTION
PIN #
Do Not Connect
JTAGSEL
JTRST*
VccIO
Vss
ModeIn
RdRdy*
WrRdy*
ValidIn*
ValidOut*
Release*
VccP
VssP
SysClock
VccInt
Vss
VccIO
Vss
VccInt
Vss
SysCmd0
SysCmd1
SysCmd2
SysCmd3
VccIO
Vss
SysCmd4
SysCmd5
VccIO
Vss
SysCmd6
SysCmd7
SysCmd8
SysCmdP
VccInt
Vss
VccInt
Vss
VccIO
Vss
Int0*
Int1*
Int2*
Int3*
Int4*
Int5*
VccIO
Vss
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
17
FUNCTION
VccIO
NMI*
ExtRqst*
Reset*
ColdReset*
VccOK
BigEndian
VccIO
Vss
SysAD16
SysAD48
VccInt
Vss
SysAD17
SysAD49
SysAD18
SysAD50
VccIO
Vss
SysAD19
SysAD51
VccInt
Vss
SysAD20
SysAD52
SysAD21
SysAD53
VccIO
Vss
SysAD22
SysAD54
VccInt
Vss
SysAD23
SysAD55
SysAD24
SysAD56
VccIO
Vss
SysAD25
SysAD57
VccInt
Vss
SysAD26
SysAD58
SysAD27
SysAD59
VccIO
Vss
Do Not Connect
Do Not Connect
Vss
PIN #
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
FUNCTION
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
VccIO
Vss
SysAD28
SysAD60
SysAD29
SysAD61
VccInt
Vss
SysAD30
SysAD62
VccIO
Vss
SysAD31
SysAD63
SysADC2
SysADC6
VccInt
Vss
SysADC3
SysADC7
VccIO
Vss
SysADC0
SysADC4
VccInt
Vss
SysADC1
SysADC5
SysAD0
SysAD32
VccIO
Vss
SysAD1
SysAD33
VccInt
Vss
SysAD2
SysAD34
SysAD3
SysAD35
VccIO
Vss
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
VccIO
Vss
Aeroflex Plainview
SAMPLE ORDERING INFORMATION
PART NUMBER
SCREENING
MIP7965-750B1I
Industrial Temperature Range
-40°C to +85°C Testing
MIP7965-750F17I
PIPELINE FREQ
(MHZ) Note 3
PACKAGE
750
256-TBGA
750
208 Lead, CQFP, F17
668
208 Lead, CQFP, F24
MIP7965-668F24I
MIP7965-668B1R
Extended Temperature Range
-55°C to +110°C Testing
Note 2
MIP7965-750B1R
MIP7965-750F17T
MIP7965-668F24T Note 1
MIP7965-750F17M
MIP7965-668F24M Note 1
MIP7965-INT Note 4
668
256-TBGA
750
Military Temperature Range,
-55°C to +125°C Testing
750
208 Lead, CQFP, F17
668
208 Lead, CQFP, F24
Military Screened,
-45°C to +115°C Testing
Note 2
750
208 Lead, CQFP, F17
668
208 Lead, CQFP, F24
Engineering Evaluation Board
668
208 Lead, CQFP, F17
Notes
1. Contact Factory for availability.
2. Contact factory for military temperature range products (CQFP hermetic MCM package will be screened at -45°C to + 115°C).
3. Contact factory for higher speed product options.
4. Interposer evaluation board with MIPS7965-668B1 processor configured as 208 lead, F17 Foot Print.
PART NUMBER BREAKDOWN
MIP 7965 –
750
B1 I
Screening
MIPS Series
(AP Custom Series)
I = Industrial Temp, -40°C to +85°C
R = Extended Temp, -55°C to +110°C
T = Military Temp, -55°C to +125°C, Note 2
M = Military Temp, -45°C to +115°C, Screened * Note 2
Base Processor Type
Maximum Pipeline Frequency
750 = 750MHz
668 = 668MHz
Package Type & Size
B1 = 26mm Sq, 256-TBGA
F17 = 1.120" Sq, 208 Lead CQFP, Note 2 & 4
F24 = 1.120" Sq, Inverted 208 Lead CQFP, Note 2
* Screened to the individual test methods of MIL-STD-883
PLAINVIEW, NEW YORK
Toll Free: 800-THE-1553
Fax: 516-694-6715
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
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Tel: 603-888-3975
Fax: 603-888-4585
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
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Tel: 949-362-2260
Fax: 949-362-2266
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com
[email protected]
Aeroflex Microelectronic Solutions reserves the right to change at
any time without notice the specifications, design, function, or form
of its products described herein. All parameters must be validated for
each customer's application by engineering. No liability is assumed
as a result of use of this product. No patent licenses are implied. All
trademarks are acknowledged. Parent company Aeroflex, Inc. 2003.
SCD7965 Rev H 10/01/10
18
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