Standard Products MIP7365 64-Bit Superscaler Microprocessor February 17, 2012 FEATURES ❑ Upscreened PMC-Sierra RM7065C ❑ Military and Industrial Grades Available ❑ Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance o 450MHz operating frequency ❑ High-performance system interface o Multiplexed address/data bus (SysAD) supports 2.5V, 3.3V I/O logic o Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 o Support for 64-bit or 32-bit external agents ❑ Integrated primary and secondary caches o All are 4-way set associative with 32-byte line size o 16-Kbytes instruction, 16-Kbytes data, 256-Kbytes on-chip secondary o Per line cache locking in primaries and secondary o Fast Packet Cache™ increases system efficiency in networking applications ❑ High-performance floating-point unit — 1600MFLOPS maximum o Single cycle repeat rate for common single-precision operations and some double-precision operations o Single cycle repeat rate for single-precision combined multiply-add operations o Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations ❑ MIPS IV superset instruction set architecture o Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution o Single-cycle floating-point multiply-add ❑ Integrated memory management unit o Fully associative joint TLB (shared by I and D translations) o 64/48 dual entries map 128/96 pages o Variable page size ❑ Embedded application enhancements o Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply instruction (MUL) o I&D Test/Break-point (Watch) registers for emulation & debug o Performance counter for system and software tuning & debug o Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software ❑ Fully static CMOS design with dynamic power down logic ❑ 216-EPad LQFP 24x24mm are pin compatible with the RM7965 and RM5261A EPad™ products NOTE: 216-Enhanced Pad package, EPad MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra SCD7365 Rev D BLOCK DIAGRAM SCD7365 Rev D 2/17/12 2 Aeroflex Plainview DESCRIPTION The MIP7365 Microprocessor is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. The MIP7365 integrates 16 Kbytes 4-way set associative instruction and data caches along with an integrated 256 Kbytes 4-way set associative secondary cache. The primary data and secondary caches are write-back and non-blocking. The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system interface supporting multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts. The MIP7365 is available in a 216-EPad LQFP package and a 256-pin TBGA package. The 216-EPad package is pin compatible with previous RM7965 and the RM5261A ExposedPad products. The MIP7365 ideally suits high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. The MIP7365 is also applicable to the low end workstation market where its balanced integer and floating-point performance provides outstanding price/performance. For additional Detail Information regarding the operation of the PMC-Sierra see the latest PMC-Sierra datasheet for the RM7065C Family Microprocessors Data Sheet, Issue No. 5: August 2006; Document No. PMC-2021816, Issue 5 SCD7365 Rev D 2/17/12 3 Aeroflex Plainview PIN DESCRIPTIONS The following is a list of control, data, clock, interrupt, and miscellaneous pins of MIP7365. System Interface PIN NAME TYPE DESCRIPTION ExtRqst* Input External request Signals that the external agent is submitting an external request. Release* Output RdRdy* Input Read Ready Signals that an external agent can now accept a processor read. WrRdy* Input Write Ready Signals that an external agent can now accept a processor write request. ValidIn* Input Valid Input Signals that an external agent is now driving a valid address or data on the bus and a valid command or data identifier on the SysCmd bus. ValidOut* Output Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. PRqst* Output Processor Request When asserted this signal requests that control of the system interface be returned to the processor. This is enabled by Mode Bit 26 PAck* Input Processor Acknowledge When asserted, in response to PRqst*, this signal indicates to the processor that it has been granted control of the system interface. RspSwap* Input Response Swap RspSwap* is used by the external agent to signal the processor when it is about to return a memory reference out of order; i.e., of two outstanding memory references, the data for the second reference is being returned ahead of the data for the first reference. In order that the processor will have time to switch the address to the tertiary cache, this signal must be asserted a minimum of two cycles prior to the data itself being presented. Note that this signal works as a toggle; i.e., for each cycle that it is held asserted the order of return is reversed. By default, anytime the processor issues a second read it is assumed that the reads will be returned in order; i.e., no action is required if the reads are indeed returned in order. This is enabled by Mode Bit 26. RdType Output SysAD[63:0] Input/Output System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. SysADC[7:0] Input/Output System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data cycles. SysCmd[8:0] Input/Output System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP Input/Output System Command/Data Identifier Bus Parity For the MIP7365, unused on input and zero on output. SCD7365 Rev C 8/25/11 Release interface Signals that the processor is releasing the system interface to slave state Read Type During the address cycle of a read request, RdType indicates whether the read request is an instruction read or a data read. 4 Aeroflex Plainview Clock/Control Interface PIN NAME TYPE DESCRIPTION SysClock Input System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. SysClock* Input System clock Differential clock input used only in HSTL I/O mode. Set SysClock* to VccIO or Do Not Connect for non-HSTL operation. TYPE DESCRIPTION VccInt Input Power supply for core. VccIO Input Power supply for I/O. VccP Input Vcc for PLL Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter circuit. VccJ Input Power supply used for JTAG. VREF_In Input Reference voltage for HSTL I/O. Do not connect for non-HSTL. Vss Input Ground Return. VssP Input Vss for PLL Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit. PIN NAME TYPE DESCRIPTION INT[9:0]* Input Interrupt Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register. NMI* Input Non-maskable interrupt Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6 in R5000 compatibility mode). Power Supply PIN NAME Interrupt Interface SCD7365 Rev C 8/25/11 5 Aeroflex Plainview JTAG Interface PIN NAME TYPE DESCRIPTION JTDI Input JTAG data in JTCK Input JTAG clock input JTDO Output JTMS Input JTAG command JTRST* Input JTAG reset. JTAG data out Notes: 1. The JTRST* input was added to the RM70xxC and RM79xx CPUs to directly control the reset to the JTAG state machine. JTAG boundary scan test equipment must be able to drive JTRST* high to allow JTAG boundary scan operation. 2. The JTRST* input must be connected to GND (Vss) through a 220Ω to 1 KΩ pull-down resistor to force the JTAG state machine into the reset state to allow normal operation (JTAG boundary scan mode disabled). 3. The JTAG interface electrical characteristics are dependent on the VccJ level chosen (2.5 V or 3.3 V). Initialization Interface PIN NAME TYPE DESCRIPTION BigEndian Input Big Endian / Little Endian Control Allows the system to change the processor addressing VccOK Input Vcc is OK When asserted, this signal indicates to the MIP7365 that the VccInt power supply has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream. ColdReset* Input Cold Reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset* Input Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. ModeClock Output Modein Input Boot Mode Data In Serial boot-mode data input. HSTL-Sel* Input HSTL/VTL Control Asserting this signal low places the system I/O pins in HSTL mode. Pulling this signal high or allowing to float places all system I/O pins in LVTLL mode. Boot Mode Clock Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. Notes: 1. In HSTL mode, maximum voltage level of ModeClock is determined by VccJ level. 2. SysClock*, VREF_In, and HSTL-SEL* signal pin are no connect on LVTTL mode. 3. Functionality of the HSTL mode is not tested by Aeroflex and guaranteed to work at Industrial temperatures only. SCD7365 Rev C 8/25/11 6 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS 1 SYMBOL RATING RANGE UNITS VTERM Terminal Voltage with respect to Vss -0.52 to 3.9 V Tc Operating Temperature I = Industrial R = Extended T = Military M = Military, Screened -40 to +85 -55 to +110 -55 to +125 -55 to +125 •C •C •C •C TSTG Storage Temperature -55 to +125 •C IIN DC Input Current ±20 mA IOUT DC Output Current 4 ±20 mA Notes: 1. Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +3.95 Volts. 3. When VIN < 0V or VIN > VccIO. 4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second. RECOMMENDED OPERATING CONDITIONS GRADE CPU SPEED TEMP (CASE) Vss VccInt VccIO VccP VccJ Industrial 450 MHz -40°C to +85°C 0V 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 Extended 450 MHz -55°C to +110°C 0V 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 Military 450 MHz -55°C to +125°C Note 5 0V 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 1.3 V ± 50 mV 3.3 V ± 150 mV or 2.5 V ± 200 mV Note 6 Notes 1. VccIO should not exceed VccInt by greater than 2.5 V during the power-up sequence. 2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended. 3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000 User Manual. 4. VccP must be connected to VccInt through a passive filter circuit. See RM7000 User Manual fo recommended circuit. 5. Contact factory for extended military temperature range products (CQFP hermetic MCM packages will be screened at -55°C to + 125°C). 6. These voltages are recommended for HSTL mode operations only. HSTL mode operation is guaranteed at Industrial temperatures only. SCD7365 Rev C 8/25/11 7 Aeroflex Plainview DC ELECTRICAL CHARACTERISTICS VccIO = 3.15 - 3.45V PARAMETER MINIMUM MAXIMUM CONDITIONS VOL - 0.2V |IOUT | = 100µA VOH VccIO - 0.2V - VOL - 0.4V VOH 2.4V - VIL -0.3V 0.8V - VIH 2.0V VccIO + 0.3V - IIN - ±5µA ±5µA |IOUT | = 2mA VIN = 0 VIN = VccIO VccIO = 2.3V – 2.7V PARAMETER MINIMUM MAXIMUM CONDITIONS VOL - 0.2V |IOUT | = 100µA VOH 2.1V - VOL - 0.4V VOH 2.0V - VOL - 0.7V VOH 1.7V - VIL -0.3V 0.7V - VIH 1.7V VccIO + 0.3V - IIN - ±15µA ±15µA |IOUT | = 1mA |IOUT | = 2mA VIN = 0 VIN = VccIO POWER CONSUMPTION CPU SPEED PARAMETER VCCINT Power (mWatts) 450MHz (IND) 450MHz (MIL) MAX MAX 1350 1350 Maximum with no FPU operation 2 3100 3250 Maximum worst case instruction mix 3250 3400 CONDITIONS Standby Active Notes: 1. Worst case supply voltage (maximum VccInt) with worst case temperature (maximum TCASE). 2. Dhrystone 2.1 instruction mix. 3. I/O supply power is application dependant, but typically <20% of VccInt. SCD7365 Rev C 8/25/11 8 Aeroflex Plainview AC CHARACTERISTICS CAPACITIVE LOAD DERATION SYMBOL PARAMETER MINIMUM MAXIMUM UNITS Mode CLD Load Derate - 2 ns/25pF LVTTL CLOCK PARAMETERS BUS SPEED PARAMETER SYMBOL TEST CONDITIONS LVTTL UNITS MIN MAX SysClock High tSCHigh Transition < 2ns 3 - ns SysClock Low tSCLow Transition < 2ns 3 - ns 33.3 133 MHz tSCP 7.5 30 ns Clock Jitter for SysClock tJitterIn - ±150 ps SysClock Rise Time tSCRise - 2 ns SysClock Fall Time tSCFall - 2 ns ModeClock Period tModeCKP - 256 ns JTAG Clock Period tJTAGCKP 4 - ns SysClock Frequency1 SysClock Period Notes: 1. Operation of the MIP7365 is only guaranteed with the Phase Loop enabled. SYSTEM INTERFACE PARAMETERS I/O TYPE PARAMETER1 Data Output2,6,7 SYM tDO TEST CONDITIONS5,6 LVTTL I/O UNITS MIN MAX LVTTL (VccIO = 3.3V): mode[14:13] = 10 (fastest) 0.75 4.5 ns LVTTL (VccIO = 3.3V): mode[14:13] = 01 (slowest) 0.75 5.5 ns Data Setup4 tDS tRISE = See above table 2.5 - ns Hold4 tDH tFALL= See above table 1.0 - ns Data Notes 1. In LVTTL mode, timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O, and from 0.48 x VccIO of clock to 0.48 x VccIO of signal for 2.5V I/O. Input Rise/Fall time = 1V/1ns. 2. Capacitive load for all LVTTL maximum output timings is 50 pF. Minimum output timings are for theoretical no load conditions untested. 4. Data Output timing applies to all signal pins whether tristate I/O or output only. 5. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only. 6. Only mode 14:13 = 01 is tested and guaranteed. 7. Data shown is for 3.3 V I/O. For 2.5 V I/O: derate tDO min by 0.25 nS, and tDO max by 0.5 nS. Mode setting is mode [14:13] = 10 (fastest) or 01 (slowest). SCD7365 Rev C 8/25/11 9 Aeroflex Plainview SCD7365 Rev C 8/25/11 10 Aeroflex Plainview THERMAL INFORMATION This product is designed to operate over a wide temperature range when used with a heat sink. Maximum long-term operating junction temperature to ensure adequate long-term life TBD at 450 MHz Maximum junction temperature for short-term excursions with guaranteed continued functional performance TBD at 450 MHz Minimum ambient temperature TBD Device Compact Model 2 Ambient θJT (°C/W) 4.19 θJB (°C/W) 5.43 Θ SA Heat Sink ΘCS θJA (°C/W) 11.65 Case ΘJT Device Compact Model Junction ΘJB Board Operating power is dissipated in any package (watts) offered at worst case power supply Power at 450MHz VccInt = 1.3 V, VccIO = 3.3 V 2.8W Notes 1. Short-term is understood as the definition stated in Telcordia Generic Requirements GR-63-Core. 2. θJC, the junction-to-case thermal resistance, θJB, the junction-to-board thermal resistance are obtained from Package vendor. 3. θSA is the thermal resistance of the heat sink to ambient. θCS is the thermal resistance of the heat sink attached material. 4. The actual θSA required may vary according to the air speed at the location of the device in the system with all the components in place. SCD7365 Rev C 8/25/11 11 Aeroflex Plainview MIP7365 216-PIN EPad LQFP PACKAGE OUTLINE 4 26.20(1.031) 25.80(1.015) 5 13.10(.516) 12.90(.508) PIN #1 ID 4X -D- 3 216 7 8 12.10(.476) 11.90(.485) SEE DETAIL "C" 1 3 -B- XX 4 26.20(1.031) 25.80(1.015) 3 5 7 DETAIL "A" -A- -E24.20(.953) 23.80(.937) 6.0(.236) 13.10(.516) 12.90(.508) 8 CO 7 RY 5 4X TOP VIEW 7 Molded depression in plastic - do not solder 4X 6.6(.260) 24.20(.953) -D23.80(.937) 5 12.10(.476) 11.90(.485) UNT BOTTOM VIEW EXPOSED PAD OPTION The solderable exposed pad must be connected to ground on the PCB DETAIL "B" 1.45(.057) 1.35(.053) 12° TYP. 0.20(.008)MIN 0.05 MIN 0° 0.20(.008) 0.40(.0157) BSC. 1.60(.063) MAX. -HDATUM PLANE 0.20(.008) AFTER PLATING 0.10(.004) 9 0°~7° BASE PLANE 0.08(.003) C GAGE PLANE 0.25(.010) -C0.15(.006) SEATING PLANE 0.05(.002) 13 0.07(.003) M C A-B S D S 0.13/0.23 0.20(.008) R 0.08(.003) 2 - 0.05 S WITH LEAD FINISH R0.08(.003) MIN. TYP. 0.75(.029) 0.45(.018) 1.00(.039) REF. 0.09/0.20 DETAIL "B" 0.09/0.16 0.13/0.18 BASE METAL 3 0.20 BSC SIDE VIEW 0.30 MAX. -A,B, or D 15 (0.35) (0.35) DETAIL "A" TYP. TYP. DETAIL "C" (EXPOSED PAD CORNER DETAIL) SCD7365 Rev C 8/25/11 12 Aeroflex Plainview MIP7365 216-PIN EPad LQFP PACKAGE OUTLINE NOTES Notes 1. All dimensions and tolerancing conform to ANSI Y14.5-1982. Inches are shown in parentheses. 2. Datum plane -H- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and -D- to be determined at centerline between leads where leads exit plastic body at datum plane -H-. 4. To be determined at seating plane -C-. 5. Dimensions do not include mold protrusion. Allowable mold protrusion is 0.254 mm on dimensions. 6. 216 is the total number of terminals. 7. These dimensions to be determined at datum plane -H-. 8. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 9. Dimension does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 10. Controlling dimension: millimeter. 11. Maximum allowable die thickness to be assembled in this package family is 0.38 mm. 12. This outline conforms to JEDEC publication 95, registration MS-026, variation BGB. 13. Defined as the distance from the seating plane to the lowest point of the package body. 14. Exposed pad shall be coplanar with bottom of package within 0.05. 15. Corner chamfer of exposed die pad shall be within 0.30 mm. SCD7365 Rev D 2/17/12 13 Aeroflex Plainview MIP7365 216-EPad LQFP NUMERICAL PINOUT vs FUNCTION PIN FUNCTION PIN FUNCTION PIN 1, 2 FUNCTION PIN FUNCTION 1 VccIO 39 SysAD48 77 VccIO 115 JTDO 2 Do Not Connect 40 SysAD16 78 SysCmd5 116 VccIO 3 Do Not Connect 41 VccInt 79 SysCmd4 117 ModeClock 4 Do Not Connect 42 BigEndian 80 SysCmd3 118 VccInt 5 Do Not Connect 43 VccIO 81 SysCmd2 119 PRQST* 6 VccInt 44 VccOK 82 VccInt 120 PACK* 7 SysAD59 45 ColdReset* 83 SysCmd1 121 RspSwap* 8 SysAD27 46 Reset* 84 SysCmd0 122 VccIO 9 SysAD58 47 ExtRqst* 85 Do Not Connect 123 VccInt 10 VccInt 48 NMI* 86 Do Not Connect 124 SysAD47 11 VccIO 49 VccInt 87 Do Not Connect 125 SysAD15 12 SysAD26 50 INT9* 88 VccInt 126 VccInt 13 VccInt 51 INT8* 89 Do Not Connect 127 SysAD46 14 SysAD57 52 INT7* 90 Do Not Connect 128 SysAD14 15 SysAD25 53 INT6* 91 VccInt 129 SysAD45 16 SysAD56 54 VccIO 92 Do Not Connect 130 SysAD13 17 SysAD24 55 VccJ 93 Do Not Connect 131 SysAD44 18 SysAD55 56 VccIO 94 Do Not Connect 132 SysAD12 19 SysAD23 57 INT5* 95 VccInt 133 VccInt 20 VccInt 58 INT4* 96 Do Not Connect 134 SysAD43 21 SysAD54 59 INT3* 97 Master Clock 135 SysAD11 22 SysAD22 60 INT2* 98 VssP 136 VccIO 23 SysAD53 61 INT1* 99 VccP 137 VccIO 24 SysAD21 62 INT0* 100 Release* 138 SysAD42 25 VccIO 63 VccInt 101 ValidOut* 139 SysAD10 26 VccIO 64 VccInt 102 ValidIn* 140 SysAD41 27 VccIO 65 Do Not Connect 103 WrRdy* 141 SysAD9 28 SysAD52 66 Do Not Connect 104 RdRdy* 142 VccInt 29 SysAD20 67 Do Not Connect 105 Do Not Connect 143 SysAD40 30 VccInt 68 VccIO 106 ModeIn 144 SysAD8 31 SysAD51 69 Do Not Connect 107 RdType 145 SysAD39 32 SysAD19 70 Do Not Connect 108 Do Not Connect 146 SysAD7 33 SysAD50 71 Do Not Connect 109 VccJ 147 SysAD38 34 SysAD18 72 VccInt 110 JTRST* 148 SysAD6 35 SysAD49 73 SysCmdP 111 VccIO 149 VccInt 36 SysAD17 74 SysCmd8 112 JTMS 150 SysAD37 37 VccIO 75 SysCmd7 113 JTCK 151 SysAD5 38 VccInt 76 SysCmd6 114 JTDI 152 SysAD36 SCD7365 Rev C 8/25/11 14 Aeroflex Plainview MIP7365 216-EPad LQFP NUMERICAL PINOUT vs FUNCTION 1, 2 CON’T PIN FUNCTION PIN FUNCTION 153 SysAD4 191 VccIO 154 VccInt 192 SysADC7 155 Do Not Connect 193 SysADC3 156 Do Not Connect 194 VccInt 157 VccInt 195 SysADC6 158 Do Not Connect 196 VccIO 159 Do Not Connect 197 SysADC2 160 Do Not Connect 198 SysAD63 161 Do Not Connect 199 SysAD31 162 VccIO 200 Do Not Connect 163 Do Not Connect 201 SysAD62 164 VccIO 202 SysAD30 165 VccIO 203 VccIO 166 Do Not Connect 204 VccIO 167 Do Not Connect 205 VccInt 168 Do Not Connect 206 SysAD61 169 Do Not Connect 207 SysAD29 170 SysAD35 208 VccInt 171 SysAD3 209 SysAD60 172 VccInt 210 SysAD28 173 SysAD34 211 Do Not Connect 174 SysAD2 212 Do Not Connect 175 VccInt 213 Do Not Connect 176 VccIO 214 Do Not Connect 177 VccInt 215 VccIO 178 SysAD33 216 VccIO 179 SysAD1 180 SysAD32 181 SysAD0 182 SysADC5 183 SysADC1 184 VccIO 185 VccInt 186 SysADC4 187 SysADC0 188 Do Not Connect 189 VccInt 190 VccIO SCD7365 Rev C 8/25/11 Notes: 1. The exposed pad on the bottom of the EPad LQFP package acts as the sole device ground and as the primary heat conduction path. As such, it must be soldered to the printed circuit board. 2. See PMC-2030256, 216-EPad LQFP Design Guidelines Application Note for details. 15 Aeroflex Plainview MIP7365 256 TBGA PACKAGE OUTLINE Symbol MIN NOM MAX A8 -- -- .067 A1 .020 (0.50) .024 (0.60) .028 (0.70) D 1.063 (27.00) E 1.063 (27.00) I .056 REF (1.435) J .056 REF (1.435) M .787 <PERIMETER> (20) aaa .008 (0.20) bbb .010 (0.25) b .024 (0.60) .030 (0.75) .035 (0.90) c .031 (0.80) .035 (0.90) .039 (1.00) e SCD7365 Rev C 8/25/11 .050 TYP (1.27) 16 Aeroflex Plainview MIP7365 256 TBGA PACKAGE OUTLINE NOTES Notes 1. Package dimensions conform to JEDEC Registration MO-149(BG-2X). 2. "e" represents the basic solder ball grid patch. 3. "M" represents the maximum solder ball matrix size. 4. Dimension "b" is measured at the maximum solder ball diameter parallel to the primary datum "c". 5. The Primary datum "c" and the seating plane are defined by the spherical crowns of the solder balls. 6. All dimensions are in inches. 7. Dimensioning and tolerancing per ASME Y-14.5M-1994. 8. After surface mount assembly solder ball will have 0.006" (TYP) collapse in "A" dimension. 9. Substrate base material is copper. 10. Package top surface shall be black. 11. Cavity depth maximum is .020". SCD7365 Rev C 8/25/11 17 Aeroflex Plainview MIP7365 256 TBGA NUMERICAL PINOUT vs FUNCTION SCD7365 Rev C 8/25/11 18 1, 2 Aeroflex Plainview MIP7365 256 TBGA NUMERICAL PINOUT vs FUNCTION SCD7365 Rev C 8/25/11 19 1, 2 Aeroflex Plainview PART NUMBER BREAKDOWN MIP7365 216-EPad LQFP MIP 7365 – 450 P R Screening MIPS Series I = Industrial Temp, -40°C to +85°C R = Extended Temp, -55°C to +110°C Base Processor Type Maximum Pipeline Frequency Package Type & Size 450 = 450MHz P = 26mm Sq, 216-EPad LQFP PART NUMBER BREAKDOWN MIP7365 256 TBGA MIP 7365 – 450 B1 R U MIPS Series Package Substrate Base Processor Type Blank = D004 U = D004U Maximum Pipeline Frequency 450 = 450MHz Screening I = Industrial Temp, -40°C to +85°C R = Extended Temp, -55°C to +110°C Package Type & Size B1 = 26mm Sq, 256-TGBA SCD7365 Rev C 8/25/11 20 Aeroflex Plainview SAMPLE ORDERING INFORMATION PART NUMBER SCREENING MIP7365-450PI 1/ Industrial Temperature Range -40°C to +85°C Testing MIP7365-450PR 1/ Extended Temperature Range -55°C to +110°C Testing MIP7365-450B1I 1/ Industrial Temperature Range -40°C to +85°C Testing MIP7365-450B1R 1/ Extended Temperature Range -55°C to +110°C Testing MIP7365-450B1IU 2/ Industrial Temperature Range -40°C to +85°C Testing MIP7365-450B1RU 2/ Extended Temperature Range -55°C to +110°C Testing PIPELINE FREQ (MHZ) Note 2 PACKAGE 450 216-EPad LQFP 450 256 TBGA Notes: 1. Substrate D004 2. Substrate D004U PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused SCD7365 Rev D 2/17/12 21