ETC RM7000B?

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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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RM7000B™
Data Sheet
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Microprocessor with
On-Chip Secondary Cache
Proprietary and Confidential
Preliminary
Issue 3, March 2002
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
PM
Legal Information
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Copyright
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© 2002 PMC-Sierra, Inc. All rights reserved.
02
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The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In
any event, you cannot reproduce any part of this document, in any form, without the express written
consent of PMC-Sierra, Inc.
20
PMC-2010588 (P3)
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Disclaimer
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None of the information contained in this document constitutes an express or implied warranty by PMCSierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the
fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts
or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document.
PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents
or use of the information, including, but not limited to, express and implied warranties of accuracy,
completeness, merchantability, fitness for a particular use, or non-infringement.
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In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential
damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or
reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such
damage.
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Trademarks
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RM7000B and Fast Packet Cache are trademarks of PMC-Sierra, Inc.
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Patents
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The technology discussed is protected by one or more of the following Patents.
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U.S. Patent Numbers 5 953 748, 5 606 683, 5 760 620
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Relevant patent applications and other patents may also exist.
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Contacting PMC-Sierra
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PMC-Sierra, Inc.
8555 Baxter Place Burnaby, BC
Canada V5A 4V7
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Tel: +1 (604) 415-6000
Fax: +1 (604) 415-6200
Document Information: [email protected]
Corporate Information: [email protected]
Technical Support: [email protected]
Web Site: http://www.pmc-sierra.com
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
PM
Revision History
Issue Date
Details of Change
3
March 2002
Updated mode bit 11 description, table 16, Section 4.39.
Updated Dhrystone value to 900, Section 1.
02
Added Section 12, Thermal Information.
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Issue
No.
20
Various updates to text description in Section 4.
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Updated Packaging Diagram table, Section 13.
Modified CP0 Register Diagram, Typical Embedded Block Diagram,
Kernel Mode Virtual Addressing.
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Changed references from external controller/device to external agent,
F type to F pipe, SysAD I/F to System I/F.
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Changed recommended operation conditions for 500 MHz VccInt and
VccP to 1.6 V +/- 50 mV to in Section 7.
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Added note 5 to Section 7, Recommended Operating Conditions.
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Various formatting and editing changes.
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New logo.
September 2001
Changed recommended operating conditions for VccInt and VccP to
1.5 V ± 50 mV. Changed clock parameter test conditions for SysClock
High/low to Transition ≤ 2 ns.
1
March 2001
Data sheet created.
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
3
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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Document Conventions
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All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface
typeface.
All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold
typeface.
All instruction names, such as MFHI, are in san serif typeface.
02
•
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The following conventions are used in this data sheet:
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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Table of Contents
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Legal Information ......................................................................................................................... 2
:43
Copyright ............................................................................................................................... 2
Disclaimer ............................................................................................................................. 2
11
Trademarks ........................................................................................................................... 2
02
Patents .................................................................................................................................. 2
20
Contacting PMC-Sierra ................................................................................................................ 2
Revision History ........................................................................................................................... 3
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1 Features ................................................................................................................................. 2
2 Block Diagram ........................................................................................................................ 3
3 Description ............................................................................................................................. 4
CPU Registers .............................................................................................................5
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4 Hardware Overview ................................................................................................................ 5
Superscalar Dispatch ...................................................................................................5
4.3
Pipeline ........................................................................................................................6
4.4
Integer Unit ..................................................................................................................7
4.5
ALU ..............................................................................................................................8
4.6
Integer Multiply/Divide ..................................................................................................8
4.7
Floating-Point Coprocessor ..........................................................................................9
4.8
Floating-Point Unit .......................................................................................................9
4.9
Floating-Point General Register File ............................................................................10
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4.10 System Control Coprocessor (CP0) .............................................................................11
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4.11 System Control Coprocessor Registers .......................................................................11
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4.12 Virtual to Physical Address Mapping ............................................................................12
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4.13 Joint TLB ......................................................................................................................13
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4.14 Instruction TLB .............................................................................................................14
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4.15 Data TLB ......................................................................................................................14
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4.16 Cache Memory .............................................................................................................14
4.17 Instruction Cache .........................................................................................................15
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4.18 Data Cache ..................................................................................................................15
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4.19 Secondary Cache ........................................................................................................17
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4.20 Secondary Caching Protocols ......................................................................................17
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4.21 Tertiary Cache .............................................................................................................18
4.22 Cache Locking .............................................................................................................19
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4.23 Cache Management .....................................................................................................20
4.24 Primary Write Buffer .....................................................................................................20
4.25 System Interface ..........................................................................................................20
4.26 System Address/Data Bus ...........................................................................................21
4.27 System Command Bus ................................................................................................21
4.28 Handshake Signals ......................................................................................................22
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Document ID: PMC-2010588, Issue 3
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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4.29 System Interface Operation .........................................................................................22
4.30 Data Prefetch ...............................................................................................................24
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4.31 Enhanced Write Modes ................................................................................................25
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4.32 External Requests ........................................................................................................25
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4.33 Test/Breakpoint Registers ............................................................................................25
4.34 Performance Counters .................................................................................................26
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4.35 Interrupt Handling ........................................................................................................28
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4.36 Standby Mode ..............................................................................................................30
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4.37 JTAG Interface .............................................................................................................30
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4.38 Boot-Time Options .......................................................................................................30
4.39 Boot-Time Modes .........................................................................................................30
5 Pin Descriptions ................................................................................................................... 32
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6 Absolute Maximum Ratings .................................................................................................. 36
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7 Recommended Operating Conditions .................................................................................. 37
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8 DC Electrical Characteristics ................................................................................................ 38
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9 Power Consumption ............................................................................................................. 39
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10 AC Electrical Characteristics ................................................................................................ 40
10.1 Capacitive Load Deration .............................................................................................40
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10.2 Clock Parameters ........................................................................................................40
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10.3 System Interface Parameters ......................................................................................41
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10.4 Boot-Time Interface Parameters ..................................................................................41
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11 Timing Diagrams .................................................................................................................. 42
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11.1 Clock Timing ................................................................................................................42
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11.2 System Interface Timing ..............................................................................................42
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12 Thermal Information ............................................................................................................. 43
13 Packaging Information .......................................................................................................... 44
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14 RM7000B Pinout .................................................................................................................. 45
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15 Ordering Information ............................................................................................................ 48
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
PM
List of Figures
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Figure 1 Block Diagram .............................................................................................................3
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Figure 2 CP0 Registers .............................................................................................................5
Figure 3 Instruction Issue Paradigm ..........................................................................................6
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Figure 4 Pipeline ........................................................................................................................7
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Figure 5 CP0 Registers .............................................................................................................12
20
Figure 6 Kernel Mode Virtual Addressing (32-bit) .....................................................................13
Figure 7 Tertiary Cache Hit and Miss ........................................................................................18
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Figure 8 Typical Embedded System Block Diagram .................................................................21
Figure 9 Processor Block Read .................................................................................................23
Figure 10 Processor Block Write ...............................................................................................24
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Figure 11 Multiple Outstanding Reads ......................................................................................24
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Figure 12 Clock Timing ..............................................................................................................42
Figure 13 Input Timing ...............................................................................................................42
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Figure 14 Output Timing ............................................................................................................42
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Figure 15 304 TBGA Drawing ...................................................................................................44
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Document ID: PMC-2010588, Issue 3
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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List of Tables
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Table 1 Instruction Issue Rules .................................................................................................5
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Table 2 Dual Issue Instruction Classes .....................................................................................6
Table 3 ALU Operations ............................................................................................................8
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Table 4 Integer Multiply/Divide Operations ................................................................................8
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Table 5 Floating Point Latencies and Repeat Rates .................................................................10
20
Table 6 Cache Attributes ...........................................................................................................19
Table 7 Cache Locking Control .................................................................................................20
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Table 8 Penalty Cycles ..............................................................................................................20
Table 9 Watch Control Register ................................................................................................26
Table 10 Performance Counter Control .....................................................................................27
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Cause Register ...........................................................................................................29
Interrupt Control Register ...........................................................................................29
IPLLO Register ...........................................................................................................29
IPLHI Register ............................................................................................................29
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Table 11
Table 12
Table 13
Table 14
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Table 15 Interrupt Vector Spacing .............................................................................................30
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Table 16 Boot Time Mode Stream .............................................................................................31
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Table 17 System Interface .........................................................................................................32
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Table 18 Clock/Control Interface ...............................................................................................33
Table 19 Tertiary Cache Interface .............................................................................................33
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Table 20 Interrupt Interface .......................................................................................................35
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Table 21 JTAG Interface ...........................................................................................................35
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Table 22 Initialization Interface ..................................................................................................35
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Table 23 (VCCIO = 3.15V – 3.45V) ...........................................................................................38
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Table 24 (VCCIO = 2.3V – 2.7V) ...............................................................................................38
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
Features
Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for
system level price/performance
• 450, 500 MHz operating frequency
• >900 Dhrystone 2.1 MIPS @ 500 MHz
High-performance system interface
• 1000 MB per second peak throughput
• 125 MHz max. freq., multiplexed address/data
• Supports two outstanding reads with out-of-order return
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
Integrated primary and secondary caches
• All are 4-way set associative with 32 byte line size
• 16 KB instruction, 16 KB data, 256 KB on-chip secondary
• Per line cache locking in primaries and secondary
• Fast Packet Cache™ increases system efficiency in
networking applications
Integrated external cache controller (up to 8 MB)
High-performance floating-point unit — 1000 MFLOPS maximum
• Single cycle repeat rate for common single-precision operations and some doubleprecision operations
• Single cycle repeat rate for single-precision combined multiply-add operations
• Two cycle repeat rate for double-precision multiply and double-precision combined
multiply-add operations
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MIPS IV superset instruction set architecture
• Data PREFETCH instruction allows the processor to overlap cache miss latency and
instruction execution
• Single-cycle floating-point multiply-add
Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 64/48 dual entries map 128/96 pages
• Variable page size
Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and
three-operand multiply instruction (MUL)
• I&D Test/Break-point (Watch) registers for emulation & debug
• Performance counter for system and software tuning & debug
• Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software
Fully static CMOS design with dynamic power down logic
Pin compatible with the RM5271, RM7000 and RM7000A in 304-pin TBGA package,
31x31mm
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
2
Figure 1
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Block Diagram
Block Diagram
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2
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
On-chip 256K Byte Secondary Cache, 4-way Set Associative
Secondary Tags
Set C
DTag
DTLB
ITag
ITLB
Primary Instruction Cache
4-way Set Associative
Store Buffer
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Primary Data Cache
4-way Set Associative
Secondary Tags
Set D
02
Secondary Tags
Set B
20
Secondary Tags
Set A
Pad Buffer
Write Buffer
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Address Buffer
A/D Bus
Pad Bus
Prefetch Buffer
Instruction Dispatch Unit
F Pipe Register
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Read Buffer
11
Extenal Cache Controller
M Pipe Register
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F-Pipe Bus
M-Pipe Bus
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Adder
StAln/Sh
Logicals
IVA
PC Incrementer
Adder
Shifter
Logicals
FA Bus
ITLB Virtual
Program Counter
DTLB Virtual
PLL/Clocks
Int Mult, Div, Madd
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Multiplier Array
Integer Register File
M Pipe
F Pipe
Branch PC Adder
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Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Load Aligner
DVA
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Comparator
System/Memory
Control
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Packer/Unpacker
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Floating-Point
Register File
Floating-Point Control
Joint TLB
Coprocessor 0
Integer Control
Floating-Point
Load/Align
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D Bus
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Description
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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PMC-Sierra’s RM7000B is a highly integrated symmetric superscalar microprocessor capable of
issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as
well as a high-throughput, fully pipelined 64-bit floating point unit.
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The RM7000B integrates 16 KB 4-way set associative instruction and data caches along with an
integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are
write-back and non-blocking. An optional external tertiary cache provides high-performance
capability even in applications with very large data sets.
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The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system
interface supporting multiple outstanding reads with out-of-order return and hardware prioritized
and vectored interrupts.
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The RM7000B ideally suits high-end embedded control applications such as internetworking,
high-performance image manipulation, high-speed printing, and 3-D visualization. The
RM7000B is also applicable to the low end workstation market where its balanced integer and
floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide
outstanding price/performance.
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Hardware Overview
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
CPU Registers
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4.1
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The RM7000B offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM7000B are described throughout this section.
CP0 Registers
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Figure 2
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The RM7000B CPU contains 32 general purpose registers (GPR), two special purpose registers
for integer multiplication and division, and a program counter; there are no condition code bits.
Figure 2 shows these processor registers. The RM7000B also contains both 32 and 64-bit CP0
registers. Only 29 of the 32 registers specified in CP0, Set 0 are implemented, and only 5 of the
32 registers in CP0, Set 1 are implemented.
Multiply/Divide Registers
0
0
63
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r1
0
HI
63
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r2
0
LO
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Program Counter
63
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r30
0
PC
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Superscalar Dispatch
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General Purpose Registers
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The RM7000B incorporates a superscalar dispatch unit that allows it to issue up to two
instructions per cycle. For purposes of instruction issue, the RM7000B defines four classes of
instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the
function, or F, pipeline and the memory, or M, pipeline. Note however that the M pipe can
execute integer as well as memory type instructions.
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Table 1 Instruction Issue Rules
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F Pipe
M Pipe
one of:
integer, branch, floating-point, integer mul, div
integer, load/store
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Figure 3 is a simplification of the pipeline section and illustrates the basics of the instruction
issue mechanism.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
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Instruction Issue Paradigm
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Figure 3
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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Instruction
Cache
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02
Dispatch
Unit
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F Pipe IBus
FP
M Pipe
Integer
M Pipe
Integer
F Pipe
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FP
F Pipe
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M Pipe IBus
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The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
Load/Store
add, sub, or, xor, shift,
etc.
lw, sw, ld, sd, ldc1, sdc1,
mov, movc, fmov, etc.
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Floating-point
Branch
fadd, fsub, fmult, fmadd,
fdiv, fcmp, fsqrt, etc.
beq, bne, bCzT, bCzF, j,
etc.
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Pipeline
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Integer
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Table 2 Dual Issue Instruction Classes
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The logical length of both the F and M pipelines is five stages with state committing (result of
instruction written back into register file) in the register write or W pipe stage. The physical
length of the floating-point execution pipeline is actually seven stages but this is completely
transparent to the user.
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Figure 4 shows instruction execution within the RM7000B when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation since the out-of-order completion of loads, stores, and long latency floating-point
operations can result in there being even more instructions in process than what is shown.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
1I
1I
2I
2I
1R
1R
2R
2R
1A
1A
I4
I5
I6
I7
1W
1W
2W
2W
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
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one cycle
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
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1I-1R:
2I:
2R:
1A:
1A:
1A-2A:
2A:
2A-2D:
1D:
2W:
2D
2D
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2R
2R
11
I2
I3
1R
1R
02
2I
2I
20
1I
1I
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I0
I1
:44
Figure 4 Pipeline
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Integer Unit
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Note that instruction dependencies, resource conflicts, and branches may result in some of the
instruction slots being occupied by NOP s.
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The RM7000B implements the MIPS IV™ Instruction Set Architecture. Additionally, the
RM7000B includes two implementation specific instructions not found in the baseline MIPS IV
ISA, but that are useful in the embedded market place. These instructions are integer multiplyaccumulate (MAD) and three-operand integer multiply (MUL).
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The RM7000B integer unit includes thirty-two general purpose 64-bit registers, the HI/LO result
registers for two-operand integer multiply/divide operations, and the program counter, or PC.
There are two separate execution units, one of which can execute F pipe instructions and one
which can execute M pipe instructions. Refer to Table 1 for the instruction issue rules.
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Note that integer multiply/divide instructions, as well as their corresponding MFHI and MFLO
instructions, can only be executed in the F pipe execution unit. Within each execution unit the
operational characteristics are the same as on previous MIPS designs with single cycle ALU
operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide
unit.
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Register File
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The RM7000B has thirty-two general purpose registers with register location 0 (r0) hard wired to
a zero value. These registers are used for scalar integer operations and address calculation. In
order to service the two integer execution units, the register file has four read ports and two write
ports and is fully bypassed both within and between the two execution units to minimize
operation latency in the pipeline.
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ALU
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4.5
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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The RM7000B has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
F Pipe
M Pipe
Adder
add, sub
add, sub, data address add
Logic
logic, moves, zero shifts (nop)
logic, moves, zero shifts (nop)
Shifter
non-zero shift
non-zero shift, store align
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Unit
Integer Multiply/Divide
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Table 3 ALU Operations
32 bit
5
DMULT,
DMULTU
any
9
DIV, DIVD
any
DDIV,
DDIVU
any
0
3
2
4
3
8
0
36
36
0
68
68
0
4
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4
Stall
Cycles
nT
16 bit
MUL
3
io
5
ett
4
32 bit
fo
16 bit
MULT/U,
MAD/U
Repeat
Rate
Latency
liv
Operand
Size
Opcode
rsd
Table 4 Integer Multiply/Divide Operations
ay
,1
9S
The RM7000B has a single dedicated integer multiply/divide unit optimized for high-speed
multiply and multiply-accumulate operations. The multiply/divide unit resides in the F pipe
execution unit. Table 4 shows the performance of the multiply/divide unit on each operation.
db
yV
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (MFHI /MFLO ) instructions.
Do
wn
loa
de
In addition to the baseline MIPS IV integer multiply instructions, the RM7000B also implements
the 3-operand multiply instruction, MUL . This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone into the Hi register is discarded. For applications where it is known
that the upper half of the multiply result is not required, using the MUL instruction eliminates the
necessity of executing an explicit MFLO instruction.
The multiply-add instructions, MAD and MADU, multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
the core primitive of almost all signal processing algorithms. Therefore, using the RM7000B
eliminates the need for a separate DSP engine in many embedded applications.
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Floating-Point Coprocessor
:44
4.7
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
r,
Floating-Point Unit
tem
be
4.8
20
02
11
:43
The RM7000B incorporates a high-performance fully pipelined floating-point coprocessor
which includes a floating-point register file and autonomous execution units for multiply/add/
convert and divide/square root. The floating-point coprocessor is a tightly coupled execution
unit, decoding and executing instructions in parallel with, and in the case of floating-point loads
and stores, in cooperation with the M pipe of the integer unit. The superscalar capabilities of the
RM7000B allow floating-point computation instructions to issue concurrently with integer
instructions.
9S
ep
The RM7000B floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square
root unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is
supported.
rsd
ay
,1
The RM7000B maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
yV
inv
ef
uo
fo
liv
ett
io
nT
add
subtract
multiply
divide
square root
reciprocal
reciprocal square root
conditional moves
conversion between fixed-point and floating-point format
conversion between floating-point formats
floating-point compare
db
•
•
•
•
•
•
•
•
•
•
•
hu
Floating-point operations include:
Do
wn
loa
de
Table 5 gives the latencies of the floating-point instructions in internal processor cycles.
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 5 Floating Point Latencies and Repeat Rates
1/2
fmadd
4/5
1/2
fmsub
4/5
1/2
21/36
19/34
fsqrt
21/36
19/34
frecip
21/36
19/34
frsqrt
38/68
36/66
fcvt.s.d
4
1
fcvt.s.w
6
3
fcvt.s.l
6
3
fcvt.d.s
4
1
fcvt.d.w
4
fcvt.d.l
4
fcvt.w.s
4
fcvt.w.d
4
fcvt.l.s
4
fcvt.l.d
4
fcmp
1
fmov, fmovc
1
:44
9S
,1
ay
rsd
1
liv
ett
io
nT
hu
1
fo
uo
1
ep
fdiv
11
1
4/5
02
4
fmult
20
fsub
fabs, fneg
1
1
1
1
1
1
1
ef
Floating-Point General Register File
inv
4.9
1
r,
4
tem
be
fadd
Repeat Rate
single/double
:43
Latency
single/double
Operation
de
db
yV
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions, LDC1 and SDC1 , the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store
doubleword instruction in every cycle.
Do
wn
loa
The floating-point control register file contains two registers; one for determining configuration
and revision information for the coprocessor, and one for control and status information. These
registers are primarily used for diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
To support superscalar operations the FGR has four read ports and two write ports and is fully
bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port
are used to support the combined multiply-add instruction while the fourth read and second write
port allows for concurrent floating-point load or store and conditional move operations.
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System Control Coprocessor (CP0)
:44
4.10
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:43
The system control coprocessor (CP0) is responsible for the virtual memory sub-system, the
exception control system, and the diagnostics capability of the processor.
20
02
11
For memory management support, the RM7000B CP0 is logically identical to the RM5200
Family. For interrupt exceptions and diagnostics, the RM7000B is a superset of the RM5200
Family, implementing additional features described in the following sections on Interrupts, Test/
Breakpoint registers, and Performance Counters.
System Control Coprocessor Registers
ep
4.11
tem
be
r,
The memory management unit controls the virtual memory system page mapping. It consists of
an instruction address translation buffer (ITLB) a data address translation buffer (DTLB), a Joint
TLB (JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
hu
rsd
ay
,1
9S
The RM7000B incorporates all CP0 registers internally. These registers provide the path through
which the virtual memory system’s page mapping is examined and modified, exceptions are
handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or
disabled, cache features). In addition, the RM7000B includes registers to implement a real-time
cycle counting facility, to aid in cache and system diagnostics, and to assist in data error
detection.
inv
ef
uo
fo
liv
ett
io
nT
To support the non-blocking caches and enhanced interrupt handling capabilities of the
RM7000B, both the data and control register spaces of CP0 are supported. In the data register
space, which is accessed using the MFC0 and MTC0 instructions, the RM7000B supports the
same registers as found in previous RM7000 processors. In the control space, which is accessed
by the previously unused CTC0 and CFC0 instructions, the RM7000B supports five additional
registers. The first three of these new 32-bit registers support the enhanced interrupt handling
capabilities; Interrupt Control, Interrupt Priority Level Lo (IPLLO), and Interrupt Priority Level
Hi (IPLHI). These registers are described further in the section on interrupt handling. Two other
registers, Imprecise Error 1 and Imprecise Error 2, have been added to help diagnose bus errors
that occur on non-blocking memory references.
Do
wn
loa
de
db
yV
Figure 5 shows the CP0 registers.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
47/63
Count
9*
Compare
11*
Perf Ctr Cntrl
22*
Info
7*
Status
12*
Cause
13*
Index
0*
EPC
14*
Watch1
18*
Random
1*
Watch2
19*
XContext
20*
Wired
6*
ECC
26*
(entries protected
from TLBWR)
TagHi
29*
Imp Error 1
26*
Imp Error 2
27*
ep
ErrorEPC
30*
9S
TagLo
28*
IntControl
20*
Config
16*
ay
,1
LLAddr
17*
IPLHI
19*
CacheErr
27*
PRId
15*
0
Watch Mask
24*
tem
be
TLB
IPLLO
18*
:43
Perf Counter
25*
11
EntryLo1
3*
BadVAddr
8*
02
EntryHi
10*
Context
4*
20
EntryLo0
2*
r,
PageMask
5*
:44
Figure 5 CP0 Registers
Used for exception
processing
Control Space Registers
hu
* Register number
Virtual to Physical Address Mapping
nT
4.12
rsd
Used for memory
management
fo
liv
ett
user mode
kernel mode
supervisor mode
uo
•
•
•
io
The RM7000B provides three modes of virtual addressing:
inv
ef
These modes allow system software to provide a secure environment for user processes. Bits in
the CP0 Status register determine which virtual addressing mode is used. In user mode, the
RM7000B provides a single, uniform virtual address space of 256 GB (2 GB in 32-bit mode).
db
yV
When operating in the kernel mode, four distinct virtual address spaces, totalling 1024 GB (4 GB
in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the
virtual address.
Do
wn
loa
de
The RM7000B processor also supports a supervisor mode in which the virtual address space is
256.5 GB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the
virtual address. Figure 6 shows the address space layout for 32-bit operations.
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Kernel Mode Virtual Addressing (32-bit)
Kernel virtual address space
0xFFFFFFFF
:44
Figure 6
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Mapped, 0.5GB
0xDFFFFFFF
Supervisor virtual address space
02
0xE0000000
11
:43
(kseg3)
20
(ksseg)
Mapped, 0.5GB
0xBFFFFFFF
Uncached kernel physical address space
tem
be
r,
0xC0000000
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
Cached kernel physical address space
,1
9S
ep
0xA0000000
(kseg0)
Unmapped, 0.5GB
0x7FFFFFFF
User virtual address space
rsd
hu
Mapped, 2.0GB
io
nT
(kuseg)
0x00000000
ay
0x80000000
fo
Joint TLB
uo
4.13
liv
ett
When the RM7000B is configured for 64-bit addressing, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
db
yV
inv
ef
For fast virtual-to-physical address translation, the RM7000B uses a large, fully associative TLB
that maps virtual pages to their corresponding physical addresses. As indicated by its name, the
JTLB is used for both instruction and data translations. The JTLB is organized as pairs of even/
odd entries, and maps a virtual address and address space identifier (ASID) into the large, 64 GB
physical address space. By default, the JTLB is configured as 48 pairs of even/odd entries. The
optional 64 even/odd entry configuration is set at boot time.
Do
wn
loa
de
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured, on
a per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4x multiples). The CP0
PageMask register is loaded with the desired page size of a mapping, and that size is stored into
the TLB, along with the virtual address, when a new entry is written. Thus, operating systems
can create special purpose maps; for example, an entire frame buffer can be memory mapped
using only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM7000B provides a random replacement algorithm to select a TLB entry to be written with a
new mapping. However, the processor also provides a mechanism whereby a system specific
number of mappings can be locked into the TLB, thereby avoiding random replacement. This
mechanism uses the CP0 Wired register and allows the operating system to guarantee that certain
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:43
:44
pages are always mapped for performance reasons and to avoid a deadlock condition. This
mechanism also facilitates the design of real-time systems by allowing deterministic access to
critical software.
r,
20
02
uncached
write-back
write-through with write-allocate
write-through without write-allocate
write-back with secondary and tertiary bypass
tem
be
•
•
•
•
•
11
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is:
9S
ep
Note that both of the write-through protocols bypass both the secondary and the tertiary caches
since neither of these caches support writes of less than a complete cache line.
Instruction TLB
hu
4.14
rsd
ay
,1
These protocols are used for both code and data on the RM7000B with data using write-back or
write-through depending on the application. The write-through modes support the same efficient
frame buffer handling as the RM5200 Family.
fo
liv
ett
io
Minimizes contention for the JTLB
Eliminates the critical path of translating through a large associative array
Allows instruction address and data address translations to occur in parallel
Saves power
uo
•
•
•
•
nT
The RM7000B uses a 4-entry instruction TLB (ITLB). The ITLB offers the following
advantages;
Data TLB
db
4.15
yV
inv
ef
Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction
address translation to occur in parallel with data address translation. When a miss occurs on an
instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the
JTLB. The operation of the ITLB is completely transparent to the user.
4.16
Do
wn
loa
de
The RM7000B uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB.
Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in parallel with instruction address translation. When a miss occurs
on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudoLRU; the least recently used entry of the least recently used pair of entries is filled. The operation
of the DTLB is completely transparent to the user.
Cache Memory
The RM7000B contains integrated primary instruction and data caches that support single cycle
access, as well as a large unified secondary cache with a three cycle miss penalty from the
primary caches. Each primary cache has a 64-bit read path and a 128-bit write path. Both caches
can be accessed simultaneously. The primary caches provide the integer and floating-point units
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Instruction Cache
02
4.17
11
:43
:44
with an aggregate bandwidth of 6.4 GB per second at an internal clock frequency of 400 MHz.
During an instruction or data primary cache refill, the secondary cache can provide a 64-bit
datum every cycle following the initial three cycle latency for a peak bandwidth of 3.6 GB per
second. For applications requiring even higher performance, the RM7000B also has a direct
interface to a large external tertiary cache.
tem
be
r,
20
The RM7000B has an integrated 16 KB, four-way set associative instruction cache that is
virtually indexed and physically tagged. The effective physical index eliminates the potential for
virtual aliases in the cache.
The data array portion of the instruction cache is 64 bits wide and protected by word parity while
the tag array holds a 24-bit physical address, 14 control bits, a valid bit, and a single parity bit.
nT
hu
rsd
ay
,1
9S
ep
By accessing 64 bits per cycle, the instruction cache is able to supply two instructions per cycle
to the superscalar dispatch unit. For signal processing, graphics, and other numerical code
sequences where a floating-point load or store and a floating-point computation instruction are
being issued together in a loop, the entire bandwidth available from the instruction cache is
consumed by instruction issue. For typical integer code mixes, where instruction dependencies
and other resource constraints restrict the level of parallelism that can be achieved, the extra
instruction cache bandwidth is used to fetch both the taken and non-taken branch paths to
minimize the overall penalty for branches.
io
A 32-byte (eight instruction) line size is used to maximize the communication efficiency
between the instruction cache and the secondary cache, tertiary cache, or memory system.
Data Cache
inv
4.18
ef
uo
fo
liv
ett
The RM7000B supports cache locking on a per line basis. The contents of each line of the cache
can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being
overwritten by a subsequent cache miss. Refills occur only into unlocked cache lines. This
mechanism allows the programmer to lock critical code into the cache, thereby guaranteeing
deterministic behavior for the locked code sequence.
db
yV
The RM7000B has an integrated 16 KB, four-way set associative data cache that is virtually
indexed and physically tagged. Line size is 32 bytes (8 words). The effective physical index
eliminates the potential for virtual aliases in the cache.
wn
loa
de
The data cache is non-blocking; that is, a miss in the data cache does not necessarily stall the
processor pipeline. As long as no instruction is encountered that is dependent on the data
reference that caused the miss, the pipeline continues to advance. Once there are two cache
misses outstanding, the processor stalls if it encounters another load or store instruction.
Do
The data array portion of the data cache is 64 bits wide and protected by byte parity while the tag
array holds a 24-bit physical address, 3 control bits, a two-bit cache state field, and two parity
bits.
The most commonly used write policy is write-back, which means that a store to a cache line
does not immediately cause memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on a
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:44
per-page basis when appropriate, such as for frame buffers. Cache protocols supported for the
data cache are as follows:
:43
1. Uncached
11
Reads to addresses in a memory area identified as uncached do not access the cache. Writes
to such addresses are written directly to main memory without updating the cache.
02
2. Write-back
ep
tem
be
r,
20
Loads and instruction fetches first search the cache, reading the next memory hierarchy level
only if the desired data is not cache resident. On data store operations, the cache is first
searched to determine if the target address is cache resident. If it is resident, the cache
contents are updated and the cache line is marked for later write-back. If the cache lookup
misses, the target line is first brought into the cache, after which the write is performed as
above.
9S
3. Write-through with write allocate
io
nT
hu
rsd
ay
,1
Loads and instruction fetches first search the cache, reading from memory only if the desired
data is not cache resident; write-through data is never cached in the secondary or tertiary
caches. On data store operations, the cache is first searched to determine if the target address
is cache resident. If it is resident, the primary cache contents are updated and main memory
is written, leaving the write-back bit of the cache line unchanged; no writes occur to the
secondary or tertiary caches. If the cache lookup misses, the target line is first brought into
the cache, after which the write is performed as above.
ett
4. Write-through without write allocate
inv
ef
uo
fo
liv
Loads and instruction fetches first search the cache, reading from memory only if the desired
data is not cache resident; write-through data is never cached in the secondary or tertiary
caches. On data store operations, the cache is first searched to determine if the target address
is cache resident. If it is resident, the cache contents are updated and main memory is written,
leaving the write-back bit of the cache line unchanged; no writes occur to the secondary or
tertiary caches. If the cache lookup misses, only main memory is written.
yV
5. Fast Packet Cache™ (Write-back with secondary and tertiary bypass)
wn
loa
de
db
Loads and instruction fetches first search the primary cache, reading from memory only if
the desired data is not resident; the secondary and tertiary caches are not searched. On data
store operations, the primary cache is first searched to determine if the target address is
resident. If it is resident, the cache contents are updated, and the cache line marked for later
write-back. If the cache lookup misses, the target line is first brought into the cache, after
which the write is performed as above.
Do
Associated with the data cache is the store buffer. When the RM7000B executes a STORE
instruction, this single-entry buffer is written with the store data while the tag comparison is
performed. If the tag matches, then the data is written into the data cache in the next cycle that
the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7000B to
execute a store every processor cycle and to perform back-to-back stores without penalty. In the
event of a store immediately followed by a load to the same address, a combined merge and
cache write occurs such that no penalty is incurred.
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Secondary Cache
:44
4.19
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
02
11
:43
The RM7000B has an integrated 256 KB, four-way set associative, block write-back secondary
cache. The secondary cache has a 32-byte line size, a 64-bit bus width to match the system
interface and primary cache bus widths, and is protected with doubleword parity. The secondary
cache tag array holds a 20-bit physical address, 2 control bits, a three bit cache state field, and
two parity bits.
ep
tem
be
r,
20
By integrating a secondary cache, the RM7000B is able to decrease the latency of a primary
cache miss without significantly increasing the number of pins and the amount of power required
by the processor. From a technology point of view, integrating a secondary cache leverages
CMOS technology by using silicon to build the structures that are most amenable to silicon
technology; building very dense, low power memory arrays rather than large power hungry I/O
buffers.
,1
9S
Further benefits of an integrated secondary cache are flexibility in the cache organization and
management policies that are not practical with an external cache. Two previously mentioned
examples are the 4-way associativity and write-back cache protocol.
nT
hu
rsd
ay
A third management policy for which integration affords flexibility is cache hierarchy
management. With multiple levels of cache, it is necessary to specify a policy for dealing with
cases where two cache lines at level n of the hierarchy could possibly be sharing an entry in level
n+1 of the hierarchy.
inv
ef
uo
fo
liv
ett
io
The RM7000B allows entries to be stored in the primary caches that do not necessarily have a
corresponding entry in the secondary; the RM7000B does not force the primaries to be a subset
of the secondary. For example, if primary cache line A is being filled and a cache line already
exists in the secondary for primary cache line B at the location where primary A’s line would
reside, then that secondary entry is replaced by an entry corresponding to primary cache line A
and no action occurs in the primary for cache line B. This operation creates the aforementioned
scenario where the primary cache line, which initially had a corresponding secondary entry, no
longer has such an entry. Such a primary line is called an orphan. In general, cache lines at level
n+1 of the hierarchy are called parents of level n’s children.
Secondary Caching Protocols
Do
4.20
wn
loa
de
db
yV
Another RM7000B cache management optimization occurs for the case of a secondary cache
line replacement where the secondary line is dirty and has a corresponding dirty line in the
primary. In this case, since it is permissible to leave the dirty line in the primary, it is not
necessary to write the secondary line back to main memory. Taking this scenario one step further,
a final optimization occurs when the aforementioned dirty primary line is replaced by another
line and must be written back. In this case it is written directly to memory, bypassing the
secondary cache.
Unlike the primary data cache, the secondary cache supports only block write-back. As noted
earlier, cache lines managed with either of the write-through protocols are not placed in the
secondary cache. A new caching attribute, write-back with secondary and tertiary bypass, allows
the secondary, and tertiary caches to be bypassed entirely. When this attribute is selected, the
secondary and tertiary caches are not filled on load misses and are not written on dirty writebacks from the primary cache.
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Tertiary Cache
:44
4.21
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
11
:43
The RM7000B has direct support for an external tertiary cache. The tertiary cache is direct
mapped and block write-through with byte parity protection for data. The RM7000B tertiary
cache operates identical to the secondary cache of the RM527x while supporting additional size
increments to support 4 MB and 8 MB caches.
20
02
The tertiary interface uses the SysAD bus for data and tags while providing a separate bus,
TcLine[17:0], for addresses, along with a number of tertiary cache specific control signals.
,1
9S
ep
tem
be
r,
A tertiary read looks nearly identical to a standard processor read except that the tag chip enable
signal, TcTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe
and indicating to the external agent that a tertiary cache access is being performed. As a result,
the external agent monitors the tertiary hit signal, TcMatch. If a hit is indicated the external
agent aborts the memory read and refrains from acquiring control of the system interface. Along
with TcTCE*, the processor also asserts the tag data enable signal, TcTDE*, which causes the
tag RAMs to latch the SysAD address internally for use as the replacement tag if a cache miss
occurs.
nT
hu
rsd
ay
On a tertiary miss, a refill is accomplished with a two signal handshake between the data output
enable signal, TcDOE*, which is deasserted by the external agent, and the tag and data write
enable signal, TcCWE*, asserted by the processor. Figure 7 illustrates a tertiary cache hit
followed by a miss.
io
Figure 7 Tertiary Cache Hit and Miss
Tertiary (Hit)
Processor
System
TcWord[1:0]
I0
fo
Index
Data1
uo
TcLine[17:0]
Data0
ef
Addr
I1
I2
Data2
Data3
Addr
Data0
Data1
Data0
Data1
I2
I3
I0
I1
Index
I3
I0
I1
inv
SysAD
liv
SysClock
yV
TcTCE*
loa
de
db
TcMatch
TcDCE*
Tertiary (Miss)
Processor
ett
Master
wn
TcCWE*
Do
TcDOE*
Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For
details of these transactions as well as detailed timing waveforms for all the tertiary cache
transactions, refer to the RM7000 Family User Manual. The tertiary cache tag can easily be
implemented with standard components such as the Motorola MCM69T618.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:44
The RM7000B cache attributes for the instruction, data, internal secondary, and optional external
tertiary caches are summarized in Table 6.
On-chip
Secondary
Size
16 KB
16 KB
256 KB
Associativity
4-way
4-way
4-way
Replacement
Algorithm.
cyclic
cyclic
cyclic
Line size
32 byte
32 byte
Index
vAddr11..0
vAddr11..0
Tag
pAddr35..12
pAddr35..12
Write policy
n.a.
read policy
11
Primary
Data
Tertiary Cache
512 K, 1 M, 2 M,
4 M, or 8 M
direct mapped
direct replacement
32 byte
32 byte
pAddr15..0
pAddr22..0
pAddr35..16
pAddr35..19
write-back, writethrough
block write-back,
bypass
block write-through,
bypass
n.a.
non-blocking (2
outstanding)
non-blocking (data non-blocking (data
only, 2 outstanding) only, 2 outstanding)
read order
critical word first
critical word first
write order
NA
sequential
miss restart
following:
complete line
Parity
per word
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
Primary
Instruction
io
first double (if
waiting for data)
critical word first
sequential
sequential
n.a.
n.a.
per doubleword
per byte
ett
per byte
critical word first
liv
Cache Locking
fo
4.22
Attribute
:43
Table 6 Cache Attributes
yV
inv
ef
uo
The RM7000B allows critical code or data fragments to be locked into the primary and
secondary caches. The user has complete control over the locking function. For instruction and
data fragments in the primary caches, locking is accomplished by setting either or both of the
cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a
load instruction for data, or a Fill_I cache operation for instructions.
Do
wn
loa
de
db
Only cache lines within sets A and B of each cache can be locked. Locking within the secondary
works identically to the primaries using a separate secondary lock enable bit and the same set
selection field. As with the primaries, only sets A and B can be locked. Table 7 summarizes the
cache locking capabilities.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
ECC[27]
ECC[28]=0→A
ECC[28]=1→B
Fill_I
Primary D
ECC[26]
ECC[28]=0→A
ECC[28]=1→B
Load/Store
Secondary
ECC[25]
ECC[28]=0→A
ECC[28]=1→B
Fill_I or
Load/Store
:43
Activate
11
Primary I
Set Select
02
Lock
Enable
4.23
tem
be
r,
20
Cache
:44
Table 7 Cache Locking Control
Cache Management
rsd
ay
,1
9S
ep
To improve the performance of critical data movement operations in the embedded environment,
the RM7000B significantly improves the speed of operation of certain critical cache
management operations. In particular, the speed of the Hit-Writeback-Invalidate and HitInvalidate cache operations has been improved, in some cases by an order of magnitude, over
that of other MIPS processors. For example, Table 8 compares the RM7000B with the R4000
processor.
Penalty
Condition RM7000B
Hit-WritebackInvalidate
Miss
Hit-Clean
12
3+n
14+n
Miss
0
7
2
9
fo
Hit-Invalidate
uo
Hit
7
3
liv
Hit-Dirty
R4000
ett
io
0
nT
Operation
hu
Table 8 Penalty Cycles
yV
inv
ef
For the Hit-Dirty case of Hit-Writeback-Invalidate in Table 8 above, if the writeback buffer is
full from some previous cache eviction, then n is the number of cycles required to empty the
writeback buffer. If the buffer is empty then n is zero.
de
Primary Write Buffer
loa
4.24
db
The penalty value in Table 8 is the number of processor cycles beyond the one cycle required to
issue the instruction that is required to implement the operation.
Do
wn
Writes to secondary cache or external memory, whether cache miss write-backs or stores to
uncached or write-through addresses, use the integrated primary write buffer. The write buffer
holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update. For uncached and
write-through stores, the write buffer significantly increases performance by decoupling the
SysAD bus transfers from the instruction execution stream.
4.25
System Interface
The RM7000B provides a high-performance 64-bit system interface which is compatible with
the RM5200 Family. As an enhancement to the system interface, the RM7000B allows half-
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:44
integral clock multipliers, thereby providing greater granularity when selecting pipeline and
system interface frequencies.
02
11
:43
The system interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit
command bus. In addition, there are ten handshake signals and ten interrupt inputs. The interface
is capable of transferring data between the processor and memory at a peak rate of 1000 Mbyte/s
with a 125 MHz SysClock.
Figure 8 Typical Embedded System Block Diagram
Flash/
Boot
ROM
Address
Control
x
x
9S
ep
DRAM
tem
be
r,
20
Figure 8 shows a typical embedded system using the RM7000B. This example shows a system
with a bank of DRAMs, an optional tertiary cache, and an interface ASIC which provides
DRAM control as well as an I/O port.
8
ay
,1
64
SysCmd
72
External
Agent
hu
RM7000B
rsd
SysAD Bus
PCI Bus
nT
25
ett
Tertiary Cache
(optional)
System Address/Data Bus
uo
4.26
fo
liv
TcLine, etc.
io
72
inv
ef
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM7000B and the rest of the system. It is protected with an 8-bit parity check bus,
SysADC[7:0].
System Command Bus
Do
4.27
wn
loa
de
db
yV
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which the RM7000B transmits data
to the system interface are programmable at boot time via mode control bits. In addition, the rate
at which the processor receives data is fully controlled by the external agent. Therefore, either a
low cost interface requiring no read or write buffering, or a faster, high-performance interface
can be designed to communicate with the RM7000B.
The RM7000B interface has a 9-bit System Command bus, SysCmd[8:0]. The command bus
indicates whether the SysAD bus carries address or data information on a per-clock basis. If the
SysAD bus carries address, the SysCmd bus indicates the transaction type (for example, a read
or write). If the SysAD bus carries data, then the SysCmd bus contains information about the
data (for example, this is the last data word transmitted, or the data contains an error). The
SysCmd bus is bidirectional to support both processor requests and external requests to the
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:44
RM7000B. Processor requests are initiated by the RM7000B and responded to by an external
agent. External requests are issued by an external agent and require the RM7000B to respond.
Handshake Signals
02
4.28
11
:43
The RM7000B supports one- to eight-byte transfers as well as 32-byte block transfers on the
SysAD bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte
address of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
tem
be
r,
20
There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*,
are driven by an external agent to indicate to the RM7000B whether it can accept a new read or
write transaction. The RM7000B samples these signals before deasserting the address on read
and write requests.
,1
9S
ep
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external agent. When an external agent requires control of the bus, it asserts
ExtRqst*. The RM7000B responds by asserting Release* to release the system interface to
slave state.
nT
hu
rsd
ay
PRqst* and PAck* are used to transfer control of the SysAD and SysCmd buses from the
external agent to the processor. These two pins have been added to the SysAD interface to
support multiple outstanding reads and facilitate non-blocking cache operations. When the
processor needs to reacquire control of the interface, it asserts PRqst*. The external agent
responds by asserting PAck* to return control of the interface to the processor.
uo
fo
liv
ett
io
RspSwap* is used by the external agent to indicate to the processor when it is returning multiple
data out of order. For example, when there are two outstanding reads, the external agent asserts
RspSwap* when it is going to return the data for the second read before it returns the data for the
first read. RspSwap* must be asserted by the external agent two cycles ahead of when it presents
data so that the processor has time to switch to the correct address for writes into the tertiary
cache.
yV
inv
ef
RdType is another new pin on the interface that indicates whether a read is an instruction read or
a data read. When asserted, the reference is an instruction read. When deasserted it is a data read.
RdType is only valid during valid address cycles.
System Interface Operation
wn
4.29
loa
de
db
ValidOut* and ValidIn* are used by the RM7000B and the external agent respectively to
indicate that there is a valid command and data on the SysAD and SysCmd buses. The
RM7000B asserts ValidOut* when it is driving these buses with a valid command and data, and
the external agent drives ValidIn* when it has control of the system interface and is driving a
valid command and data.
Do
To support non-blocking caches and data prefetch instructions, the RM7000B allows two
outstanding reads. An external agent may respond to read requests in whatever order it chooses
by using the response order indicator pin RspSwap*. No more than two read requests are
submitted to the external agent. Support for multiple outstanding reads can be enabled or
disabled via a boot-time mode bit. Refer to Table 16 for a complete list of mode bits.
The RM7000B can issue read and write requests to an external agent, while an external agent can
issue null and read responses to the RM7000B.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:43
:44
For processor reads, the RM7000B asserts ValidOut* and simultaneously drives the address and
read command on the SysAD and SysCmd buses. If the system interface has RdRdy* asserted,
then the processor tristates its drivers and releases the system interface to slave state by asserting
Release*. The external agent can then begin sending data to the RM7000B.
02
11
Figure 9 shows a processor block read request and the external agent read response for a system
with either no tertiary cache or a transaction where the tertiary is being bypassed.
20
Figure 9 Processor Block Read
Addr
Data0
Data1
SysCmd
Read
NData
NData
Data2
Data3
NData
NEOD
ep
ValidOut*
tem
be
SysAD
r,
SysClock
9S
ValidIn*
ay
,1
RdRdy*
rsd
WrRdy*
hu
Release*
ett
io
nT
In Figure 9 the read latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern is
DDxxDD. Figure 10 shows a processor block write where the processor was programmed with
write-back data rate boot code 2, or DDxxDDxx.
fo
liv
Figure 11 shows a typical sequence resulting in two outstanding reads both with initial tertiary
cache accesses, as explained in the following sequence.
Do
wn
loa
de
db
yV
inv
ef
uo
1. The processor issues a read which misses in the tertiary cache.
2. The external agent takes control of the bus in preparation for returning data to the processor.
3. The processor encounters another internal cache miss and therefore asserts PRqst* in order
to regain control of the bus.
4. The external agent pulses PAck*, returning control of the bus to the processor.
5. The processor issues a read for the second miss.
6. The second cycle also misses in the tertiary.
7. The RspSwap* pin is asserted to denote the out of order response. Not shown in the figure is
the completion of the data transfer for the second miss, or any of the data transfer for the first
miss.
8. The external agent retakes control of the bus and begins returning data (out of order) for the
second miss to the processor
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 10 Processor Block Write
Data0
Data1
Data2
Data3
SysCmd
Write
NData
NData
NData
NEOD
:43
Addr
11
SysAD
:44
SysClock
02
ValidOut*
20
ValidIn*
tem
be
r,
RdRdy*
WrRdy*
9S
ep
Release*
Processor
Master
System
Tertiary (Miss)
Processor
ay
2
SysCmd
Read1
Data0
Data1
hu
Addr1
Addr2
Data0
Data1
Read2
Data02
Data12
NData
NData
7
io
RspSwap*
System
Tertiary (Miss)
5
nT
SysAD
rsd
SysClock
ett
ValidOut*
liv
8
fo
ValidIn*
uo
Release*
ef
PRqst*
yV
inv
PAck*
3
4
1
6
db
TcMatch
Data Prefetch
de
4.30
,1
Figure 11 Multiple Outstanding Reads
Do
wn
loa
The RM7000B supports the MIPS IV integer data prefetch (PREF ) and floating-point data
prefetch (PREFX ) instructions. These instructions are used by the compiler or by an assembly
language programmer when it is known or suspected that an upcoming data reference is going to
miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be
hidden under the execution of other instructions. In cases where the execution of a prefetch
instruction would cause a memory management or address error exception the prefetch is treated
as a NOP.
The “Hint” field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation)
or it can allocate and fill a cache line with zeroes on a primary data cache miss.
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Enhanced Write Modes
:44
4.31
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
11
:43
The RM7000B implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write on the SysAD bus every four
SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were
wait states.
tem
be
r,
20
02
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD bus utilization. However, at high frequencies the processor may drive a subsequent write
onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the cycle to be missed.
9S
ep
Write reissue mode is an enhancement to pipelined write mode and allows the processor to
reissue missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation,
the cycle is aborted by the processor and reissued at a later time.
rsd
External Requests
hu
4.32
ay
,1
In write reissue mode, a rate of one write every two bus cycles can be achieved. Pipelined writes
have the same two bus cycle write repeat rate, but can issue one additional write following the
deassertion of WrRdy*.
ef
Test/Breakpoint Registers
inv
4.33
uo
fo
liv
ett
io
nT
The RM7000B can respond to certain requests issued by an external agent. These requests take
one of two forms: Write requests and Null requests. An external agent executes a write request
when it wishes to update one of the processors writable resources such as the internal interrupt
register. A null request is executed when the external agent wishes the processor to reassert
ownership of the processor external interface. Once the external agent has acquired control of the
processor interface via ExtRqst*, it can execute a null request after completing an independent
transaction between itself and system memory in a system where memory is connected directly
to the SysAD bus. Normally this transaction would be a DMA read or write from the I/O system.
loa
de
db
yV
To facilitate hardware and software debugging, the RM7000B incorporates a pair of Test/Breakpoint, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately
enabled to watch for a load address, a store address, or an instruction address. All address
comparisons are done on physical addresses. An associated register, Watch Mask, has also been
added so that either or both of the Watch registers can compare against an address range rather
than a specific address. The range granularity is limited to a power of two.
Do
wn
When enabled, a match of either Watch register results in an exception. If the Watch is enabled
for a load or store address then the exception is the Watch exception as defined for the R4000 by
Cause exception code 23. If the Watch is enabled for instruction addresses then a newly defined
Instruction Watch exception is taken and the Cause code is 16. The Watch register which caused
the exception is indicated by Cause bits 25:24. Table 9 summarizes a Watch operation.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 9 Watch Control Register
62
Store
Load
60:36
35:2
Instr
0
Addr
1:0
31:2
1
Mask
Mask
Watch2
Note
Mask
Watch1
r,
The W1 and W2 bits of the Cause register indicate which Watch register caused a particular Watch
exception.
Performance Counters
ep
4.34
0
tem
be
1.
0
20
02
Watch Mask
61
:43
Watch1, 2
63
:44
Bit Field/Function
11
Register
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
To facilitate system tuning, the RM7000B implements a performance counter using two new
CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter
which causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register
containing a 5-bit field which selects one of twenty-two event types as well as a handful of bits
which control the overall counting function. Note that only one event type can be counted at a
time and that counting can occur for user code, kernel code, or both. The event types and control
bits are listed in Table 10.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Event Type
11
02
20
r,
tem
be
ep
9S
,1
ay
rsd
hu
nT
io
ett
liv
Reserved (must be zero)
yV
7:5
Count in Kernel Mode
wn
loa
de
db
8
9
fo
inv
16:
17:
18:
19:
1A:
1B:
1C:
1D:
1E:
Clock cycles
Total instructions issued
Floating-point instructions issued
Integer instructions issued
Load instructions issued
Store instructions issued
Dual issued pairs
Branch prefetches
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Data cache misses
Data TLB misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Primary cache writebacks
Dcache miss stall cycles (cycles where both cache miss tokens taken and a third address is
requested)
Cache misses
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles doe to pending non-blocking loads
Write buffer full stall cycles
Cache instruction stall cycles
Multiplier stall cycles
Stall cycles due to pending non-blocking loads - stall start of exception
uo
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C:
0D:
0E:
0F:
10:
11:
12:
13:
14:
15:
ef
4:0
Description
:43
PerfControl
Field
:44
Table 10 Performance Counter Control
Do
10
0:
1:
Count in User Mode
0:
1:
Disable
Enable
Count Enable
0:
1:
31:11
Disable
Enable
Disable
Enable
Reserved (must be zero)
The performance counter interrupt only occurs when interrupts are enabled in the Status register,
IE=1, and the Interrupt Mask bit 13 (IM13) of the coprocessor 0 interrupt control register is set.
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Interrupt Handling
02
4.35
11
:43
:44
Since the performance counter can be set up to count clock cycles, it can be used as either a
second timer, or a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging
system or software “hangs.” Typically the software is setup to periodically update the count so
that no interrupt occurs. When a hang occurs the interrupt ultimately triggers, thereby breaking
free from the hang-up.
r,
20
In order to provide better real time interrupt handling, the RM7000B provides an extended set of
hardware interrupts, each of which can be separately prioritized and separately vectored.
tem
be
In addition to the standard six external interrupt pins, the RM7000B provides four more interrupt
pins for a total of ten external interrupts.
,1
9S
ep
As described above, the performance counter is also a hardware interrupt source using INT13.
Historically in the MIPS architecture, interrupt 7 (INT7) was used as the timer interrupt. The
RM7000B provides a separate interrupt, INT12, for this purpose, thereby releasing INT7 for use
as a pure external interrupt.
nT
hu
rsd
ay
All interrupts (INT[13:0]), the Performance Counter, and the Timer, have corresponding
interrupt mask bits, IM[13:0], and interrupt pending bits, IP[13:0], in the Status, Interrupt
Control, and Cause registers. The bit assignments for the Interrupt Control and Cause registers
are shown in Table 11 and Table 12. The Status register has not changed from the RM5200
Family and is not shown.
ett
io
The IV bit in the Cause register is the global enable bit for the enhanced interrupt features. If this
bit is clear then interrupt operation is compatible with the RM5200 Family.
uo
fo
liv
In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field as
described below. The Interrupt Mask field (IM[13:8]) contains the interrupt mask for interrupts
eight through thirteen. IM[15:14] are reserved for future use.
ef
Setting the Timer Exclusive (TE) bit moves the Timer interrupt to INT12. Clearing the TE bit
causes the Timer interrupt to be logically OR’ed onto INT7.
db
yV
inv
The setting for Mode Bit 11 is used to determine if the Timer Interrupt replaces the external
interrupt (INT5*) as an input to IP7 in the Cause Register. If Mode Bit 11 is set to 0, the Timer
Interrupt is gated to IP7. If Mode Bit 11 is set to 1, external INT5* is gated to IP7.
wn
loa
de
In order to utilize both the external Interrupt (INT5*) and the internal Timer Interrupt, Mode Bit
11 must be set to 1, and TE must be set to 1. In this case, the Timer Interrupt will utilize IP12,
and INT5* will utilize IP7. Please also reference the logic diagram for interrupt signals in the
RM7000 User Manual.
Do
The Interrupt Control register uses IM13 to enable the Performance Counter Control.
Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority Level
Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).
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RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
BD
29:28
0
27
CE
26
0
25
W2
24
W1
23:8
IV
7
IP[15:0]
0
IM[15:8]
6:5
TE
4:0
0
0
20
7
EXC
Spacing
Table 13 IPLLO Register
23:20
19:16
15:12
IPL7
IPL6
IPL5
IPL4
IPL3
19:16
15:12
11:8
7:4
IPL2
IPL13
IPL12
IPL11
11:8
ay
0
IPL0
IPL10
7:4
3:0
IPL9
IPL8
hu
0
23:20
rsd
27:24
IPL1
,1
Table 14 IPLHI Register
31:28
3:0
ep
27:24
9S
31:28
tem
be
r,
0
15:8
0:1
02
Table 12 Interrupt Control Register
31:16
6:2
:43
30
11
31
:44
Table 11 Cause Register
fo
liv
ett
io
nT
In the IPLLO and IPLHI registers, each interrupt is represented by a four-bit field, thereby
allowing each interrupt to be programmed with a priority level from 0 to 15 inclusive. The
priorities can be set in any manner, including having all the priorities set exactly the same.
Priority 0 is the highest level and priority 15 the lowest. The format of the priority level registers
is shown in Table 13 and Table 14 above. The priority level registers are located in the
coprocessor 0 control register space.
db
yV
inv
ef
uo
In addition to programmable priority levels, the RM7000B also permits the spacing between
interrupt vectors to be programmed. For example, the minimum spacing between two adjacent
vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set
up the vectors as jumps to the actual interrupt service routines or, if interrupt latency is not
paramount, to include the entire interrupt service routine at one vector. Table 15 illustrates the
complete set of vector spacing selections along with the coding as required in the Interrupt
Control register [4:0].
Do
wn
loa
de
In general, the active interrupt priority, combined with the spacing setting, generates a vector
offset which is then added to the interrupt base address of 0x200 to generate the interrupt
exception offset. This offset is then added to the exception base to produce the final interrupt
vector address.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
0x0
0x000
0x1
0x020
0x2
0x040
0x4
0x080
0x8
0x100
0x10
0x200
others
reserved
r,
20
02
11
:43
Spacing
tem
be
4.36
ICR[4:0]
:44
Table 15 Interrupt Vector Spacing
Standby Mode
9S
ep
The RM7000B provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
hu
rsd
ay
,1
Executing the WAIT instruction enables interrupts and causes the processor to enter Standby
Mode. If the SysAD bus is currently idle when the WAIT instruction completes the W pipe stage,
the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or PLL,
internal timer/counter, and the “wake up” input pins: INT[9:0]*, NMI*, ExtReq*, Reset*, and
ColdReset* continue to operate in their normal fashion.
fo
JTAG Interface
uo
4.37
liv
ett
io
nT
If the SysAD bus is not idle when the WAIT instruction completes the W pipe stage, then the
WAIT is treated as a NOP. Once the processor is in Standby, any interrupt, including the internally
generated timer interrupt, causes the processor to exit Standby and resume operation where it left
off. The WAIT instruction is typically inserted in the idle loop of the operating system or real time
executive.
inv
Boot-Time Options
yV
4.38
ef
The RM7000B interface supports JTAG boundary scan in conformance with IEEE 1149.1. The
JTAG interface is useful for checking the integrity of the processor’s pin connections.
Boot-Time Modes
wn
4.39
loa
de
db
The RM7000B operating modes are initialized at power-up by the boot-time mode control
interface. The serial boot-time mode control interface operates at a very low frequency
(SysClock divided by 256), allowing the initialization information to be kept in a low cost
EPROM or system interface ASIC.
Do
The boot-time serial mode stream is defined in Table 16. Bit 0 is presented to the processor as the
first bit in the stream following VCCOK being asserted. Bit 255 is the last bit transferred.
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 16 Boot Time Mode Stream
System configuration identifiers - software
visible in processor Config[21:20] register
Write-back data rate
19:18
Reserved: Must be zero
11
02
20
r,
tem
be
ep
,1
rsd
25
JTLB Size.
48 dual-entry
64 dual-entry
db
de
On-chip secondary cache control.
0:
1:
26
loa
wn
Do
Reserved: Must be zero
0:
1:
Disable
Enable
Output driver strength - 100% = fastest
00:
01:
10:
11:
15
24
Internal Timer Interrupt gated to IP7
External INT5* gated to IP7
Enable the external tertiary cache
0:
1:
14:13
hu
Timer Interrupt Enable/Disable
0:
1:
12
23:21
R4000 compatible non-block writes
reserved
pipelined non-block writes
non-block write re-issue
yV
11
nT
Non-Block Write Control
00:
01:
10:
11:
Integer multipliers (2,3,4,5,6,7,8,9)
Half integer multipliers (2.5,3.5,4.5)
liv
Little endian
Big endian
fo
10:9
0:
1:
ett
Specifies byte ordering. Logically ORed with
BigEndian input signal.
0:
1:
Pclock to SysClock multipliers.
ay
Multiply by 2/x
Multiply by 3/x
Multiply by 4/x
Multiply by 5/2.5
Multiply by 6/x
Multiply by 7/3.5
Multiply by 8/x
Multiply by 9/4.5
io
0:
1:
2:
3:
4:
5:
6:
7:
8
20
SysClock to Pclock Multiplier
Mode bit 20 = 0 / Mode bit 20 = 1
uo
7:5
DDDD
DDxDDx
DDxxDDxx
DxDxDxDx
DDxxxDDxxx
DDxxxxDDxxxx
DxxDxxDxxDxx
DDxxxxxxDDxxxxxx
DxxxDxxxDxxxDxxx
reserved
9S
0:
1:
2:
3:
4:
5:
6:
7:
8:
9-15:
:43
17:16
ef
4:1
Reserved: Must be zero
inv
0
Mode bit Description
:44
Mode bit Description
Enable two outstanding reads with out-oforder return
0:
1:
255:27
Disable
Enable
Disable
Enable
Reserved: Must be zero
67% strength
50% strength
100% strength
83% strength
External tertiary cache RAM type:
0:
1:
Dual-cycle deselect (DCD)
Single-cycle deselect (SCD)
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Pin Descriptions
:44
5
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
:43
The following is a list of control, data, clock, tertiary cache, interrupt, and miscellaneous pins of
the RM7000B.
Description
ExtRqst*
Input
External request
Signals that the external agent is submitting an external request.
Release*
Output
Release interface
Signals that the processor is releasing the system interface to slave
state
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write
request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd
bus.
PRqst*
Output
Processor Request
When asserted this signal requests that control of the system interface
be returned to the processor. This is enabled by Mode Bit 26.
PAck*
Input
RspSwap*
Input
02
Type
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
Pin Name
11
Table 17 System Interface
RdType
Output
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the
processor that it has been granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor when
it is about to return a memory reference out of order; i.e., of two
outstanding memory references, the data for the second reference is
being returned ahead of the data for the first reference. In order that the
processor will have time to switch the address to the tertiary cache, this
signal must be asserted a minimum of two cycles prior to the data itself
being presented. Note that this signal works as a toggle; i.e., for each
cycle that it is held asserted the order of return is reversed. By default,
anytime the processor issues a second read it is assumed that the
reads will be returned in order; i.e., no action is required if the reads are
indeed returned in order. This is enabled by Mode Bit 26.
Read Type
During the address cycle of a read request, RdType indicates whether
the read request is an instruction read or a data read.
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Description
SysAD[63:0]
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
SysADC[7:0]
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
SysCmd[8:0]
Input/Output
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
SysCmdP
Input/Output
System Command/Data Identifier Bus Parity
For the RM7000B, unused on input and zero on output.
20
02
11
:43
:44
Type
tem
be
r,
Pin Name
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Description
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
VCCP
Input
VCC for PLL
,1
9S
Type
nT
hu
rsd
ay
Pin Name
ep
Table 18 Clock/Control Interface
VSSP
io
Quiet VCCInt for the internal phase locked loop. Must be connected to
VCCInt through a filter circuit.
VSS for PLL
ett
Input
uo
fo
liv
Quiet VSS for the internal phase locked loop. Must be connected to
VSSInt through a filter circuit.
Table 19 Tertiary Cache Interface
Output
db
yV
inv
TcCLR*
Type
ef
Pin Name
Tertiary Cache Write Enable
Asserted to cause a write to the cache. Two identical signals are
provided to balance the capacitive load relative to the remaining cache
interface signals.
Output
Tertiary Cache Data RAM Chip Enable
When asserted this signal causes the data RAMs to read out their
contents. Two identical signals are provided to balance the capacitive
load relative to the remaining cache interface signals
Input
Tertiary Cache Data RAM Output Enable
When asserted this signal causes the data RAMs to drive data onto
their I/O pins. This signal is monitored by the processor to determine
when to drive the data RAM write enable in a tertiary cache miss refill
sequence.
loa
wn
Do
TcDCE[1:0]*
TcDOE*
Tertiary Cache Block Clear
Requests that all valid bits be cleared in the Tag RAMs. Many RAMs
may not support a block clear therefore the block clear capability is not
required for the cache to operate.
Output
de
TcCWE[1:0]*
Description
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Output
Tertiary Cache Line Index
TcMatch
Input
Tertiary Cache Tag Match
This signal is asserted by the cache Tag RAMs when a match occurs
between the value on its data inputs and the contents of the addressed
location in the RAM.
TcTCE*
Output
Tertiary Cache Tag RAM Chip Enable
When asserted this signal will cause either a probe or a write of the Tag
RAMs depending on the state of the Tag RAMs write enable signal.
This signal is monitored by the external agent and indicates to it that a
tertiary cache access is occurring.
TcTDE*
Output
Tertiary Cache Tag RAM Data Enable
When asserted this signal causes the value on the data inputs of the
Tag RAM to be latched into the RAM. If a refill of the RAM is necessary,
this latched value will be written into the Tag RAM array. Latching the
Tag allows a shared address/data bus to be used without incurring a
penalty to re-present the Tag during the refill sequence.
TcTOE*
Output
Tertiary Cache Tag RAM Output Enable
When asserted this signal causes the Tag RAMs to drive data onto their
I/O pins.
TcWord[1:0]
Input/Output
Tertiary Cache Double Word Index
Driven by the processor on cache hits and by the external agent on
cache miss refills.
TcValid
Input/Output
Tertiary Cache Valid
This signal is driven by the processor as appropriate to make a cache
line valid or invalid. On Tag read operations the Tag RAM will drive this
signal to indicate the line state.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:43
:44
TcLine[17:0]
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PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 20 Interrupt Interface
Description
INT[9:0]*
Input
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the
interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6
in R5000 compatibility mode).
:44
Type
20
02
11
:43
Pin Name
tem
be
Description
JTDI
Input
JTAG data in
JTAG serial data in.
JTCK
Input
JTAG clock input
JTAG serial clock input.
JTDO
Output
JTAG data out
JTAG serial data out.
JTMS
Input
JTAG command
JTAG command signal, signals that the incoming serial data is
command data.
rsd
ay
,1
9S
ep
Type
nT
hu
Pin Name
r,
Table 21 JTAG Interface
Description
BigEndian
Input
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without
rewriting the mode ROM.
VCCOK
Input
ett
Type
yV
inv
ef
uo
fo
liv
Pin Name
io
Table 22 Initialization Interface
Input
When asserted, this signal indicates to the RM7000B that the VCCInt
power supply has been above the recommended value for more than
100 milliseconds and will remain stable. The assertion of VCCOK
initiates the reading of the boot-time mode control serial stream.
Cold Reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Input
Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
ModeClock
Output
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
ModeIn
Input
Boot Mode Data In
Serial boot-mode data input.
Do
wn
loa
Reset*
de
db
ColdReset*
VCC is OK
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:44
Absolute Maximum Ratings1
Limits
Unit
VTERM
Terminal Voltage with respect to VSS
–0.52 to +3.9
TCASE
Operating Temperature
0 to +85
TSTG
Storage Temperature
–55 to +125
IIN
DC Input Current3
±20
IOUT
DC Output Current4
±20
:43
Rating
20
02
11
Symbol
V
°C
°C
mA
mA
r,
6
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
tem
be
Notes
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 V.
3.
When VIN < 0V or VIN > VCCIO
4.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30
seconds.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
1.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
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:44
Recommended Operating Conditions
Temperature
VSS
VCCInt
VCCIO
VCCP
450 MHz
0°C to +85°C
(Case)
0V
1.5 V ± 50 mV
3.3 V ± 150 mV
or
2.5 V ± 200 mV
1.5 V ± 50 mV
500 MHz
0°C to +70°C
(Case)
0V
1.6 V ± 50 mV
3.3 V ± 150 mV
or
2.5 V ± 200 mV
1.6 V ± 50 mV
:43
CPU Speed
20
02
11
7
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
tem
be
r,
Notes
VCCIO should not exceed VCCInt by greater than 2.0 V during the power-up sequence.
2.
Applying a logic high state to any I/O pin before VCCInt becomes stable is not recommended.
3.
As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering
JTAG test mode. Refer to the RM7000B Family Users Manual, Appendix E.
4.
VCCP must be connected to VCCInt through a passive filter circuit. See the RM7000 Family User’s
Manual for recommended circuit.
5.
The 500 MHz production part specified with VCCInt = 1.6 V at 70°C also guarantees operation at
475 MHz with VCCInt = 1.5 V at 85°C.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
1.
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DC Electrical Characteristics
:44
8
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
VOL
VOH
Maximum
Conditions
0.2 V
|IOUT|= 100 µA
0.4 V
|IOUT| = 2 mA
20
VOL
02
VCCIO - 0.2 V
2.4 V
VIL
-0.3 V
0.8 V
VIH
2.0 V
VCCIO + 0.3 V
r,
VOH
VIN = 0
9S
ep
±15 µA
±15 µA
IIN
,1
Table 24 (VCCIO = 2.3V – 2.7V)
Minimum
VOH
Conditions
0.2 V
|IOUT|= 100 µA
rsd
VOL
hu
2.1 V
VOL
nT
0.4 V
2.0
io
VOH
VIL
-0.3 V
VIH
1.7 V
fo
1.7
uo
VOH
liv
ett
VOL
0.7 V
|IOUT| = 1 mA
|IOUT| = 2 mA
0.7 V
VCCIO + 0.3 V
±15 µA
±15 µA
VIN = 0
VIN = VCCIO
Do
wn
loa
de
db
yV
inv
ef
IIN
VIN = VCCIO
Maximum
ay
Parameter
:43
Minimum
11
Parameter
tem
be
Table 23 (VCCIO = 3.15V – 3.45V)
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Power Consumption
:44
9
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
CPU Speed
600
02
standby
2
Maximum with no FPU operation
2500
Maximum worst case instruction mix
3150
20
active
Max1
600
2800
3500
r,
VCCInt
Power
(mWatts)
Max1
Conditions
11
Parameter
:43
450 MHz 500 MHz
tem
be
Notes
Worst case supply voltage (maximum VCCInt) with worst case temperature (maximum TCase).
2.
Dhrystone 2.1 instruction mix.
3.
I/O supply power is application dependant, but typically <20% of VCCInt.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
1.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
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AC Electrical Characteristics
10.1
Capacitive Load Deration
CLD
Max
Units
2
ns/25pF
02
Clock Parameters
Conditions
Min
tem
be
450 MHz
Max
SysClock High
tSCHigh
Transition ≤ 2 ns
3
SysClock Low
tSCLow
Transition ≤ 2 ns
ep
Symbol
Test
9S
3
SysClock Frequency
tJitterIn
SysClock Rise Time
tSCRise
SysClock Fall Time
tSCFall
ModeClock Period
tModeCKP
JTAG Clock Period
tJTAGCKP
3
ns
3
ns
125
33.3
125
MHz
30
8.5
30
ns
±150
±150
ps
2
2
ns
2
2
ns
256
256
tSCP
rsd
hu
nT
Units
4
4
tSCP
liv
Operation of the RM7000B is only guaranteed with the Phase Lock Loop Enabled.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
1.
Max
ett
Note
Min
10
ay
Clock Jitter for
SysClock
500 MHz
33.3
,1
tSCP
io
SysClock Period
r,
CPU Speed
Parameter
:43
Load Derate
Min
11
Symbol
20
10.2
Parameter
:44
10
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
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System Interface Parameters
:44
10.3
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
CPU Speed
mode14..13 = 015,6 (slowest)
1.0
5.5
1.0
tDS6
trise = see above table
2.5
2.5
ns
tDH
tfall = see above table
1.0
1.0
ns
Data Hold4
(fastest)
r,
Data Setup4
mode14..13 = 10
02
4.5
tDO
1.0
Max Units
1.0
Data Output2,3
5,6
Notes
4.5
ns
5.5
ns
Timings are measured from 0.425 x VCCIO of clock to 0.425 x VCCIO of signal for 3.3V I/O. Timings
are measured from 0.48 x VCCIO of clock to 0.48 x VCCIO of signal for 2.5V I/O.
2.
Capacitive load for all output timings is 50 pF.
3.
Data Output timing applies to all signal pins whether tristate I/O or output only.
4.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5.
Only mode 14:13 = 10 is tested and guaranteed.
6.
Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by 0.5 nS.
hu
rsd
ay
,1
9S
ep
1.
Mode Data Setup
tDS
Mode Data Hold
tDH
io
Symbol
liv
ett
Parameter
nT
Boot-Time Interface Parameters
Min
Max
Units
4
SysClock cycles
0
SysClock cycles
Do
wn
loa
de
db
yV
inv
ef
uo
fo
10.4
Max Min
11
Min
20
Symbol Test Conditions
tem
be
Parameter
500 MHz
:43
450 MHz
1
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
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Timing Diagrams
11.1
Clock Timing
:43
Clock Timing
11
Figure 12
:44
11
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
tHigh
tLow
±tJitterIn
20
tFall
11.2
tem
be
r,
tRise
02
SysClock
System Interface Timing
9S
Input Timing
,1
Figure 13
ep
(SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
rsd
ay
SysClock
tDH
Data
Output Timing
ett
Figure 14
io
nT
hu
Data
tDS
uo
fo
liv
SysClock
tDOmin
Data
Data
Do
wn
loa
de
db
yV
inv
ef
Data
tDOmax
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Thermal Information
:44
12
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
76°C at 500 MHz
02
11
Maximum long-term operating junction temperature to ensure adequate long-term
life
:43
This product is designed to operate over a wide temperature range when used with a heat sink
and is suited for commercial applications such as central office equipment.
76°C at 500 MHz
90°C at 450 MHz
tem
be
r,
20
Maximum junction temperature for short-term excursions with guaranteed continued
functional performance
90°C at 450 MHz
1.3
(°C/W)
4.6
nT
hu
rsd
ΘJB
,1
ΘJC (°C/W)
9S
2
ay
Device Compact Model
4.2 W
ett
Power at 500 MHz
liv
VccInt = 1.6 V
uo
fo
VccI/O = 3.3 V
ΘSA
Heat Sink
ΘCS
Case
ΘJC
Device Compact
Model
Junction
ΘJB
inv
ef
Board
yV
Notes
Ambient
3.8 W
VccInt = 1.5 V
VccI/O = 3.3 V
io
Operating power is dissipated in package
(watts) at worst case power supply
Power at 450 MHz
-5°C
ep
Minimum ambient temperature
Short-term is understood as the definition stated in Telcordia Generic Requirements GR-63-Core.
2.
ΘJC, the junction-to-case thermal resistance, ΘJB, the junction-to-board thermal resistance are
obtained from Package vendor.
3.
ΘSA is the thermal resistance of the heat sink to ambient. ΘCS is the thermal resistance of the heat sink
attached material.
4.
The actual ΘSA required may vary according to the air speed at the location of the device in the system
with all the components in place.
Do
wn
loa
de
db
1.
5.
The 500 MHz production part (VCCInt = 1.6 V, maximum long-term operating junction temperature =
76°C, maximum junction temperature for short-term excursions = 76°C) also guarantees operation at
475 MHz; with VCCInt = 1.5 V, maximum long-term operating junction temperature = 90°C, and
maximum junction temperature for short-term excursions = 90°C.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
43
304 TBGA Drawing
1.27 mm
:43
Figure 15
:44
Packaging Information
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OO
A1 ball
corner
ink mark
02
1.27 mm
11
D
20
13
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
r,
E1, N
e
ep
DETAIL B
tem
be
E
e
9S
D1, M
BOTTOM VIEW
,1
TOP VIEW
rsd
A
b
ay
DETAIL A
SIDE VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
f
hu
A2
DETAIL B
aaa
ett
A1
io
nT
P
liv
DETAIL A
Min
A
Nominal
1.45
0.60
A2
0.85
inv
ef
A1
30.80
yV
D, E
M,N
0.65
e
Max
Note
1.65
Overall Thickness
0.65
0.70
Ball Height
0.90
0.95
Body Thickness
31.00
31.20
27.94
23 x 23
0.75
Body Size
Ball Footprint
Ball Matrix
Number of Rows Deep
0.85
1.27
Ball Diameter
Ball Pitch
aaa
0.15
Coplanarity
bbb
0.15
Parallel
wn
Do
1.55
4
loa
de
M1
db
D1, E1
b
uo
Symbol
fo
Body Size: 31.0 x 31.0 mm Package
f
P
0.30
0.35
0.25
0.40
Seating Plan Clearance
Encapsulation Height
Note:
1.
All dimensions in millimeters unless otherwise indicated.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
44
RM7000B Pinout
:44
14
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Function
Pin
Function
Pin
Function
Pin
Function
A1
VCCIO
A2
VSSlO
A3
VSSlO
A4
TcLine11
A5
Do not connect
A6
VSSlO
A7
Do Not Connect
A8
A9
SysAD32
A10
SysADC1
A11
Do Not Connect
A12
A13
VCClnt
A14
VCClnt
A15
SysAD63
A16
A17
SysAD61
A18
VSSlO
A19
Do Not Connect
A21
VSSlO
A22
VSSlO
A23
VCCIO
B2
VCCIO
B3
VSSlnt
B4
VSSlO
B6
SysAD35
B7
SysAD34
B8
VCClnt
B10
SysADC5
B11
SysADC0
B12
B14
SysADC6
B15
Do Not Connect
B18
SysAD28
B19
B22
VCCIO
C3
:43
Pin
11
02
20
VSSlO
VSSlO
VSSlnt
B5
TcLine10
B9
SysAD33
Do Not Connect
B13
SysADC7
B16
SysAD30
B17
SysAD29
TcLine5
B20
VSSlO
B21
VSSlnt
B23
VSSlO
C1
VSSlO
C2
VSSlnt
VCCIO
C4
VCCIO
C5
Do Not Connect
C6
TcLine9
C7
SysAD3
C8
SysAD2
C9
C10
SysAD0
C11
SysADC4
C12
VCClnt
hu
VCClnt
C13
SysADC3
C14
SysADC2
C15
SysAD62
C16
VCClnt
C17
SysAD60
C18
TcLine6
C19
Do Not Connect
C20
VCCIO
C21
VCCIO
C22
VSSlnt
C23
VSSlO
D1
TcLine13
D2
VSSlO
D3
VCCIO
D4
VCCIO
D5
VCCIO
D6
VCCIO
D7
TcLine8
D8
VCClnt
D9
VCCIO
D10
SysAD1
D11
VCClnt
D12
VCCIO
D13
VCClnt
D14
SysAD31
D15
VCCIO
D16
VCClnt
D17
TcLine7
D18
VCCIO
D19
VCCIO
D20
VCCIO
D21
VCCIO
D22
VSSlO
D23
Do Not Connect
E1
VCClnt
E2
TcLine14
E3
TcLine12
E4
VCCIO
E20
VCCIO
E21
Do Not Connect
E22
Do Not Connect
E23
TcLine1
F1
VSSlO
F2
TcLine16
F3
TcLine15
F4
VCCIO
F20
VCCIO
F21
TcLine3
F22
TcLine0
F23
VSSlO
G1
SysAD36
G2
SysAD4
G3
TcLine17
G4
VCClnt
G20
TcLine2
G21
VCClnt
G22
SysAD59
G23
SysAD58
H1
VSSlO
H2
SysAD37
H3
SysAD5
H4
Do Not Connect
H20
VCClnt
H21
SysAD27
H22
SysAD26
H23
VSSlO
J1
SysAD7
J2
SysAD6
J3
VCClnt
J4
VCCIO
J20
VCCIO
J21
VCClnt
J22
SysAD57
J23
SysAD56
K1
SysAD40
K2
SysAD8
K3
SysAD39
K4
SysAD38
ep
9S
,1
ay
rsd
nT
io
ett
liv
fo
ef
inv
db
de
loa
wn
Do
tem
be
B1
uo
TcLine4
yV
r,
A20
VSSlO
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
45
Function
Pin
Function
Pin
Function
SysAD25
K21
SysAD24
K22
SysAD55
K23
SysAD23
L1
SysAD10
L2
SysAD41
L3
SysAD9
L4
VCClnt
L20
VCClnt
L21
SysAD54
L22
SysAD22
L23
M1
VSSlO
M2
SysAD11
M3
SysAD42
M4
M20
VCCIO
M21
SysAD52
M22
SysAD21
M23
VSSlO
N1
SysAD43
N2
VCClnt
N3
SysAD12
N4
SysAD44
N20
SysAD19
N21
SysAD51
N22
VCClnt
N23
SysAD20
P1
SysAD13
P2
SysAD45
P3
SysAD14
P4
VCClnt
P20
VCClnt
P21
SysAD49
P22
SysAD18
P23
SysAD50
R1
SysAD46
R2
SysAD15
R3
SysAD47
R4
VCCIO
R20
VCCIO
R21
SysAD16
R22
SysAD48
R23
SysAD17
T1
VSSlO
T2
RspSwap*
T3
PRqst*
T4
VCClnt
T20
ExtRqst*
T21
VccOK
T22
T23
VSSlO
U1
PAck*
U2
VCClnt
U3
ModeClock
U4
JTCK
U20
VCClnt
U21
NMI*
U22
Reset*
U23
ColdReset*
V1
VSSlO
V2
JTDO
JTMS
V4
VCCIO
V20
VCCIO
V21
INT9*
V22
VCClnt
V23
VSSlO
W1
JTDI
W2
VCCIO
W3
Do Not Connect
W4
VCCIO
W20
VCCIO
W21
INT6*
W22
INT8*
W23
VCClnt
Y1
Do Not Connect
Y2
VSSlO
Y3
VCCIO
Y4
VCCIO
Y5
VCCIO
Y6
VCCIO
Y7
RdRdy*
Y8
Release*
Y9
VCCIO
Y10
Y11
VCClnt
Y12
VCCIO
Y13
SysCmd5
Y14
VCClnt
Y15
VCCIO
Y16
VCClnt
Y17
INT2*
Y18
VCCIO
Y19
VCCIO
Y20
VCCIO
Y21
VCCIO
Y22
VSSlO
Y23
INT7*
AA1
VSSlO
AA2
VSSlnt
AA3
VCCIO
AA4
VCCIO
AA5
Do Not Connect
AA6
TcMatch
AA7
ValidOut*
AA8
SysClock
AA9
VCClnt
ef
inv
:43
11
SysAD53
02
20
r,
tem
be
ep
9S
,1
ay
rsd
fo
liv
ett
io
nT
V3
TcWord0
db
de
BigEndian
:44
K20
hu
Pin
uo
Function
yV
Pin
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
VCCIO
Do Not Connect
AA11
Do Not Connect
AA12
SysCmd0
AA13
SysCmd4
AA14
SysCmd8
AA15
TcTCE*
AA16
TcValid
AA17
VCClnt
AA18
INT3*
AA19
Do Not Connect
AA20
VCCIO
AA21
VCCIO
AA22
VSSlnt
AA23
VSSlO
AB1
VSSlO
AB2
VCCIO
AB3
VSSlnt
AB4
VSSlO
AB5
Modeln
AB6
Validin*
AB7
VCCP
AB8
VCClnt
AB9
VCClnt
AB10
TcCWE0*
AB11
TcDCE0*
AB12
SysCmd1
AB13
SysCmd3
AB14
SysCmd7
AB15
TcClr*
AB16
TcTDE*
AB17
TcDOE*
AB18
INT0*
AB19
INT4*
AB20
VSSlO
AB21
VSSlnt
AB22
VCCIO
Do
wn
loa
AA10
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
46
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Function
Pin
Function
Pin
Function
Pin
Function
AB23
VSSlnt
AC1
VCCIO
AC2
VSSlnt
AC3
VSSlO
AC4
RdType
AC5
WrRdy*
AC6
VSSlO
AC7
VSSP
AC8
VSSlO
AC9
TcWord1
AC10
TcCWE1*
AC11
AC12
VSSlO
AC13
SysCmd2
AC14
SysCmd6
AC15
AC16
VSSlO
AC17
TcTOE*
AC18
VSSlO
AC19
INT1*
AC20
INT5*
AC21
VSSlO
AC22
VSSlO
AC23
VCCIO
:43
:44
Pin
SysCmdP
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
TcDCE1*
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
47
RM7000B -123
T
:44
Ordering Information
I
:43
15
PM
RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
02
tem
be
r,
T = TBGA
20
Package Type:
11
Temperature Grade:
(blank) = commercial
I = Industrial
ep
Device Maximum Speed
,1
9S
Device Type
B = 0.13 micron process geometry
ay
Valid Combinations
rsd
RM7000B-450T
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
RM7000B-500T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010588, Issue 3
48