UT01VS50L - Aeroflex Microelectronic Solutions

Standard Products
UT01VS50L Voltage Supervisor
Data Sheet
July 28, 2014
www.aeroflex.com/voltsupv
FEATURES
INTRODUCTION
 4.75V to 5.5V Operating voltage range
 Power supply (VDD) monitor set by the internal voltage
reference at 4.65V
 Precision Input Voltage Monitor using an internal 1.25V
voltage reference
 Watchdog Timer Circuit monitoring activity on WDI input
- Nominal timeout 1.6s
 RESET output responding to the VDD monitor and the
manual reset input MR
- Nominal RESET pulse width 200ms
 RESET level valid for VDD>=1.2V
 Operating Temperature Range -55oC to +125oC
 Low Power, Typical 400uA
 Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm2/mg @125oC
- SET Immune: <80 MeV-cm2/mg
 Packaging options:
- 8-lead dual-in-line flatpack
 Standard Microelectronics Drawing (SMD) 5962-11213
- QML Q and V
The UT01VS50L’s function is to monitor vital supply and signal
voltages in microprocessor systems. It provides for safe reset
during power up, power down and brownout conditions by using
an internal precision voltage reference.
The UT01VS50L monitors activity at an independent watchdog
input by employing an internal timer and a watchdog output that
goes low if the input is not toggled within 1.6s. It provides for
precision voltage threshold detection on an independent voltage
input which could be used for battery or supply-low monitoring
of a supply voltage other than VDD.
The UT01VS50L includes an active low manual reset with an
internal pull-up.
APPLICATIONS
 Voltage Supervisor function for various systems including
microprocessors, microcontrollers, DSPs and FPGAs
 Critical battery and power supply monitoring
 Replacement of older discrete solutions to improve reliability,
accuracy and reduce complexity of the systems
WDO
RESET &
DIGITAL CONTROL
MR
VDD
RESET
+
-
WDI TIMER
4.65 V
GND
VREF
1.25 V
WDI TRANSITION
DETECTOR
OSC
WDI
-
PFO
PFI
+
Figure 1. UT01VS50L Functional Block Diagram
1
PIN DESCRIPTIONS
Number
Pins
Type
Description
1
MR
Digital Input
TTL/CMOS
compatible
Manual Reset Input with an internal pull-up. Active low. MR low forces the reset
output RESET low. Required minimum MR pulse width is 150ns. RESET is held low
for duration of the reset timer.
2
VDD
Supply
Power supply. Operating voltage range is 4.75V to 5.5V. VDD level is monitored
internally by a dedicated comparator circuit, which employs an internal bandgap
voltage reference nominally equal to 1.25V. Every time VDD falls below the threshold
voltage, nominally 4.65V, RESET and WDO outputs are forced low. (See WDO and
RESET descriptions.) (Figure 4.)
3
GND
Supply
ASIC Ground. This pin should be tied to ground and establishes the reference for
voltage detection.
4
PFI
Analog Input
Threshold detector input. Voltage on this input is fed directly to an internal
comparator where it is compared to the bandgap voltage reference of 1.25V. It can be
used for detection of low battery or power failure of voltage supplies other than VDD.
When voltage at PFI input drops below its threshold value of 1.25V, PFO output is
forced low, otherwise, stays high.
5
PFO
Digital Output
Threshold detector output. Active low, push-pull output driver. It responds directly
to PFI input. If PFI voltage is below the bandgap reference voltage, PFO is low. If PFI
is above the reference voltage, PFO output is high.
6
WDI
Digital Input
Watchdog timer input pin. This pin is typically used to monitor microprocessor
activity. It can assume three states: low, high and float. If WDI is floating or connected
to a high impedance three state buffer, the watchdog timer is not active, and the
corresponding watchdog output WDO is high. Watchdog timer is also not active any
time RESET is low. Providing that RESET is not asserted, any change of state at WDI
that is longer than 50ns will start the timer, or restart it, if the timer is already running
(Figure 3.). If there is no activity within the timeout period, nominally 1.6sec, the
timer will stop running and WDO output will go low (Figure 3).
7
RESET
Digital Output
Reset output. Active low, push-pull output driver. This output responds to both: VDD
monitoring circuits and the manual reset input MR.
On power up, RESET is guaranteed to be logic low for all VDD values from 1.2V up
to the reset threshold, nominally 4.65V. Once this threshold is reached, an internal
RESET timer is activated. During the countdown RESET output is kept low. It is
raised high upon completion of countdown, typically after 200ms. If a brown out
condition occurs during the reset timer countdown, the reset timer would be reset and
another countdown would start after VDD levels were restored above the reset
threshold. On power down, when VDD falls below the threshold voltage, RESET goes
low and is guaranteed to stay low until VDD drops below 1.2V.
If MR is asserted low, RESET is forced low and the reset timer is kept reset. When
MR is released high, the timer is activated and RESET is kept low until completion
of the reset timeout, when it is raised high.
2
Number
Pins
Type
Description
8
WDO
Digital Output
Watchdog output. Active low, push-pull output driver. This pin is usually connected
to a non-maskable interrupt input of a microprocessor. On power up, WDO responds
to VDD monitoring circuitry. It stays low until the reset threshold, 4.65V nominally,
is reached. At that point, WDO is raised high. The internal watchdog timer is activated
after RESET is released. If there is no activity on WDI input, WDO goes low after
the watchdog timer times out, which is typically after 1.6sec. Any activity on WDI
will force WDO output to go high and the watchdog timer will be activated. If WDI
is floating or connected to a high impedance buffer output, the timer is kept in a reset
state and WDO stays high. When VDD drops below 4.65V, WDO goes low regardless
of whether the watchdog timer has timed out or not. RESET goes low simultaneously
which prevents an interrupt.
If WDI input is left unconnected, WDO can be used as a low line output. Since a
floating WDI disables the internal watchdog timer, WDO goes low when VDD drops
below 4.65V, thus, functioning as a low line output. (Figure 4.)
MR
VCC
1
8
WDO
2
7
RESET
UT01VS50L
GND
3
6
WDI
PFI
4
5
PFO
Figure 2. UT01VS50L Pin Configuration
3
OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
UNITS
Total Ionizing Dose (TID)
300
krad(Si)
Single Event Latchup Immune (SEL)
<110
MeV-cm2/mg
Single Event Transient Immune (SET)
<80
MeV-cm2/mg
ABSOLUTE MAXIMUM RATINGS 1
(Referenced to GND)
SYMBOL
LIMITS
UNITS
Voltage supply
7.2
V
TJ
Maximum junction temperature
175
°C
T
Storage temperature
-65 to +150
°C
PD
Power dissipation
2.5
W
Vin
Input voltages
-0.3V to (VDD+0.3V)
V
+300
°C
15
°C/W
1000
V
VDD
PARAMETER
Tiead
Lead Temperature (soldering, 10 seconds)
ΘJC
Thermal resistance, junction-to-case
VESD
ESDHBM
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNITS
VDD
Positive supply voltage
4.75 to 5.5
V
TC
Case temperature range
-55 to +125
°C
GND
Negative supply voltage
0.0
V
4
ELECTRICAL CHARACTERISTICS 1,2
(VDD = 4.75V to 5.5V:-55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
530
μA
0.8
V
Power Supply
IDD
VDD supply current
VDD=5.5V
Digital Inputs and Outputs (MR, RESET, WDI, WDO, PFO)
VIL
Digital input low
VDD=4.75V
VIH
Digital input high
VDD=5.5V
VIL_MR
Manual reset input low
VDD=4.75V
VIH_MR
Manual reset input high
VDD=5.5V
VOL3
Digital output low
VDD=4.75V, IOL =3.2mA
VOH3
Digital output high
VDD=4.75V, IOH =800μA
3.5
V
0.8
2.0
V
V
0.4
VDD - 1.5
V
V
Timing and Threshold Voltages
VDD falling reset assertion
VDD < 4.5V
0.2
0.8
μs
tRS
Reset pulse width
VDD=4.75V
140
280
ms
tWD
Watchdog time-out period
VDD=5.5V
1.0
2.25
s
tWP
Watchdog input pulse width
VDD=4.75V, VIL = 0.4V,
VIH =0.8XVDD
50
VRT
Reset threshold voltage
4.5
Reset threshold voltage hysteresis
20
mV
150
ns
tRST-ASSRT4
VRTHYS
tMR
Manual reset (MR) input pulse
width
VDD=4.75V
tMD
Manual reset (MR) to reset out
delay
VDD=4.75V
IPFI4
Threshold detector input (PFI)
current
VDD=5.5V
VPFI
Threshold detector input (PFI)
threshold voltage
IMR
IWDI
ns
4.75
V
100
ns
-20
20
nA
VDD=5.0V
1.20
1.30
V
Manual reset pull-up current
VDD=5.5V, MR=0.0V
-500
-100
μA
Watchdog input (WDI) current
WDI pin = VDD = 5.5V
WDI pin = 0V; VDD = 5.5V
35
-35
μA
μA
Analog Input PFI
tRPFI
PFI rising threshold crossing to
PFO delay
15
μs
tFPFI
PFI falling threshold crossing to
PFO delay
35
μs
5
Notes:
1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance at 25oC per MIL-STD-883 Method 1019, Condition A, up to
the maximum TID level procured (see ordering information).
2. Unless otherwise specified, VDD = 4.75V to 5.5V, -55°C < TC < +125°C. RESET is the only parameter operable within 1.2V and the minimum recommended
operating supply voltage.
3. VOL, VOH characteristics apply to WDO, PFO and RESET
4. Guaranteed by design, but not tested.
6
tMR
VDD
MR
GND
tWP
tWD
tWD
VDD
WDI
GND
tWD
VDD
WDO
GND
tMD
tRS
VDD
RESET
GND
Figure 3. WDI and WDO timing waveforms. Reset externally triggered by MR.
VDD
VDD
4.65V
4.65V
GND
tRST_ASSRT
tRS
tWD
tRS
tWD
VDD
RESET
GND
tMD
VDD
MR
GND
tMR
WDI
VDD
GND
VDD
WDO
GND
Figure 4. RESET and WDO are driven low for VDD <4.65 volts. WDO is driven high when MR is low.
7
VDD 5V
VDD
VIN_ANALOG
R1
R2
uP
1 MR
WDO 8
2 VDD
RESET 7
RESET
3 GND
WDI 6
I/O
4 PFI
PFO 5
VTH= (R1+R2)/R2 ) * VPFI
VPFI=1.25V +/- 50mV
Figure 5. UT01VS50L Under Voltage Monitor and Detection
Shown in Figure 5 is an application for monitoring the under voltage of a power supply connected to a microprocessor or ASIC. If
the analog voltage monitored falls below the desired threshold value, the PFO output connected to the MR input will transition low
causing the RESET output to be asserted low indicating an under voltage condition.
3.3V_REG
VDD_IO
VREG 3.3V
VDD 5V
VIN
EN
UT01VS50L
R1
VTH= (R1+R2)/R2 ) * VPFI
VPFI=1.25V +/- 50mV
R2
1 MR
WDO 8
2 VDD
RESET 7
3 GND
WDI 6
4 PFI
PFO 5
VOUT
RESET
VREG 2.5V
WDI OPEN
VIN
VOUT
2.5V_REG
VDD
5V
Tolerant
CMOS
AND GATE
EN
1 MR
WDO 8
2 VDD
RESET 7
3 GND
WDI 6
4 PFI
PFO 5
R6
VTH= (R3+R4)/R4 ) * VPFIR3
VPFI=1.25V +/- 50mV
R4
R7
3.3V REG
LED
2.5V REG
LED
UT01VS50L
Figure 6. Under Voltage Monitoring and sequencing of 3.3V and 2.5V Power Supplies
Shown in Figure 6 are two Voltage Supervisors configured to monitor both the 3.3V and 2.5V power supplies of a system. The 3.3V
regulated supply is monitored by the PFI pin of the top Voltage Supervisor, while the 2.5 V regulated supply is monitored by the
PFI pin of the bottom Voltage Supervisor. The cross coupled connection of PFO to MR assures that RESET will be asserted when a
brown out occurs on either the 3.3V or 2.5V regulated supplies.
8
VDD 5V
R1
R2
VDD
1 MR
WDO
2 VDD
RESET 7
3 GND
WDI 6
4 PFI
PFO 5
uP
8
RESET
I/O
VTH= (R1+R2)/R2 ) * VPFI
VPFI=1.25V +/- 50mV
Figure 7. UT01VS50L Over Voltage Power Supply Monitoring and Reset
Shown in Figure 7 is an application to monitor and detect power supply over voltage through the use of the PFI pin. When the
voltage at the PFI input, (VTH) exceeds VREF, (1.2 to 1.3V) the PFO output transitions from low to high causing the MR output to
transition from high to low. This asserts a RESET indicating the voltage being monitored has exceeded the over voltage monitor
limit.
9
VDD 5V
VDD
R1
R2
1 MR
WDO 8
2 VDD
RESET 7
3 GND
WDI 6
4 PFI
PFO
uP
RESET
I/O
5
UT01VS50L
UNDER VOLTAGE
MONITOR
5V AND
GATE
VTH_UND= (R1+R2)/R2 ) * VPFI
VPFI=1.25V +/- 50mV
1 MR
WDO 8
2 VDD
RESET 7
3 GND
WDI 6
4 PFI
PFO 5
R3
R4
RESET
I/O
VTH_OV= (R3+R4)/R4 ) * VPFI
VPFI=1.25V +/- 50mV
UT01VS50L
OVER VOLTAGE
MONITOR
Figure 8. UT01VS50L Over Voltage Power Supply Monitoring and Reset
Shown in Figure 8 is an application using two UT01VS50L Voltage Supervisors to monitor both under voltage and over voltage of
a power supply. In this application the top Voltage Supervisor monitors the under-voltage of a 5V power supply while the bottom
Voltage Supervisor monitors the over voltage of the same 5V power supply.
The 5V supply is monitored through the PFI input of both Voltage Supervisors. Resistor values for both under voltage and over
voltage monitoring can be set to accommodate a range of power supply voltages.
During normal operation where VDD is within the allowed range (VDD_UND < VDD < VDD_OV), RESET of both Voltage
Supervisors will be at logic high level. The Table 1 below shows the truth table for functional, under voltage detection and over
voltage detection.
10
Table 1. Under Voltage Over Voltage Truth Table
VDD
PFO_UND
PFO_OV
RESET_UND
RESET_OV
RESET
uP or ASIC Mode
Normal Operation
VDD < VDD_UND
VDD > VDD_OV
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
Normal
Reset Asserted
Reset Asserted
11
Figure 5. 8-pin Dual-In-Line Flatpack
12
ORDERING INFORMATION
UT01VS50L VOLTAGE SUPERVISOR
UT******
*
*
*
*
*
Lead Finish: (Notes: 1)
(C) = Gold
Screening Level: (Notes: 2 and 3)
(P) = Prototype Flow
(C) = HiRel Flow (Temperature range -55oC to +125oC)
Case Outline:
(X) = 8-lead Ceramic Flat Package
TID Tolerance:
(-) = None
Device Type
(L) = Active low push-pull RESET
Generic UT01VS50 part number:
(01VS50)
Notes:
1. Lead finish is "C" (Gold) only.
2. Prototype flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25°C only. Lead finish is Gold "C" only. Radiation neither tested nor
guaranteed.
3. HiRel Flow per Aeroflex Manufacturing Flows Document. Radiation neither tested nor guaranteed.
13
UT01VS50L VOLTAGE SUPERVISOR
5962
*
*****
**
*
*
*
Lead Finish: (NOTE: 1)
(C) = Gold
Case Outline:
(X) = 8-Lead Ceramic Flatpack
Screening Level:
(Q) = QML Class Q
(V) = QML Class V
Device Type:
(13) = UT01VS50L (Temperature Range: -55oC to +125oC)
Drawing Number:
11213 = 5.0V Single Channel Voltage Supervisor
Total Dose:
(R) = 100 krad(Si)
(F) = 300 krad(Si)
Federal Stock Class Number: No Options
Notes:
1. Lead finish is “C” (gold) only.
14
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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[email protected]
Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
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