L4947PD 5V-0.5A VERY LOW DROP REGULATOR WITH RESET PRECISE OUTPUT VOLTAGE (5V ± 4%) OVER FULL TEMPERATURE RANGE (– 40 / 125 °C) VERY LOW VOLTAGE DROP (0.75Vmax) OVER FULL T RANGE OUTPUT CURRENT UP TO 500mA RESET FUNCTION POWER-ON RESET DELAY PULSE DEFINED BY THE EXTERNAL CAPACITOR + 80V LOAD DUMP PROTECTION – 80V LOAD DUMP PROTECTION REVERSE VOLTAGE PROTECTION SHORT CIRCUIT PROTECTION AND THERMAL SHUT-DOWN (with hysteresis) LOW START UP CURRENT DESCRIPTION The L4947PD is a monolithic integrated circuit in HiPSO package specially designed to provide a stabilized supply voltage for automotive and industrial electronic systems. Thanks to its very low voltage drop, in automotive applications the L4947PD can work correctly even during the cranking phase, when the battery voltage could PowerSO20 ORDERING NUMBER: L4947PD fall as low as 6V. Furthermore, it incorporates a complete range of protection circuits against the dangerous overvoltages always present on the battery rail of the car. The reset function makes the device particularly suited to supply microprocessor based systems : a signal is available (after an externally programmable delay) to reset the microprocessor at power-on phase ; at power-off, this signal becomes low inhibiting the microprocessor. BLOCK DIAGRAM PNP OUTPUT TRANSISTOR INPUT 17 OUTPUT 3 ANTI SAT. DUMP PROTECT. START REF. ERROR AMP. THERMAL PROTECTION OUTPUT CURRENT LIMITER RESET OUTPUT 19 RESET CIRCUIT GROUND This 1-20 is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without 1-20 notice. 2 June 2000 DELAY CAPACITOR D94AT106 1/6 L4947PD ABSOLUTE MAXIMUM RATINGS Symbol Vi VR TJ, Tstg Parameter DC Input Voltage DC Reverse Input Voltage Transient Input Overvoltages : Load Dump : 5ms ≤ trise ≤ 10ms τf Fall Time Constant = 100ms RSOURCE ≥ 0.5Ω Field Decay : 5ms ≤ tfall ≤ 10ms, RSOURCE ≥ 10Ω τr Rise Time Constant = 33ms Low Energy Spike : trise = 1µs, tfall = 500µs, RSOURCE ≥ 10Ω fr Repetition Frequency = 5Hz Value Unit 35 – 18 80 V V V – 80 V ± 100 V 35 V – 55 to 150 °C Value Unit 3 °C/W Reset Output Voltage Junction and Storage Temperature Range Note: The circuit is ESD protected according to MIL-STD-883C. PIN CONNECTION (Top view) GND 1 20 GND DELAY CAP. 2 19 RESET +VOUT 3 18 N.C. N.C. 4 17 +VIN N.C. 5 16 N.C. N.C. 6 15 N.C. N.C. 7 14 N.C. N.C. 8 13 N.C. N.C. 9 12 N.C. GND 10 11 GND D94AT107A THERMAL DATA Symbol R th j-case Parameter Thermal Resistance Junction-case Max TEST CIRCUIT IN 17 Ci 100nF 100nF OUT Co 47µF(*) RESET OUTPUT RP L4947PD 2 Cd 3 19 1-20 D94AT108 (*) Min 20µF, ESR <10Ω over full temperature range RP (pull up resistor) and RL (load) are both equal to 1kΩ. 2/6 L4947PD ELECTRICAL CHARACTERISTICS (refer to the test circuit, Vi = 14. 4V, Co = 47µF, ESR < 10Ω, Rp = 1KΩ, RL = 1KΩ, –40°C ≤ TJ ≤ 125°C, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit 4.80 5.00 5.20 V 4.90 5.00 5.10 V 26 V 50 mV 15 60 mV 0.40 0.55 0.75 V V 10 13 180 mA mA mA Vo Output Voltage Io = 0mA to 500mA Over Full T Range TJ = 25°C Vi Operating Input Voltage Io = 0mA to (*) 500mA ∆V o Line Regulation Vi = 6V to 26V ; Io = 5mA ∆V o Vi –Vo Load Regulation Io = 5mA to 500mA Dropout Voltage Io = 500mA, TJ = 25°C Over Full T Range Quiescent Current Io = 0mA, TJ = 25°C Io = 0mA Over Full T Io = 500mA Over Full T 5 6.5 110 Iq ∆Vo T Temperature Output Voltage Drift SVR Supply Volt. Rej. Isc Output Short Circuit Current VR Reset Output Saturation Voltage Io = 350mA ; f = 120Hz Co = 100µF ; Vi = 12V ± 5Vpp 6 5 – 0.5 mV/°C 50 60 dB 0.50 0.80 1.5V < Vo < VRT (off), IR = 1.6mA 3.0V < Vo < VRT (off), IR = 8mA 1.50 A 0.40 V 0.40 V 50 µA V IR Reset Output Leakage Current VO in Regulation, VR = 5V VRT peak Power On-Off Reset out Peak Voltage 1KΩ Reset Pull-up to Vo VRT (off) Power OFF Vo Threshold Vo @ Reset Out H to L Transition VRT (on) Power ON Vo Threshold Vo @ Reset Out L to H Transition VHyst Power ON-Off Hysteresis VRT (on) –VRT (off) Delay Comparator Threshold Vd @ Reset Out L to H Transition 3.65 4.00 4.35 V Vd @ Reset Out H to L Transition 3.20 3.55 3.90 V Vd V dH 0.65 4.75 Delay Capacitor Charging Current Vd = 3V, TJ = 25°C Vdisch Delay Capacitor Discharge Voltage Vo < VRT (off) Td Power on Reset Delay Time Cd = 100nF, TJ = 25°C Vo – 0.15 VRT (off) + 0.05 V Vo – 0.04 0.05 Delay Comparator Hysteresis Id 1.0 10 V V 0.45 V 20 /µA 0.55 1.20 V 20 30 ms (*) For a DC voltage 26 < Vi < 37V the device is not operating FUNCTIONAL DESCRIPTION The L4947PD is a very low drop 5V/0.5A voltage regulator provided with a reset function and therefore particularly suited to meet the requirements of supplying the microprocessor systems used in automotive and industrial applications. The block diagram shows the basic structure of the device : the reference, the error amplifier, the driver, the power PNP, the protection and reset functions. The power stage is a Lateral PNP transistor which allows a very low dropout voltage (typ. 400mV at TJ = 25°C, max. 750mV over the full temperature range @ IO = 500mA). The typical curve of the dropout voltage as a function of the junction temperature is shown in Fig. 1 : that is the worst case, where IO = 500mA. The current consumption of the device (quiescent 3/6 L4947PD current) is maximum 13mA - over full T - when no load current is required. The internal antisaturation circuit allows a drastic reduction in the current peak which takes place during the start up. The reset function supervises the regulator output voltage inhibiting the microprocessor when the device is out of regulation and resetting it at the power-on after a settable delay. The reset is LOW when the output voltage value is lower than the reset threshold voltage. At the power-on phase the output voltage increases (see Fig. 2) and when it reaches the power-on VO threshold VRT (On) - the reset output becomes HIGH after a delay time set by the external capacitor C d. At the power-off the output voltage decreases : at the VRT(Off) threshold value (VO-0.15V typ. value) the reset output instantaneously goes down (LOW status) inhibiting the microprocessor. The typical Figure 1: Typical Dropout Voltage vs. Tj (Io = 500mA). power on-off hysteresis is 50mV. The three gain stages (operational amplifier, driver and power PNP) require the external capacitor (Comin = 20µF) to guarantee the global stability of the system. Load dump and field decay protections (± 80V), reverse voltage (– 18V) and short circuit protection, thermal shutdown are the main features that make the L4947PD specially suitable for applications in the automotive enviroment. EXTERNAL COMPENSATION Since the purpose of a voltage regulator is to supply and load variations, the open loop gain of the regulator must be very high at low frequencies. This may cause instability as a result of the various poles present in the loop. To avoid this instability dominant pole compensation is used to reduce phase shift due to other poles at the unity gain frequency. The lower the frequency of these others poles at the unity gain frequency. The lower the frequency of these other poles, the greater must be capacitor esed to create the dominant pole for the same DC gain. Where the output transistor is a lateral PNP type there is a pole in the regulation loop at a frequencybtoo low to be compensated by a capacitor which can be integrated. An external compensation is therefore necessary so a very high value capacitor must be connected from the output to ground. The paeassitic equivalent series resistance of the capacitor used adds a zero to the regulation loop. This zero may compromise the stability of the system since its effect tends to cancel the effect of the pole added. In regulators this ESR must be less than 3Ω and the minimum capacitor value is 47µF. Figure 2: Reset Waveforms: (1) Without External Capacitor Cd. (2) With External Capacitor Cd. VO VRT(on) VRT(off ) Vrthys Vrpeak VR (1) (2) Vrsat Td Vdthh Vdthl Vdisch (2) VD 4/6 D94AT109 L4947PD DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T MIN. mm TYP. 0.1 0 0.4 0.23 15.8 9.4 13.9 MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547 1.27 11.43 10.9 inch TYP. 0.050 0.450 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10° (max.) 8° (max.) 5.8 0 15.5 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 10 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.394 PowerSO20 (1) ”D and F” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006”). - Critical dimensions: ”E”, ”G” and ”a3” N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G C E2 E1 BOTTOM VIEW (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 5/6 L4947PD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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