FAIRCHILD TMB2193MS100

www.fairchildsemi.com
TMB2193MS100
Demonstration Board for the TMC2193
Description
•
•
•
•
•
•
The TMB2193MS100 demonstration board provides a flexible base for evaluating the performance of the TMC2193
Digital Video Encoder (DENC). The demonstration board
can be driven by either a D1 or Genlock signal, or it can supply the synchronization signals needed to drive a framestore
or any MPEG Decoder. Both YCbCr, in either 4:2:2, D1, or
4:4:4 formats, and RGB inputs are supported. The board
provides high quality analog composite video, analog
S-video, analog component video and digital composite
video outputs.
10-bit or 20-bit Parallel YCbCr input
24-bit RGB input
D1, Genlock and Master mode operation
Composite, S-video and component analog outputs
Digital Composite output
Fairchild demo board compatibility
Applications
•
•
•
•
Evaluation of TMC2193 DENC
Evaluation of TMC2072 Genlock interface
Output for TMC2068P7C Decoder demo board
System Breadboarding
Block Diagram
RBUS
Connector
+5V 0V -5V
96 Way
Edge
Connector
(female)
Analog Outputs:
Composite
S-Video
RGB
YPbPr
Sync
1
FPGA
MCU
TMC2072
Digital Inputs:
10 bit D1
24 bit RGB
20 bit YCbCr
PXCK
TMC2193
Digital Outputs:
32
HSYNC
VSYNC
MPXCK
Digital Outputs (Optional):
10 bit DCVBS
HSYNC
VSYNC
PXCK
Analog
LPF
65-B2193-01
Rev. 0.9.0
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
Preliminary Information
Features
TMB2193MS100
PRODUCT SPECIFICATION
Functional Description
Preliminary Information
The TMB2193MS100 is designed to demonstrate the performance of the TMC2193 Digital Video Encoder (DENC). For
a complete description of the TMC2193, please refer to the
TMC2193 data sheet. The TMB2193MS100 is compatible
with other Fairchild Demo boards. Typical configurations
are the TMC2067P7C, the TMC2068P7C, and the
TMB2193MS100 or the TMB0001MS100 and the
TMB2193MS100. The first configuration requires an analog
composite or S-video input and supplies a re-encoded analog
composite or S-video output. The later requires a parallel
D1 input and supplies an encoded analog composite or
S-video output.
The TMC2193 can be operated in D1, Genlock or Master
mode. In the D1 mode the synchronization is derived from
the TRS codes embedded in the D1 data stream. The
TMB2193MS100 has the TMC2072 Genlock front end,
which supplies the HSYNC, VSYNC and subcarrier information to the TMC2193 for the Genlock operation of the
encoder. In Master mode the synchronization is driven by
the TMC2193, supplying the line (HSYNC) and field
(VSYNC or BnT) synchronization signals. With the
TMC2193 running in Master mode the TMB2193MS100
demo board interfaces directly to either a MPEG decoder or
a video framestore with no additional glue logic.
The TMB2193MS100 has an onboard microcontroller
(MCU) to program the TMC2193, the TMC2072, and to
configure the FPGA. All the default register maps are held
within the MCU. Table 1 provides a description of each of
the default register maps. A control register map is written to
the TMC2193, the TMC2072, and to Port 2 of the MCU each
time the MRST\ button is pressed. The MCU determines
which map to load from the PROG[3-0] (Px) dip switches.
The TMC2193, 2072 and the MCU can also be driven by the
Raydemo software. The interface is provided by the RBUS
connector on the TMB2193MS100 and the TMC2070P7C
R-Bus interface board. With this setup the user can configure the TMC2193, the TMC2072 and the MCU with any
IBM compatible PC.
Table 1. Default Control Register Maps
2
P3
P2
P1
P0
Format
Mode
Source
Output Mode
0
0
0
0
NTSC
MASTER
Mod. Ramp
Composite, S-Video
0
0
0
0
0
1
NTSC
MASTER
75% CB
Composite, YPBPR
1
0
NTSC
MASTER
100% CB
Composite, RGB
0
0
1
1
NTSC
D1
D1
Composite, YPBPR
0
1
0
0
NTSC
D1
D1
Composite, RGB
0
1
0
1
NTSC
D1
D1
DCVBS
0
1
1
0
NTSC
Genlock
601
Composite, YPBPR
0
1
1
1
NTSC
Genlock
601
Composite, RGB
1
0
0
0
PAL
MASTER
Mod. Ramp
Composite, S-Video
1
0
0
1
PAL
MASTER
75% CB
Composite, YPBPR
1
0
1
0
PAL
MASTER
100% CB
Composite, RGB
1
0
1
1
PAL
D1
D1
Composite, YPBPR
1
1
0
0
PAL
D1
D1
Composite, RGB
1
1
0
1
PAL
D1
D1
DCVBS
1
1
1
0
PAL
Genlock
601
Composite, YPBPR
1
1
1
1
PAL
Genlock
601
Composite, RGB
PRODUCT SPECIFICATION
TMB2193MS100
CPLD Description
The Altera 10K20 CLPD functions as the central matrix for
routing the buses to the TMC2193. Eight (8) control pins are
connected from port 2 of the MCU to the CLPD. These pins
are used to configure the CPLD and are broken up into 2
buses: FPGA control1 is on pins P2[7:4] and FPGA control2
is on pins P2[3:0]. The 10K20 default configuration routes
the 3 buses from the input edge connector and the bus from
the framestore header to the pixel data (PD[23:0]) port of the
TMC2193. This enables the various input formats of the
TMC2193 to be supported. In addition, the PD input can be
delayed in respect to the HSIN and VSIN for proper data
alignment. Table 2 describes the function of the pixel data
formatting.
The FPGA Control 2 bus selects which subcarrier reference
signal to be used; either the GRS from the TMC2072 or the
xRS signal from bus B of the input edge connector. FGPA
Control 2 also selects which set of synchronization signals
are to used; either the IXHSYNC and IXVSYNC from the
input edge connector or the TMC2072 GHSYNC and
GVSYNC.
Table 3. FPGA Control 2
FGPA
Control2 bit#
Function
Description
REFSEL
CVBS Input
0
B[5:2] bus
1
GENLOCK
3-2
1
FGPA
Control1 bit#
SYNCSEL
HSIN, VSIN Input
Function
Description
0
IXH and IXV
3-2
PDMODE
PD Input
1
GH and GV
00
10-bit format, A bus
01
20-bit format, C and
B buses
10
24-bit format, C, A,
and B buses
11
10-bit format, A bus
delayed
PDDEL
PD delay
00
0 pxck’s of delay
01
1 pxck’s of delay
10
2 pxck’s of delay
11
3 pxck’s of delay
1-0
0
FPGA Controls 1 and 2 can be accessed by the Raydemo
software. The dialog box exists in the MCU icon of the
TMB2193MS100 window. The functions of these controls
are purposely left generic to allow for the reconfiguration of
the CPLD.
The 10K20 utilization is approximately 20% of the available
logic cells. This allows for additional functions to be
implemented in the 10K20 such as notch filters, interpolation
filters for 4:2:2 to 4:4:4 conversion, simple comb filtering
and ancillary data insertion. These are just some of the
possibilities.
Table 4. Switch, Button, and Jumper Description
Button
Description
MRST
Resets the AT89C55. When the GLOBAL RESET jumper is in place, the reset line on all
boards connected to the TMB2193MS100 are driven by MRST.
Jumpers
Description
GLOBAL RESET
When GLOBAL RESET is open, only the TMC2193, the TMC2072, the framestore header
and the AT89C55 receive the reset pulse from MRST. When GLOBAL RESET is closed,
the reset line on all boards connected to the TMB2193MS100 are driven by MRST.
CASC INT
Cascade Programming Enable.
When CASC INT is open, the AT89C55 automatically initializes the devices after reset.
When CASC INT is closed, the AT89C55 will wait for a LOW pulse on the PGM_IN pin
before initializing the devices on the TMB2193MS100.
RBUSEN
When RBUSEN is open, the RBUS port is disabled.
When RBUSEN is closed, the RBUS port is enabled.
3
Preliminary Information
Table 2. FPGA Control 1
No Modes
TMB2193MS100
PRODUCT SPECIFICATION
Table 4. Switch, Button, and Jumper Description (continued)
Button
Description
JP20, JP21, JP22,
JP23
When JPx is open, the output video is a single 75Ohm termination.
Switches
Description
E1
Onboard Clock Selection.
When JPx is closed, the output video is a double 75Ohm termination.
Selects either the PXCK from the TMC2072 or the onboard TTL clock oscillator.
Preliminary Information
E2
Master Clock Selection.
When Pass is selected the clock source for the entire board is either the TMC2072 PXCK
or the TTL clock oscillator. When IXPCK is selected the clock source for the entire board
is the PXCK from the input header.
E3
Output Header Clock Selection.
Selects either PXCK or PXCK for the output header.
Dip Switches
Description
SA1-0
Configures the bits 2 and 1 of the TMC2193 RBUS chip address. When SAx is ON
(down), ESAx is in a LOW state. When SAx is OFF (up), ESAx is in a HIGH state.
CAS
Configures the bit 2 of the TMC2072 RBUS chip address. When CAS is ON (down),
GSA1 is in a LOW state. When CAS is OFF (up), GSA1 is in a HIGH state.
ERS
Configures the bit 1 of the TMC2072 RBUS chip address. When ERS is ON (down),
GSA0 is in a LOW state. When ERS is OFF (up), GSA0 is in a HIGH state.
P3-0
Control Register Programming.
P3-0 selects which control register map to configure the devices with. Refer to Table 1
Default Control Register Maps for a description.
Setup Procedure
Power Supply Requirements
Set E1 to MPXCK and E2 to PASS, enable the onboard TTL
clock oscillator as the clock source.
The TMB2193MS100 board requires 1.5 Amps from the +5
Volt power supply and 0.5 Amps from the -5 Volt power supply. Both the +5 Volt and -5 Volt supplies are connected to
the input connector to supply the power requirements of any
upstream board. The +5 Volt power supply not only drives
TTL logic devices but it also provides the power and voltage
references to the D/A’s in the TMC2193. Therefore, it is recommended that a bench power supply be used with the cable
lengths kept to a minimum.
1.
Set ESA1-0 to ON (down).
2.
Set P3-0 to 0h, P3 is ON (down), P2 is ON (down), P1 is
ON (down), and P0 is ON (down).
3.
Plug in power supply connector and apply power. The
LED’s corresponding to +5 Volts and -5 Volts should be
illuminated.
4.
Reset board by pressing the MRST button.
5.
Connect a scope probe to TP25 and adjust R39 until the
sync to blank amplitude is 286 mV.
6.
Connect a scope probe to TP19 and adjust R36 until the
sync to blank amplitude is 286 mV.
7.
Connect a scope probe to TP21 and adjust R37 until the
sync to blank amplitude is 286 mV.
8.
Connect a scope probe to TP23 and adjust R38 until the
burst amplitude is 286 mV.
4
IXPXCK
IXHSYNC
IXVSYNC
PGM_IN
A[0..9]
B[0..9]
C[0..9]
A_DEL[0..9]
GPXCK
GHSYNC
GVSYNC
CVBS[0..7]
GMCU[0..6]
HEADERIN
RESET
FRESET
MPXCK
HSOUT
VSOUT
SCL
SDA
HEADERIN
GENLOCK
SCL
SDA
GMCU[0..6]
PGM_IN
SCL
SDA
FRESET\
RESET\
GPXCK
IXPXCK
FPGA
FPXCK
IXPXCK
FMCU[0..7]
A[0..9]
B[0..9]
C[0..9]
A_DEL[0..9]
CVBS[0..7]
675MCLK
GHSYNC
GVSYNC
IXHSYNC
IXVSYNC
FPGA
CKDRIVE
MCU
VSOUT
PGM_IN
135MCLK
SCL
SDA
GMCU[0..6]
MCU
135MCLK
FMCU[0..7]
FPXCK
IXPXCK
A[0..9]
B[0..9]
C[0..9]
A_DEL[0..9]
CVBS[0..7]
675MCLK
GHSYNC
GVSYNC
IXHSYNC\
IXVSYNC\
MPXCK
GPXCK
IXPXCK
CKDRIVE
PGM_OUT
RESET
FRESET
FMCU[0..7]
EMCU[0..3]
VSIN
HSIN
OLENG[0..5]
PD[0..23]
ECVBS[0..9]
675MCLK
135MCLK
MPXCK
EPXCK
FPXCK
OPXCK
EMCU[0..3]
EPXCK
VSIN
HSIN
OLENG[0..5]
PD[0..23]
ECVBS[0..9]
TMC2193
HSOUT
VSOUT
DCVBS[0..9]
Document Number
TMB2193
Thursday, September 04, 1997
Date:
TOP
Size
B
Title
5580 Morehouse Dr.
San Diego, CA 92121
Sheet
PGM_OUT
OPXCK
HSOUT
VSOUT
DCVBS[0..9]
Raytheon Electronics - Semiconductor Division
EMCU[0..3]
SCL
SDA
EPXCK
VSIN
HSIN
OLENGI[0..5]
PD[0..23]
ECVBS[0..9]
TMC2193
Preliminary Information
GENLOCK
1
of
{Schematic}
POWER
HEADEROUT
RESET
PGM_OUT
SCL
SDA
OPXCK
HSOUT
VSOUT
DCVBS[0..9]
HEADEROUT
65-B2193-02
12
Rev
0.9.0
PRODUCT SPECIFICATION
TMB2193MS100
Figure 1.
5
TMB2193MS100
PRODUCT SPECIFICATION
VCC
Q
10
12
11
CLK
Y1
Preliminary Information
675MCLK
Q
8
C3
0.1µF
PLACE COMPONENTS ON THIS
PAGE CLOSE TO THE
GENLOCK.
MPXCK
OUT
Q
CLK
CL
6
1
Q
D
PR
D
CL
3
U10B
74F74
9
13
2
PR
4
135MCLK
U10A
74F74
5
5
E1
SELECT
27MHz
GPXCK
GPXCK
VCC
VCC
C2
0.1µF
VCC
C1
0.1µF
E2
SELECT
U1A
IXPXCK
PASS
2
4
6
8
A1
A2
A3
A4
1
Y1
Y2
Y3
Y4
18
16
14
12
MPXCK
EPXCK
FPCXK
OPXCK
MPXCK
EPXCK
FPXCK
OPXCK
G
74F240
U1B
11
13
15
17
IXPXCK
U2A
1
2
A1
A2
A3
A4
19
Y1
Y2
Y3
Y4
9
7
5
3
G
74F240
74F14
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA 92121
(619) 457-1000
Title
CKDRIVE.SCH
Size
B
Date:
Document Number
TMB2193
Friday, February 07, 1997
Rev
0.9.0
Sheet
9
of
12
65-B2193-03
Figure 2.
6
FMCU[0..7]
CVBS[0..7]
C[0..9]
B[0..9]
675MCLK
9
7
5
3
1
FMCU0
FMCU1
FMCU2
FMCU3
FMCU4
FMCU5
FMCU6
FMCU7
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
HEADER 5X2
10
8
6
4
2
JP1
BYTE
BLASTER
EPC1PC8
IXPXCK
FPXCK
IXHSYNC\
IXVSYNC\
GHSYNC
GVSYNC
A[0..9]
DATA
nCASC
R3
1K
DCLK
OE
nCS
U4
C19
0.1µF
2
3
4
R2
1K
A_DEL[0..9]
VCC
R1
1K
6
1
R4
1K
IXPXCK
FPXCK
IXHSYNC\
IXVSYNC\
GHSYNC
GVSYNC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A_DEL0
A_DEL1
A_DEL2
A_DEL3
A_DEL4
A_DEL5
A_DEL6
A_DEL7
A_DEL8
A_DEL9
R5
1K
A_DEL8
A_DEL7
A_DEL6
A_DEL4
A_DEL3
A_DEL1
A_DEL0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
FPXCK
C7
PD10
PD11
C6
C8
IXHSYNC\
IXVSYNC\
PD4
PD3
PD2
PD1
PD0
OLENG5
OLENG4
FMCU0
A_DEL5
A_DEL9
FMCU1
FMCU2
A_DEL2
8
9
10
12
13
17
18
19
20
21
22
23
26
27
28
29
30
31
32
125
55
122
128
54
56
124
126
105
4
1
34
116
114
113
112
111
110
109
108
106
3
142
141
144
143
11
7
107
2
14
77
76
35
74
EPF10K10TC144
8
9
10
12
13
17
18
19
20
21
22
23
26
27
28
29
30
31
32
GCLK0
GCLK1
DEV_CLRn
DEV_OE
DEDIN
DEDIN
DEDIN
DEDIN
TDI
TDO
TCLK
TMS
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
nCE
nCEO
nWS
nRS
nCS
CS
RDYnBSY
CLKUSR
DCLK
CONF_DONE
INIT_DONE
MSEL0
MSEL1
nSTATUS
nCONFIG
U11
140
138
137
136
135
133
132
131
130
121
120
119
118
117
102
101
100
99
98
97
96
95
92
91
90
89
88
87
86
83
82
81
80
79
78
73
72
70
69
68
67
65
64
63
62
60
59
51
49
48
47
46
44
43
42
41
39
38
37
36
33
140
138
137
136
135
133
132
131
130
121
120
119
118
117
102
101
100
99
98
97
96
95
92
91
90
89
88
87
86
83
82
81
80
79
78
73
72
70
69
68
67
65
64
63
62
60
59
51
49
48
47
46
44
43
42
41
39
38
37
36
33
FMCU3
FMCU4
FMCU5
FMCU6
FMCU7
CVBS7
CVBS6
CVBS5
CVBS4
CVBS3
CVBS2
CVBS1
CVBS0
GVSYNC
GHSYNC
OLENG3
OLENG2
OLENG1
OLENG0
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
PD9
PD8
PD7
PD6
PD5
VSIN
HSIN
ECVBS9
ECVBS8
ECVBS7
ECVBS6
ECVBS5
ECVBS4
ECVBS3
ECVBS2
C9
C5
C4
C3
C2
C1
C0
B9
B8
B7
B6
B5
B4
B3
B2
OLENG0
OLENG1
OLENG2
OLENG3
OLENG4
OLENG5
VSIN
HSIN
C10
0.1µF
C4
0.1µF
C13
0.1µF
C7
0.1µF
OLENG[0..5]
VSIN
HSIN
C12
0.1µF
C6
0.1µF
Document Number
TMB2193
Thursday, September 04, 1997
Date:
FPGA.SCH
Size
B
Title
5580 Morehouse Dr.
San Diego, CA 92121
C9
0.1µF
Sheet
ECVBS0
ECVBS1
ECVBS2
ECVBS3
ECVBS4
ECVBS5
ECVBS6
ECVBS7
ECVBS8
ECVBS9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
C14
0.1µF
C8
0.1µF
Raytheon Electronics - Semiconductor Division
C11
0.1µF
C5
0.1µF
Preliminary Information
VCC
VCC
3
of
Rev
0.9.0
65-B2193-04
12
ECVBS[0..9]
PD[0..23]
PRODUCT SPECIFICATION
TMB2193MS100
Figure 3.
7
SCL
SDA
C32
0.1µF
VCC
GMCU[0..6]
OUT
GCS
GRW\
GA0
SDA
GSA0
20MHz
Y2
5
33
R16
33
R15
1
GMCU0
GMCU1
GMCU2
GMCU3
GMCU4
GMCU5
GMCU6
J1
BNC
2
C30
TP1
VID_IN
A
A
A
JP8
JP7
JP6
B
B
B
1
33
R10
220
R8
0.1µF
C22
GSA1
GRESET\
R6
75
0.1µF
0.1µF
STUFF: A for TMC2072
B for TMC22071A
JP5
JP4
JP3
H3
R12
4.75K
VCC
GD0
22µF/6.3V
R14
4.75K
VCC
R13
4.75K
VCC
22µF/6.3V
20MCLK
R9
75
C29
GRESET\
GCS
GA0
GRW\
GD0
GSA1
GSA0
C21
C20
VCC
R7
75
0.1µF
C23
76
71
66
43
53
54
19
20
86
94
91
93
4
5
1
2
3
7
9
65
61
58
10
11
12
13
14
15
0.1µF
C26
0.1µF
C27
AGND
H5
PTH
NC
NC
NC
NC
NC
NC
NC
21
22
23
24
25
28
29
30
99
85
84
83
80
79
78
17
34
40
H6
PTH
H7
PTH
H8
PTH
82
DDS OUT 75
CBYP 77
PFD IN 45
PXCK
31
(BURL) 35
(FID0) 36
(FID1) 37
(FID2) 62
NC 59
NC 56
NC
88
COMP 70
VREF 68
RT 57
RB
INT
VALID
LDV
32
GHSYNC 33
GVSYNC
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
0.1µF
C28
GND
TMC22071AKHC(2072KHC)_2
NC
NC
NC
NC
NC
NC
NC
NC
PXCK SEL
EXT PXCK
CLK IN
CLK OUT
R/W (SDA)
CS (SCL)
A0 (SA0)
(SA1)
(SA2)
RESET
D0
VIN1
VIN2
VIN3
NC
NC
NC
NC
NC
NC
U5
0.1µF
C25
DGND
0.1µF
C24
1
+
1
1
GPXCK
H1
H2
GHSYNC
GVSYNC
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
C37
0.1µF
TP2
GH
TP4
GPXCK
C38
0.1µF
TP3
GV
CVBS[0..7]
6.8pF
C33
C40
390pF
C34
0.1uF
VCC
GHSYNC
GVSYNC
GPXCK
Date:
Size
B
Title
Monday, January 20, 1997
Document Number
TMB2193
GENLOCK.SCH
5580 Morehouse Drive
San Diego, CA 92121
(619) 457-1000
Sheet
C35
0.1uF
C31
0.1uF
Raytheon Electronics - Semiconductor Division
C39
150pF
10µH
L1
Preliminary Information
1
Figure 4.
1
2
of
12
65-B2193-05
Rev
0.9.0
CR1
1.235V
GVSYNC
GPXCK
GHSYNC
CVBS[0..7]
STUFF EITHER
C36 OR CR1
C36
0.1uF
R11
3.3K
1
2
8
+
1
TMB2193MS100
PRODUCT SPECIFICATION
Size
B
Date:
72
39
19
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
10
11
12
13
14
15
16
17
18
SCL
IXVSYNC\
IXHSYNC\
IXPXCK
Thursday, September 04, 1997
Sheet
P1
SIMM72
Title
Document Number
TMB2193
Rev
0.9.0
4
of
65-B2193-06
12
Figure 5.
Preliminary Information
2
3
4
5
6
7
8
9
A_DEL9
A_DEL8
A_DEL7
A_DEL6
A_DEL5
A_DEL4
A_DEL3
A_DEL2
A_DEL1
A_DEL0
GND
2
3
4
5
6
7
8
9
VDD
11
12
13
14
15
16
17
18
GND
20
21
22
23
24
25
26
27
28
29
VDD
31
32
33
34
35
36
37
38
GND
40
41
42
43
44
45
46
47
VDD
49
50
51
52
53
54
55
56
57
58
VDD
60
61
62
63
64
65
66
67
68
69
70
71
GND
A[0..9]
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
PRODUCT SPECIFICATION
TMB2193MS100
10 BIT FRAMESTORE
MPXCK
HSOUT
VSOUT
FRESET\
SDA
A_DEL[0..9]
A_DEL[0..9]
A[0..9]
VCC
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 6.
RESET\
SDA
SCL
FRESET\
MPXCK
HSOUT
VSOUT
EURO96F
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P2A
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
RESET\
SCL
SDA
MPXCK
VSOUT
HSOUT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EURO96F
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P2B
-5V
-12V
+12V
PGM_IN
HSOUT
VSOUT
MPXCK
IMASTER/SLAVE
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
EURO96F
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P2C
SDA
RESET\
SCL
IXVSYNC\
IXHSYNC\
IXPXCK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A[0..9]
IXHSYNC\
IXVSYNC\
IXPXCK
SCL
SDA
{Value}
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
A_DEL[0..9]
HSOUT
VSOUT
MPXCK
HSOUT
VSOUT
MPXCK
R17
10K
Thursday, September 04, 1997
Date:
HEADERIN.SCH
Document Number
TMB2193
Size
B
Title
5580 Morehouse Drive
San Diego, CA92121
(619) 457-1000
Raytheon Semiconductor - La Jolla
A[0..9]
IXHSYNC
IXVSYNC
IXPXCK
SCL
SDA
FRESET
FS_CONN
-5V
PGM_IN
Preliminary Information
Sheet
IXPXCK
IXVSYNC\
IXHSYNC\
10
of
C[0..9]
B[0..9]
A[0..9]
Rev
0.9.0
65-B2193-07
12
A_DEL[0..9]
PGM_IN
IXPXCK
IXVSYNC\
IXHSYNC\
TMB2193MS100
PRODUCT SPECIFICATION
PRODUCT SPECIFICATION
TMB2193MS100
96 WAY EDGE CONNECTIONS FROM THE TMC2193 BOARD
E3
SELECT
+12V
-12V
PXCK
PXCK4
U2B
OPXCK
3
4
P3A
DCVS[0..9]
DCVBS[0..9]
HSOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P3B
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PGM_OUT
EURO96M
VSOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P3C
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PXCK4
VSOUT
HSOUT
RESET\
SCL
SDA
EURO96M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EURO96M
Raytheon Electronics - Semiconductor Division
SDA
SCL
RESET\
SDA
5580 Morehouse Drive
San Diego, CA92121
(619) 457-1000
SCL
RESET\
Title
HEADEROUT.SCH
PGM_OUT
Size
B
PGM_OUT
Date:
Document Number
TMB2193
Wednesday, January 22, 1997
Rev
0.9.0
Sheet 6
of
12
65-B2193-08
Figure 7.
11
Preliminary Information
DCVBS0
DCVBS1
DCVBS2
DCVBS3
DCVBS4
DCVBS5
DCVBS6
DCVBS7
DCVBS8
DCVBS9
VSOUT
-5V
PXCK\
74F14
HSOUT
VCC
TMB2193MS100
PRODUCT SPECIFICATION
VDD
D1
DIODE SCHOTTKY
A_IN
A_OUT
D2
DIODE SCHOTTKY
R18
75 Ohm
Preliminary Information
Raytheon Electronics - Semiconductor Division
5580 Morehouse Dr.
San Diego, CA 92121
Title
LPF.SCH
Size
A
Document Number
TMB2193
Date:
Thursday, September 04, 1997
Rev
0.9.0
Sheet
11
of
12
65-B2193-09
Figure 8.
12
5
74F14
U2C
SA1
SA0
CAS
ERS
P0
P1
P2
P3
VSOUT
135MCLK
PGM_IN
SDA
SCL
GMCU[0..6]
EMCU[0..3]
1
2
3
4
5
6
7
8
6
SW DIP-8
S2
MRST
C41
S1
10.0µF/16V
R21
10K
16
15
14
13
12
11
10
9
VCC
9
R50
10K
GMCU0
GMCU1
GMCU2
GMCU3
GMCU4
GMCU5
GMCU6
EMCU0
EMCU1
EMCU2
EMCU3
R49
10K
MRESET\
8
R53
10K
VSOUT
135MCLK
PGM_IN
SDA
SCL
GRESET\
GCS
GA0
GRW\
GD0
GSA1
GSA0
ERESET\
EDCVBSEN\
ESA1
ESA0
R52
10K
C42
0.1µF
R51
10K
VCC
74F14
U2D
VCC
R54
10K
R55
10K
RESET\
R20
4K7
ESA1
ESA0
GSA1
GSA0
PROG0
PROG1
PROG2
PROG3
R56
10K
PLACE NEAR
STANDOFF
UART
UART
4
3
2
1
JP10
135MCLK
1
C43
0.1µF
H10
VCC
135MCLK
H4
RXD
TXD
VCC
1
H9
1
VCC
MRESET\
ERESET\
GRESET\
FRESET\
EDCVBSEN\
PROG0
PROG1
PROG2
PROG3
GCS
GAO
GRW\
GD0
SCL
SDA
10
20
21
2
3
4
5
6
7
8
9
43
42
41
40
39
38
37
36
CAS_PROGEN
JP11
CASCADE INIT
R22
4K7
1
12
23
34
EA/VPP
ALE/PROG
PSEN
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
35
33
32
11
13
14
15
16
17
18
19
24
25
26
27
28
29
30
31
4
3
2
1
10K
H11
1
H12
Date:
Size
B
Title
Friday, September 19, 1997
Document Number
TMB2193
MCU.SCH
5580 Morehouse Dr.
San Diego, CA 92121
8
PGM_OUT
RBUSEN
JP9
Sheet
FRESET\
RESET\
Raytheon Electronics - Semiconductor Division
VCC
1
10K
R24
1OHM, 1/4W C
FMCU[0..7]
F BEAD
R23
R19
2
of
1
FB3
RXD
TXD
VSOUT
PGM_IN
PGM_OUT
CAS_PROGEN
FMCU0
FMCU1
FMCU2
FMCU3
FMCU4
FMCU5
FMCU6
FMCU7
VCC
SCL
+5V
SDA
GND
15-83-0064
P4
U7
AT89C55 44 PIN PLCC
RST
XTAL2
XTAL1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
NC
NC
NC
NC
Preliminary Information
VCC
12
65-B2193-10
Rev
0.9.0
PGM_OUT
FMCU[0..7]
FRESET\
RESET\
SDA
SCL
D3
GREEN
PRODUCT SPECIFICATION
TMB2193MS100
Figure 9.
13
TMB2193MS100
PRODUCT SPECIFICATION
TP9
VDD
VCC
+5V
+5V
2
FB1
P5V
+ C44
22µF
35V
JP12
CR2
RED
LED
1
F BEAD
C46
0.1µF
50V
+
C45
0.47µF
35V
CR3
1N4004
C47
0.01µF
50V
DGND AGND
GND
1
2
1
2
3
VDDA
+
C48
22µF
35V
+
C50
0.1µF
50V
FB2
C49
0.47µF
35V
C51
0.01µF
50V
CR4
1N4004
TP10
CR5
ORANGE
LED
-5V
VEE
-5V
1
2
POWER3
2
1
N5V
Preliminary Information
F BEAD
Ground Test Points
TP11
GND
TP12
GND
TP13
GND
TP14
GND
TP15
GND
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA92121
(619) 457-1000
Title
POWER.SCH
Size
B
Date:
Figure 10.
14
Document Number
TMB2193
Thursday, January 23, 1997
Rev
0.9.0
Sheet
12
of
12
PRODUCT SPECIFICATION
TMB2193MS100
VCC
R57
10K
R58
10K
R59
10K
R60
10K
R61
10K
R62
10K
U9
1
AIN
24
DIN
13
CIN
12
BIN
AIN
AOUT
DIN
DOUT
CIN
COUT
BIN
BOUT
5
AOUT
20
DOUT
17
COUT
8
BOUT
JP14 A2XEN
R41
D
R42
D
R43
D
R44
D
4
9
16
21
JUMPER
JP15 B2XEN
D IS150 OHM (1%)
7
18
JUMPER
NC1
NC2
ST-163E
C2XEN
JP20
JUMPER
JP21
JUMPER
JP22
JUMPER
JP23
JUMPER
R45
75
R46
75
R47
75
R48
75
Preliminary Information
JP16
A2X
B2X
C2X
D2X
JUMPER
JP17
D2XEN
JUMPER
JP18
NC1EN
JUMPER
JP19
ALL 1%
NC2EN
JUMPER
DO NOT STUFF
Title
MMC
Size
A
Date:
Document Number
TMB2193
Thursday, September 04, 1997
Rev
0.9.0
Sheet
7
of
12
65-B2193-12
Figure 11.
15
VCC
EMCU[0..3]
SCL
SDA
HSIN
VSIN
EPXCK
ECVBS[0..9]
OLENGI[0..5]
PD[0..23]
C61
0.1uF
C62
0.1uF
TP26
PXCK
C63
0.1uF
C64
0.1uF
TP29
HSIN
C65
0.1uF
EMCU[0..3]
TP27
TP28
VSOUT HSOUT
ECVBS[0..9]
OLENG[0..5]
PD[0..23]
C66
0.1uF
TP30
VSIN
C67
0.1uF
R40
4K7
VDD
C68
0.1uF
SCL
SDA
EMCU2
EMCU3
EMCU1
HSOUT
VSOUT
EMCU0
ECVBS0
ECVBS1
ECVBS2
ECVBS3
ECVBS4
ECVBS5
ECVBS6
ECVBS7
ECVBS8
ECVBS9
OLENG0
OLENG1
OLENG2
OLENG3
OLENG4
OLENG5
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
EDCVBSEN\ 57
58
59
60
61
ESA1
ESA0
62
56
55
73
74
75
95
ERESET\ 94
93
92
91
90
89
88
87
86
85
84
25
24
23
22
21
20
52
51
50
49
48
47
46
45
44
43
42
41
38
37
36
35
34
33
32
31
30
29
28
27
DCVEN
SER
CS/SCL
R/W/SDA
A1/SA1
A0/SA0
HSIN
VSIN
PDC
HSOUT
VSOUT
PXCK
RESET
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
CVBS8
CVBS9
OL0
OL1
OL2
OL3
OL4
KEY
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
2
5
10
15
19
80
79
78
77
76
1
7
12
17
3
6
11
16
98
TMC2193KHC
D0
D1
D2
D3
D4
D5
D6
D7
70
69
68
67
66
65
64
63
83
FLD0 82
FLD1 81
FLD2
LINE0
LINE1
LINE2
LINE3
LINE4
VDDA
VDDA
VDDA
VDDA
C_BYB4
C_BYB3
C_BYB2
C_BYB1
V_REF
99
R_REF4 8
R_REF3 13
R_REF2 18
R_REF1
COMP2
CH/R/P_R
Y/B/P_B
COMP/G/Y
REFDAC
U8
DCVBS0
DCVBS1
DCVBS2
DCVBS3
DCVBS4
DCVBS5
DCVBS6
DCVBS7
DCVBS8
DCVBS9
C55
0.1uF
TP24
DA4
TP22
DA3
TP20
DA2
TP18
DA1
TP16
RDA
COUT
BOUT
DOUT
AOUT
A_OUT
{Schematic}
C57
0.1uF
DCVBS[0..9]
C56
0.1uF
1
2
3
4
5
6
7
8
TP25
ODA4
TP23
ODA3
TP21
ODA2
TP19
ODA1
TP17
ORDA
R33
8.25K Ohm
1
J2
RDAC
STUFF EITHER C54 OR D4
Document Number
TMB2193
Thursday, September 04, 1997
Date:
TMC2193.SCH
Size
B
Title
5580 Morehouse Dr.
San Diego, CA 92121
2
5
of
R35
8.25K Ohm
1
J5
DAC3
R34
8.25K Ohm
1
Sheet
VDD
J4
DAC2
3.3K Ohm
R27
D4
1.235V
R36
10K Pot
0.1uF
C54
2
R37
10K Pot
R28
10K Ohm
2
1
R29
10K Ohm
J3
DAC1
2
Raytheon Electronics - Semiconductor Division
VSOUT
HSOUT
1
2
R32
8.25K Ohm
DCVBS[0..9]
C58
0.1uF
JP13
VDD
CONNECT Cx TO VDDA PIN
AND CBYPy PIN DIRECTLY
{Schematic}
CIN
BIN
DIN
AIN
MMC
A_IN
LPF
2
VCC
1
2
39
54
72
96
DGND
DGND
DGND
DGND
DGND
26
40
53
71
97
VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
4
9
14
100
1
3
3
1
2
1
Figure 12.
3
1
16
Rev
0.9.0
65-B2193-13
12
R38
10K Pot
2
2
R39
10K Pot
R31
10K Ohm
DAC4
J6
R30
10K Ohm
3
Preliminary Information
TMB2193MS100
PRODUCT SPECIFICATION
PRODUCT SPECIFICATION
TMB2193MS100
Table 5. TMB2193MS100 Parts List
Item
Quantity
Reference
1
48
2
Part
Number
Description
C1 C2 C3 C4 C5 C6 C7 C8
C9 C10 C11 C12 C13 C14
C19 C20 C21 C22 C23
C24C25 C26 C27 C28 C31
C32 C34 C35 C36 C37 C38
C42 C43 C46 C50 C54 C55
C56 C57 C58 C61 C62 C63
C64 C65 C66 C67 C68
MiniReel: 605-611
0.1mF (0805 FP)
2
C29 C30
Minireel
22mF/6.3v (D FP)
3
1
C33
MiniReel: 605-168
6.8pF (0805 FP)
4
1
C39
MiniReel: 605-315
150pF (0805 FP)
5
1
C40
MiniReel: 605-339
390pF (0805 FP)
6
1
C41
MiniReel: 642-810
10.0mF/16V (B FP)
7
2
C44 C48
MiniReel: 645-823
22mF/25v (D FP)
8
2
C45 C49
MiniReel: 641-647
0.47mF/25v (A FP)
9
2
C47 C51
MiniReel: 605-510
0.01mF (0805 FP)
10
5
R1 R2 R3 R4 R5
MiniReel: 615-410
1K (0805 FP)
11
7
R6 R7 R9 R45 R46 R47
R48
MiniReel: 615-275
75 (0805 FP)
12
1
R8
MiniReel: 615-822
220 (0805 FP)
13
3
R10 R15 R16
MiniReel: 615-844
33 (0805 FP)
14
1
R11
MiniReel: 615-844
3.3K (0805 FP)
15
3
R12 R13 R14
MiniReel: 615-447
4.75K (0805 FP)
16
18
R17 R21 R23 R24 R49 R50
R51 R52 R53 R54 R55 R56
R57 R58 R59 R60 R61 R62
MiniReel: 615-510
10K (0805 FP)
17
1
R18
MiniReel: 615-275
75 (0805 FP)
18
1
R19
ROHM
1 OHM, 1/4W Carbon
19
3
R20 R22 R40
MiniReel: 615-848
4.7k (0805 FP)
20
1
R27
MiniReel: 615-844
3.3K Ohm (0805 FP)
21
4
R28 R29 R30 R31
MiniReel: 615-849
10K Ohm (0805 FP)
22
4
R32 R33 R34 R35
MiniReel: 615-415
8.25K Ohm (0805 FP)
23
4
R36 R37 R38 R39
Bourns
10K Pot (SMT)
24
4
R41 R42 R43 R44
25
1
L1
MiniReel
10uH (3225M FP)
26
3
FB1 FB2 FB3
Ferrite
Ferrite Bead
27
2
CR1 D4
Linear Technology
1.235V Reference
28
2
D1 D2
Motorola
Diode Schottky
29
2
CR3 CR4
MiniReel: 76-4004
Diode Rectifier
30
1
CR2
Hewlett Packard
Red LED
31
1
CR5
Hewlett Packard
Orange LED
32
1
D3
Hewlett Packard
Green LED
35
1
JP1
Amp
Header 5X2
Preliminary Information
Manufacturer
150 (0805 FP)
17
TMB2193MS100
PRODUCT SPECIFICATION
Preliminary Information
Table 5. TMB2193MS100 Parts List (continued)
Item
Quantity
Reference
36
6
37
Part
Number
Manufacturer
Description
JP9 JP11 JP20 JP21 JP22
JP23
Amp
2 Pin Header
1
JP10
Amp
4 Pin Header
38
1
JP13
Amp
8 Pin Header
39
1
P1
Amp
72 Pin Header
40
1
JP12
Beau
Power, Plug Power,
Socket
41
6
J1 J2 J3 J4 J5 J6
Amphenol
BNC
42
1
P2
Amp
96 Pin Euro Connector
(Female)
43
1
P3
Amp
96 Pin Euro Connector
(Male)
44
1
P4
Molex
Rbus Connector
45
3
E1 E2 E3
Secma
SPDT Switch
46
1
S1
ITT Canon
SMT Push Button
Switch
47
1
S2
Alco
8 Position DIP Switch
48
21
TP1 TP2 TP3 TP4 TP9
TP10 TP16 TP17 TP18
TP19 TP20 TP21 TP22
TP23 TP24 TP25 TP26
TP27 TP28 TP29 TP30
Mouser
Test Point
49
5
TP11 TP12 TP13 TP14
TP15
Bare Wire
Ground Point
50
1
U1
Motorola
74F240
51
1
U2
Motorola
74F14
52
1
U4
Atmel
Serial Eprom
53
1
U5
Fairchild
Genlock
54
1
U7
Atmel
Microprocessor
55
1
U8
Fairchild
Encoder
56
1
U9
MMC
Video Filter
ST-163E
57
1
U10
Motorola
74F74
58
1
U11
Altera
FPGA
59
1
Y1
Ecliptec
27MHz
60
1
Y2
Ecliptec
20MHz
18
PRODUCT SPECIFICATION
TMB2193MS100
Table 6. INPUT 96 Way Connector (Female)
row A
row B
row C
32
+5V
32
GND
32
+5V
31
D1 or R/V [bit 0]
31
+5V
31
GND
30
D1 or R/V [bit 1]
30
+5V
30
PXCK
29
D1 or R/V [bit 2]
29
+5V
29
GND
28
D1 or R/V [bit 3]
28
GND
28
PCK
27
D1 or R/V [bit 4]
27
Analog Composite/luma
27
GND
D1 or R/V [bit 5]
26
GND
26
CREF
D1 or R/V [bit 6]
25
Analog chroma
25
GND
24
D1 or R/V [bit 7]
24
XEN
24
VSYNC
23
D1 or R/V [bit 8]
23
GND
23
HSYNC
22
D1 or R/V [bit 9]
22
XDIR
22
HREF
21
Comp, G/Y, or Luma [bit 0]
21
XHSYNC
21
VREF
20
Comp, G/Y, or Luma [bit 1]
20
XVSYNC
20
ODD IN
19
Comp, G/Y, or Luma [bit 2]
19
XPXCK
19
GND
18
Comp, G/Y, or Luma [bit 3]
18
XRS [bit 3]
18
NTSC/PAL
17
Comp, G/Y, or Luma [bit 4]
17
XRS [bit 2]
17
CLAMP pulse
16
Comp, G/Y, or Luma [bit 5]
16
XRS [bit 1]
16
RGB
15
Comp, G/Y, or Luma [bit 6]
15
XRS [bit 0]
15
14
Comp, G/Y, or Luma [bit 7]
14
GND
14
13
Comp, G/Y, or Luma [bit 8]
13
-5V
13
12
Comp, G/Y, or Luma [bit 9]
12
-5V
12
LOCK
11
Chroma or B/U [bit 0]
11
-5V
11
D1
10
Chroma or B/U [bit 1]
10
GND
10
RESET
9
Chroma or B/U [bit 2]
9
PGM_IN
9
SCL
8
Chroma or B/U [bit 3]
8
-12V
8
GND
7
Chroma or B/U [bit 4]
7
-12V
7
SDA
6
Chroma or B/U [bit 5]
6
IE (input enable)
6
OE (output enable)
5
Chroma or B/U [bit 6]
5
GND
5
BLANK (DAC)
4
Chroma or B/U [bit 7]
4
4
3
Chroma or B/U [bit 8]
3
3
2
Chroma or B/U [bit 9]
2
+12V
2
+12V
1
GND
1
GND
1
GND
Preliminary Information
26
25
19
TMB2193MS100
PRODUCT SPECIFICATION
Input Edge Connector Design Notes
Signal Flow FORWARD
TMC1185
Chrominance
BPF and
Clamp Circuit
FPGA
TMC2072
TMC3003
Decoder
Input Logic
TMC2242
TMC22153
32 32
Preliminary Information
SW1
SW2
High Quality
LPF
Digital
LPFs
EPROM
1
High Quality
LPF
10 bit
ADCs
1
High Quality
LPF
TMC2242
1
2:1 MUX
TMC1185
1
Y/Composite
LPF and
Clamp Circuit
32 32
SW1
DC Supply
+5V 0V -5V
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
65-B2193-14
Signal Flow BACKWARD
1.
Boards with different revision letters may not be
compatible. Damage may occur if they are connected together!
2.
XPXCK is a two times pixel clock fed BACKWARD.
3.
XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4.
5.
20
The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed
FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
6.
PGM_IN is a negative going pulse, logically ANDed
with the onboard program start pulse, for initiating the
programming sequence for components on that board.
Care must be taken to ensure that multiple devices do
not try to drive the RBUS at any given time. Minimum
width of PGM_IN is 1uS.
7.
The RESET pin on the input edge connector should be
connected directly to the RESET pin on the output connector. A link should be used to connect any pulse to the
RESET line.
8.
The MASTER/SLAVE, XDIR, PGM_IN and RESET
pins on the input edge connector should be connected to
+5V through a 10k pull up resistor.
9.
The CLAMP signal is fed BACKWARD from a
MASTER to a SLAVE board. The CLAMP signal
should not be fed FORWARD.
PRODUCT SPECIFICATION
TMB2193MS100
Table 7. OUTPUT 96 Way Connector (Male)
row A
row B
row C
1
+5V
1
GND
1
+5v
2
D1 or R/V [bit 0]
2
+5V
2
GND
3
D1 or R/V [bit 1]
3
+5V
3
PXCK
4
D1 or R/V [bit 2]
4
+5V
4
GND
5
D1 or R/V [bit 3]
5
GND
5
PCK
6
D1 or R/V [bit 4]
6
Analog Composite/luma
6
GND
D1 or R/V [bit 5]
7
GND
7
CREF
D1 or R/V [bit 6]
8
Analog chroma
8
GND
9
D1 or R/V [bit 7]
9
XEN
9
VSYNC
10
D1 or R/V [bit 8]
10
GND
10
HSYNC
11
D1 or R/V [bit 9]
11
XDIR
11
HREF
12
Comp, G/Y, or Luma [bit 0]
12
XHSYNC
12
VREF
13
Comp, G/Y, or Luma [bit 1]
13
XVSYNC
13
ODD IN
14
Comp, G/Y, or Luma [bit 2]
14
XPXCK
14
GND
15
Comp, G/Y, or Luma [bit 3]
15
XRS [bit 3]
15
NTSC/PAL
16
Comp, G/Y, or Luma [bit 4]
16
XRS [bit 2]
16
CLAMP pulse
17
Comp, G/Y, or Luma [bit 5]
17
XRS [bit 1]
17
RGB
18
Comp, G/Y, or Luma [bit 6]
18
XRS [bit 0]
18
19
Comp, G/Y, or Luma [bit 7]
19
GND
19
20
Comp, G/Y, or Luma [bit 8]
20
-5V
20
21
Comp, G/Y, or Luma [bit 9]
21
-5V
21
LOCK
22
Chroma or B/U [bit 0]
22
-5V
22
D1
23
Chroma or B/U [bit 1]
23
GND
23
RESET
24
Chroma or B/U [bit 2]
24
PGM_OUT
24
SCL
25
Chroma or B/U [bit 3]
25
-12V
25
GND
26
Chroma or B/U [bit 4]
26
-12V
26
SDA
27
Chroma or B/U [bit 5]
27
IE (input enable)
27
OE (output enable)
28
Chroma or B/U [bit 6]
28
GND
28
BLANK (DAC)
29
Chroma or B/U [bit 7]
29
29
30
Chroma or B/U [bit 8]
30
30
31
Chroma or B/U [bit 9]
31
+12V
31
+12V
32
GND
32
GND
32
GND
Preliminary Information
7
8
21
TMB2193MS100
PRODUCT SPECIFICATION
Output Edge Connector Design Notes
Signal Flow FORWARD
TMC1185
Chrominance
BPF and
Clamp Circuit
FPGA
TMC2072
TMC3003
Decoder
Input Logic
TMC2242
TMC22153
32 32
Preliminary Information
SW1
SW2
High Quality
LPF
Digital
LPFs
EPROM
1
High Quality
LPF
10 bit
ADCs
1
High Quality
LPF
TMC2242
1
2:1 MUX
TMC1185
1
Y/Composite
LPF and
Clamp Circuit
32 32
SW1
DC Supply
+5V 0V -5V
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
65-B2193-14
Signal Flow BACKWARD
1.
Boards with different revision letters may not be compatible; damage may occur if they are connected
together.
8.
The MASTER/SLAVE, XDIR, PGM_OUT and RESET
pins on the output edge connector should be connected
to +5V through a 10k pull up resistor.
2.
XPXCK is a two times pixel clock fed BACKWARD.
9.
3.
XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not
be fed FORWARD.
4.
The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5.
XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
6.
PGM_OUT negative going signal pulse for initiating
programming of down stream boards, generated once
the devices on the board have been programmed. Care
must be taken to ensure that multiple devices do not try
to drive the RBUS at any given time. The Minimum
width of PGM_OUT is 1uS.
7.
The RESET pin on the output edge connector should be
connected directly to the RESET pin on the input connector. A link should be used to connect any pulse to the
RESET line.
22
Related Products
•
•
•
•
•
TMB22153MS101 Decoder demonstration board
TMB1185MS102 ADC demonstration board
TMB0000UG100 RBUS Interface
TMB0001MS100 Parallel D1 interface board
Raydemo software
PRODUCT SPECIFICATION
TMB2193MS100
Notes:
Preliminary Information
23
TMB2193MS100
PRODUCT SPECIFICATION
Ordering Information
Product Number
Temperature
Range
Speed
Grade
Screening
Package
Package
Marking
TMB2193MS100
25°C
27 MHz
Commercial
4" by 5" Printed Circuit Board
TMB2193MS100
A schematic database is available in OrCAD™ format. Contact the factory.
The TMB2193MS100 Demonstration Board, design documentation, and software are provided as a design example for the
customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a
particular purpose.
Preliminary Information
FCC Compliance
This device has not been approved by the Federal Communications Commission (FCC). This board is intended for the evaluation of Fairchild products only. This device is not and may not be offered for sale or lease or sold or leased until the approval
of the FCC has been obtained.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/3/98 0.0m 002
Stock# DS7TMB2193
Ó 1998 Fairchild Semiconductor Corporation