4.0 MONITOR TERMINAL ARCHITECTURE

4.0 MONITOR TERMINAL ARCHITECTURE
In many applications, the SMMIT Monitor Terminal (SMT)
may be required to be the Backup Bus Controller (BBC). With
this in mind, the SMT architecture is designed to function like
the SBC’s architecture. The SMT’s architecture is based on a
monitor block structure and internal, programmable registers.
Designed to run autonomously and reduce host overhead, the
SMT automatically executes data handling, message error
checking, memory control, and related protocol functions.
Discussed in this section are the following monitor features and
functions:
 Command History List
 Executable Architecture
 BIT Capability
 Interrupt History List
 Monitor All or Selected Terminals
 Memory Management
4.1 Register Descriptions
To initialize the SMMIT as a monitor terminal, the designer
must understand the internal registers. A complete description
of each register and the associated bits is provided. These
registers offer many programmable functions and allow host
access to extensive information. All register bits are active high
and reflect a logic zero condition (0000 hex) after Master Reset
(except those reflecting input pins). Each register associated
with the monitor mode of operation is described below.
Register
Number
Name
Register Address
0
Control Register
0000 (hex)
1
Operational Status Register
0001 (hex)
2
Current Command Register
0002 (hex)
3
Interrupt Mask Register
0003 (hex)
4
Pending Interrupt Register
0004 (hex)
5
Interrupt Log List Pointer Register
0005 (hex)
6
BIT Word Register
0006 (hex)
7
Time-Tag Register
0007 (hex)
8-10
Not Applicable
0008 to 000A (hex)
11
Initial Monitor Command Block Pointer Register
000B (hex)
12
Initial Monitor Data Pointer Register
000C (hex)
13
Monitor Block Counter Register
000D (hex)
14
Monitor Filter Register
000E (hex)
15
Monitor Filter Register
000F (hex)
16-31
Not Applicable
0010 to 001F (hex)
Note: Reference section 9.1.2 for SMMIT XT 8-bit register address numbers.
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4.1.1 Control Register (Read/Write) - Register 0
To operate the SMMIT as a monitor terminal, use the following bits. To make changes to the SMT and this register, the STEX bit
(Bit 15) must be logic zero.
Note: The user has 5s after TERACT active to stop execution.
Bit
Number
Mnemonic
Description
15
STEX
Start Execution. Assertion of this bit commences operation of the
SMMIT. A Control Register write negating this bit inhibits operation
of the SMMIT. After execution has begun, a write of a logic zero will
halt the SMT after completing the current 1553 message.
14
SBIT
Start BIT. Assertion of this bit places the SMMIT into the Built-In
Test routine. The BIT test has a 93.4% fault coverage. If the SMMIT
has been started, the host must halt the device in order to place the
SMMIT into the Built-In Test routine (STEX = 0).
Note: If Start BIT (SBIT) and Start Execution (STEX) are both set on
one register write, BIT has priority.
13
SRST
Software Reset. Assertion of this bit immediately places the SMMIT
into a software reset. The software reset (which takes 5s to execute)
clears all internal logic, just as the MRST does. Note: During autoinitialization, do not load this bit with a logic one. SRST will only
function after READY is asserted.
12-11
N/A
Not Applicable.
10
ETCE
External Timer Clock Enable. If this bit is set to logic one, the SMT
will use the external input clock to drive the Time-Tag counter. If set
to logic zero, the SMT will use an internal clock to drive the time tag
counter. Refer to section 4.1.8 for additional information.
Note: The user can only change the clock frequency before starting the
device (i.e., setting bit 15 of Register 0 to a logic one).
9
--
See section 5, Enhanced SMMIT Family Operation.
8-7
N/A
Not Applicable.
6
BUFR
Buffer Mode Enable. Assertion of this bit enables the buffer mode of
operation. For more detailed information on this feature refer to
section 9.1.5 and 9.2.3.
5
SMTC
Monitor Control. This bit determines whether the SMT will monitor
all RTs or selected RTs. If this bit is set to logic zero, the SMT will
monitor all RTs. If this bit is set to logic one, the SMT will monitor only
the RTs as specified in the Monitor Filter Registers (Registers 14 and
15).
4
BCEN
Broadcast Enable. This bit, if set to logic one, allows RT address 31 to
be used as a Broadcast message. If set to logic zero, then address 31 is
a normal address.
3-2
N/A
Not Applicable.
1
INTEN
Interrupt Log List Enable. Assertion of this bit enables the Interrupt
Log List. Negation of this bit prevents the logging of interrupts as they
occur.
0
N/A
Not Applicable.
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4.1.2 Operational Status Register (Read/Write) - Register 1
This register reflects pertinent status information for the SMT and is not reset to 0000 (hex) on MRST. Instead, the register reflects
the actual stimulus applied to input pins MSEL(1:0), A/B STD, and LOCK. Assertion of the LOCK input prevents the modification
of the remote terminal address, mode selects, and the A or B Standard bits. In this case, a write to this register’s most significant
nine bits is meaningless. If LOCK is negated, a read of this register reflects the information written into this register’s most significant
nine bits.
Note: To make changes to the SMT and this register, the STEX bit (Register 0, bit 15) must be logic zero.
Bit
Number
Mnemonic
Description
15-10
N/A
Not Applicable.
9
MSEL(1)
Mode Select 1. In conjunction with Mode Select 0, this bit determines
the SMMIT mode of operation.
8
MSEL(0)
Mode Select 0. In conjunction with Mode Select 1, this bit determines
the SMMIT mode of operation.
MSEL(1)
MSEL(0)
Mode of Operation
0
0
Bus Controller = SBC
0
1
Remote Terminal = SRT
1
0
Monitor Terminal = SMT
1
1
SMT/SRT
7
A/B STD
Military Standard 1553A or 1553B Standard. This bit determines
whether the SMT will look for the RT’s response in 9s (MIL-STD1553A) or in 15s (MIL-STD-1553B). Assertion of this bit forces the
SMT to declare a time-out error condition if the RT has not responded
in 9s. Negation of this bit allows the SMT to declare a time-out error
condition if the RT has not responded in 15s. See section 4.7 and
section 5.0, Enhanced SMMIT Family Operation, for additional
information.
6
LOCK
LOCK Pin. This read-only bit reflects the inverted state of the LOCK
input pin. The Lock pin is latched on the rising edge of MRST. If modes
of operation must change, the user must perform a MRST.
5
AUTOEN
AUTOEN Pin. This read-only bit defines whether or not the auto enable
feature will be used in the design. This bit shows the inverse of the auto
enable (AUTOEN) input pin.
4
N/A
Not Applicable.
3
EX
SMMIT Executing. This read-only bit indicates whether the SMT is
presently executing or whether it is idle. A logic one indicates that the
SMMIT is executing, logic zero idle.
2
N/A
Not Applicable.
1
READY
READY Pin. This read-only bit reflects the inverted state of the output
pin READY and is cleared on reset.
0
TERACT
Terminal Active Pin. Assertion of this bit indicates that the SMT is
presently processing a message. This read-only bit reflects the inverted
state of output pin TERACT and is cleared on reset.
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4.1.3 Current Command Register (Read-only) - Register 2
This register contains the last valid command that was transmitted over the 1553 bus. In a RT-RT transfer, this register will update
as each of the two commands are received by the SMT.
Bit
Number
Mnemonic
Description
15-0
CC(15:0)
Current Command. These bits contain the latest 1553 word that was
received by the SMT.
4.1.4 Interrupt Mask Register (Read/Write) - Register 3
The SMT interrupt architecture allows the host or subsystem to mask or temporarily disable the service of interrupts. While masked,
interrupt activity does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for that event.
An interrupt is masked if the corresponding bit of this register is set to logic zero.
Bit
Number
Mnemonic
Description
15
DMAF
DMA Fail Interrupt.
14-13
N/A
Not Applicable.
12
BITF
BIT Fail Interrupt.
11
MERR
Message Error Interrupt.
10-1
N/A
Not Applicable.
0
MBC
Monitor Block Counter Interrupt.
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4.1.5 Pending Interrupt Register (Read-only) - Register 4
The Pending Interrupt Register contains information that identifies events that generate interrupts. The assertion of any bit in this
register asserts an output pin, MSG_INT or YF_INT (three clock cycles). Writing to the most significant four bits of this register
generates a YF_INT.
Bit
Number
Mnemonic
Description
15
DMAF
DMA Fail Interrupt. Once the SMMIT has issued the DMAR signal,
an internal timer is started. If all DMA activity has not been completed,
the interrupt is generated (if not masked). In the SMT mode, the
YF_INT interrupt is generated, current command processing will end,
and the SMT will remain on-line.
14-13
N/A
Not Applicable.
12
BITF
BIT Fail Interrupt. Assertion of this bit indicates a BIT failure.
Interrogate the BIT Word Register to determine the specific failure.
YF_INT interrupt generated (if not masked), operation continues.
11
MERR
Message Error Interrupt. This bit is set if a message error occurs. The
SMT can detect Manchester, sync-field, word count, 1553 word parity,
bit count, and protocol errors. This bit will be set and interrupt generated
after message processing is complete. MSG_INT interrupt generated
(if not masked).
10-1
N/A
Not Applicable.
0
MBC
Monitor Block Counter Interrupt. This bit is set if the SMT’s monitor
block counter reaches zero (transition from 1 to 0). It should be noted
that the SMT does not discriminate between error-free messages and
those messages with errors. MSG_INT interrupt generated (if not
masked).
Note: The user must read or write a SMMIT register after reading the Pending Register to invoke the automatic clear of the Pending
Interrupt Register. For example, a Subaddress Access interrupt results in a Pending Interrupt Register of 040016. A read of the
Pending Interrupt Register returns a value of 040016. A subsequent read of the Interrupt Mask Register (i.e., Register 316), followed
by a Pending Interrupt Register read returns a value of 000016. The intervening read of the Interrupt Mask Register clears of the
Pending Interrupt Register at the end of the Interrupt Mask Register read.
4.1.6 Interrupt Log List Pointer Register (Read/Write) - Register 5
This register indicates the starting address of the Interrupt Log List. The Interrupt Log List is a 32-word ring-buffer that contains
information pertinent to the service of interrupts. The SMMIT architecture requires the location of the Interrupt Log List on a 32word boundary. The most significant 11 bits of this register designate the location of the Interrupt Log List within a 32K memory
space. Initialize the lower five bits of this register to a logic zero. The SMMIT controls the lower five bits to implement the ringbuffer architecture. The host or subsystem reads this register to determine the location and number of interrupts within the Interrupt
Log List (least significant five bits).
Bit
Number
Mnemonic
Description
15-0
INTA(15:0)
Interrupt Log List Pointer Bits. These bits indicate the starting location
of the Interrupt Log List.
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4.1.7 BIT Word Register (Read/Write)- Register 6
This register contains information on the current health of the SMT. The lower eight bits of this register are user-defined.
Bit
Number
Mnemonic
Description
15
DMAF
DMA Fail. This bit is set if all DMA activity has not been completed
between the time DMAR asserts and when the timer decrements to zero.
The DMA activity includes DMAR to DMAG and all wait states. In
the event of a DMA failure, current message processing terminates;
monitor terminal waits for next 1553 message. DMAF asserts, and
YF_INT is generated (if not masked).
14-13
N/A
Not Applicable.
12
BITF
BIT Fail. Assertion of this bit indicates a BIT failure. Interrogate bits
11 through 8 to determine the specific failure.
11
CHAF
Channel A Fail. Assertion of this bit indicates a BIT test failure in
Channel A.
10
CHBF
Channel B Fail. Assertion of this bit indicates a BIT test failure in
Channel B.
9
MSBF
Memory Test Fail. Most significant memory byte failure (SMMIT
XTE). User-Defined Bits (SMMIT E & SMMIT LXE/DXE).
8
LSBF
Memory Test Fail. Least significant memory byte failure (SMMIT
XTE). User-Defined Bits (SMMIT E & SMMIT LXE/DXE).
7-0
UDB(7:0)
User-Defined Bits.
4.1.8 Time-Tag Register (Read/Write) - Register 7
This register reflects the state of a 16-bit free running ring counter. This counter will remain a free running counter as long as the
device is not in MRST or in a software reset state. The resolution of this counter is user-defined via input TCLK or fixed at a period
of 64s. The Time-Tag counter begins operation on the rising edge to MRST.
Bit
Number
Mnemonic
Description
15-0
TT(15:0)
Time-Tag Counter Bits. These bits indicate the state of the 16-bit
internal counter.
4.1.9 Initial Monitor Block Pointer Register (Read/Write) - Register 11
This register contains the starting location of the monitor blocks.
Note: It is recommended that this register not be changed while the SMT is active (i.e., Register 1, bit 3 = 1).
Bit
Number
Mnemonic
Description
15-0
MBA(15:0)
Initial Monitor Block Address. These bits indicate the starting location
of the monitor block.
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4.1.10 Initial Monitor Data Pointer Register (Read/Write) - Register 12
This register contains the starting location of the monitor data.
Note: It is recommended that this register not be changed while the SMT is active (i.e., Register 1, bit 3 = 1).
Bit
Number
Mnemonic
Description
15-0
MDA(15:0)
Initial Monitor Data Address. These bits indicate the starting location
of the monitor data.
4.1.11 Monitor Block Counter Register (Read/Write) - Register 13
This register contains the number of the monitor block the user wishes to log. After execution begins, this register automatically
decrements as commands are logged. When this register is decremented from one to zero, an interrupt will be generated, if enabled.
The SMT will start over at the initial pointers as identified in Registers 11 and 12.
Note: It is recommended that this register not be changed while the SMT is active (i.e., Register 1, bit 3 = 1).
Bit
Number
Mnemonic
Description
15-0
MBC(15:0)
Monitor Block Count. These bits indicate the number of monitor blocks
to log.
4.1.12 Monitor Filter Register (Read/Write) - Register 14
This register determines which RTs (RT 31 through RT 16) the SMT will monitor. Reset value is 0000 (hex). A logical "1" indicates
the monitor captures all data to and from the remote terminal.
Bit
Number
Mnemonic
Description
15-0
MF(31:16)
Monitor Filter. These bits determine which RT to monitor.
4.1.13 Monitor Filter Register (Read/Write) - Register 15
This register determines which RTs (RT 15 through RT 0) the SMT will monitor. Reset value is 0000 (hex). A logical "1" indicates
the monitor captures all data to and from the remote terminal.
Bit
Number
Mnemonic
Description
15-0
MF(15:0)
Monitor Filter. These bits determine which RT to monitor.
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4.2 SMT Architecture
To meet the MIL-STD-1553 monitor requirements, the SMT
utilizes a monitor block architecture that takes advantage of both
internal registers and external memory. The monitor block,
which is located in external contiguous memory, requires eight
locations for each message. These eight locations include a
message information word, two command word locations, a data
pointer, two status word locations, a time-tag location, and an
unused location.
Message information Word
Command Word 1
Command Word 2
Data Pointer
Status Word 1
The host, or ROM for autonomous operation, must initialize the
starting locations of the monitor block, the Data Pointer, Block
Counter, and the Interrupt Log Pointer. From then on, the SMT
will build a monitor block for each message it receives over the
1553 bus. Figure 11 shows a diagram of the monitor block
followed by a description of each location associated with the
monitor block.
Status Word 2
Time-Tag
Unused
Figure 12. Monitor Block Diagram
The first memory location of each monitor block contains the
message information word. Each message information word
contains the opcode, retry number, bus definition, RT-RT
messages, and the message information.
15
12 11
0100
10
0 0
9
8
CHA/B
7
RT-RT
0
Message Information
4.2.1 Message Information Word
Bit
Number
Description
15-12
Default. With the monitor block architecture resembling the SBC Command Block architecture,
these bits default to a “0100” state (which is the Execute and Continue opcode) in case the monitor
must switch to the BC mode of operation.
11-10
Default. With the monitor block architecture resembling the SBC, these bits default to a “00” state.
If the monitor must switch to the BC, the retries will be set at four per message.
9
Channel A/B. This bit defines on which of the two buses the command was received. (Logic 1 =
Bus A, Logic 0 = Bus B).
8
RT-RT Transfer. This bit defines whether or not the message associated with this monitor block
was a RT-RT transfer and whether the SMT saved the second command word. This bit will be set
only if the SMT is instructed to monitor the Receive RT.
7-0
Message Information. These bits define the conditions of the message received by the SMT for
that particular monitor block. Each of the message information bits is defined in the following
section.
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4.2.1.1 Message Information Bits
Message information bits are provided as a means to supply more data on the message. In a RT-RT transfer, the information applies
to the complete message. Each message information bit is defined below.
Bit
Number
Description
7
Message Error. This bit will be set if the monitor detects an error in either the command word, data
words, or the RT’s status.
6
Mode Code without Data. This bit will be set if the monitor detects that the command being
processed is a mode code without data words.
5
Broadcast. This bit will be set if the monitor detects that the command being processed is a broadcast
message.
4
Reserved.
3
Time-out Error. This bit will be set if the SRT did not receive the proper number of data words,
e.g., the number of data words received was less than the word count specified in the command
word.
2
Overrun Error. This bit will be set if the SRT received a word when none were expected or the
number of data words received was greater than expected.
1
Parity Error. This bit will be set if a parity error has occurred on the data words or the RT’s status
word.
0
Manchester Error. This bit will be set if a Manchester error has occurred on either the data words
or the RT’s status word.
4.2.2 Command Words
The next two locations in the SMT monitor block are for
command words. In non-RT-RT 1553 messages, only the first
command word will be stored. However, in a RT-RT transfer,
the first command word is the Receive Command and the second
command word is the Transmit Command.
4.2.3 Data Pointer
The fourth location in the SMT monitor block is the data pointer.
This pointer points to the first memory location to store the data
words associated with the message for this block. Note that the
data associated with each individual message will be stored
contiguously. This data structure allows the SMT to store the
specified number of data words. (Note: In a RT-RT transfer, the
SMT uses the data pointer as the location in memory to store
the transmitting data in the transfer.)
4.2.4 Status Words
The next two locations in the SMT monitor block are for status
words. As the RT responds to the BC’s command, the
corresponding status word will be stored in Status Word 1.
However, in a RT-RT transfer, the first status word will be the
status of the Transmitting RT while the second status word will
be the status of the Receiving RT.
4.2.5 Time-Tag
The seventh location in the SMT monitor block is the time-tag
associated with the message. The time-tag is stored into this
location at the end of message processing (i.e., captured after
the command is validated).
4.2.6 Unused
The last location in the SMT monitor block is unused.
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4.3 Monitor Block Chaining
The host determines the first monitor block by setting the start
address in the initial monitor block Pointer Register (Register
11). Figure 13 shows the SMT monitor blocks as the blocks
execute in a contiguous fashion (monitor block count Register
13 = 5).
4.4 Memory Architecture
Figure 14 shows the monitor blocks, data locations, and the
Interrupt Log List as separate entities within memory. The
configuration shows that the first block of memory is allocated
for the monitor blocks. Notice that Register 11 points to the
initial monitor block location, Register 12 points to the initial
Data location, Register 5 points to the Interrupt Log, and
Register 13 contains the monitor block count. After execution
begins, the SMT will build command blocks and store data
words until the count reaches zero. When the count reaches zero,
the SMT will simply wrap back to the initial values and start
again.
Monitor Block #1
Monitor Block
Count = 5
Monitor Block #2
Monitor Block
Count = 4
Monitor Block #3
Monitor Block
Count = 3
Monitor Block #4
Monitor Block
Count = 2
Monitor Block #5
Monitor Block
Count = 1
Monitor Block #6
Monitor Block
Count = 0
Figure 13. Monitor Block Structuring
Initial
Monitor
Command
Block
Pointer
Register
Reg 11
Monitor
(Memory)
Msg Info Word
CMD Words
Data Ptr
Status Words
Time-Tag
Unused
Initial
Monitor
Data Pointer
Register
Reg 12
Data
Storage
Memory
Interrupt Log
List Pointer
Register
Reg 5
Msg Info Word
CMD Words
Data Ptr
Status Words
Time-Tag
Unused
Msg Info Word
CMD Words
Data Ptr
Status Words
Time-Tag
Unused
Figure 14. Memory Architecture for Monitor Mode
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Interrupt
(Memory)
Int Info Word
Monitor Block
4.5 Message Processing
To process messages, the SMT uses data supplied in the internal
registers along with external memory. The SMT uses eight
external memory locations for each message called a monitor
block. The monitor block is updated at the end of command
processing. The following paragraphs discuss the monitor block
in detail.
The SMMIT features two different modes of transferring data
to RAM: Buffer and Non-Buffer. The user selects the Buffer or
Non-Buffer transfer mode by setting the BUFR bit (bit 6) in the
Control Register. See sections 9.1.5 or 9.2.3 for additional
information.
The host or subsystem controlling the SMT allocates memory
spaces for each monitor block. The top of the monitor blocks
can reside at any address location. Initialized by the host, the
SMT is linked to the monitor block via the initial monitor block
Pointer Register and the Monitor Block Counter Register
contents. Each monitor block contains a Message Information
Word, Command Word 1, Command Word 2, Data Pointer,
Status Word 1, Status Word 2, and Time-Tag. Refer to sections
4.2.1 - 4.2.6 for a full description of each location.
The Message Information word allows the SMT to tell the host
or subsystem on which bus the command was received, whether
the message was a RT-RT transfer, and conditions associated
with the message. The SMT also stores each command word
associated with the message into the appropriate location. For
normal 1553 commands, only the first command word location
will contain data. For RT-RT commands, the second command
word location will contain data, and bit 8 in the Message
Information word will be set.
For each command, the Data Pointer determines where to store
data words. The SMT stores data sequentially from the top
memory location. The SMT also stores each status word
associated with the message into the appropriate location. For
normal 1553 commands, only the first status word location will
contain data. For RT-RT commands, the second status word
location will contain data.The SMT begins monitoring after
Control Register bit 15=1 (i.e., assertion of STEX).
After reception, the SMT begins post-processing. The SMT
performs a DMA burst during post-processing. An optional
interrupt log entry is performed after a monitor block is entered.
Monitor Time-Out:
MIL-STD-1553A = 9s
MIL-STD-1553B = 15s
See section 5, Enhanced SMMIT Family Operation for
additional information.
4.5.1 Error Condition Message Processing
When the monitor detects an error condition in either the
command word, data words, or the RT’s status, the monitor
block will not store the data. The monitor block counter
increments. The initial message data pointer remains constant.
The monitor block pointer increments. Message information
bits of the monitor block are changed to reflect the error. An
interrupt is given indicating a message has occurred. See section
4.2.1.1 for additional information.
4.6 Remote Terminal/Monitor Terminal Operation
For applications that require simultaneous Remote Terminal and
Monitor Terminal operations, the SMMIT should be
configured as both a remote terminal (SRT) and monitor
terminal (SMT). This feature allows the SRT to communicate
on the bus for one specific address and the SMT to monitor the
bus for other specific addresses. Configuration as both SMT and
SRT precludes the SMMIT from monitoring its own remote
terminal address.
When the SMMIT is configured as both SRT and SMT, the
SRT has priority over the SMT. For example, commands to the
SRT will always take priority over monitoring functions for the
SMT. The examples below describe what happens if the SRT is
defined as terminal address 1 and the SMT is to monitor terminal
address 12.
Example 1:
Bus A
Bus B
CMD/TA =12
CMD/TA =1
In this example, the SMT will decode the first command on bus
A, realize the message is for terminal address 12, and start
monitoring the message. However, as soon as the SRT realizes
the second command on bus B is to terminal address 1, the SRT
will take priority and begin SRT message processing.
Example 2:
Bus A
Bus B
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CMD/TA =1
CMD/TA =12
In example 2, the SRT will decode the first command on bus A,
realize the message is for terminal address 1, and start message
processing. As the message on bus B is received, the SMMIT
will realize it is to terminal address 12, but since the SRT has
priority the SMT will not switch to the monitor mode.
The above examples also apply to a RT-RT message. For
example, if the first command in a RT-RT transfer matches the
terminal address of the SRT, the entire message will be
processed by the SRT (Message 1). However, if the first
command in a RT-RT transfer matches the terminal address of
the SMT and the second command matches the terminal address
of the SRT, the SRT will take priority and process the message
(Message 2). Below is a RT-RT message example.
Message 1
CMD/TA =1
CMD/TA =12
Message 2
CMD/TA =12
CMD/TA =1
4.7 MIL-STD-1553A Operation
To maximize flexibility, the SMMIT has been designed to
operate in many different systems which use various protocols.
Specifically, two of the protocols that the SMMIT may be
interfaced to are MIL-STD-1553A and MIL-STD-1553B. To
meet these protocols, the SMMIT may be configured through
an external pin or through control register bits (depending on
the state of the LOCK pin).
Table 6. MIL-STD-1553A Operation
A/B STD
(pin)
RESULT
0
1553B response, 1553B standard
1
1553A response, 1553A standard
When configured as a MIL-STD-1553A monitor, the SMMIT
will operate as follows:

Looks for the RT response within 9s (see section 5,
Enhanced SMMIT Family Operation);
 Defines all mode codes without data;
 Defines subaddress 00000 as a mode code.
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