ETC 5962R9211804VYC

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R208-93.
93-08-06
Monica L. Poelking
B
Changes in accordance with NOR 5962-R187-94.
94-06-08
Monica L. Poelking
C
Add device type 02. Editorial changes throughout.
96-01-05
Monica L. Poelking
D
Changes in accordance with NOR 5962-R299-97.
97-05-29
Monica L. Poelking
E
Add device type 03. Editorial changes throughout. - TVN
98-06-29
Monica L. Poelking
F
In table IA: Add test conditions for IIN; change the limits for QIDD; remove the test
condition VDD = 4.5 V for all the propagation delay tests; change the limits for ta
and ti in memory read timing section; change the limits of tc in DMA timing
section; and change the limit of ta in JTAG timing section. Include pin connections
for case outlines X and Z in radiation exposure connections. Editorial changes
throughout. - TVN
98-09-18
Monica L. Poelking
G
In table I, change IIN limits; add a footnote to QIDD; add tc in power-up master reset
timing section. Correct the JTAG timing waveforms. – TVN
99-05-26
Monica L. Poelking
H
Add device type 04. Editorial changes throughout. – TVN
00-07-18
Monica L. Poelking
J
Add notes to memory write and memory read waveforms. Add figure B-1 to
appendix A. Editorial changes throughout. – TVN
01-03-15
Thomas M. Hess
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REV STATUS
OF SHEETS
PREPARED BY
Thomas M. Hess
PMIC N/A
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
CHECKED BY
Thomas M. Hess
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
93-06-07
REVISION LEVEL
MICROCIRCUIT, DIGITAL, CMOS, MIL-STD-1553
SERIAL MICROCODED MONOLITHIC MULTI-MODE
INTELLIGENT TERMINAL, MONOLITHIC SILICON
SIZE
CAGE CODE
A
5962-92118
67268
J
SHEET
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1
OF
45
5962-E271-01
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
H
Federal
stock class
designator
\
92118
01
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
/
V
X
X
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
02
UT69151
UT69151E
03
04
UT69151E
UT69151E
Circuit function
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
Descriptive designator
CMGA3-P84
See figure 1
See figure 1
Terminals
Package style
84
84
132
Pin grid array
Leaded chip carrier
Leaded chip carrier with unformed
leads, nonconductive tier bar
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage range (VDD)..............................................................................
Voltage on any pin ..........................................................................................
Latchup immunity (ILU) ....................................................................................
DC input current (II) .........................................................................................
Maximum power dissipation (PD) .....................................................................
Storage temperature range (TSTG)....................................................................
Lead temperature (soldering, 5 seconds) .........................................................
Thermal resistance, junction-to-case (ΘJC).......................................................
Maximum junction temperature (TJ).................................................................
-0.3 V dc to +7.0 V dc
-0.3 V dc to VCC + 0.3 V dc
±150 mA
±10 mA
2.5 W
-65°C to +150°C
+300°C
15°C/W
175°C
1.4 Recommended operating conditions.
Supply voltage range (VDD)..............................................................................
DC input voltage (VIN)......................................................................................
Maximum input voltage (VIL) ............................................................................
Maximum input voltage, 24 MHz input (VILC) ....................................................
Minimum input voltage (VIH) ............................................................................
Minimum input voltage, 24 MHz input (VIHC) ....................................................
Operating frequency (fIN) .................................................................................
Duty cycle (DC)................................................................................................
Case operating temperature range (TC) ...........................................................
Radiation features:
Total dose:
Device type 02......................................................................................
Device type 04......................................................................................
Single event phenomenon (SEP) effective
LET, no upsets:
Device type 02...............................................................................
Device type 04...............................................................................
LET, no latchup:
Device type 02...............................................................................
Device type 04...............................................................................
Dose rate upset (20 ns pulse) ....................................................................
Dose rate latchup ......................................................................................
Dose rate survivability ...............................................................................
Neutron irradiated......................................................................................
+4.5 V dc to +5.5 V dc
0 V dc to VDD
0.8 V dc
0.3 VDD
2.2 V dc
0.7 VDD
24 ±0.01% MHz
50 ±5%
-55°C to +125°C
≥ 1 x 106 Rads (Si)
= 300k Rads (Si)
= 47 MeV/(mg/cm2)
< 14.4 MeV/(mg/cm2)
> 136 MeV/(mg/cm2)
> 128 MeV/(mg/cm2)
2/
2/
2/
2/
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) ................................................ 95.12 percent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed
in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in
the solicitation.
1/
2/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
When characterized as a result of the procuring activities request, the condition will be specified.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
3
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 MIL-STD-1835 -
Test Methods and Procedures for Microelectronics.
Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings (SMD's).
Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents which are DOD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture.
(Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
Piscataway, NJ 08854-4150.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents may also be available in or through libraries or other informational sevices.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class
M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
H
SHEET
4
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Boundary scan instruction codes. The boundary scan instruction codes shall be as specified on figure 4.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figures 5
through 13.
3.2.6 Radiation exposure connections. The radiation exposure connecttions shall be as specified on figure 14.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate
of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for
this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
3.11 IEEE 1149.1 compliance. Theses devices shall be compliant with IEEE 1149.1.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
H
SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Symbol
Device
type
Test conditions 1/
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Unit
Limits
Min
Max
Low level input voltage,
except TCK input
VIL1
All
1, 2, 3
0.8
Low level input voltage,
TCK input only
VIL2
01, 02
04
1, 2, 3
0.8
03
High level input voltage
VIH
Low level input voltage
VILC
High level intput voltage
VIHC
Low level output
voltage
VOL
High level output
voltage
VOH
Input leakage current
IIN
24 MHz input only
Outputs loads
IOL = 4.0 mA
0.7
All
1, 2, 3
All
1, 2, 3
All
1, 2, 3
All
1, 2, 3
2.2
0.3VDD
0.7VDD
0.4
IOL = 1.0 µA 2/
Outputs loads
0.05
IOH = 4.0 mA
All
1, 2, 3
2.4
IOH = 1.0 µA 2/
TTL driven
inputs
VIN = VDD
or VSS
Inputs with
pull-up
resistors
V
VDD-0.05
All
1, 2, 3
-10
VIN = VDD
All
1, 2, 3
-10
+10
VIN = VSS
01, 02
04
-900
-150
03
-167
-27
µA
+10
Three-state output
leakage current, TTL
loaded outputs
IOZ
Single-drive buffer
VO = VDD or VSS
All
1, 2, 3
-10
+10
µA
Short-circuit output
current, output loads
IOS
2/ 3/
Single-drive buffer
VDD = 5.5 V, VO = 0 V
All
1, 2, 3
-100
+100
mA
Input capacitance
CIN
All
4
15
pF
Output capacitance
COUT
f = 1 MHz at 0 V
See 4.4.1c
All
4
15
Bidirectional
capacitance
CIO
All
4
25
Quiescent current
4/
QIDD
01, 02
03
1, 3
35
µA
2
1
mA
Pre-irradiation
level R
04
1, 3
35
µA
2
1
mA
Pre-irradiation
level F
04
1, 3
35
µA
2
5
mA
40
mA
Standby operating
current
SIDD
Functional tests
f = 0 MHz
5/
f = 24 MHz
All
1, 2, 3
See 4.4.1b
All
7, 8
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
6
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Device
type
Test conditions 1/
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Unit
Limits
Min
Max
Register write timing
Address setup time 6/
ta
Data setup time 6/
tb
Data hold time 6/
All
9, 10, 11
0
All
9, 10, 11
10
tc
All
9, 10, 11
8
Address hold time 6/
td
All
9, 10, 11
8
CS (L) to CS (H) 6/
te
All
9, 10, 11
105
Access delay 6/ 7/ 8/
tf
All
9, 10, 11
85
tg
All
9, 10, 11
0
th
All
9, 10, 11
0
CS assertion to output
enable 6/
tI
All
9, 10, 11
0
40
CS negation to output
three-state 2/
tj
All
9, 10, 11
5
35
Address setup time 6/
ta
All
9, 10, 11
0
CS assertion to output
enable data valid 6/
tb
All
9, 10, 11
CS negation to output
disabled 2/
tc
All
9, 10, 11
5
Address hold time 6/
td
All
9, 10, 11
0
CS assertion to output
enable data invalid 6/
te
All
9, 10, 11
0
Access delay 6/ 7/ 8/
tf
All
9, 10, 11
45
CS (L) to CS (H) 2/
tg
All
9, 10, 11
105
01, 02
04
9, 10, 11
0
18
03
9, 10, 11
0
21
All
9, 10, 11
15
35
RD/ WR assertion to
CL = 35 pF minimum
See figures 5 and 12
ns
CS assertion 2/
CS negation to
RD/ WR negation 2/
Register read timing
CL = 35 pF minimum
See figures 6 and 12
ns
95
35
40
Memory write timing
Address propagation
delay
Address valid to RCS ,
RWR assertion 6/
ta
CL = 35 pF minimum
See figures 7 and 12
tb
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
H
SHEET
7
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Device
type
Test conditions 1/
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Unit
Limits
Min
Max
Memory write timing – Continued
DTACK setup time 6/
tc
RCS and RWR hold
time 6/ 9/
td
Data propagation delay
6/
CL = 35 pF minimum
See figures 7 and 12
ns
All
9, 10, 11
10
All
9, 10, 11
20
50
te
All
9, 10, 11
20
60
Address hold time 6/
tg
All
9, 10, 11
10
30
DTACK hold time 6/
th
All
9, 10, 11
10
RWR and RCS pulse
ti
01, 02
04
9, 10, 11
34
03
9, 10, 11
32
tj
All
9, 10, 11
15
125
Data hold time 2/
tk
All
9, 10, 11
10
40
Address propagation
delay
ta
01, 02
04
03
9, 10, 11
0
18
9, 10, 11
0
21
tb
All
9, 10, 11
15
35
DTACK setup time 6/
tc
All
9, 10, 11
10
RCS and RRD hold
time 6/ 9/
td
All
9, 10, 11
20
Data setup delay 6/
te
01, 02
04
03
9, 10, 11
12
9, 10, 11
10
Data hold delay
tf
01, 02
04
03
9, 10, 11
0
9, 10, 11
2
DTACK hold time
tg
th
All
All
9, 10, 11
9, 10, 11
10
10
RRD and RCS pulse
ti
01, 02
04
9, 10, 11
34
03
9, 10, 11
32
All
9, 10, 11
15
width ( DTACK tied to
ground)
RWR and RCS ↑ to
DMACK ↑
2/ 9/
Memory read timing
Address valid to RCS ,
CL = 35 pF minimum
See figures 8 and 12
ns
RRD assertion 6/
Address hold time 6/
width ( DTACK tied to
ground)
RRD and RCS ↑ to
DMACK ↑
tj
50
30
45
2/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
H
SHEET
8
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Unit
Limits
Min
Max
DMA timing
TERACT assertion to
DMAR assertion 2/
ta
DMAR assertion to
DMACK negation 2/
tb
CL = 35 pF minimum
See figures 9 and 12
µs
All
9, 10, 11
01
02, 03
04
9, 10, 11
9, 10, 11
7
16
Remote terminal
All
9, 10, 11
7
Remote terminal
with monitor
All
9, 10, 11
7
All
01, 02
04
9, 10, 11
9, 10, 11
0
7
30
03
All
9, 10, 11
9, 10, 11
5
0
30
35
0
5
5
Bus controller
Monitor
5
DMAG assertion to
DMACK assertion 6/
tc
DMAG assertion to
DMAR negation 2/
td
DMACK assertion to
address bus active
te
01, 02
04
03
9, 10, 11
9, 10, 11
-5
DMACK assertion to
DMAG negation 6/
tf
All
9, 10, 11
10
DMACK negation to
DMAG assertion 2/
tg
All
9, 10, 11
500
DMACK assertion to
RAM control active
(negated)
th
01, 02
04
03
9, 10, 11
0
5
-5
5
DMACK negation to
address three-state 2/
ti
All
9, 10, 11
5
DMACK assertion to
RAM control disabled
2/
tj
All
9, 10, 11
5
ns
Power-up master reset timing
MRST pulse width 2/
ta
All
9, 10, 11
MRST negation to
ROMEN assertion 2/
tb
All
9, 10, 11
5
µs
MRST negation to
tc
All
9, 10, 11
10
µs
td
All
9, 10, 11
500
ns
CL = 35 pF minimum
See figures 10 and 12
500
ns
READY assertion 2/
DMACK negation to
ROMEN negation 2/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
H
SHEET
9
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Unit
Limits
Min
Max
Biphase timing
Biphase output skew
ta
Biphase input skew
(low to high) 2/
tb
Biphase input skew
(high to low) 2/
Biphase input pulse
width 2/
CL = 35 pF minimum
See figures 11 and 12
All
9, 10, 11
10
All
9, 10, 11
250
tc
All
9, 10, 11
250
td
All
9, 10, 11
ns
250
JTAG timing
See figure 13
TCK frequency
All
9, 10, 11
TCK period
ta
All
9, 10, 11
1000
1
TCK high time
tb
All
9, 10, 11
1/2ta
TCK low time
tc
All
9, 10, 11
1/2ta
TCK rise time
td
All
9, 10, 11
5
TCK fall time
te
All
9, 10, 11
5
TDI, TMS setup time
tf
All
9, 10, 11
250
TDI, TMS hold time
tg
All
9, 10, 11
250
TDO valid delay
th
All
9, 10, 11
250
MHz
ns
1/
Device type 02 supplied to this drawing will meet all levels M, D, L, R, F, G and H of irradiation. However, this device is
only tested at the 'H' level. Device type 04 supplied to this drawing will meet levels R and F of irradiation and will only be
tested at the levels suplied. Pre and Post irradiation values are identical unless otherwise specified in table IA. When
performing post irradiation electrical measurements for any RHA level, TA = +25°C. Unless otherwise specified, all testing
shall be conducted under worst-case conditions. "GND" may not vary from 0 V dc by more than ±50 mV.
2/
This parameter is guaranteed, but not tested, to the values in table IA herein.
3/
Tested one output at a time for a maximum duration of 1 second.
4/
Device type 02 post irradiation limit is 1 mA for subgroup 1. Device type 04 post irradiation limit is 1 mA irradiation level
R and 5 mA irradiation level F for subgroup 1.
5/
Tested with all inputs tied to VDD.
6/
For device type 03, this parameter is guaranteed, but not tested, to the values in table IA herein.
7/
Minimum pulse width from latter rising edge of RD/ WR or CS to first falling edge.
8/
Read cycle followed by a read cycle - minimum 45 ns.
Read cycle followed by a write cycle - minimum 45 ns.
Write cycle followed by a read cycle - minimum 85 ns.
Write cycle followed by a write cycle - minimum 85 ns.
9/
Pulse width duration is measured with respect to the device's recognition of DTACK assertion.
STANDARD
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APR 97
SIZE
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REVISION LEVEL
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SHEET
10
TABLE IB. SEP test limits. 1/
Device
type
TA =
Temperature
±10°C
02
04
1/
2/
3/
4/
VDD = 4.5 V
Bias for
latch-up test
VDD = 5.5 V
no latch-up
LET = 4/
Effective LET
no upsets
[MeV/(mg/cm2)]
Maximum device
cross section
LET 3/
+25°C
= 47
1.6 x 10-3 cm2
> 136
+25°C
< 14.4
1.5 x 10-4 cm2
> 128
For SEP test conditions, see 4.4.4.4.
Technology characterization and model verfication supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
LET = 136 for device type 02 and LET = 128 for device type 04.
Test at worst case temperature TA = +125°C.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
2/
SIZE
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REVISION LEVEL
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SHEET
11
Case Y
FIGURE 1. Case outline.
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Case Y
Millimeters
Inches
Symbol
Min
Nom
A
Max
Min
Nom
Max
3.30
0.130
A1
2.03
2.74
0.080
0.108
b
.36
.46
0.014
0.018
C
.15
.20
0.006
0.008
e
1.27
0.50
D/E
28.91
29.52
1.138
1.162
HD/HE
45.59
46.36
1.795
1.825
L
.66
0.026
S1
.13
0.005
N
84
84
FIGURE 1. Case outline - Continued.
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Case Z
FIGURE 1. Case outline - Continued.
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COLUMBUS, OHIO 43216-5000
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REVISION LEVEL
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14
Device
type
All
Case
outline
X
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
A1
RRD
B11
ROMEN
F9
VDD
K2
TIMERONA
A2
A0
C1
D15
F10
VSS
K3
TA
A3
A1
C2
TCLK
F11
DMACK
K4
RA
A4
A3
C5
24 MHz
G1
D8
K5
TB
A5
A6
C6
VDD
G2
D7
K6
TB
A6
A4
C7
A9
G3
D6
K7
READY
A7
A7
C10
CS
G9
TDO
K8
RTA3
A8
A10
C11
AUTOEN
G10
TDI
K9
RTA0
A9
A12
D1
D13
G11
TMS
K10
LOCK
A10
A13
D2
D14
H1
D5
K11
MSEL1
A11
RD/ WR
D10
YF_ INT
H2
D4
L1
D0
B1
DTACK
D11
MSG_INT
H10
MRST
L2
TA
B2
RCS
E1
D10
H11
TRST
L3
RA
B3
RWR
E2
D11
J1
D3
L4
TIMERONB
B4
A2
E3
VDD
J2
D1
L5
RB
B5
A5
E9
TCK
J5
RB
L6
VDD
B6
VSS
E10
DMAG
J6
VSS
L7
TERACT
B7
A8
E11
DMAR
J7
SSYSF
L8
RTA4
B8
A11
F1
D9
J10
A/ B STD
L9
RTA2
B9
A14
F2
D12
J11
MSEL0
L10
RTA1
B10
A15
F3
VSS
K1
D2
L11
RTPTY
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
E
SHEET
15
Device
type
All
Case
outline
Y
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
RCS
22
TIMERONA
43
LOCK
64
A15
2
TCLK
23
TA
44
A/ B STD
65
A14
3
DTACK
24
TA
45
MSEL1
66
A13
4
D15
25
RA
46
MSEL0
67
A12
5
D14
26
RA
47
MRST
68
A11
6
D13
27
TIMERONB
48
TRST
69
A10
7
D12
28
TB
49
TDO
70
A9
8
D11
29
TB
50
TDI
71
A8
9
D10
30
RB
51
TMS
72
A7
10
D9
31
VSS
52
VSS
73
VDD
11
VSS
32
VDD
53
VDD
74
VSS
12
VDD
33
RB
54
TCK
75
24 MHz
13
D8
34
TERACT
55
DMAR
76
A6
14
D7
35
READY
56
DMAG
77
A5
15
D6
36
SSYSF
57
DMACK
78
A4
16
D5
37
RTA4
58
MSG_INT
79
A3
17
D4
38
RTA3
59
YF_ INT
80
A2
18
D3
39
RTA2
60
AUTOEN
81
A1
19
D2
40
RTA1
61
ROMEN
82
A0
20
D1
41
RTA0
62
CS
83
RWR
21
D0
42
RTPTY
63
RD/ WR
84
RRD
FIGURE 2. Terminal connections - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
E
SHEET
16
Device
type
All
Case
outline
Z
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
VSS
28
NC
55
NC
82
VSS
109
A9
2
RCS
29
NC
56
NC
83
VDD
110
A8
3
TCLK
30
D2
57
SSYSF
84
TCK
111
NC
4
DTACK
31
D1
58
RTA4
85
DMAR
112
NC
5
NC
32
D0
59
RTA3
86
DMAG
113
NC
6
NC
33
VSS
60
RTA2
87
NC
114
A7
7
D15
34
VDD
61
NC
88
NC
115
VDD
8
D14
35
TIMERONA
62
NC
89
NC
116
VSS
9
D13
36
TA
63
RTA1
90
DMACK
117
24 MHz
10
D12
37
TA
64
RTA0
91
MSG_INT
118
A6
11
D11
38
RA
65
RTPTY
92
YF_ INT
119
A5
12
NC
39
NC
66
VDD
93
AUTOEN
120
NC
13
NC
40
NC
67
VSS
94
NC
121
NC
14
NC
41
RA
68
LOCK
95
NC
122
NC
15
D10
42
TIMERONB
69
A/ B STD
96
ROMEN
123
A4
16
VSS
43
TB
70
NC
97
CS
124
A3
17
VDD
44
TB
71
NC
98
RD/ WR
125
A2
18
D9
45
NC
72
NC
99
VSS
126
A1
19
D8
46
NC
73
MSEL1
100
VDD
127
NC
20
D7
47
NC
74
MSEL0
101
A15
128
NC
21
NC
48
RB
75
MRST
102
A14
129
A0
22
NC
49
VSS
76
NC
103
A13
130
RWR
23
NC
50
VDD
77
NC
104
NC
131
RRD
24
D6
51
RB
78
TRST
105
NC
132
VDD
25
D5
52
TERACT
79
TDO
106
A12
26
D4
53
READY
80
TDI
107
A11
27
D3
54
NC
81
TMS
108
A10
NC = No connection
FIGURE 2. Terminal connections - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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SHEET
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FIGURE 3. Block diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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Device types 02 and 04
Instruction name
Instruction code
BYPASS
1111
SAMPLE/PRELOAD
0010
EXTEST
0000
INTEST
0001
RUNBIST
0111
IDCODE
0100
GL-TRISTATE
0011
INTERNAL-SCAN
0101
PRIVATE
0110
USER-SELECTABLE
1000 → 1110
Device type 03
Instruction name
Instruction code
BYPASS
1111
SAMPLE/PRELOAD
0010
EXTEST
0000
FIGURE 4. Boundary scan instruction codes.
STANDARD
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FIGURE 5. Register write.
FIGURE 6. Register read.
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NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 7. Memory write.
NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 8. Memory read.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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DSCC FORM 2234
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SHEET
21
FIGURE 9. DMA timing.
FIGURE 10. Power-up master reset.
STANDARD
MICROCIRCUIT DRAWING
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FIGURE 11. Biphase timing.
NOTES: V switch = (VOLmax + VOLmin)/2
CL = 35 pF
FIGURE 12. AC test circuit.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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FIGURE 13. JTAG timing waveforms.
Case
outline
Open
VDD = 5 V ± 0.5 V
Ground
X
A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, B1, B2, B3,
B4, B5, B7, B8, B9, B10, B11, C1, C7, D1, D2, D10,
D11, E1, E2, E11, F1, F2, F11, G1, G2, G3, G9, H1,
H2, J1, J2, K1, K2, K3, K5, K6, K7, L1, L2, L4, L7
A11, C2, C6, C11,
E3, E9, F9, G10,
H10, J5, K4, K9,
K10, K11, L6, L8, L9
B6, C5, C10, E10, F3,
F10, G11, H11, J6,
J7, J10, J11, K8, L3,
L5, L10, L11
Y
1, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18, 19, 20,
21, 22, 23, 24, 27, 28, 29, 34, 35, 49, 55, 57, 58, 59,
61, 64, 65, 66, 67, 68, 69, 70, 71, 72, 76, 77, 78, 79,
80, 81, 82, 83, 84
2, 12, 26, 32, 33, 37,
39, 41, 43, 45, 47,
50, 53, 54, 60, 63, 73
11, 25, 30, 31, 36, 38,
40, 42, 44, 46, 48, 51,
52, 56, 62, 74, 75
Z
2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 18, 19, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 35, 36,
37, 39, 40, 42, 43, 44, 45, 46, 47, 52, 53, 54, 55, 56,
61, 62, 70, 71, 72, 76, 77, 79, 85, 87, 88, 89, 90, 91,
92, 94, 95, 96, 101, 102, 103, 104, 105, 106, 107, 108,
109, 110, 111, 112, 113, 114, 118, 119, 120, 121, 122,
123, 124, 125, 126, 127, 128, 129, 130, 131
3, 17, 34, 41, 50, 51,
58, 60, 64, 66, 68,
73, 75, 80, 83, 84,
93, 98, 100, 115, 132
1, 16, 33, 38, 48, 49,
57, 59, 63, 65, 67, 69,
74, 78, 81, 82, 86, 97,
99, 116, 117
NOTE: Each pin except B6, C6, E3, F3, F9, F10, J6, and L6 for case outline X (11, 12, 31, 32, 52, 53, 73, and 74 for
case outline Y; and 1, 16, 17, 33, 34, 49, 50, 66, 67, 82, 83, 99, 100, 115, 116, and 132 for case outline Z) will
have a resistor of 2.49 kΩ ± 5% for irradiation testing.
FIGURE 14. Radiation exposure connections.
STANDARD
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
b.
Burn-in test, method 1015 of MIL-STD-883.
(1)
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015.
(2)
TA = +125°C, minimum.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained
under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in test method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E
inspections (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been
fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein).
c.
Subgroup 4 (CIN, COUT, and CI/O measurements) shall be measured only for the initial test and after process or design
changes which may affect input capacitance. A minimum sample of 5 devices with zero failures shall be required.
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
---
1
1
Final electrical
parameters (see 4.2)
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 2/ 3/
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
1, 2, 3
Group D end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
1, 2, 3
Group E end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
1, 2, 3
Group A test
requirements (see 4.4)
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
3/ Delta limits, as specified in table IIB herein, shall be required when specified and the delta values shall be
completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Parameter
Symbol
Delta limits
Quiescent current
QIDD
±10% of measured values or
35 µA whichever is greater
NOTE: If the device is tested at or below 35 µA, no deltas are required.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB
in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test
circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point
electrical parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater
than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the
pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after
any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test
method 1020 of MIL-STD-883 and as specified herein (See 1.4). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may effect the RHA capability of the
process.
4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of
MIL-STD-883 and herein (see 1.4).
a.
Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b.
Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.4). SEP testing shall be
performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at
initial qualification and after any design or process changes which may affect the upset or latchup characteristics. The
recommended test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° ≤
angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be ≥ 100 errors or ≥ 106 ions/cm2.
c.
The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be ≥ 20 microns in silicon.
e.
The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
Test four devices with zero failures.
2
5
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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of
users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone
(614) 692-0674.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535, MIL-HDBK-1331, and table III herein.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a.
RHA upset levels.
b.
Test conditions (SEP).
c.
Number of upsets (SEP).
d.
Number of transients (SEP).
e.
Occurrence of latchup (SEP).
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TABLE III. Pin descriptions.
Name
Type 1/
Active 2/
Description
Data bus
D0
TTB
--
Bit 0 (LSB) of the bidirectional Data bus.
D1
TTB
--
Bit 1 of the bidirectional Data bus.
D2
TTB
--
Bit 2 of the bidirectional Data bus.
D3
TTB
--
Bit 3 of the bidirectional Data bus.
D4
TTB
--
Bit 4 of the bidirectional Data bus.
D5
TTB
--
Bit 5 of the bidirectional Data bus.
D6
TTB
--
Bit 6 of the bidirectional Data bus.
D7
TTB
--
Bit 7 of the bidirectional Data bus.
D8
TTB
--
Bit 8 of the bidirectional Data bus.
D9
TTB
--
Bit 9 of the bidirectional Data bus.
D10
TTB
--
Bit 10 of the bidirectional Data bus.
D11
TTB
--
Bit 11 of the bidirectional Data bus.
D12
TTB
--
Bit 12 of the bidirectional Data bus.
D13
TTB
--
Bit 13 of the bidirectional Data bus.
D14
TTB
--
Bit 14 of the bidirectional Data bus.
D15
TTB
--
Bit 15 (MSB) of the bidirectional Data bus.
Address bus
A0
TTB
--
Bit 0 (LSB) of the bidirectional Address bus.
A1
TTB
--
Bit 1 of the bidirectional Address bus.
A2
TTB
--
Bit 2 of the bidirectional Address bus.
A3
TTB
--
Bit 3 of the bidirectional Address bus.
A4
TTB
--
Bit 4 of the bidirectional Address bus.
A5
TTB
--
Bit 5 of the bidirectional Address bus.
A6
TTB
--
Bit 6 of the bidirectional Address bus.
A7
TTB
--
Bit 7 of the bidirectional Address bus.
A8
TTB
--
Bit 8 of the bidirectional Address bus.
A9
TTB
--
Bit 9 of the bidirectional Address bus.
A10
TTB
--
Bit 10 of the bidirectional Address bus.
A11
TTB
--
Bit 11 of the bidirectional Address bus.
A12
TTB
--
Bit 12 of the bidirectional Address bus.
A13
TTB
--
Bit 13 of the bidirectional Address bus.
A14
TTB
--
Bit 14 of the bidirectional Address bus.
A15
TTB
--
Bit 15 (MSB) of the bidirectional Address bus.
See footnotes at end of table.
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TABLE III. Pin descriptions - Continued.
Name
Type 1/
Active 2/
Description
Remote terminal address inputs
RTA0
TUI
--
Remote Terminal Address bit 0. This is bit 0 of the RT address. This is the least
significant bit for the RT address.
RTA1
TUI
--
Remote Terminal Address bit 1. This is bit 1 of the RT address.
RTA2
TUI
--
Remote Terminal Address bit 2. This is bit 2 of the RT address.
RTA3
TUI
--
Remote Terminal Address bit 3. This is bit 3 of the RT address.
RTA4
TUI
--
Remote Terminal Address bit 4. This is the most significant bit of the RT address.
RTPTY
TUI
--
Remote Terminal Parity. This is an odd parity input for the RT address.
TDO
TTO
--
TDO. This output performs the operation of Test Data Output as defined in the IEEE
Standard 1149.1. This cell provides the output signal for the Test Access Port (TAP).
This noninverfting output buffer is optimized for driving TTL loads.
TCK
TUI
--
TCK. This input performs the operation of Test Clock input as defined in the IEEE
Standard 1149.1. This noninverting input buffer is optimized for driving TTL input
levels.
TMS
TUI
--
TMS. This input performs the operation of Test Mode Select as defined in the IEEE
Standard 1149.1. This cell provides the input signal for the Test Access Port (TAP).
This noninverting input buffer is optimized for driving TTL input levels.
TDI
TUI
--
TDI. This input performs the operation of Test Data In as defined in the IEEE Standard
1149.1. This cell provides the input signal for the Test Access Port (TAP). This
noninverting input buffer is optimized for driving TTL input levels.
TRST
TUI
--
TRST . This input provides the reset to the TAP controller as defined in the IEEE
Standard 1149.1. This non-inverting input buffer is optimized for driving TTL input
JTAG testability pins
levels. When not exercising JTAG, tie TRST to a logical 0.
Biphase inputs
RA
TI
--
Receive Channel A (true). This is the Manchester-encoded true signal input for channel
A. (Quiescent low).
RA
TI
--
Receive Channel A (complement). This is the Manchester-encoded complement signal
input for channel A. (Quiescent low).
RB
TI
--
Receive Channel B (true). This is the Manchester-encoded true signal input for channel
B. (Quiescent low).
RB
TI
--
Receive Channel B (complement). This is the Manchester-encoded complement signal
input for channel B. (Quiescent low).
Biphase outputs
TA
TO
--
Transmit Channel A (true). This is the Manchester-encoded true signal output for
channel A. The signal is idle low. (Quiescent low).
TA
TO
--
Transmit Channel A (complement). This is the Manchester-encoded complement
signal output for channel A. The signal is idle low. (Quiescent low).
TB
TO
--
Transmit Channel B (true). This is the Manchester-encoded true signal output for
channel B. The signal is idle low. (Quiescent low).
TB
TO
--
Transmit Channel B (complement). This is the Manchester-encoded complement
signal output for channel B. The signal is idle low. (Quiescent low).
See footnotes at end of table.
STANDARD
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TABLE III. Pin descriptions - Continued.
Name
Type 1/
Active 2/
Description
DMA signals
DMAR
TTO 3/
AL
DMA Request. This signal is asserted when access to RAM is required. It goes
inactive upon receipt of the DMAG signal.
DMAG
TI
AL
DMA Grant. Once this input is received, the device is allowed to access RAM.
DMACK
TTO 3/
AL
DMA Acknowledge. This signal is asserted by the device to indicate the receipt of
DMAG . The signal remains active until all RAM bus activity is completed.
DTACK
TI
AL
Data Transfer Acknowledge. This pin indicates that a data transfer is to occur and
that the device may complete the memory cycle.
Control signals
RD/ WR
TI
--
Read/Write. This indicates the direction of data flow with respect to the host. A
logic high signal means the host is trying to read data from the device, and a logic
low signal means the host is trying to write data to the device.
CS
TI
AL
Chip Select. This pin selects the device when accessing the internal registers.
RRD
TTO
AL
RAM Read. This signal is generated by the device to read data from RAM.
RWR
TTO
AL
RAM Write. This signal is generated by the device to write data to RAM.
RCS
TTO
AL
RAM Chip Select. This signal is used in conjunction with the RRD / RWR signals to
access RAM.
AUTOEN
TUI
AL
Auto Enable. This pin, when active, enables automatic initialization applications.
ROMEN
TTO 3/
AL
ROM Enable. This pin, when active, enables the ROM for automatic initialization
applications.
SSYSF
TUI
AL
Subsystem Fail. Upon receipt, this signal propagates directly to the RT 1553
Status word.
24 MHz
CI
--
24 MHz Clock. This 24 MHz input clock requires a 50% ±10% duty cycle with an
accuracy of ±0.01%.
MRST
TUI
AL
Master Reset. This input pin resets the internal encoders, decoders, all register,
and associated logic.
TI
--
Mode Select 1. This pin is the most significant bit for the mode select. For proper
mode selection, see below:
MSEL1
MSEL1
MSEL0
TI
--
MSEL0
Mode of Operation
0
0
Bus Controller = SBC
0
1
Remote Terminal = SRT
1
0
Monitor Terminal = SMT
1
1
SMT/SRT
Mode Select 0. This pin is the least significant bit for the mode select. (See
MSEL1 for proper logic states.)
See footnotes at end of table.
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TABLE III. Pin descriptions - Continued.
Name
Type 1/
Active 2/
Description
Control signals - Continued.
TI
--
Timer Clock. This internal timer is a 16-bit counter with a 64 µs resolution when
using the 24 MHz input clock. For different applications, the user may input a
clock (0-60 MHz) to establish the timer resolution. (Duty Cycle = 50% ±10%).
A/ B STD
TUI
--
Military Standard A or B. This pin defines whether the device will be used a
MIL-STD-1553A or 1553B mode of operation.
LOCK
TUI
AL
Lock. This pin, when set active, prevents software changes to both the RT
address, A/ B STD, and mode select.
TCLK
Status signals
TERACT
TO
AL
Terminal Active. This output pin indicates that the terminal is actively processing a
1553 command.
TIMERONA
TO
AL
Timer On A. This is a 800 µs fail-safe transmitter enable timer for channel A. This
ouput is reset on receipt of a new command or after 760 µs.
TIMERONB
TO
AL
Timer On B. This is a 800 µs fail-safe transmitter enable timer for channel B. This
ouput is reset on receipt of a new command or after 760 µs.
MSG_INT
TTO 3/
AL
Message Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse)
upon the occurrence of interrupt events which are enabled.
YF_ INT
TTO 3/
AL
YOU Failed Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse)
upon the occurrence of interrupt events which are enabled.
READY
TO
AL
Ready. This signal indicates the device has completeed initialization or BIT, and
regular execution may begin.
Power/Ground
VDD
--
--
+5 Volt Power (± 10%)
VSS
--
--
Digital ground.
1/ TO = TTL output
TTB = Three-state TTL bidirectional
CI = CMOS input
TUI = TTL input (internally pulled high)
TI = TTL input
TTO = Three-state TTL output
2/ AH = Active high
AL = Active low
3/
High impedance and active low.
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
10. SCOPE
10.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices
using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes
consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or
Identification Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
10.2 PIN. The PIN is as shown in the following example:
5962
H
Federal
stock class
designator
\
92118
RHA
designator
(see 10.2.1)
01
V
Device
type
(see 10.2.2)
Device
class
designator
(see 10.2.3)
/
9
Die
code
(see 10.2.4)
X
Die
detail
(see 10.2.5)
\/
Drawing number
10.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
10.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type 1/
Generic number
01
02
UT69151
UT69151E
03
04
UT69151E
UT69151E
Circuit function
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
MIL-STD-1553 bus controller, remote terminal, monitor interface
MIL-STD-1553 bus controller, remote terminal, monitor interface
radiation hardened
10.2.3 Device class designator.
Device class
Device requirements documentation
Q or V
Certification and qualification to the die requirements of MIL-PRF-38535
10.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline.
10.2.5. Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for
each product and variant supplied to this appendix.
1/
Device types 01and 03 are not available as QML die only.
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
10.2.5.1 Die physical dimensions.
Die type
Figure number
02
04
A-1
B-1
10.2.5.2 Die bonding pad locations and electrical functions.
Die type
Figure number
02
04
A-1
B-1
10.2.5.3 Interface materials.
Die type
Figure number
02
04
A-1
B-1
10.2.5.4 Assembly related information.
Die type
Figure number
02
04
A-1
B-1
10.3. Absolute maximum ratings.
See paragraph 1.3 within the body of this drawing for details.
10.4 Recommended operating conditions.
See paragraph 1.4 within the body of this drawing for details.
20. APPLICABLE DOCUMENTS.
20.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following
specifications, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of
Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein.
SPECIFICATION
MILITARY
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
MILITARY
MIL-STD-883 - Test Methods and Procedures for Microelectronics.
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
HANDBOOK
MILITARY
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD’s).
(Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific
acquisition functions should be obtained from the contracting activity or as directed by the contracting activity).
20.2. Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
30. REQUIREMENTS
30.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
30.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
30.2.1 Die physical dimensions. The die physical dimensions shall be as specified in 10.2.5.1 and on figures A-1 and B-1.
30.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in 10.2.5.2 and on figures A-1 and B-1.
30.2.3 Interface materials. The interface materials for the die shall be as specified in 10.2.5.3 and on figures A-1 and B-1.
30.2.4 Assembly related information. The assembly related information shall be as specified in 10.2.5.4 and figures A-1
and B-1.
30.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
30.4 Electrical test requirements. The test requirements shall include functional and parametric testing sufficient to make
the packaged die capable of meeting the electrical performance requirements in table IA.
30.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in 10.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
30.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
30.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
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APPENDIX A FORMS A PART OF SMD 5962-92118
40. QUALITY ASSURANCE PROVISIONS
40.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not effect the form, fit or function as described herein.
40.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a)
Wafer lot acceptance for Class V product using the criteria defined within MIL-STD-883 test method 5007.
b)
100% wafer probe (see paragraph 30.4).
c)
100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010
or the alternate procedures allowed within MIL-STD-883 test method 5004.
40.3 Conformance inspection
40.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein.
50. Die carrier
50.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
60. NOTES
60.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
60.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614) 692-0674.
60.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within
MIL-PRF-38535 and MIL-STD-1331.
60.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have
agreed to this drawing.
STANDARD
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Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions.
Device type 02
Device type 04
Die physical dimensions
Die size
495 mils x 495 mils
495 mils x 495 mils
17.5 ±1 mils
24.6 ±0.8 mils
Die thickness
Interface materials
Top metallization
Si Al Cu 9 kA –12.5 kA
TiW-AlCu-TiW 6.2 kA -7.6 kA
None: Backgrind
None: Backgrind
Glassivation
Nitride
PSG
Oxide/Nitride
Thickness
9 kA / ±11 kA
9 kA -11 kA
Substrate
Backside metallization
Type
EPI on single crystal silicon
EPI on single crystal silicon
Substrate potential
Tied to VDD
Tied to GND
Special assembly
instructions
None
None
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
37
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
1
2
3
0.2173
0.2110
0.2047
0.2406
0.2406
0.2406
VDD
VSS
No connect
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0.1984
0.1921
0.1858
0.1795
0.1732
0.1669
0.1606
0.1543
0.1480
0.1417
0.1354
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0410
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
RCS
No connect
TCLK
No connect
DTACK
No connect
No connect
D15
No connect
D14
No connect
D13
No connect
VDDQ
VSSQ
VDD
VSS
No connect
D12
No coonect
D11
No connect
No connect
No connect
No connect
No connect
30
31
32
33
34
35
36
37
38
39
40
0.0347
0.0284
0.0221
0.0158
0.0095
0.0031
-0.0032
-0.0095
-0.0158
-0.0221
-0.0284
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
D10
No connect
D9
No connect
VSSQ
VSS
VDD
VDDQ
No connect
D8
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
38
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
-0.0346
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
-0.0724
-0.0787
-0.0850
-0.0913
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
YCENTER
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2173
0.2110
0.2047
0.1984
0.1921
0.1858
0.1795
0.1732
0.1669
0.1606
PAD NAME
D7
No connect
No connect
No connect
No connect
No connect
D6
No connect
D5
No connect
VSS
VDD
VSSQ
VDDQ
No connect
D4
No connect
D3
No connect
No connect
No connect
No connect
No connect
D2
No connect
D1
No connect
D0
VSS
VDD
VSSQ
VDDQ
TIMERONA
No connect
TA
No connect
TA
No connect
RA
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
39
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
81
82
83
84
-0.2349
-0.2349
-0.2349
-0.2349
0.1543
0.1480
0.1417
0.1354
No connect
No connect
RA
No connect
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0409
0.0347
0.0284
0.0221
0.0158
0.0095
0.0032
-0.0032
-0.0095
-0.0158
TIMERONB
No connect
VSS
VDD
VSSQ
VDDQ
No connect
TB
No connect
TB
No connect
No connect
No connect
No connect
No connect
RB
No connect
RB
No connect
VSSQ
VSS
VDD
VDDQ
No connect
109
110
111
112
113
114
115
116
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.0221
-0.0284
-0.0374
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
TERACT
No connect
READY
No connect
No connect
No connect
No connect
No connect
117
118
119
120
-0.2349
-0.2349
-0.2349
-0.2349
-0.0724
-0.0787
-0.0850
-0.0913
SSYSF
No connect
RTA4
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
40
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2173
-0.2110
-0.2047
-0.1984
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2406
-0.2406
-0.2406
-0.2406
VDDQ
VSSQ
VDD
VSS
No connect
RTA3
No connect
RTA2
No connect
No connect
No connect
No connect
No connect
RTA1
No connect
RTA0
No connect
RTPTY
VDDQ
VSSQ
VDD
VSS
LOCK
No connect
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
A/ B STD
No connect
No connect
No connect
No connect
No connect
MSEL1
No connect
MSEL0
No connect
MRST
No connect
VDDQ
VSSQ
VDD
VSS
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
41
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
PAD NAME
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
TRS
TDO
TDI
TMS
TCK
VDDQ
VDD
VSS
VSSQ
No connect
DMAR
No connect
DMAG
No connect
No connect
No connect
No connect
No connect
DMACK
No connect
MSG_INT
No connect
VSS
VDD
VSSQ
VDDQ
No connect
YF_ INT
No connect
AUTOEN
No connect
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
42
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NOTE:
XCENTER
0.1606
0.1669
0.1732
0.1795
0.1858
0.1921
0.1984
0.2047
0.2110
0.2173
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
YCENTER
PAD NAME
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2173
-0.2110
-0.2047
-0.1984
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
No connect
No connect
No connect
ROMEN
No connect
CS
No connect
RD/ WR
VSS
VDD
VSSQ
VDDQ
A15
No connect
A14
No connect
A13
No connect
No connect
No connect
A12
No connect
A11
No connect
A10
No connect
VSS
VDD
VSSQ
VDDQ
No connect
A9
No connect
A8
No connect
No connect
No connect
No connect
No connect
A7
The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
43
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
XCENTER
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
YCENTER
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
0.1606
0.1669
0.1732
0.1795
0.1858
0.1921
0.1984
0.2047
0.2110
0.2173
PAD NAME
No connect
MHz24
No connect
VDDQ
VDD
VSS
VSSQ
No connect
A6
No connect
A5
No connect
No connect
No connect
No connect
No connect
A4
No connect
A3
No connect
VDDQ
VSSQ
VDD
VSS
No connect
A2
No connect
A1
No connect
No connect
No connect
No connect
No connect
A0
No connect
RWR
No connect
RRD
VDDQ
VSSQ
NOTE: The die center is the coordinate origin (0,0).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
H
SHEET
44
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
NOTES:
1. Die bondpad numbers are for reference only.
2. Dimensions are in inches and are basic.
3. Die thickness is 0.0175 ±0.001.
4. Die backside is as lapped.
5. The die center is the coordinate origin (0,0).
6. Backside bias is VDD for device type 02.
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
45
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
1
2
3
0.2173
0.2110
0.2047
0.2406
0.2406
0.2406
VDD
VSS
No connect
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0.1984
0.1921
0.1858
0.1795
0.1732
0.1669
0.1606
0.1543
0.1480
0.1417
0.1354
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0410
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
RCS
No connect
TCLK
No connect
DTACK
No connect
No connect
D15
No connect
D14
No connect
D13
No connect
VDDQ
VSSQ
VDD
VSS
No connect
D12
No coonect
D11
No connect
No connect
No connect
No connect
No connect
30
31
32
33
34
35
36
37
38
39
40
0.0347
0.0284
0.0221
0.0158
0.0095
0.0031
-0.0032
-0.0095
-0.0158
-0.0221
-0.0284
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
D10
No connect
D9
No connect
VSSQ
VSS
VDD
VDDQ
No connect
D8
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
46
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
-0.0346
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
-0.0724
-0.0787
-0.0850
-0.0913
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
YCENTER
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2406
0.2173
0.2110
0.2047
0.1984
0.1921
0.1858
0.1795
0.1732
0.1669
0.1606
PAD NAME
D7
No connect
No connect
No connect
No connect
No connect
D6
No connect
D5
No connect
VSS
VDD
VSSQ
VDDQ
No connect
D4
No connect
D3
No connect
No connect
No connect
No connect
No connect
D2
No connect
D1
No connect
D0
VSS
VDD
VSSQ
VDDQ
TIMERONA
No connect
TA
No connect
TA
No connect
RA
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
47
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
81
82
83
84
-0.2349
-0.2349
-0.2349
-0.2349
0.1543
0.1480
0.1417
0.1354
No connect
No connect
RA
No connect
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
0.1291
0.1228
0.1165
0.1102
0.1039
0.0976
0.0913
0.0850
0.0787
0.0724
0.0661
0.0598
0.0535
0.0472
0.0409
0.0347
0.0284
0.0221
0.0158
0.0095
0.0032
-0.0032
-0.0095
-0.0158
TIMERONB
No connect
VSS
VDD
VSSQ
VDDQ
No connect
TB
No connect
TB
No connect
No connect
No connect
No connect
No connect
RB
No connect
RB
No connect
VSSQ
VSS
VDD
VDDQ
No connect
109
110
111
112
113
114
115
116
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.0221
-0.0284
-0.0374
-0.0409
-0.0472
-0.0535
-0.0598
-0.0661
TERACT
No connect
READY
No connect
No connect
No connect
No connect
No connect
117
118
119
120
-0.2349
-0.2349
-0.2349
-0.2349
-0.0724
-0.0787
-0.0850
-0.0913
SSYSF
No connect
RTA4
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
48
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
PAD NAME
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2349
-0.2173
-0.2110
-0.2047
-0.1984
-0.0976
-0.1039
-0.1102
-0.1165
-0.1228
-0.1291
-0.1354
-0.1417
-0.1480
-0.1543
-0.1606
-0.1669
-0.1732
-0.1795
-0.1858
-0.1921
-0.1984
-0.2047
-0.2110
-0.2173
-0.2406
-0.2406
-0.2406
-0.2406
VDDQ
VSSQ
VDD
VSS
No connect
RTA3
No connect
RTA2
No connect
No connect
No connect
No connect
No connect
RTA1
No connect
RTA0
No connect
RTPTY
VDDQ
VSSQ
VDD
VSS
LOCK
No connect
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
A/ B STD
No connect
No connect
No connect
No connect
No connect
MSEL1
No connect
MSEL0
No connect
MRST
No connect
VDDQ
VSSQ
VDD
VSS
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
49
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
XCENTER
YCENTER
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
PAD NAME
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
TRS
TDO
TDI
TMS
TCK
VDDQ
VDD
VSS
VSSQ
No connect
DMAR
No connect
DMAG
No connect
No connect
No connect
No connect
No connect
DMACK
No connect
MSG_INT
No connect
VSS
VDD
VSSQ
VDDQ
No connect
YF_ INT
No connect
AUTOEN
No connect
No connect
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
50
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NOTE:
XCENTER
0.1606
0.1669
0.1732
0.1795
0.1858
0.1921
0.1984
0.2047
0.2110
0.2173
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
YCENTER
PAD NAME
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2406
-0.2173
-0.2110
-0.2047
-0.1984
-0.1921
-0.1858
-0.1795
-0.1732
-0.1669
-0.1606
-0.1543
-0.1480
-0.1417
-0.1354
-0.1291
-0.1228
-0.1165
-0.1102
-0.1039
-0.0976
-0.0913
-0.0850
-0.0787
-0.0724
-0.0661
-0.0598
-0.0535
-0.0472
-0.0409
-0.0347
No connect
No connect
No connect
ROMEN
No connect
CS
No connect
RD/ WR
VSS
VDD
VSSQ
VDDQ
A15
No connect
A14
No connect
A13
No connect
No connect
No connect
A12
No connect
A11
No connect
A10
No connect
VSS
VDD
VSSQ
VDDQ
No connect
A9
No connect
A8
No connect
No connect
No connect
No connect
No connect
A7
The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
51
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
Die bonding pad locations and electrical functions
PAD
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
XCENTER
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
0.2349
YCENTER
-0.0284
-0.0221
-0.0158
-0.0095
-0.0032
0.0032
0.0095
0.0158
0.0221
0.0284
0.0347
0.0409
0.0472
0.0535
0.0598
0.0661
0.0724
0.0787
0.0850
0.0913
0.0976
0.1039
0.1102
0.1165
0.1228
0.1291
0.1354
0.1417
0.1480
0.1543
0.1606
0.1669
0.1732
0.1795
0.1858
0.1921
0.1984
0.2047
0.2110
0.2173
PAD NAME
No connect
MHz24
No connect
VDDQ
VDD
VSS
VSSQ
No connect
A6
No connect
A5
No connect
No connect
No connect
No connect
No connect
A4
No connect
A3
No connect
VDDQ
VSSQ
VDD
VSS
No connect
A2
No connect
A1
No connect
No connect
No connect
No connect
No connect
A0
No connect
RWR
No connect
RRD
VDDQ
VSSQ
NOTE: The die center is the coordinate origin (0,0).
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
52
Appendix A
APPENDIX A FORMS A PART OF SMD 5962-92118
NOTES:
1. Die bondpad numbers are for reference only.
2. Dimensions are in inches and are basic.
3. Die thickness is 0.0175 ±0.001.
4. Die backside is as lapped.
5. The die center is the coordinate origin (0,0).
6. Backside bias is GND for device type 04.
FIGURE B-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-92118
A
REVISION LEVEL
J
SHEET
53
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 01-03-15
Approved sources of supply for SMD 5962-92118 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
5962-9211801MXA
3/
5962-9211801MXC
3/
5962-9211801MYA
3/
5962-9211801MYC
3/
5962H9211802QXA
3/
5962H9211802QXC
3/
5962H9211802QYA
3/
5962H9211802QYC
3/
5962H9211802QZA
3/
5962H9211802QZC
3/
5962H9211802VXA
3/
5962H9211802VXC
3/
5962H9211802VYA
3/
5962H9211802VYC
3/
5962H9211802VZA
3/
5962H9211802VZC
3/
5962H9211802Q9A
3/
5962H9211802V9A
3/
5962-9211803QXA
65342
UT69151EGCA
5962-9211803QXC
65342
UT69151EGCC
5962-9211803QYA
65342
UT69151EWCA
5962-9211803QYC
65342
UT69151EWCC
See footnotes at end of table.
Vendor
similar
PIN 2/
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9211803QZA
65342
UT69151EFCA
5962-9211803QZC
65342
UT69151EFCC
5962R9211804QYA
65342
UT69151EWCAR
5962R9211804QYC
65342
UT69151EWCCR
5962R9211804VYA
65342
UT69151EWCAR
5962R9211804VYC
65342
UT69151EWCCR
5962R9211804Q9B
65342
UT69151EQ-DIER
5962R9211804V9B
65342
UT69151EV-DIER
5962F9211804QYA
65342
UT69151EWCAF
5962F9211804QYC
65342
UT69151EWCCF
5962F9211804VYA
65342
UT69151EWCAF
5962F9211804VYC
65342
UT69151EWCCF
5962F9211804Q9B
65342
UT69151EQ-DIEF
5962F9211804V9B
65342
UT69151EV-DIEF
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ No longer available from an approved source of supply.
Vendor CAGE
number
65342
Vendor name
and address
UTMC Microelectronics System Inc.
4350 Centennial Boulevard
Colorado Springs, Colorado 80907-3486
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.