R2J20601NP Driver – MOS FET Integrated SiP (DrMOS) REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Description The R2J20601NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the package standard “Driver – MOS FET integrated SiP (DrMOS)” proposed by Intel Corporation. Features • • • • • • • • • • • • Built-in power MOS FET suitable for applications with 12 V input and low output voltage Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers VIN operating-voltage range: 16 V max High-frequency operation (above 1 MHz) possible Large average output current (35 A) Achieve low power dissipation (About 5.6 W at 1 MHz, 25 A) Controllable driver: Remote on/off Built-in Schottky diode for bootstrapping Low-side drive voltage can be independently set Small package: QFN56 (8 mm × 8 mm × 0.8 mm) Pb-free Outline VCIN BOOT GH VIN 1 14 56 15 Driver Tab Reg5V DISBL# MOS FET Driver High-side MOS Tab VSWH Low-side MOS Tab PWM 43 CGND VLDRV GL REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 1 of 13 PGND 28 42 29 (Bottom view) QFN56 package 8 mm × 8 mm R2J20601NP Block Diagram VCIN Reg5V UVL BOOT GH SBD 5 V Gen. DISBL# Driver chip VIN 2 µA High-side MOS FET CGND Level shifter VSWH VCIN Input logic (TTL level) (3 state in) PWM Overlap protection Low-side MOS FET PGND CGND VLDRV Notes: 1. Truth table for the DISBL# pin. DISBL# Input “L” “Open” “H” Driver Chip Status Shutdown (GL, GH = “L”) Shutdown (GL, GH = “L”) Enable (GL, GH = “Active”) 2. Output signal from the UVL block "H" For activation UVL Output Logic Level For shutdown "L" VL REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 2 of 13 VH VCIN GL R2J20601NP VIN VIN VIN VIN VIN VIN VIN GH CGND BOOT VCIN VLDRV NC CGND Pin Arrangement 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VIN 15 56 PWM VIN 16 55 DISBL# VIN 17 54 Reg5V VIN 18 53 NC VIN 19 52 GL VIN 20 51 CGND VSWH 21 50 VSWH PGND 22 49 VSWH PGND 23 48 VSWH PGND 24 47 VSWH PGND 25 46 VSWH PGND 26 45 VSWH PGND 27 44 VSWH PGND 28 43 VSWH VIN CGND 32 33 34 35 36 37 38 39 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND 40 41 42 VSWH 31 VSWH 30 VSWH 29 PGND VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name CGND NC VLDRV Pin No. 1, 6, 51, Tab 2, 53 3 Description Control signal ground No connect Low side gate supply voltage VCIN BOOT GH VIN VSWH 4 5 7 8 to 20, Tab 21, 40 to 50, Tab Control input voltage (+12 V input) Bootstrap voltage pin High side gate signal Input voltage Phase output/Switch output PGND GL Reg5V DISBL# PWM 22 to 39 52 54 55 56 Power ground Low side gate signal +5 V logic power supply output Signal disable PWM drive logic input REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 3 of 13 Remarks Should be connected to PGND externally For 5 V to 12 V gate drive voltage for Low side gate driver Driver Vcc input To be supplied +5 V through internal SBD Pin for Monitor Pin for Monitor Disabled when DISBL# is “L” R2J20601NP Absolute Maximum Ratings (Ta = 25°C) Item BOOT voltage DISBL# voltage PWM voltage Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN (DC) VCIN (AC) VLDRV (DC) VLDRV (AC) VSWH (DC) VSWH (AC) VBOOT Vdisble Vpwm Reg5V current Operating junction temperature Ireg5V Tj-opr Rating 25 8 35 –0.3 to +16 20 –0.3 to +16 20 –0.3 to +16 20 16 20 22 –0.3 to VCIN –0.3 to +5.3 –0.3 to +0.3 –10 to +0.1 –40 to +150 Storage temperature Tstg –55 to +150 Power dissipation Average output current Input voltage Supply voltage Low side driver voltage Switch node voltage Notes: 1. 2. 3. 4. 5. 6. Units W W A V °C Notes 1 1 2 2, 6 2 2, 6 2 2, 6 2 2, 6 2 2 2, 4 2, 5 3 V V V V V V V mA °C Pt(25) represents a PCB temperature of 25°C, and Pt(100) represents 100°C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). The specification values indicated “AC” are limited within 100 ns. Safe Operating Area 40 Condition VOUT = 1.3 V VIN = 12 V VLDRV = 5 V VCIN = 12 V L = 0.45 µH fPWM = 1 MHz Average Output Current (A) 35 30 25 20 15 10 5 0 0 25 50 75 100 PCB Temperature (°C) REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 4 of 13 125 150 175 R2J20601NP Electrical Characteristics (Ta = 25°C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified) Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN bias current Symbol VH VL dUVL ICIN Min 8.1 6.5 — 10.5 Typ 9.0 7.2 1.8 *1 14.0 Max 9.9 7.9 — 18.5 Units V V V mA VLDRV bias current ILDRV 31.5 40.7 46.5 mA PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window VH-PWM VL-PWM RIN-PWM VIN-SD 3.5 0.9 30 4.1 1.5 70 5V Regulator Shutdown hold-off time Output voltage Line regulation tHOLD-OFF Vreg Vreg-line VL-PWM — 4.75 –10 3.8 1.2 50 — 240 *1 5.0 0 VH-PWM — 5.25 10 V V kΩ V ns V mV Vreg-load VDISBL VENBL –10 0.9 1.9 0 1.2 2.4 10 1.5 2.9 mV V V Ireg = 0 to 10 mA DISBL# Input Load regulation Disable threshold Enable threshold Input current IDISBL 0.5 2.0 5.0 µA DISBL# = 1 V Supply PWM Input Note: 1. Reference values for design. Not 100% tested in production. REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 5 of 13 Test Conditions VH – VL fPWM = 1 MHz, ton-PWM = 125 ns fPWM = 1 MHz, ton-PWM = 125 ns PWM = 1 V VCIN = 12 V to 16 V R2J20601NP Typical Application +12 V +5 V to 12 V +12 V VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20601NP PWM PGND CGND GH GL VCIN VLDRV BOOT DISBL# VIN VSWH Reg5V R2J20601NP PGND PWM PWM1 CGND GH GL PWM PWM2 control circuit PWM3 PWM4 +1.3 V VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20601NP PGND PWM CGND GH GL VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20601NP PGND PWM CGND REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 6 of 13 GH GL Signal Power GND GND R2J20601NP Test Circuit VB VLDRV VCIN A A A IIN ILDRV V VIN ICIN VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20601NP 5 V pulse PGND PWM CGND GH Electric load IO GL Averaging Average Output Voltage V VO circuit Note: PIN = IIN × VIN + ILDRV × VLDRV + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 7 of 13 R2J20601NP Typical Data Power Loss vs. Input Voltage Power Loss vs. Output Current 9 10 VIN = 12 V 8 VCIN = 12 V VLDRV = 5 V fPWM = 1 MHz Power Loss (W) Power Loss (W) 7 VOUT = 1.3 V 6 L = 0.45 µH 5 4 3 VCIN = 12 V VLDRV = 5 V 9 VOUT = 1.3 V fPWM = 1 MHz L = 0.45 µH 8 7 6 2 5 1 0 0 5 10 15 20 25 4 30 Iout = 25 A Iout = 30 A 5 6 8 9 10 11 12 13 14 15 16 Input Voltage Vin (V) Output Current (A) Power Loss vs. Switching Frequency Power Loss vs. Output Voltage 10 11 VIN = 12 V 10 VCIN = 12 V VLDRV = 5 V VOUT = 1.3 V Power Loss (W) 9 Power Loss (W) 7 8 VIN = 12 V VCIN = 12 V 7 VLDRV = 5 V fPWM = 1 MHz L = 0.45 µH 6 9 L = 0.45 µH 8 7 6 5 5 4 0.8 Iout = 25 A Iout = 30 A 1.2 1.6 2.0 2.4 2.8 Output Voltage Vout (V) REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 8 of 13 3.2 3.6 4 3 250 Iout = 25 A Iout = 30 A 500 750 1000 1250 Switching Frequency (kHz) 1500 R2J20601NP Typical Data (cont.) Power Loss vs. Output Inductance Power Loss vs. VLDRV 10 10 Power Loss (W) Power Loss (W) 9 8 VIN = 12 V VCIN = 12 V 7 VLDRV = 5 V VOUT = 1.3 V fPWM = 1 MHz 6 5 VIN = 12 V VCIN = 12 V 9 VOUT = 1.3 V fPWM = 1 MHz L = 0.45 µH 8 7 6 5 Iout = 25 A Iout = 30 A 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 4 Iout = 25 A Iout = 30 A 5 6 7 8 Output Inductance (µH) VLDRV (V) Average ICIN vs. Switching Frequency Average ILDRV vs. Switching Frequency 25 VIN = 12 V VCIN = 12 V VOUT = 1.3 V 160 IOUT = 0 L = 0.45 µH Average ICIN (mA) Average ILDRV (mA) 200 120 80 40 0 250 VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V 500 9 10 11 12 13 14 15 16 750 1000 1250 Switching Frequency (kHz) REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 9 of 13 1500 VIN = 12 V VCIN = 12 V VOUT = 1.3 V 20 IOUT = 0 L = 0.45 µH 15 10 5 0 250 VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V 500 750 1000 1250 Switching Frequency (kHz) 1500 R2J20601NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. Driver The driver has two types of power-supply voltage input pin, VCIN and VLDRV. VCIN supplies the operating voltage to the internal logic circuit. The low-side driving voltage is applied to VLDRV, so setting of the gate-driving voltage for the low-side MOS FET is independent of the voltage on VCIN. The VLDRV setting voltage is from 5 V to 16 V. The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 9 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 7.2 V or less. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit , the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled. VCIN L H H H VLDRV >5 V >5 V >5 V >5 V DISBL# ∗ L H Open Reg5V 0 5V 5V 5V Driver state Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. The built-in 5 V regulator is a series regulator with temperature compensation. The voltage output by this regulator determines the operating voltage of the internal logic and gate-voltage swing for the high-side MOS FET. A ceramic capacitor with a value of 0.1 µF or more must be connected between the CGND plane and the Reg5V pin. The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (Reg5V + 3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 10 of 13 R2J20601NP The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.8 V or more is required to make the circuit return to normal operation. 240 ns(tHOLD-OFF) PWM 240 ns(tHOLD-OFF) 3.8 V 1.2 V GH GL 240 ns(tHOLD-OFF) PWM 3.8 V 1.2 V GH GL Figure 1 REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 11 of 13 240 ns(tHOLD-OFF) R2J20601NP The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 240 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. From this circuit configuration, we can see that the voltage on the PWM pin when open-circuit will be about 2.5 V, so the tri-state protection function will operate. Reg5V M1 50 k PWM pin Tri-state detection signal Input logic 50 k To internal control Figure 2 Equivalent Circuit for the PWM-pin Input For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so VBOOT is boosted to VSWH + 5 V. The GH and GL pins are the gate-monitor pins for each MOS FET. MOS FETs The MOS FETs incorporated in R2J20601NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 12 of 13 R2J20601NP Package Dimensions Previous Code TNP-56TV D B MASS[Typ.] 0.17g 0.85 A 42 29 0.55 2.20 28 0.85 42 43 28 Reference Symbol C 2.25 0.55 E e 43 3.55 29 0.85 RENESAS Code PWQN0056KA-A 3.50 JEITA Package Code P-HWQFN56-8x8-0.50 4 0. 15 14 1 t 56 14 1 b C ×M C A B 0.85 15 Lp 56 Nom Max D 7.90 8.00 8.10 E 7.90 8.00 8.10 A2 A A C 0 b 0.18 0.05 0.23 C ( Ni/Pd/Au plating ) e 0.50 0.30 0.40 0.50 x 0.10 y 0.08 y1 0.10 t 0.15 HE ZD ZE c c1 REJ03G0237-0700 Rev.7.00 Jun 30, 2008 Page 13 of 13 0.28 b1 HD A1 c y 0.80 A1 Lp y1 C Dimension in Millimeters Min 0.20 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2