Using SourceSynchronous Signaling with DPA in Stratix GX Devices January 2003, ver. 1.1 Application Note 236 Introduction Expansion in the telecommunications market and growth in Internet use requires systems to move more data faster than ever. To meet this demand, system designers rely on solutions such as differential signaling and emerging high-speed interface standards including RapidIO, POS-PHY 4, SFI-4, or XSBI. Preliminary Information These new protocols support differential data rates up to 1 gigabit per second (Gbps) and higher. At these high data rates, it becomes more challenging to manage the skew between the clock and data signals. One solution to this challenge is to use clock data recovery (CDR) to eliminate skew between data channels and clock signals. Another potential solution, dynamic phase alignment (DPA), is beginning to be incorporated by some of these protocols. The StratixTM GX family of devices are the first FPGA devices to have an embedded dynamic phase aligner. This application note explains how to take advantage of the DPA feature in device high-speed I/O circuitry to increase system efficiencies and bandwidth. It will describe the skew issue in high-speed systems and provide a brief description of the sourcesynchronous circuitry in Stratix GX devices. The document will then describe an overview of the DPA block, I/O support with DPA, fast PLL support with DPA, a full description of DPA operation, and finally a comparison between CDR and source-synchronous interfaces. The source-synchronous high-speed interface in Stratix GX devices is a dedicated circuit embedded into the programmable logic device (PLD) allowing for high-speed communications. AN 202: Using High-Speed Differential I/O Standards in Stratix Devices provides information on Stratix GX device high-speed I/O standard features and functions. Skew & Dynamic Phase Alignment Altera Corporation AN-236-1.1 A typical problem designers face with high-speed source-synchronous systems is when clock or data signal transitions occur at different times with respect to each other (see Figure 1). When this happens, the receiver does not sample the data at the correct time, causing system errors. This problem is due to the inherent skew of the transmitter device, varying trace lengths and capacitive loading, variations in threshold voltages, transmission-line mis-terminations, or system reconfigurations. This results in inaccurate data transmission from one point to another and interrupted communication between components within the system. 1 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information A dynamic clock-data synchronization or phase alignment solution is optimal for high-speed systems because it provides a better tolerance to signal noise without the higher power consumption of devices which correct for skew using an individual analog PLL for each receiver channel. The dynamic phase aligner in Stratix GX devices shares the same components across many receiver channels, therefore reducing power consumption. Figure 1. Clock to Data Skew Clock One Byte Data Channel 1 Data Channel 2 Bit 0 Bit 0 Bit 1 Bit 1 Bit 2 Bit 2 Bit 3 One Byte Bit 4 Bit 3 Bit 4 Bit 5 Bit 5 Bit 6 Bit 6 Bit 7 Bit 7 Channel 0 Dynamic Phase Aligner Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Channel 1 Dynamic Phase Aligner Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 4 Bit 5 Bit 6 Bit 7 One Byte One Byte Skew One Byte Data Channel n Bit 0 Stratix GX I/O Banks 2 Bit 1 Bit 2 Bit 3 One Byte Bit 4 Bit 5 Bit 6 Bit 7 Channel n Dynamic Phase Aligner Bit 0 Bit 1 Bit 2 Bit 3 Stratix GX devices contain seven I/O banks, as shown in Figure 2. I/O banks one and two support high-speed LVDS, LVPECL, 3.3-V PCML, HSTL class I and II, and SSTL-2 class I and II inputs and outputs. These two banks also incorporate an embedded dynamic phase aligner within the source-synchronous interface (see Figure 2). The dynamic phase aligner corrects for the phase difference between the clock and data lines caused by skew. The dynamic phase aligner operates automatically and continuously without requiring a fixed training pattern, and allows the source-synchronous circuitry to capture data correctly regardless of the channel-to-clock skew. Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Figure 2. DPA Support in Stratix GX Devices I/O Bank 3 I/O Banks 1 and 2 Also Support (1): ■ Differential I/O Standards: - True LVDS - LVPECL - 3.3-V PCML - HyperTransport Technology ■ Single-Ended I/O Standards: - 3.3-, 2.5-, 1.8-V LVTTL - GTL+ - CTT - SSTL-2 Class I and II - SSTL-3 Class I and II I/O Bank 2 I/O Bank 4 These I/O Banks Support ■ 3.3-, 2.5-, 1.8-V LVTTL ■ 3.3-V PCI, PCI-X ■ GTL ■ GTL+ ■ AGP ■ CTT ■ SSTL-18 Class I and II ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II ■ HSTL Class I and II I/O Bank 5 Contains Transceiver Blocks I/O Bank 5 I/O Bank 1 Individual Power Bus I/O Bank 7 I/O Bank 6 Note to Figure 2: (1) You can only use the differential receiver and clock input pins as inputs for single-ended standards. Dedicated SourceSynchronous Circuitry Altera Corporation The differential I/O channels in Stratix GX I/O banks 1 and 2 can interface with LVDS, LVPECL, or 3.3-V PCML I/O standards in sourcesynchronous mode. Stratix GX devices transmit or receive serial channels along with clocks. The receiving Stratix GX device can multiply the lowspeed clock by a factor of 1, 2, 4, 8, or 10 for serializer/deserializer (SERDES) operation. The SERDES factor (J) can be 4, 8, or 10 (only 8 or 10 with DPA) and determines the width of the bus driving into the logic array. The SERDES factor (J) does not have to equal the clockmultiplication value (W). The Stratix GX device can bypass the dedicated SERDES for a serialization or deserialization factor of 1 or 2. If the serialization/deserialization factor is 2, the I/O element (IOE) uses the double data rate (DDR) input and output. Table 1 shows the clock multiplication factors and the SERDES factors supported by Stratix GX devices. 3 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Table 1. Clock Multiplication Factors Factor Integer Clock Multiplication W 1, 2, 4, 8, or 10 SERDES J 4, 8, or 10 (1) Note to Table 1: (1) The SERDES factor J can only be 8 or 10 when using DPA. In the receiver circuitry, the fast PLL generates the high-frequency clock to deserialize the serial data through a shift register. The parallel data is synchronized with the low-frequency clock, and the receiver sends both to the logic array. On the transmitter side, the parallel data from the logic array is first fed into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then transmitted out by the output buffers. Figure 3 shows the dedicated receiver and transmitter interface. For more information on the Stratix GX source-synchronous operation, refer to AN 202: Using High-Speed Differential I/O Interfaces in Stratix Devices. Figure 3. Source-Synchronous Differential I/O Receiver/Transmitter Interface Example Receiver Circuit Stratix GX Logic Array Serial Shift Registers 840 Mbps RXIN+ RXIN− PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 ×W RXCLKIN+ RXCLKIN− Fast PLL RXLOADEN Parallel Registers PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 ×W/J Transmitter Circuit R4, R8, and R24 Interconnect Parallel Registers Parallel Register Data 10 10 Local Interconnect ×W/J PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Serial Register TXOUT+ TXOUT− ×W Fast PLL TXLOADEN TXLOADEN The enable signal RXLOADEN loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock in both modes (with or without DPA). Figure 4 shows the clock and data relationship in the receiver. 4 Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Figure 4. Receiver Timing Diagram Internal ×1 clock Internal ×10 clock RXLOADEN Receiver data input n–1 n–0 9 8 7 6 5 4 3 2 1 0 Figure 5 shows the timing relationship between the data and clock in the Stratix GX transmitter in ×10 mode. Figure 5. Transmitter Timing Diagram Internal ×1 clock Internal ×10 clock TXLOADEN Receiver data input DPA Block Overview n–1 n–0 9 8 7 6 5 4 3 2 1 0 Each Stratix GX receiver channel features a DPA block. The block contains a dynamic phase selector for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer shown in Figure 6. The dynamic phase aligner uses both the source clock and the serial data. The dynamic phase aligner automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data. Figure 6 shows the relationship between Stratix GX source-synchronous circuitry and the Stratix GX source-synchronous circuitry with DPA. Altera Corporation 5 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Figure 6. Source-Synchronous DPA Circuitry Receiver Circuit rxin+ rxin- Deserializer Stratix GX Logic Array Dynamic Phase Aligner 8 Deserializer ×W clkrxin+ clkrxin- PLL ×1 Unlike the de-skew function in APEXTM 20KE and APEX 20KC devices or the clock-data synchronization (CDS) circuit in APEX II devices, you do not have to use a fixed training pattern with DPA in Stratix GX devices or assert a pin to activate the circuit. Table 2 shows the differences between source-synchronous circuitry with DPA and source-synchronous circuitry without DPA circuitry in Stratix GX devices. Table 2. Source-Synchronous Circuitry with & without DPA Feature Data rate Deserialization factors 6 Source-Synchronous Circuitry Without DPA With DPA 300 to 840 Megabits per second (Mbps) 415 Mbps to 1 Gbps 1, 2, 4, 8, 10 8, 10 Clock frequency 33 to 644.5 MHz 77.75 to 644.5 MHz Interface pins I/O banks 1 and 2 I/O banks 1 and 2 Receiver pins Dedicated inputs Dedicated inputs Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices DPA Input Support Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to support differential I/O standards at speeds up to 1 Gbps with DPA (or up to 840 Mbps without DPA). Stratix GX device source-synchronous circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards. Additionally, the clock input pins in I/O banks 1 and 2 support differential HSTL. Table 3 shows the I/O standards that the dynamic phase aligner supports and their corresponding supply voltage. See AN 202: Using High-Speed Differential I/O Interfaces in Stratix Devices for more information on these I/O standards. All Stratix GX device differential receiver input pins and clock pins in I/O banks 1 and 2 are dedicated input pins for differential I/O standards, but can be either input or output pins for single-ended I/O standards. Transmitter pins can be either input or output pins for both differential and single-ended I/O standards. See Table 4. Table 3. DPA Differential I/O Standards I/O Standard VCC I/O (V) LVDS, LVPECL, 3.3-V PCML 3.3 Differential HSTL 1.5 Table 4. Bank 1 & 2 Input Pins Input Pin Type Differential Single ended I/O Standard Receiver Pin Transmitter Pin Differential Input only Input or output Single ended Input or output Input or output Single ended Input or output Input or output Interface & Fast PLL This section describes the number of channels that support DPA and their relationship with the PLL in Stratix GX devices. EP1SGX10 and EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices have four dedicated fast PLLs for clock multiplication. Table 5 shows the maximum number of channels in each Stratix GX device that support DPA. Altera Corporation 7 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Table 5. Stratix GX Source-Synchronous Differential I/O Resources Device Fast PLLs Pin Count Receiver Channels (1) Transmitter Receiver & Channels Transmitter Channel (1) Speed (Gbps) (2) EP1SGX10C 2 (3) 672 22 EP1SGX10D 2 (3) 672 22 22 1 10,570 EP1SGX25C 2 672 39 39 1 25,660 EP1SGX25D 2 25,660 22 1 LEs 10,570 672 39 39 1 1,020 39 39 1 25,660 EP1SGX25F 2 1,020 39 39 1 25,660 EP1SGX40D 4 (4) 1,020 45 45 1 41,250 EP1SGX40G 4 (4) 1,020 45 45 1 41,250 Notes to Table 5: (1) (2) (3) (4) This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of the device. Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps. One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA. Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA The receiver and transmitter channels are interleaved so that each I/O row in I/O banks 1 and 2 of the device has one receiver channel and one transmitter channel per row. Figures 7 and 8 show the fast PLL and channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40 devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations. 8 Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Figure 7. PLL & Channel Layout in EP1SGX10 & EP1SGX25 Devices 1 RX 1 TX 11 Rows for EP1SGX10 Devices & 19 Rows for EP1SGX25 Devices 8 1 TX 1 RX INCLK0 Fast PLL 1 (1) INCLK1 Fast PLL 2 Eight-Phase Clock Eight-Phase Clock 1 RX 1 TX 8 11 Rows for EP1SGX10 Devices & 20 Rows for EP1SGX25 Devices 1 TX 1 RX Note to Figure 7: (1) Altera Corporation Fast PLL 1 in EP1SGX10 devices does not support DPA. 9 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Figure 8. PLL & Channel Layout in EP1SGX40 Devices CLKIN PLL (1) 1 RX 1 TX 22 Rows 8 1 TX 1 RX INCLK0 Fast PLL 1 INCLK1 Fast PLL 2 Eight-Phase Clock Eight-Phase Clock 1 RX 1 TX 8 23 Rows 1 TX 1 RX CLKIN PLL (1) Note to Figure 8: (1) 10 Corner PLLs do not support DPA. Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices DPA Operation The DPA receiver circuitry contains the dynamic phase selector, the deserializer, the synchronizer, and the data realigner (see Figure 9). This section describes the DPA operation, synchronization and data realignment. You can enable or disable DPA operation on a channel-tochannel basis. In the SERDES with DPA mode, the source clock is fed to the fast PLL through the dedicated clock input pins. This clock is multiplied by the multiplication value W to match the serial data rate. For information on the deserializer, see “Dedicated Source-Synchronous Circuitry” on page 3. Figure 9. DPA Receiver Circuit DPA Receiver Circuit Dynamic Phase Selector rxin+ rxin- Stratix GX Logic Array Serial Data (1) Deserializer 10 Synchronizer 10 Data Realigner Parallel Clock ×W Clock (1) 8 inclk+ inclk - Fast PLL GCLK ×1 Clock RCLK Reset Note to Figure 9: (1) These are phase-matched and retimed high-speed clocks and data. The dynamic phase selector matches the phase of the high-speed clock and data before sending them to the deserializer. The fast PLL supplies eight phases of the same clock (each a separate tap from a four-stage differential voltage-controlled oscillator (VCO)) to all the differential channels associated with the selected fast PLL. The DPA circuitry inside each channel locks to a phase closest to the serial data's phase and sends the retimed data and the selected clock to the deserializer. Each channel's DPA circuit can independently choose a different clock phase. The data phase detection and the clock phase selection process is automatic and continuous. The eight phases of clock gives the DPA circuit a granularity of one eighth of the unit interval (UI) or 125 ps at 1 Gbps. Figure 10 illustrates the clocks generated by the fast PLL circuitry and their relationship to a data stream. Altera Corporation 11 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Figure 10. Fast PLL Clocks & Data Input Data input D0 D1 D2 D3 D4 D5 Dn Clock A Clock B Clock C Clock D Clock A' Clock B' Clock C' Clock D' Protocols, Training Pattern & DPA Lock Time The dynamic phase aligner uses a fast PLL for clock multiplication, and the dynamic phase selector for the phase detection and alignment. The dynamic phase aligner uses the high-speed clock out of the dynamic phase selector to deserialize high-speed data and the receiver’s source synchronous operations. At each rising edge of the clock, the dynamic phase selector determines the phase difference between the clock and the data and automatically compensates for the phase difference between the data and clock. The actual lock time for different data patterns varies depending on the data’s transition density (how often the data switches between 1 and 0) and jitter characteristic. The DPA circuitry is designed to lock onto any data pattern with sufficient transition density, so the circuitry will work with current and future protocols. Experiments and simulations show that the DPA circuitry locks when the data patterns listed in Table 6 are repeated for the specified number of times. There are other suitable patterns not shown in Table 6 and/or pattern lengths, but the lock time may vary. The circuit can adjust for any phase variation that may occur during operation. 12 Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices If the dynamic phase selector loses lock, the DPA circuitry sends a loss-oflock signal for each channel to the logic array. You can then pull the dynamic phase selector RESET signal low to reset the dynamic phase selector. You can also reset the DPA operation by asserting the DPA RESET node. Table 6. Training Patterns for Different Protocols Protocols Training Pattern Number of Repetitions 256 SPI-4, NPSI Ten 0’s, ten 1’s (00000000001111111111) RapidIO Four 0’s, four 1’s (00001111) or one 1, two 0’s, one 1, four 0’s (10010000) Other designs Eight alternating 1’s and 0’s (10101010 or 01010101) SFI-4, XSBI Not specified Phase Synchronizer Each receiver has its own dynamic phase synchronizer. The receiver dynamic phase synchronizer aligns the phase of the parallel data from all the receivers to one global clock. The synchronizers in each channel consist of a first-in first-out (FIFO) buffer clocked by the global clock (GCLK) and parallel clock. The global clock (GCLK) and parallel clock input into the synchronizers must have identical frequency and differ only in phase. Therefore, the operation does not require an empty/full flag or read/write enable signals. The dynamic phase selector aligns each data signal with one of the eight phases of the global clock, so each signal has the same frequencies. Each synchronizer is written with a different clock phase, depending on the phase of the received data. The global clock reads all synchronizers, so all data is the same phase for use in the logic array. Receiver Data Realignment In DPA Mode While DPA operation aligns the incoming clock phase to the incoming data phase, it does not guarantee the parallelization boundary or byte boundary. When the dynamic phase aligner realigns the data bits, the bits may be shifted out of byte alignment, as shown in Figure 11. Altera Corporation 13 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Figure 11. Misaligned Captured Bits Correct Alignment 0 1 2 3 4 5 6 7 6 7 0 1 2 Incorrect Alignment 3 4 5 The dynamic phase selector and synchronizer align the clock and data based on the power-up of both communicating devices, and the channel to channel skew. However, the dynamic phase selector and synchronizer cannot determine the byte boundary, and the data may need to be bytealigned. The dynamic phase aligner’s data realignment circuitry shifts data bits to correct bit misalignments. The Stratix GX circuitry contains a data-realignment feature controlled by the logic array. Stratix GX devices perform data realignment on the parallel data after the deserialization block. The data realignment can be performed per channel for more flexibility. The data alignment operation requires a state machine to recognize a specific pattern. The procedure requires the bits to be slipped on the data stream to correctly align the incoming data to the start of the byte boundary. The DPA uses its realignment circuitry and the global clock for data realignment. Either a device pin or the logic array asserts the internal rx_channel_data_align node to activate the DPA data-realignment circuitry. Switching this node from low to high activates the realignment circuitry and the data being transferred to the logic array is shifted by one bit. A state machine and additional logic can monitor the incoming parallel data and compare it against a known pattern. If the incoming data pattern does not match the known pattern, you can activate the rx_channel_data_align node again. Repeat this process until the realigner detects the desired match between the known data pattern and incoming parallel data pattern. 14 Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices The DPA data-realignment circuitry allows further realignment beyond what the J multiplication factor allows. You can set the J multiplication factor to be 8 or 10. However, since data must be continuously clocked in on each low-speed clock cycle, the upcoming bit to be realigned and previous n − 1 bits of data will be selected each time the data realignment logic’s counter passes n − 1. At this point the data is selected entirely from bit-slip register 3 (see Figure 12) as the counter is reset to 0. The logic array receives a new valid byte of data on the next divided low speed clock cycle. Figure 12 shows the data realignment logic output selection from data in the data realignment register 2 and data realignment register 3 based on its current counter value upon continuous request of data slipping from the logic array. Figure 12. DPA Data Realigner Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 D19 D9 D29 D19 D99 D89 D119 D99 D129 D119 D18 D8 D28 D18 D98 D18 D118 D98 D128 D118 D17 D7 D27 D17 D97 D87 D117 D97 D127 D117 D16 D6 D26 D16 D96 D86 D116 D96 D162 D116 D15 D5 D25 D15 D95 D85 D115 D95 D125 D115 D14 D4 D24 D14 D94 D84 D114 D94 D124 D114 D13 D3 D23 D13 D93 D83 D113 D93 D123 D113 D12 D2 D22 D12 D92 D82 D112 D92 D122 D112 D11 D1 D21 D11 D91 D81 D111 D91 D121 D111 D10 D0 D20 D10 D90 D80 D110 D90 D120 D110 One bit slipped Zero bits slipped. Counter = 0 D10 is the upcoming bit to be slipped. One bit slipped. Counter = 1 D21 is the upcoming bit to be slipped. Seven more bits slipped Eight bits slipped. Counter = 8 D98 is the upcoming bit to be slipped. One more bit slipped Nine bits slipped. Counter = 9 D119 is the upcoming bit to be slipped. One more bit slipped 10 bits slipped. Counter = 0 Real data will resume on the next byte. Use the rx_channel_data_align signal within the device to activate the data realigner. You can use internal logic or an external pin to control the rx_channel_data_align signal. To ensure the rising edge of the rx_channel_data_align signal is latched into the control logic, the rx_channel_data_align signal should stay high for at least two lowfrequency clock cycles. Figure 13 shows the timing diagram of the DPA circuit. The byte boundary of the data is shifted by one bit on each risingedge of the rx_channel_data_align signal. Thus one bit will be lost every time the data is slipped. Altera Corporation 15 16 Bit5 Byte1 Byte2 Bit2 Byte0 Bit1 Byte1 Bit0 RXPDAT3 Bit7 To logic array Bit6 Byte3 Byte3 Bit4 Byte2 Bit3 Byte 3 RXPDAT2 RXPDAT1 rx_channel_data_align Global divided clock DPA clock after alignment Retimed data Clock before alignment Byte4 Bit4 Byte 4 Bit3 Bit5 Bit6 Bit7 Bit0 Bit2 Byte2 Byte3 Byte4 Bit1 Byte5 Bit4 Byte 5 Bit3 Bit5 Bit6 Bit7 Bit0 Bit2 Byte3 Byte4 Byte5 Bit1 Byte6 Bit4 Byte 6 Bit3 Bit5 Bit6 Bit7 Bit0 Bit2 Byte4 Byte5 Byte6 Bit1 Byte7 Bit4 Byte 7 Bit3 Bit5 Bit6 Bit7 Byte6 Byte8 Bit2 Byte7 Bit1 One Bit Realigned Here Byte6[0] Byte5[7..1] Bit0 Bit3 Bit4 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Preliminary Information Figure 13. Data Realignment to Clock Timing Relationship Altera Corporation Preliminary Information AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices In order to manage the alignment procedure, a state machine should be built in the FPGA logic array to generate the realignment signal. The following guidelines outline the requirements for this state machine. ■ ■ ■ ■ ■ The design must include an input synchronizing register to ensure that data is synchronized to the ×W/J clock. After the state machine, use another synchronizing register to capture the generated rx_channel_data_align signal and synchronize it to the ×W/J clock. Since the skew in the path from the output of this synchronizing register to the PLL is undefined, the state machine must generate a pulse that is high for one ×W/J clock period. Since the rx_channel_data_align generator circuitry only generates a single fast clock period pulse for each rx_channel_data_align pulse, you cannot generate additional rx_channel_data_align pulses until the signal comparing the incoming data to the alignment pattern is reset low. To guarantee the state machine does not incorrectly generate multiple rx_channel_data_align pulses to shift a single bit, the state machine must hold the rx_channel_data_align signal low for at least three ×1 clock periods between pulses. SourceSynchronous Circuitry with DPA vs. CDR The DPA feature and source-synchronous channels are complementary features within Stratix GX devices to be used with high-speed transceiver blocks. The channels on the transceiver side of the device use an embedded circuit dedicated for receiving and transmitting serial data streams to and from the system board at frequencies up to 3.125 Gbps. These channels are clustered in serial transceiver blocks that contain four channels each and handle complex encoding and decoding schemes. If your system requires more than 20 high-speed channels, can not use complex encoding and decoding schemes, or has a maximum data rate of 1.0 Gbps or below, you can use the channels in I/O banks 1 and 2 to implement a source-synchronous interface with DPA. However, DPA requires that the same clock drive all clock and data channels. Summary DPA technology eliminates the restriction of phase-matching the serial data and the source clock at the receiver channels. As a result, DPA eliminates tight board routing and topology restrictions, simplifies channel-to-channel skew calculation, and improves system performance. The combination of DPA technology with 3.125-Gbps transceivers allows Stratix GX devices to address a variety of applications and to effectively implement silicon bridges between protocols. Altera Corporation 17 AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices Revision History Preliminary Information The information contained in AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices supersedes information published in previous versions. Version 1.1 The following changes were made to AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices version 2.2: ■ 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: [email protected] 18 Updated Figures 4 and 5. Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. 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