2015.02.04 AN731 SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Subscribe Send Feedback Simultaneous Switching Noise (SSN) Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input Cyclone III and Cyclone IV devices provide an external clock input option for the global clock network. The input clock can be differential or single-ended. The advantages of a differential clock over a single-ended clock scheme are: • The differential clock is more immune to the common-mode noise, SSN and ground bounce • The differential clock is more robust for changing reference or discontinuity For the single-ended clock input option, SSN can impact the clock input, even if the clock frequency is low frequency below 100 MHz. As shown in Figure 1, when the multi-aggressor input or output signals toggle simultaneously in one bank, large SSN is induced, that degrades power and ground integrity. When the input clock it is degraded by SSN, it can cause the PLL to lose lock, and cause the counter to malfunc‐ tion. To limit SSN and crosstalk, you must restrict the number of switching outputs in a single bank. If the single-ended clock input is close to the potential crosstalk aggressor signal, it may also result in crosstalk that can cause a glitch in the victim single-ended clock signal. Cyclone III and Cyclone IV devices are designed with wire-bond packages. The inductive coupling between adjacent pins of a wire-bonded package can result in a higher noise. The package inductance of a two-layer wire-bond package is much higher compared to that of a 4-layer package, because it does not have a good reference plane. © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. 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Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2 AN731 2015.02.04 SSN Guidelines for External Clock Inputs Figure 1: Example of a Single-ended Clock Input If possible use differential external clock input scheme (LVDS). Board Package Cyclone III & Cyclone IV PLL Powers Original Differential CLK Pair Divider PLL Single-Ended CLK In SSN Coupling Counter Out PLL_LOCK SE CLK Out Error Counter Out PLL_LOCK SE CLK Out Crosstalk Locked PLL Unlock Clock Frequency Change VCCIO Possible Aggressor Inputs (Noise Source) Possible Aggressor Outputs (Noise Source) 1 Bank SSN SSN SSN SSN SSN Guidelines for External Clock Inputs Victim Clock Pin Assignments Assignments for pins adjacent to the clock input pin affect SSN. You can assign the ground to the balls surrounding the victim clock input signals to reduce the impact of SSN as shown in Figure 2. SSN is directly proportional to the mutual inductance of the ground path. You can reduce the effect of SSN by assigning all of the ground balls surrounding the single-ended clock, as shown in Figure 2(a). If you cannot assign all of the ground balls, then you must try to have a minimum of four ground balls around the single-ended clock path as shown in Figure 2 (b). The ground balls decrease the mutual inductance of the victim single-ended clock and block crosstalk from adjacent potential aggressor I/O signals. It is recommended that you do not assign any other clock signal or normal I/O signal on the original differential clock pair. This signal can cause large coupling noise on the single-ended clock input signal. Altera Corporation SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback AN731 2015.02.04 External Single-ended Clock Input SSN Requirements 3 Figure 2: Single-ended Clock Input Ground Balls surrounding Victim Clock Input Signals (a) (b) GND GND GND DQ GND DQ GND Single Clock GND GND Single Clock GND GND GND GND DQ GND DQ External Single-ended Clock Input SSN Requirements You can assign ground on the original differential clock pair, when you use the external clock input as a single-ended clock. As shown in the following figure, the differential signal pair in the package, is laid out as differential, with a value of 100 ohms. It ensures that the original differential clock pair has a strong coupling structure. It is recommended that you do not assign any other clock signal or normal I/O signal on the original differential clock pair, if you assign an external clock input as a single-ended clock. This signal can cause large coupling noise on the single-ended clock input signal. SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback Altera Corporation 4 AN731 2015.02.04 Effects of I/O Termination Figure 3: Package Design Example for a Differential Clock Input Signal Pair Top Layer GND Plane GND GND SE_CLK CLK_n CLK_p Signal GND Vias Signal Bottom Layer GND Plane CLK_n GND CLK_p SE_CLK Signal Signal Effects of I/O Termination Unterminated signals can cause signal reflection. These reflections can manifest themselves as crosstalk noise on the victim clock signal. The reflected waveforms in the multi-aggressor signals will transmit back-and-forth and can cause crosstalk noise on the victim clock input signal and can have an effect on power and ground. As shown in Figure 4, terminating potential aggressor signals appropriately will reduce the possibility of degrading the victim clock signal quality and power and ground noise. In Cyclone III and Cyclone IV devices, signal I/O standard can be selected in terminated or un-terminated mode. Altera Corporation SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback AN731 2015.02.04 Effect of slow Aggressor Signal slew rate on SSN 5 Figure 4: Reflection Due to Matched and Open Termination (a) Waveforms with Matched Termination Waveform at B Waveform at A Vs Zs A Z0 Z0 Matched Termination (No Reflection) (b) Waveforms with Open Termination Reflected Waveform Waveform at C Vs Zs C Waveform at D D Z0 Open Termination (All Reflection) Note: I/O Standards with or without Termination • Terminated I/O standards: SSTL, HSTL • Un-terminated I/O standards: LVTTL, LVCMOS • As per the JEDEC, the LVTTL and LVCMOS, PCI, and PCI-X I/O standards do not specify a recommended termination scheme. Effect of slow Aggressor Signal slew rate on SSN As shown in the following equation, crosstalk is inversely proportional to rise time. This means that there is an increase in crosstalk when the aggressor signal has fast rise and fall time. Figure 6 shows an example of a victim signal that is degraded by crosstalk. In order to decrease SSN due to crosstalk, use the slowest slew rate for potential aggressor signals, especially when multiple I/O signals are switching simultaneously. Figure 5: Crosstalk Equation VFar-End Crosstalk 1 Tr SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback Altera Corporation 6 AN731 2015.02.04 Effect of fast slew rate of Victim Clock on SSN Figure 6: Crosstalk Mechanism 50 Ω A t=0 Aggressor B 50 Ω TD = Time Delay of Line Near End Far End Victim 50 Ω 50 Ω A B Near End Far End Inductive Coupling Is Dominant 0 TD 2TD Effect of fast slew rate of Victim Clock on SSN Crosstalk or SSN on power and ground can induce a glitch or jitter on the victim clock input signal. Increasing the ramp time (V/ns) of the victim clock input signal will mitigate this affect. Fast rise and fall edges reduce the time the clock signal is above VIH and below VIL and can push out the glitch from VIH or VIL zone such that it no longer affects the clock and reset signals. Figure 7: Benefit of Faster Slew Rate on Victim Clock Input Victim Clock Input Glitch Altera Corporation New Edge Rate (Faster) Victim Clock Input Glitch Original Edge Rate (Slower) SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback AN731 2015.02.04 I/O Restriction Guidelines 7 I/O Restriction Guidelines To reduce the impact of SSN due to potential aggressor signals, I/O restrictions are essential to control the number of toggling aggressor signals in the same I/O bank. Table 1, lists the percentages of the total number of I/O pins that can be toggled without inducing any error on the victim single-ended clock under SSN and/or crosstalk condition. Table 1: I/O Restriction Guidelines per Bank The numbers in the following table are based on actual measurements, that were done using an Altera characterization system setup. These measurements may vary based on your system design and the board configuration. As shown below, the crosstalk is the primary cause of attenuation or malfunction of the victim clock input. Percentage of Simultaneous Switching Pins per Bank Aggressor I/O Standards 4-Layer Wire-bonding Package 2-Layer Wire-bonding Package Forward toggling pattern Reverse toggling pattern Forward toggling pattern Reverse toggling pattern 3.0V LVCMOS 16mA (fast slew rate) 13% 95% 5% 5% 2.5V LVTTL 16mA (fast slew rate) 55% 95% 27% 84% 2.5V LVTTL 12mA (fast slew rate) 55% 96% 27% 84% 2.5V LVTTL 4mA 100% 100% 100% 100% 2.5V SSTL 2.5V Class II 16mA (fast slew rate) 100% 100% 100% 100% Following tests are performed to better understand crosstalk and the effect of power and/or ground noise on the victim clock inputs: • Forward toggling pattern test • In this test each aggressor, starting from the closest to the farthest from the victim is switched on one by one, until an error occurs. The main influence of crosstalk on the victim clock input is measured, and the number of switched-on aggressors are noted. • Reverse toggling pattern test • In this test each aggressor, starting from the farthest to the closest from the victim, is switched on one by one, until an error occurs. The primary influence of power and ground noise on the victim clock input is measured, and the number of switched-on aggressors are noted. Reverse toggling pattern test confirms that a 2-layer substrate package is more susceptible to SSN than a 4-layer substrate package. It is difficult to quantify the effect of SSN and crosstalk on the victim clock input separately. SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback Altera Corporation 8 AN731 2015.02.04 Single-ended Clock Input Pad Placement Guideline You can prevent the PLL unlock issue or counter malfunction by using the potential aggressor signals with lower current strength and terminated I/O standard. Single-ended Clock Input Pad Placement Guideline • You can put two single-ended clocks on any of the four dedicated pins. • Asynchronous input or output signals are not allowed on the two left most and right most pins. • If you want to put three or four single-ended clocks on the four dedicated pins. • Check mutual inductance of these pins • Contact Altera mySupport if you can not correlate the pad location and mutual inductance • To avoid crosstalk, do not put the aggressor pin adjacent to the victim clock input pin . • Separate the aggressor pin and the victim pin by two or more pins • You can check the separation in Quartus II Pad Viewer Figure 8: Single-ended Clock Input Pad Placement Guideline Single-ended input or output signals are not allowed on the two left-most and right-most pins to provide a single-ended clock input on the general-purpose pins. 7 8 5 6 X L L X O L Asynchronous I/O signas are not allowed at two pins on the left and two pins on the right. p n Q Two single-ended Clock pins can be located in the four dedicated clock pins. Related Information • • • • Cyclone IV Device Pin Connection Guideline Cyclone III Device Pin Connection Guideline Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines Input Signal Edge Rate Guidance Revision History Date February 2015 Altera Corporation Version 2015.02.04 Changes Initial release SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions Send Feedback