2015.06.09 AN-522 Implementing Bus LVDS Interface in Supported Altera Device Families Subscribe Send Feedback Bus LVDS (BLVDS) extends the capability of LVDS point-to-point communication to multipoint configuration. Multipoint BLVDS offers an efficient solution for multipoint backplane applications. A good multipoint design must consider the capacitive load and termination on the bus to obtain better signal integrity. You can minimize the load capacitance by selecting a transceiver with low pin capacitance, connector with low capacitance, and keeping the stub length short. You can implement the BLVDS interface in supported Altera® device families: • Arria® 10, Arria V, and Arria II devices • Cyclone® V, Cyclone IV, Cyclone III, and Cylone III LS devices • Stratix® V, Stratix IV, and Stratix III devices The programmable features of the drive strength and slew rate options in these devices enable you to customize your multipoint system for maximum performance. To determine the maximum data rate supported, you must perform a simulation or measurement based on your specific system setup and application. You can use the included Cyclone III BLVDS design example to analyze the performance of a multipoint application. The design example is applicable to all supported Altera devices. For Arria 10 devices, you need to migrate the design example to Arria 10 devices first before you can use it. BLVDS Overview Typical multipoint BLVDS system consists of a number of transmitter and receiver pairs (transceivers) that are connected to the bus. Figure 1: Multipoint BLVDS R R T R T R T R T R T T The configuration in the preceding figure provides bidirectional half-duplex communication while minimizing interconnect density. Any transceiver can assume the role of a transmitter, with the © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2 AN-522 2015.06.09 Effective Impedance remaining transceivers acting as receivers (only one transmitter can be active at a time). Bus traffic control, either through a protocol or hardware solution is typically required to avoid driver contention on the bus. The performance of a multipoint BLVDS is greatly affected by the capacitive loading and termination on the bus. One of the multipoint BLVDS design consideration is the effective differential impedance of a fully loaded bus, referred to as effective impedance, and the propagation delay through the bus. Other multipoint BLVDS design considerations include fail-safe biasing, connector type and pin-out, PCB bus trace layout, and driver edge rate specifications. Effective Impedance The effective impedance depends on the bus trace characteristic impedance Zo and capacitive loading on the bus. The connectors, the stub on the plug-in card, the packaging, and the receiver input capacitance all contribute to capacitive loading, which reduces the bus effective impedance. Figure 2: Effective Differential Impedance Equation Use this equation to approximate the effective differential impedance of the loaded bus (Zeff). Where: • • • • • • • Zdiff (Ω) ≈ 2 × Zo = the differential characteristic impedance of the bus Co (pF/inch) = characteristic capacitance per unit length of the bus CL (pF) = capacitance of each load N = number of loads on the bus H (inch) = d × N = total length of the bus d (inch) = spacing between each plug-in card Cd (pF/inch) = CL/d = distributed capacitance per unit length across the bus The increment in load capacitance or closer spacing between the plug-in cards reduces the effective impedance. To optimize the system performance, it is important to select a low capacitance transceiver and connector. Keep each receiver stub length between the connector and transceiver I/O pin as short as possible. Figure 3: Normalized Effective Impedance Versus Cd/Co This figure shows the effects of distributed capacitance on normalized effective impedance. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 3 Propagation Delay 1.1 1.0 0.9 0.8 Zeff / Zdiff 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 10 Cd / Co Termination is required at each end of the bus, while the data flows in both directions. To reduce reflection and ringing on the bus, you must match the termination resistor to the effective impedance. For a system with Cd/Co = 3, the effective impedance is 0.5 times of Zdiff. With double terminations on the bus, the driver sees an equivalent load of 0.25 times of Zdiff; and thus reduces the signals swing and differential noise margin across the receiver inputs (if standard LVDS driver is used). The BLVDS driver addresses this issue by increasing the drive current to achieve similar voltage swing at the receiver inputs. Propagation Delay The propagation delay (tPD = Zo × Co) is the time delay through the transmission line per unit length. It depends on the characteristic impedance and characteristic capacitance of the bus. Figure 4: Effective Propagation Delay For a loaded bus, you can calculate the effective propagation delay with this equation. You can calculate the time for the signal to propagate from driver A to receiver B as the tPDEFF × length of line between driver A and receiver B. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 4 AN-522 2015.06.09 BLVDS Technology in Altera Devices BLVDS Technology in Altera Devices In supported Altera devices, the BLVDS interface is supported in any row or column I/O banks that are powered by a VCCIO of 1.8 V (Arria 10 devices) or 2.5 V (other supported devices). The interface is supported on the differential I/O pins, but not the clock pins in these I/O banks. • The BLVDS transmitter uses two single-ended output buffers with the second output buffer programmed as inverted. • The BLVDS receiver uses a dedicated LVDS input buffer. Figure 5: BLVDS I/O Buffers in the Supported Devices OE Output Data Input Data To device core Output Data Single-ended Output Buffer Near-End Series Termination Diff Input Buffer Bi-directional Pins Single-ended Output OE Buffer (inverted) Different input or output buffers are used depending on the application type: • Multidrop application—the input or output buffer is used, depending on whether the device is intended for driver or receiver operation. • Multipoint application—the output buffer and input buffer shares the same I/O pins. An output enable (oe) signal is required to tri-state the LVDS output buffer when it is not sending signals. • Do not enable the on-chip series termination (RS OCT) for the output buffer. • Use external resistors at the output buffers to provide impedance matching to the stub on the plugin card. • Do not enable the on-chip differential termination (RD OCT) for the differential input buffer because the bus termination is usually implemented using the external termination resistors at both ends of the bus. I/O Standards for BLVDS Interface in Altera Devices You can implement the BLVDS interface using the relevant I/O standards and current strength requirements for the supported Altera devices. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 5 I/O Standards for BLVDS Interface in Altera Devices Table 1: I/O Standard and Features Support for the BLVDS Interface in Supported Altera Devices Devices Cyclone III Cyclone IV Pin DIFFIO I/O Standard BLVDS Differential SSTL-2 Class I V CCIO (V) 2.5 2.5 Current Strength Option Column I/ O Row I/O 8, 10, 12 8, 12 DIFFIO_RX(1) Stratix IV Differential SSTL-2 Class II Arria V Cyclone V DIFFIO_RX(1) Stratix V Arria 10 LVDS Option Setting Quartus II Setting Slow 8, 12 8, 12 Medium (default), (default), 16 16 Fast (default) Arria II Stratix III Slew Rate 2.5 16 16 0 1 2 Slow 0 Medium 1 Medium fast 2 Fast (default) 3 Slow 0 Medium 1 Medium fast 2 Fast (default) 3 Differential SSTL-2 Class I 2.5 8, 10, 12 8, 12 Slow 0 Differential SSTL-2 Class II 2.5 16 16 Fast (default) 1 Differential SSTL-18 Class I 1.8 4, 6, 8, 10, 12 — Slow 0 Differential SSTL-18 Class II 1.8 16 — Fast (default) 1 For more information, refer to the respective device documentation as listed in the related information section: • For pin assignments information, refer to the device pin-out files. • For the I/O standards features, refer to the device handbook I/O chapter. • For the electrical specifications, refer to the device datasheet or DC and switching characteristics document. Related Information • Cyclone V Device Pin-Out Files • Cyclone IV Device Pin-Out Files (1) DIFFIO_TX pin does not support true LVDS differential receivers. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 6 AN-522 2015.06.09 BLVDS Power Consumption • • • • • • • • • • • • • • • • • • • • • • • • • Cyclone III Device Pin-Out Files Arria 10 Device Pin-Out Files Arria V Device Pin-Out Files Arria II GX Device Pin-Out Files Stratix V Pin-Out Files Stratix IV Pin-Out Files Stratix III Device Pin-Out Files I/O Features in Cyclone V Devices I/O Features in Cyclone IV Devices I/O Features in the Cyclone III Device Family I/O and High Speed I/O in Arria 10 Devices I/O Features in Arria V Devices I/O Features in Arria II Devices I/O Features in Stratix V Devices I/O Features in Stratix IV Device Stratix III Device I/O Features Cyclone V Device Datasheet Cyclone IV Device Datasheet Cyclone III Device Datasheet Arria 10 Device Datasheet Arria V Device Datasheet Device Datasheet for Arria II Devices Stratix V Device Datasheet DC and Switching Characteristics for Stratix IV Devices Stratix III Device Datasheet: DC and Switching Characteristics BLVDS Power Consumption In comparison to other high-performance bus technologies such as GTL, which uses more than 40 mA, BLVDS typically drives out current in the range of 10 mA. For example, based on the Cyclone III PowerPlay Early Power Estimator (EPE) estimation for typical power characteristics of Cyclone III devices in an ambient temperature of 25°C, the average power consumption of a BLVDS bidirectional buffer at a data rate of 50 MHz and an output enabled 50% of the time is approximately 17 mW. • Before implementing your design into the device, use the Excel-based EPE for the supported device you use to get an estimated magnitude of the BLVDS I/O power consumption. • For input and bidirectional pins, the BLVDS input buffer is always enabled. The BLVDS input buffer consumes power if there is switching activity on the bus (for example, other transceivers are sending and receiving data, but the Cyclone III device is not the intended recipient). • If you use BLVDS as an input buffer in multidrop or as a bidirectional buffer in multipoint applica‐ tions, Altera recommends entering a toggle rate that includes all activities on the bus, not just activities intended for the Altera device BLVDS input buffer. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Design Example 7 Figure 6: Example of BLVDS I/O Data Entry in the Cyclone III EPE 9.0 SP2 This figure shows the BLVDS I/O entry in the Cyclone III EPE. For Arria II, Arria V, Arria 10, Cyclone V, Stratix III, Stratix IV, and Stratix V devices, select 2.5-V Differential SSTL Class I or Class II under the I/O standard column in the relevant EPE. Altera recommends that you use the Quartus® II PowerPlay Power Analyzer to perform an accurate BLVDS I/O power analysis after you complete your design. The PowerPlay Power Analyzer estimates power based on the specifics of the design after place-and-route is completed. The PowerPlay Power Analyzer applies a combination of user-entered, simulation-derived, and estimated signal activities which, combined with the detailed circuit models, yields very accurate power estimates. Related Information • PowerPlay Power Analysis chapter, Quartus II Handbook Provides more information about the Quartus II PowerPlay Power Analyzer. • PowerPlay Early Power Estimator (EPE) and Power Analyzer page Provides more information about the EPE and the Quartus II PowerPlay Power Analyzer. Design Example The design example shows you how to instantiate the BLVDS I/O buffer in the supported devices with the relevant general purpose I/O (GPIO) IP cores in the Quartus II software. • Arria 10 devices—use the Altera GPIO IP core. • All other supported devices—use the ALTIOBUF IP core. You can download the design example from the link in the related information. For the BLVDS I/O buffer instance, Altera recommends the following items: • Implement the ALTIOBUF IP core in bidirectional mode with the differential mode turned on. • Assign the I/O standard to the bidirectional pins: • Cyclone III and Cyclone IV devices—BLVDS I/O standard. • Arria II, Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V devices—2.5 V Differential SSTL Class I or II I/O standard. • Arria 10—1.8 V Differential SSTL Class I or II I/O standard. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 8 AN-522 2015.06.09 Design Example Guidelines for Arria 10 Devices Table 2: Input or Output Buffers Operation During Write and Read Operations Write Operation (BLVDS I/O Buffer) Read Operation (Differential Input Buffer) • Receive a serial data stream from the • Receive the data from the bus through the p and n bidirec‐ tional pins FPGA core through the doutp input port • Sends the serial data to the FPGA core through the din port • Create an inverted version of the data • Transmit the data through the two single-ended output buffers connected to the p and n bidirec‐ tional pins • The oe port receives the oe signal from the device core to enable or disable the single-ended output buffers. • Keep the oe signal low to tri-state the output buffers during read operation. • The function of the AND gate is to stop the transmitted signal from going back into the device core. The differential input buffer is always enabled. Related Information • Design Examples for AN 522 Provides the Quartus II design examples used in this application note. • I/O Buffer (ALTIOBUF) IP Core User Guide • Altera GPIO IP Core User Guide • Introduction to Altera IP Cores Design Example Guidelines for Arria 10 Devices These steps are applicable to Arria 10 devices only. Ensure that you use the Altera GPIO IP core. 1. Open the StratixV_blvds.qar file to import the Stratix V design example into the Quartus II software. 2. Migrate the design example to use the Altera GPIO IP core: a. On the menu, select Project > Upgrade IP Components. b. Double click the "ALIOBUF" entity. The MegaWizard Plug-In Manager window for the ALTIOBUF IP core appears. c. Turn off Match project/default. d. In Currently selected device family, select Arria 10. e. Click Finish and then click Finish again. f. In the dialog box that appears, click OK. The Quartus II software performs the migration process and then displays the Altera GPIO IP parameter editor. 3. Configure the Altera GPIO IP core to support a bidirectional input and output buffer: a. In Data Direction, select Bidir. b. In Data width, enter 1. c. Turn on Use differential buffer. d. Click Finish and generate the IP core. 4. Connect the modules and the input and output ports as shown in the following figure: Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Design Example Guidelines for All Supported Devices Except Arria 10 9 Figure 7: Input and Output Ports Connection Example for Arria 10 Devices 5. In the Assignment Editor, assign the relevant I/O standard as shown in the following figure according to your device. You can also set the current strength and slew rate options. Otherwise, the Quartus II software assumes the default settings for Arria 10 devices—1.8 V Differential SSTL Class I or II I/O standard. Figure 8: BLVDS I/O Assignment in the Quartus II Assignment Editor for Arria 10 Devices Note: For Arria 10 devices, you can manually assign both the p and n pin locations for LVDS pins with the Assignment Editor. 6. Compile and perform functional simulation with the ModelSim®-Altera software. Related Information ModelSim-Altera Software Support Provides more information about the ModelSim-Altera software and contains various links to topics such as installation, usage, and troubleshooting. Design Example Guidelines for All Supported Devices Except Arria 10 These steps are applicable to all supported devices except Arria 10. Ensure that you use the ALTIOBUF IP core. 1. Create an ALTIOBUF IP core that can support a bidirectional input and output buffer: Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 10 AN-522 2015.06.09 Design Example Guidelines for All Supported Devices Except Arria 10 a. Instantiate the ALTIOBUF IP core. b. Configure the module As a bidirectional buffer. c. In What is the number of buffers to be instantiated, enter 1. d. Turn on Use differential mode. 2. Connect the modules and the input and output ports as shown in the following figure: Figure 9: Input and Output Ports Connection Example for All Supported Devices Except Arria 10 3. In the Assignment Editor, assign the relevant I/O standard as shown in the following figure according to your device. You can also set the current strength and slew rate options. Otherwise, the Quartus II software assumes the default settings. • Cyclone III and Cyclone IV devices—BLVDS I/O standard to the bidirectional p and n pins as shown in the following figure. • Arria II, Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V devices—2.5 V Differential SSTL Class I or II I/O standard. Figure 10: BLVDS I/O Assignment in the Quartus II Assignment Editor Note: You can manually assign both the p and n pin locations for each supported device with the Assignment Editor. The supported devices and the pins you can manually assign are as follows: • Cyclone III, Cyclone IV—DIFFIO • Arria II, Arria V, Cyclone V, Stratix III, Stratix IV, Stratix V—DIFFIO_RX 4. Compile and perform functional simulation with the ModelSim-Altera software. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Performance Analysis 11 Figure 11: Example of Functional Simulation Results When the oe signal is asserted, the BLVDS is in write operation mode. When the oe signal is deasserted, the BLVDS is in read operation mode. Note: For simulation using Verilog HDL, you can use the blvds_tb.v testbench, which is included in the respective design example. Related Information ModelSim-Altera Software Support Provides more information about the ModelSim-Altera software and contains various links to topics such as installation, usage, and troubleshooting. Performance Analysis The multipoint BLVDS performance analysis demonstrates the impact of the bus termination, loading, driver and receiver characteristics, and the location of the receiver from the driver on the system. Note: The performance analysis of a multipoint BLVDS in this section is based on the Cyclone III BLVDS input/output buffer information specification (IBIS) model simulation in HyperLynx. Altera recommends that you use these Altera IBIS models for simulation: • Stratix III, Stratix IV, and Stratix V devices—device-specific 2.5 V Differential SSTL IBIS model • Arria 10(2) devices: • Output buffer—1.8 V Differential SSTL IBIS model • Input buffer—LVDS IBIS model Related Information Altera IBIS Model Provides downloads of Altera device models. (2) The Arria 10 IBIS models are preliminary and are not available on the Altera IBIS model web page. If you require these preliminary Arria 10 IBIS models, contact Altera. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 12 AN-522 2015.06.09 System Setup System Setup Figure 12: Multipoint BLVDS with Cyclone III BLVDS Transceivers This figure shows the schematic of a multipoint topology with ten Cyclone III BLVDS transceivers (named U1 to U10). Vcc Vcc 130 KΩ 130 KΩ 50 Ω 50 50 Ω 50 5050 Ω 5050 Ω RT RT Input data Output data 50 ΩΩ RS GND Input data Cyclone III Device U10 Cyclone III Device OE OE Output data 50 ΩΩ U2 Cyclone III Device U1 RS RS 50 ΩΩ 50 ΩΩ RS RS GND RS 50 ΩΩ 100 KΩ 50 ΩΩ 50 100 KΩ 5050 Ω 50 50 ΩΩ 50 Ω 50 OE 50 ΩΩ Output data Input data The bus transmission line is assumed to have the following characteristics: • • • • • • • A stripline Characteristic impedance of 50 Ω Characteristic capacitance of 3.6 pF per inch Length of 10 inches Bus differential characteristic impedance of approximately 100 Ω Spacing between each transceiver of 1 inch Bus terminated at both ends with termination resistor RT In the example shown in the preceding figure, the fail-safe biasing resistors of 130 kΩ and 100 kΩ pulls the bus to a known state when all the drivers are tri-stated, removed, or powered off. To prevent excessive loading to the driver and waveform distortion, the magnitude of the fail-safe resistors must be one or two orders higher than RT. To prevent a large common-mode shift from occurring between the active and tri-state bus conditions, the mid-point of the fail-safe bias must be close to the offset voltage of the driver (+1.25 V). You can power up the bus with the common power supplies (VCC). Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Bus Termination 13 Cyclone III and Cyclone IV BLVDS transceivers are assumed to have the following characteristics: • • • • Default drive strength of 12 mA Slow slew rate settings by default Pin capacitance of each transceiver of 6 pF Stub on each BLVDS transceiver is a 1 inch microstrip of characteristic impedance of 50 Ω and characteristic capacitance of 3 pF per inch • Capacitance of the connection (connector, pad, and via in PCB) of each transceiver to the bus is assumed to be 2 pF • Total capacitance of each load is approximately 11 pF For 1 inch load spacing, the distributed capacitance is equal to 11 pF per inch. To reduce reflection caused by the stubs, and also to attenuate the signals coming out of the driver, an impedance matching 50 Ω resistor RS is placed at the output of each transceiver. Bus Termination The effective impedance of the fully loaded bus is 52 Ω if you substitute the bus characteristic capacitance and the distributed capacitance per unit length of the setup into the effective differential impedance equation. For optimum signal integrity, you must match RT to 52 Ω. The following figures show the effects of matched-, under-, and over-termination on the differential waveform (VID) at the receiver input pins. The data rate is 100 Mbps. In these figures, under-termination (RT = 25 Ω) results in reflections and significantly reduction of the noise margin. In some cases, under termination even violates the receiver threshold (VTH = ±100 mV). When RT is changed to 50 Ω, there is a substantial noise margin with respect to VTH and the reflection is negligible. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 14 AN-522 2015.06.09 Bus Termination Figure 13: Effect of Bus Termination (Driver in U1, Receiver in U2) In this figure, U1 acts as the transmitter and U2 to U10 are the receivers. RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.6 0.4 VID (V) 0.2 0.0 -0.2 -0.4 -0.6 5 10 15 20 25 30 35 Time (ns) Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Bus Termination 15 Figure 14: Effect of Bus Termination (Driver in U1, Receiver in U10) In this figure, U1 acts as the transmitter and U2 to U10 are the receivers. 0.6 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.4 VID (V) 0.2 0.0 -0.2 -0.4 -0.6 5 10 15 20 25 30 35 Time (ns) Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 16 AN-522 2015.06.09 Bus Termination Figure 15: Effect of Bus Termination (Driver in U5, Receiver in U6) In this figure, U5 is the transmitter and the rest are receivers. 0.6 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.4 VID (V) 0.2 0.0 -0.2 -0.4 -0.6 5 10 15 20 25 30 35 Time (ns) Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Stub Length 17 Figure 16: Effect of Bus Termination (Driver in U5, Receiver in U10) In this figure, U5 is the transmitter and the rest are receivers. 0.6 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.4 VID (V) 0.2 0.0 -0.2 -0.4 -0.6 5 10 15 20 25 30 35 Time (ns) The relative position of the driver and receiver on the bus also affects the received signal quality. The nearest receiver to the driver experiences the worst transmission line effect because at this location, the edge rate is the fastest. This is made worse when the driver is located at the middle of the bus. For example, compare Figure 13 and Figure 15 . VID at receiver U6 (driver at U5) shows larger ringing than that at receiver U2 (driver at U1). On the other hand, the edge rate is slowed down when the receiver is located further away from the driver. The largest rise time recorded is 1.14 ns with the driver located at one end of the bus (U1) and the receiver at the other end (U10). Related Information Effective Impedance on page 2 Stub Length Longer stub length not only increases the flight time from the driver to the receiver, but also results in a larger load capacitance, which causes larger reflection. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 18 AN-522 2015.06.09 Stub Termination Figure 17: Effect of Increasing Stub Length (Driver in U1, Receiver in U10) This figure compares the VID at U10 when the stub length is increased from one inch to two inches and the driver is at U1. 1 inch stub 2 inch stub 0.5 0.4 0.3 0.2 V ID (V) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 Time (ns) Stub Termination You must match the driver impedance to the stub characteristic impedance. Placing a series termination resistor RS at the driver output greatly reduces the adverse transmission line effect caused by long stub and fast edge rates. In addition, RS can be changed to attenuate the VID to meet the specification of the receiver. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Driver Slew Rate 19 Figure 18: Effect of Stub Termination (Driver in U1, Receiver in U2 and U10) This figure compares the VID at U2 and U10 when U1 is transmitting. RS=50 Ohm; U2 RS=50 Ohm; U10 RS=0 Ohm; U2 RS=0 Ohm; U10 1.2 0.8 V ID (v) 0.4 0.0 -0.4 -0.8 -1.2 5 10 15 20 25 30 35 Time (ns) Driver Slew Rate A fast slew rate helps to improve the rise time, especially at the receiver furthest from the driver. However, a faster slew rate also magnifies ringing due to reflection. Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 20 AN-522 2015.06.09 Overall System Performance Figure 19: Effect of Driver Edge Rate (Driver in U1, Receiver in U2 and U10) This figure shows the driver slew rate effect. A comparison is made between the slow and fast slew rate with a 12 mA drive strength. The driver is at U1 and the differential waveforms at U2 and U10 are examined. fast; U2 0.6 slow; U2 fast; U10 0.4 slow; U10 V ID (V) 0.2 0.0 -0.2 -0.4 -0.6 5.0 10.0 15.0 20.0 25.0 30.0 35.0 Time (ns) Overall System Performance The highest data rate supported by a multipoint BLVDS is determined by looking at the eye diagram of the furthest receiver from a driver. At this location, the transmitted signal has the slowest edge rate and affects the eye opening. Although the quality of the received signal and the noise margin goal depend on the applications, the wider the eye opening, the better. However, you must also check the receiver nearest to the driver, because the transmission line effects tend to be worse if the receiver is located closer to the driver. Altera Corporation Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback AN-522 2015.06.09 Document Revision History 21 Figure 20: Eye Diagram at 400 Mbps (Driver in U1, Receiver in U2 and U10) This figure illustrates the eye diagrams at U2 (red curve) and U10 (blue curve) for a data rate at 400 Mbps. Random jitter of a 1% unit interval is assumed in the simulation. The driver is at U1 with default current strength and slew rate settings. The bus is fully loaded with optimum RT = 50 Ω . The smallest eye opening is at U10, which is furthest from U1. The eye height sampled at the 0.5 unit interval is 692 mV and 543 mV for U2 and U10, respectively. There is a substantial noise margin with respect to VTH = ±100mV for both cases. Document Revision History Date June 2015 Version 2015.06.09 Changes • Updated the design example files. • Updated design example guidelines: • Moved the steps for Arria 10 devices into a new topic. • Added steps to migrate the design examples to use Altera GPIO IP core for Arria 10 devices. • Updated the design example steps to match the updated design examples. • Updated all links to updated website location and web-based documentation (if available). Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback Altera Corporation 22 AN-522 2015.06.09 Document Revision History Date August 2014 Version Changes 2014.08.18 • Updated application note to add Arria 10 device support. • Restructured and rewrote several sections for clarity and style update. • Updated template. June 2012 2.2 • Updated to include Arria II, Arria V, Cyclone V, and Stratix V devices. • Updated Table 1 and Table 2. April 2010 2.1 Updated the design example link in the “Design Example” section. November 2009 2.0 • Included Arria II GX, Cyclone III, and Cyclone IV device families in this application note. • Updated Table 1,Table 2, and Table 3. • Update Figure 5, Figure 6, Figure 8 through Figure 11. • Updated design example files. November 2008 1.1 • • • • • • • • • July 2008 1.0 Initial release. Altera Corporation Updated to new template Updated "BLVDS Technology in Altera Devices" chapter Updated "Power Consumption of BLVDS" chapter Updated "Design Example" chapter Replaced Figure 4 on page 7 Updated "Design Example Guidelines" chapter Updated "Performance Analysis" chapter Updated "Bus Termination" chapter Updated "Summary" chapter Implementing Bus LVDS Interface in Supported Altera Device Families Send Feedback