A B C D 8/18/05 3 2 1 5 4 Created schematic and changed the component from the 2S60 on the DSP board to the 2S180 on this Pro version of the board Change Description 3 01 Rev Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 1 of 40 Rev 01 Stratix II 2S180 Edition Rev 01 Revision History Date 4 D A B C DSP Pro Development Board 5 A B C D fse_D[7:0] fse_A[24:0] flash_RY_BY_n flash_WP_n flash_OE_n flash_RW_n flash_CS_n flash_RESET_n cpld_CLKOSC Configuration PLD DTR1 RTS1 RXD1 DSR1 DCD1 CTS1 TXD1 RI1 Serial Port proto_IO[40:0] CARDSEL_n RESET_n OSC CLKIN CLKOUT Protocard 2 proto_IO[40:0] CARDSEL_n RESET_n OSC CLKIN CLKOUT cf_IO[41:0] cf_CS_n cf_PRESENT_n cf_ATASEL_n cf_POWER cf_RESET_n Protocard 1 adcB_D[11:0] adcA_D[11:0] 5 user_PB[3:0] hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP pld_LED[7:0] enet_RESET proto1_RESET_n proto2_RESET_n cf_RESET_n cpld_USER[2:0] pld_PGM[2:0] pld_MSEL[3:0] pld_DCLK pld_CONFIG_n pld_CONFIG_DONE pld_STATUS_n pld_RECONFIGREQ_n pld_INIT_DONE pld_CONFIG_D[7:0] pld_RU_n_LU Page 9,10 ADC adc_PLLCLK1 adc_PLLCLK2 adc_CLK_IN1 adc_CLK_IN1_n adc_CLK_IN2 adc_CLK_IN2_n Page 34,35 Page 37 5 Mictor Connector pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] Page 30-33 Page 3-5 Page 16 user_PB[3:0] hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP pld_LED[7:0] enet_RESET proto1_RESET_n proto2_RESET_n cf_RESET_n cpld_USER[2:0] pld_PGM[2:0] pld_MSEL[3:0] pld_DCLK pld_CONFIG_n pld_CONFIG_DONE pld_STATUS_n pld_RECONFIGREQ_n pld_INIT_DONE pld_CONFIG_D[7:0] pld_RU_n_LU flash_D[7:0] flash_A[24:0] flash_RY_BY_n flash_WP_n flash_OE_n flash_RW_n flash_CS_n flash_RESET_n cpld_CLKOSC DTR1 RTS1 RXD1 DSR1 DCD1 CTS1 TXD1 RI1 proto2_IO[40:0] proto2_CARDSEL_n proto2_RESET_n proto2_OSC proto2_CLKIN proto2_CLKOUT proto1_IO[40:0] proto1_CARDSEL_n proto1_RESET_n proto1_OSC proto1_CLKIN proto1_CLKOUT cf_IO[41:0] cf_CS_n cf_PRESENT_n cf_ATASEL_n cf_POWER cf_RESET_n adcB_D[11:0] adcA_D[11:0] adc_PLLCLK1 adc_PLLCLK2 adc_CLK_IN1 adc_CLK_IN1_n adc_CLK_IN2 adc_CLK_IN2_n pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] 4 dacA_D[14:1] dacB_D[14:1] dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n dac_CLKIN1 dac_CLKIN2 dac_DACCLKIN1 dac_DACCLKIN2 audio_CLK audio_LRCIN audio_LRCOUT audio_DIN audio_DOUT audio_MODE audio_SDIN audio_SCLK audio_CS_n audio_BCLK dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n dacA_D[14:1] dacB_D[14:1] audio_CLK audio_LRCIN audio_LRCOUT audio_DIN audio_DOUT audio_MODE audio_SDIN audio_SCLK audio_CS_n audio_BCLK hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP user_PB[3:0] pld_LED[7:0] dacA_D[14:1] dacB_D[14:1] dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n dac_CLK_IN1 dac_CLK_IN2 dac_DACCLKIN1 dac_DACCLKIN2 Page 11-13 audio_CLK audio_LRCIN audio_LRCOUT audio_DIN audio_DOUT audio_MODE audio_SDIN audio_SCLK audio_CS_n audio_BCLK Page 7 dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n dacA_D[14:1] dacB_D[14:1] audio_CLK audio_LRCIN audio_LRCOUT audio_DIN audio_DOUT audio_MODE audio_SDIN audio_SCLK audio_CS_n audio_BCLK hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP user_PB[3:0] pld_LED[7:0] DAC Audio pld_DCLK pld_CONFIG_n pld_CONFIG_DONE pld_STATUS_n pld_INIT_DONE pld_RECONFIGREQ_n cpld_USER[2:0] pld_PGM[2:0] pld_MSEL[3:0] pld_CONFIG_D[7:0] pld_RU_n_LU DTR1 RTS1 RXD1 DSR1 DCD1 CTS1 TXD1 RI1 proto2_IO[40:0] proto2_CARDSEL_n proto2_CLKOUT proto1_IO[40:0] proto1_CARDSEL_n proto1_CLKOUT cf_IO[41:0] cf_CS_n cf_PRESENT_n cf_ATASEL_n cf_POWER cf_RESET_n adc_PLLCLK1 adc_PLLCLK2 adcA_D[11:0] adcB_D[11:0] pld_CLKFB pld_CLKIN0 pld_CLKIN1 pld_DACCLKIN pld_CLKIN0_n pld_CLKIN1_n pld_CLKOUT Page 17-26 pld_DCLK pld_CONFIG_n pld_CONFIG_DONE pld_STATUS_n pld_INIT_DONE pld_RECONFIGREQ_n cpld_USER[2:0] pld_PGM[2:0] pld_MSEL[3:0] pld_CONFIG_D[7:0] pld_RU_n_LU DTR1 RTS1 RXD1 DSR1 DCD1 CTS1 TXD1 RI1 proto2_IO[40:0] proto2_CARDSEL_n proto2_CLKOUT proto1_IO[40:0] proto1_CARDSEL_n proto1_CLKOUT cf_IO[41:0] cf_CS_n cf_PRESENT_n cf_ATASEL_n cf_POWER cf_RESET_n adc_PLLCLK1 adc_PLLCLK2 adcA_D[11:0] adcB_D[11:0] pld_CLKFB pld_CLKIN0 pld_CLKIN1 pld_DACCLKIN pld_CLKIN0_n pld_CLKIN1_n pld_CLKOUT 4 Page 27-29 3 3 Power Page 6 Page 39 adi_D[33:0] ADI Connector evm_D[31:0] evm_A[21:2] evm_BE_n[3:0] evm_CLKX0 evm_CLKR0 evm_FSX0 evm_FSR0 evm_DX0 evm_IACK evm_INUM0 evm_CNTL0 evm_DMAC0 evm_DR0 evm_STAT0 evm_AWE_n evm_ARE_n evm_AOE_n evm_ARDY evm_ACE2_n evm_ACE3_n evm_CLKOUT2 evm_INT[3:0] evm_RESET vga_R[7:0] vga_G[7:0] vga_B[7:0] vga_HSYNC vga_VSYNC vga_BLANK_n vga_SYNC_n vga_CLOCK sdram_DQ[63:0] sdram_A[11:0] sdram_DQM[7:0] sdram_BA[1:0] sdram_WE_n sdram_RAS_n sdram_CAS_n sdram_CS_n sdram_CKE sdram_CLK flash_D[7:0] flash_A[24:0] flash_OE_n flash_RW_n flash_CS_n flash_RY_BY_n flash_WP_n sram_BE_n[3:0] sram_OE_n sram_WE_n sram_CS_n se_D[31:0] se_A[19:1] pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] adi_D[33:0] evm_D[31:0] evm_A[21:2] evm_BE_n[3:0] evm_CLKX0 evm_CLKR0 evm_FSX0 evm_FSR0 evm_DX0 evm_IACK evm_INUM0 evm_CNTL0 evm_DMAC0 evm_DR0 evm_STAT0 evm_AWE_n evm_ARE_n evm_AOE_n evm_ARDY evm_ACE2_n evm_ACE3_n evm_CLKOUT2 evm_INT[3:0] evm_RESET adi_D[33:0] evm_D[31:0] evm_A[21:2] evm_BE_n[3:0] evm_CLKX0 evm_CLKR0 evm_FSX0 evm_FSR0 evm_DX0 evm_IACK evm_INUM0 evm_CNTL0 evm_DMAC0 evm_DR0 evm_STAT0 evm_AWE_n evm_ARE_n evm_AOE_n evm_ARDY evm_ACE2_n evm_ACE3_n evm_CLKOUT2 evm_INT[3:0] evm_RESET enet_BE_n[3:0] enet_AEN enet_IOR_n enet_IOW_n enet_IOCHRDY enet_ADS_n enet_LDEV_n enet_INTRQ0 enet_LCLK enet_DATACS_n enet_W_R_n enet_CYCLE_n enet_RDYRTN_n enet_SRDY_n enet_VLBUS_n TI EVM Connector adi_D[33:0] evm_D[31:0] evm_A[21:2] evm_BE_n[3:0] evm_CLKX0 evm_CLKR0 evm_FSX0 evm_FSR0 evm_DX0 evm_IACK evm_INUM0 evm_CNTL0 evm_DMAC0 evm_DR0 evm_STAT0 evm_AWE_n evm_ARE_n evm_AOE_n evm_ARDY evm_ACE2_n evm_ACE3_n evm_CLKOUT2 evm_INT[3:0] evm_RESET enet_BE_n[3:0] enet_AEN enet_IOR_n enet_IOW_n enet_IOCHRDY enet_ADS_n enet_LDEV_n enet_INTRQ0 enet_LCLK enet_DATACS_n enet_W_R_n enet_CYCLE_n enet_RDYRTN_n enet_SRDY_n enet_VLBUS_n vga_R[7:0] vga_G[7:0] vga_B[7:0] vga_HSYNC vga_VSYNC vga_BLANK_n vga_SYNC_n vga_CLOCK sdram_DQ[63:0] sdram_A[11:0] sdram_DQM[7:0] sdram_BA[1:0] sdram_WE_n sdram_RAS_n sdram_CAS_n sdram_CS_n sdram_CKE sdram_CLK flash_D[7:0] flash_A[24:0] flash_OE_n flash_RW_n flash_CS_n flash_RY_BY_n flash_WP_n sram_BE_n[3:0] sram_OE_n sram_WE_n sram_CS_n se_D[31:0] se_A[19:1] pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] PLD 2 2 1 DSP Pro Stratix II 2S180 (Maine Pro) Date: Thursday, August 18, 2005 Size Document Number CustomP06-10217-01 Title 1 Sheet 2 of enet_D[31:0] enet_A[15:1] enet_BE_n[3:0] enet_AEN enet_IOR_n enet_IOW_n enet_ADS_n enet_INTRQ0 enet_LDEV_n enet_IOCHRDY enet_RESET enet_LCLK enet_DATACS_n enet_W_R_n enet_CYCLE_n enet_RDYRTN_n enet_SRDY_n enet_VLBUS_n Page 14 vga_R[7:0] vga_G[7:0] vga_B[7:0] vga_HSYNC vga_VSYNC vga_BLANK_n vga_SYNC_n vga_CLOCK Page 40 sdram_DQ[63:0] sdram_A[11:0] sdram_DQM[7:0] sdram_BA[1:0] sdram_WE_n sdram_RAS_n sdram_CAS_n sdram_CS_n sdram_CLK sdram_CKE Page 36 D[7:0] A[24:0] flash_OE_n flash_RW_n flash_CS_n flash_RY_BY_n flash_WP_n flash_RESET_n Page 15 A[19:2] D[31:0] sram_BE_n[3:0] sram_OE_n sram_WE_n sram_CS_n Page 38 pld_CLKOUT DA_EXT_CLK0 DA_EXT_CLK1 DA_EXT_CLK2 CLKIN0_n CLKIN1_n CLKIN2_n CLKIN3_n pld_CLK0 pld_CLK1 pld_CLK2 osc_CLK0 osc_CLK1 osc_CLK2 osc_CLK3 osc_CLK4 osc_CLK5 osc_CLK6 osc_CLK7 osc_CLK8 Page 8 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> se_D[31:0] se_A[15:1] enet_BE_n[3:0] enet_AEN enet_IOR_n enet_IOW_n enet_ADS_n enet_INTRQ0 enet_LDEV_n enet_IOCHRDY enet_RESET enet_LCLK enet_DATACS_n enet_W_R_n enet_CYCLE_n enet_RDYRTN_n enet_SRDY_n enet_VLBUS_n vga_R[7:0] vga_G[7:0] vga_B[7:0] vga_HSYNC vga_VSYNC vga_BLANK_n vga_SYNC_n vga_CLOCK sdram_DQ[63:0] sdram_A[11:0] sdram_DQM[7:0] sdram_BA[1:0] sdram_WE_n sdram_RAS_n sdram_CAS_n sdram_CS_n sdram_CLK sdram_CKE flash_D[7:0] flash_A[24:0] flash_OE_n flash_RW_n flash_CS_n flash_RY_BY_n flash_WP_n flash_RESET_n se_A[19:2] se_D[31:0] sram_BE_n[3:0] sram_OE_n sram_WE_n sram_CS_n pld_CLKOUT dac_DACCLKIN1 dac_DACCLKIN2 pld_DACCLKIN adc_CLK_IN1_n adc_CLK_IN2_n pld_CLKIN0_n pld_CLKIN1_n proto1_CLKIN proto2_CLKIN pld_CLKFB pld_CLKIN0 pld_CLKIN1 proto1_OSC proto2_OSC cpld_CLKOSC adc_CLK_IN1 adc_CLK_IN2 dac_CLKIN1 dac_CLKIN2 Top Level Hierarchy 40 Ethernet VGA SDRAM Flash SRAM Clocks Rev 01 A B C D A B C D 5 adcA_ENC adcA_ENC_n SMAREC J1 49R9 R4 49R949R9 R1 R2 5 2 5 4 3 adcA_EXT_GND 1 C16 0u1 0u1 C17 49R9 R7 0_jump R3 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 Do Not stuff R7 AGND VCC3_3 C15 0u1 adcA_D0 adcA_D1 adcA_D2 adcA_D3 adcA_D4 adcA_D5 adcA_D6 adcA_D7 adcA_D8 adcA_D9 adcA_D10 adcA_D11 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 4 AGND 0u1 C18 adcA_AIN adcA_AIN_n 4 6 5 4 T1 NC P 3 2 1 AD9433BSQ ENCODE ENCODE_n AIN AIN_n OR VREFIN VREFOUT SFDR_MODE DFS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 ADT2_1T S 8 7 49 50 14 45 46 42 41 30 29 28 27 26 25 20 19 18 17 16 15 U1 AD9433 adcA_D[11:0] AGND 0u1 C21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND DGND DGND DGND DGND VCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD 1 3 4 9 11 33 34 35 38 39 40 43 48 51 12 21 24 31 2 5 6 10 36 37 44 47 52 13 22 23 32 3 3 2 T2 4 NC 5 S AGND 0u001 C5 6 ADT1_1W T 1 P 3 0u001 C6 0u001 C7 49R9 R8 49R9 R6 0u1 R9 R5 0u1 C9 0u001 0u001 C8 C2 C1 0u1 C10 0u1 C3 33 0u1 C19 33 10p C20 2 AGND 0u1 C11 0u1 C4 VCC3_3 2 10u C13 adcA_AIN adcA_AIN_n 0u1 C12 2 AVCC5 0u1 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> AGND 10u L1 Ferrite_Bead_33ohm C14 C407 1 1 3 of ADC A 40 Rev 01 A B C D A B C adcB_ENC adcB_ENC_n 5 SMAREC J2 49R9 R14 49R949R9 R11 R12 5 2 D 5 4 3 adcB_EXT_GND 1 C37 0u1 0u1 C38 49R9 R17 0_jump R13 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 Do Not stuff R17 AGND VCC3_3 C36 0u1 adcB_D0 adcB_D1 adcB_D2 adcB_D3 adcB_D4 adcB_D5 adcB_D6 adcB_D7 adcB_D8 adcB_D9 adcB_D10 adcB_D11 AGND 0u1 C39 adcB_AIN adcB_AIN_n 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 49R9 4 6 5 4 T3 NC P 3 2 1 AD9433BSQ ENCODE ENCODE_n AIN AIN_n OR VREFIN VREFOUT SFDR_MODE DFS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 ADT2_1T S 8 7 49 50 14 45 46 42 41 30 29 28 27 26 25 20 19 18 17 16 15 U2 adcB_D[11:0] 4 AD9433 AGND 0u1 C42 GND GND GND GND GND GND GND GND GND GND GND GND GND GND DGND DGND DGND DGND VCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD 1 3 4 9 11 33 34 35 38 39 40 43 48 51 12 21 24 31 2 5 6 10 36 37 44 47 52 13 22 23 32 3 2 T4 4 NC 5 S 6 ADT1_1W T 1 P AGND 3 3 0u001 C26 0u001 C27 49R9 R18 49R9 R16 0u001 0u1 C29 0u001 0u001 C28 C23 C22 33 R19 0u1 C40 33 R15 0u1 C30 0u1 C24 AGND 10p C41 0u1 C31 0u1 C25 VCC3_3 adcB_AIN adcB_AIN_n 0u1 C32 2 0u1 C33 2 10u C34 2 AVCC5 0u1 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> AGND 10u 1 L3 Ferrite_Bead_33ohm C35 C406 1 4 of ADC B 40 Rev 01 A B C D A B C D 95R3 adc_CLK_IN2 R26 143 R25 143 SY10EPT28L 4 8 7 6 5 8 7 6 5 143 R27 95R3 adc_CLK_IN1_n R23 VCC3_3 IN_LVPECL VCC IN_LVPECL_n OUT_LVTTL OUT_LVPECL IN_LVTTL OUT_LVPECL_n GND U4 SY10EPT28L 95R3 adc_CLK_IN1 5 4 IN_LVPECL VCC IN_LVPECL_n OUT_LVTTL OUT_LVPECL IN_LVTTL OUT_LVPECL_n GND R22 VCC3_3 1 2 3 4 1 2 3 4 U3 R21 VCC3_3 adcB_ENC adcB_ENC_n adcA_ENC adcA_ENC_n 5 143 R28 3 0u1 C43 VCC3_3 95R3 adc_CLK_IN2_n R24 VCC3_3 0u1 C44 VCC3_3 3 1 3 5 1 3 5 2 4 6 2 4 6 2 4 6 2 4 6 adc_PLLCLK2 adc_CLK_IN2 adc_CLK_IN2_n adc_PLLCLK1 adc_CLK_IN1 adc_CLK_IN1_n Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 S2 S1 Sheet 5 1 of Shunt_jumper Shunt_jumper 40 ADC Clock Selection 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 2x3Header 1 3 5 J4 2x3Header 1 3 5 J3 Clock buffer must be connected to the same VCC that the IO for the ADC is using. 2 Rev 01 A B C D A B C D 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 5 20X2Header GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J5 VCC.GND.GND B13.BOR.NC B12.NC.DRX B11.NC.DXB B10.NC.DXA B9.B0.DX0 B8.B1.DX1 B7.B2.DX2 B6.B3.DX3 * .B4.DX4 * .B5.DX5 B5.B6.DX6 B4.B7.DX7 B3.B8.DX8 B2.B9.DX9 B1.B10.DX10 B0.B11.DX11 GND.GND.GND GND.DR.DRA GND.GND.GND AD6645.9433.9430 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 4 4 adi_D16 adi_D0 adi_D1 adi_D2 adi_D3 adi_D4 adi_D5 adi_D6 adi_D7 adi_D8 adi_D9 adi_D10 adi_D11 adi_D12 adi_D13 adi_D14 adi_D15 adi_D[33:0] 3 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 Sheet 6 adi_D33 adi_D17 adi_D18 adi_D19 adi_D20 adi_D21 adi_D22 adi_D23 adi_D24 adi_D25 adi_D26 adi_D27 adi_D28 adi_D29 adi_D30 adi_D31 adi_D32 1 of 40 Rev 01 ADI Connector 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. VCC.GND.GND B13.BOR.NC B12.NC.DRY B11.NC.DYB B10.NC.DYA B9.B0.DY0 B8.B1.DY1 B7.B2.DY2 B6.B3.DY3 * .B4.DY4 * .B5.DY5 B5.B6.DY6 B4.B7.DY7 B3.B8.DY8 B2.B9.DY9 B1.B10. DY10 B0.B11.DY11 GND.GND.GND GND.DR.DRB GND.GND.GND AD6645.9433.9430 <Core Design> 20X2Header GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J6 2 A B C D A B C D 5 4 3 2 1 5 4 3 2 1 Line Out 1 1 5 4 3 2 1 SJ_3515N J9 5 Amplified Line Out SJ_3515N J8 SJ_3515N J7 5 1 1 2 L10 BLM21P221SN 2 L11 BLM21P221SN L8 BLM21P221SN 2 L9 BLM21P221SN 1 2 1 2 L5 BLM21P221SN 2 L6 BLM21P221SN 4K7 R30 4K7 R29 R38 47K5 47K5 47K5 47K5 R37 R36 R34 R33 4K7 R32 R35 4K7 R31 4 100 100 4 C58 220u C57 220u C53 C52 C46 C45 0u47 0u47 0u47 0u47 9 10 RALINEOUT LALINEOUT 12 13 17 18 20 19 LLINEOUT RLINEOUT LLINEIN RLINEIN AIC23 LHPOUT RHPOUT LOUT ROUT MICBIAS MICIN LLINEIN RLINEIN U5 audio_SDIN audio_SCLK audio_MODE 1 2 3 4 8 7 6 5 3 DGND BVDD DVDD HPGND HPVDD AGND VMID AVDD BCLK CS_n SDIN SCLK MODE DOUT DIN LRCIN LRCOUT CLKOUT XTO XTI.MCLK 5K6 RP1 3 28 1 27 11 8 15 16 14 3 21 23 24 22 6 4 5 7 2 26 25 VCC3_3 audio_CLK audio_BCLK audio_CS_n audio_SDIN audio_SCLK audio_MODE audio_DOUT audio_DIN audio_LRCIN audio_LRCOUT 0u1 C50 0u1 C54 10u C51 0u001 C55 0u1 C47 10u C56 2 VCC3_3 0u001 C48 1 2 L7 SMFerrite 2 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 10u C49 VCC3_3 1 7 of 40 Audio Rev 01 A B C D A B C D J10 SMAREC J12 SMAREC J11 SMAREC 1 0u1 C59 VCC3_3 4 3 4 5 2 5 2 5 2 3 4 3 2 5 DA_EXT_CLK 1 CLKIN_n 1 CLKIN_p 1 L12 47nH 5 0u1 0u001 4 8 OUT 100Mhz GND OE_n VCC Y1 Do not Stuff R40 for Ocilator operation. Stuff R40 when using Clock input. C61 C60 1 5 49R9 R42 49R9 R41 330 R40 R39 OSC_Socket 4 49R9 Ocilator Half Socket XY1 4 49FCT3805 OEB_n INB OEA_n INA MON_n U6 12 11 9 10 13 49FCT3805 OEB_n INB OEA_n INA MON_n U8 pld_CLKOUT 12 11 9 10 13 OB0 OB1 OB2 OB3 OB4 OA0 OA1 OA2 OA3 OA4 OB0 OB1 OB2 OB3 OB4 OA0 OA1 OA2 OA3 OA4 U7 19 18 17 15 14 2 3 4 6 7 12 11 9 10 49FCT3805 OEB_n INB OEA_n INA MON_n OA0 OA1 OA2 OA3 OA4 2 3 4 6 7 OB0 OB1 OB2 OB3 OB4 CLKIN0_n CLKIN1_n CLKIN2_n CLKIN3_n 3 DA_EXT_CLK0 DA_EXT_CLK1 DA_EXT_CLK2 19 18 17 15 14 osc_CLK5 osc_CLK6 osc_CLK7 osc_CLK8 19 18 17 15 14 13 osc_CLK0 osc_CLK1 osc_CLK2 osc_CLK3 osc_CLK4 2 3 4 6 7 3 pld_CLK0 pld_CLK1 pld_CLK2 2 2 C311 0u1 C143 0u1 VCC3_3 0u001 C144 0u001 C313 0u001 C314 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 0u1 C312 CLOCK CAPS U6 U7 U8 1 8 of 40 Rev 01 Clocks A B C D A B C D TDI TCK TDO TMS B14 C11 B13 D11 A13 E11 B12 C10 flash_RY_BY_n pld_RU_n_LU VCC3_3 RP3 1K 5 1 3 5 7 9 U9A IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 2 4 6 8 10 2 4 6 8 10 2x5Shrouded 1 3 5 7 9 J13 TRST VCC3_3 male header JTAG connections: pin# jtag 1 TCK 2 GND 3 TDO 4 Vcc 5 TMS 6 Vccio 7 (NC) 8 (NC) 9 TDI 10 GND Configuration PLD EPM1270_256FBGA A12 D10 B11 E10 A11 F10 B10 C9 G2 G4 G1 G5 H2 G6 A15 D12 E2 F4 E1 F5 F2 F6 F1 G3 K6 L1 C3 E4 D2 E5 D1 F3 H3 J1 H4 J2 J4 K1 J3 K2 C2 E3 K13 K15 K12 K16 D3 H1 fse_D7 proto1_RESET_n proto2_RESET_n enet_RESET flash_WP_n flash_CS_n flash_OE_n flash_RW_n fse_A24 fse_D0 fse_D1 fse_D2 fse_D3 fse_D4 fse_D5 fse_D6 fse_A16 fse_A17 fse_A18 fse_A19 fse_A20 fse_A21 fse_A22 fse_A23 fse_A8 fse_A9 fse_A10 fse_A11 fse_A12 fse_A13 fse_A14 fse_A15 fse_A0 fse_A1 fse_A2 fse_A3 fse_A4 fse_A5 fse_A6 fse_A7 VCC3_3 J9 H10 H8 J7 VCCINT VCCINT VCCINT VCCINT GNDINT GNDINT GNDINT GNDINT GNDIO GNDIO GNDIO GNDIO GNDIO H7 H9 J8 J10 K7 K8 K9 G7 G8 5 5 6 7 8 4 3 2 1 E8 B8 A8 A9 E9 B9 D9 A10 E7 B6 F7 A6 C8 B7 D8 A7 D6 B4 E6 A4 C7 B5 D7 A5 L5 M2 K3 M1 K4 L2 K5 C4 P2 N3 M4 N2 L3 N1 L4 M3 L11 M16 L12 C12 B16 C13 M7 R6 K11 P9 R9 T9 T8 L16 K14 L15 1 2 3 4 5 6 7 8 SPST8 SW2 4 16 15 14 13 12 11 10 9 4 D5 M15 P13 R16 M13 D4 N12 M14 P15 N13 P14 P12 T15 R12 M11 T12 pld_CONFIG_D0 pld_CONFIG_D1 pld_CONFIG_D2 pld_CONFIG_D3 pld_CONFIG_D4 pld_CONFIG_D5 pld_CONFIG_D6 pld_CONFIG_D7 flash_RESET_n flash_CE_nLED pld_BOOTSEL cf_RESET_n cpld_USER0 cpld_USER1 pld_RECONFIGREQ_n cpld_USER2 P3 N4 L6 1 2 3 4 1 2 3 4 8 7 6 5 5K6 RP4 8 7 6 5 VCC3_3 MPGM0 MPGM1 MPGM2 MAX_EN pld_RU_n_LU cpld_USER0 cpld_USER1 cpld_USER2 5K6 RP2 TCK TMS TDI IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO.GCLK0 IO.GCLK1 IO.GCLK2 IO.GCLK3 IO.DEV_OE IO.DEV_CLRn VCC3_3 EPM1270_256FBGA TCK TMS TDI P8 R7 L7 T6 L14 N15 N7 T5 R13 P11 T13 N11 N9 R8 N8 T7 P10 R11 N10 T11 M10 R10 R14 M12 N16 L13 A2 B3 C6 C5 N14 B1 MASTER_RESET_n pld_MSEL3 pld_MSEL0 pld_MSEL1 pld_MSEL2 MAX_EN H5 J5 J12 H12 M8 M9 cpld_CLKOSC U9B TDO VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO max_LED0 max_LED1 max_LED2 max_LED3 max_LED4 max_LED5 max_LED6 max_LED7 L10 P4 R1 P5 T2 N5 R3 P6 M5 H6 J6 C1 P1 F8 A14 F9 A3 H11 J11 C16 P16 T3 T14 L9 L8 0u001 0u1 0u1 C133 0u001 C134 3 pld_BOOTSEL pld_BOOTSEL determines whether to force a boot from the default boot sector, or the user-programmed boot sector. C132 C131 0u1 C135 VCC3_3 TDO 0u001 C136 5K6 R49 VCC3_3 pld_CONFIG_DONELED pld_USERLED pld_LOADLED pld_SAFELED pld_ERRLED pld_LED0 pld_LED1 pld_LED2 pld_LED3 pld_LED4 pld_LED5 pld_LED6 pld_LED7 D14 E12 C15 E13 C14 E14 D13 T10 R4 N6 T4 M6 R5 P7 pld_PGM0 pld_PGM1 pld_PGM2 MPGM0 MPGM1 MPGM2 pld_DCLK pld_CONFIG_DONE pld_CONFIG_n pld_STATUS_n pld_INIT_DONE 3 E16 F11 E15 F12 D16 F13 D15 F14 G16 G12 G15 G11 F16 G13 F15 G14 J15 J14 J16 J13 H16 H13 H15 H14 CONFIG PLD CAPS U9 U10 G9 G10 A1 A16 B2 B15 K10 R2 R15 T1 T16 1 2 0u1 0u001 C138 0u1 C315 140 R44 PBswitch SW3 3 4 0u1 5K6 R48 cpld_CLKOSC 10 9 8 7 6 5 36 35 34 32 31 30 29 28 44 43 42 41 40 39 38 37 138 137 136 134 133 132 131 fse_A7 fse_A8 fse_A9 fse_A10 fse_A11 fse_A12 fse_A13 fse_A14 fse_A15 fse_A16 fse_A17 fse_A18 fse_A19 fse_A20 fse_A21 fse_A22 fse_A23 fse_A24 fse_D3 fse_D4 fse_D5 fse_D6 fse_D7 0u001 C318 pld_RU_n_LU flash_RY_BY_n flash_CS_n flash_OE_n flash_RW_n proto1_RESET_n proto2_RESET_n enet_RESET flash_WP_n pld_PGM[2:0] max_LED[7:0] pld_LED[7:0] fse_A[24:0] fse_D[7:0] H128 H125 H123 G99 G101 G104 G105 G107 G109 F83 F85 F88 F89 F91 F93 F96 E69 E72 E73 E75 E77 E78 E80 D49 D51 D53 D54 D56 D59 D61 D64 C33 C35 C37 C40 C41 C43 C45 C48 B19 B21 B24 B25 B27 B29 A3 A5 A6 A11 A13 A14 A16 TDI TMS TCK TDO GCLK1 GCLK2 GCLRn OE1 U10 2 1 2 PBswitch SW1 VCC1_2 pld_CONFIG_D[7:0] pld_MSEL[3:0] 1K max_LED0 max_LED1 max_LED2 max_LED3 max_LED4 max_LED5 max_LED6 55 56 60 61 62 63 65 VCC3 VCC5 VCCA PBR LTC1326_5 RST 5 RST 6 SRST 7 Thursday, August 18, 2005 Date: 1 DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size C Title Sheet 9 of 40 1K MASTER_RESET_n R47 VCC3_3 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. 1 2 3 U11 cpld_USER0 cpld_USER1 pld_RECONFIGREQ_n cpld_USER2 54 53 49 48 8 flash_RESET_n flash_CE_nLED pld_BOOTSEL cf_RESET_n pld_MSEL3 pld_MSEL0 pld_MSEL1 pld_MSEL2 MAX_EN pld_ERRLED pld_USERLED pld_LOADLED pld_SAFELED 114 116 117 118 119 120 121 122 90 91 92 93 94 96 97 1 max_LED7 pld_CONFIG_DONELED pld_LED0 pld_LED1 pld_LED2 pld_LED3 pld_LED4 pld_LED5 pld_LED6 pld_LED7 106 107 108 109 110 111 112 113 82 83 84 86 87 88 pld_PGM0 pld_PGM1 pld_PGM2 MPGM0 MPGM1 MPGM2 pld_CONFIG_D7 pld_DCLK pld_CONFIG_DONE pld_CONFIG_n pld_STATUS_n pld_INIT_DONE 74 75 77 78 79 80 81 98 99 100 101 102 103 pld_CONFIG_D0 pld_CONFIG_D1 pld_CONFIG_D2 pld_CONFIG_D3 pld_CONFIG_D4 pld_CONFIG_D5 pld_CONFIG_D6 66 67 68 69 70 71 72 <Core Design> 10K VCC3_3 R45 H115 H117 H120 H121 I129 I131 I133 I136 I137 I139 I141 I144 J147 J149 J152 J153 J155 J157 J160 K163 K165 K168 K169 K171 K173 L179 L181 L184 L185 L187 L189 L192 M193 M195 M197 M200 M201 M203 M206 M208 N211 N213 N216 N217 N219 N221 O227 O229 O232 O233 O235 O237 O240 P241 P243 P245 P246 P249 P253 P256 Configuration PLD R46 VCC3_3 VCC3_3 VCC5 PB_RESET_n cpld_USER[2:0] 3 4 Label this button very clearly with the words. POWER ON RESET and put a box around the button and text. EPM7256AETC144 45 46 47 27 26 25 23 22 21 19 18 16 15 14 12 11 2 1 143 142 141 140 139 fse_A0 fse_A1 fse_A2 fse_A3 fse_A4 fse_A5 fse_A6 fse_D0 fse_D1 fse_D2 4 20 89 104 125 128 127 126 TDI TMS TCK TDO MASTER_RESET_n VCC3_3 0u001 C317 VCC3_3 C316 93R1 pld_RECONFIGREQ_n C137 VCC3_3 cpld_CLKOSC R43 VCC3_3 2 24 50 73 76 95 115 144 GNDINT1 GNDINT2 GNDINT3 GNDINT4 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 52 57 124 129 51 58 123 130 VCCINT1 VCCINT2 VCCINT3 VCCINT4 GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 GNDIO7 GNDIO8 GNDIO9 3 13 17 33 59 64 85 105 135 Rev 01 A B C D A B C D 5 6 7 8 hex_1A hex_1B hex_1C hex_1D 5 8 7 6 5 1 2 3 4 hex_0E hex_0F hex_0G hex_0DP hex_1E hex_1F hex_1G hex_1DP 1 2 3 4 hex_0A hex_0B hex_0C hex_0D 5 220 RP10 220 RP8 220 RP7 220 RP5 1 2 3 4 4 3 2 1 8 7 6 5 8 7 6 5 6 1 VCC3_3 6 1 VCC3_3 7Segment_Display 7 DP 3 G 2 F 4 E 5 D 8 C 9 B U13 10 A 7Segment_Display 7 DP 3 G 2 F 4 E 5 D 8 C 9 B U12 10 A 4 4 1 2 1 2 1 2 1 2 max_LED4 max_LED5 max_LED6 max_LED7 max_LED0 max_LED1 max_LED2 max_LED3 4 3 2 1 4 3 2 1 PBswitch PBswitch SW 7 PBswitch SW 6 PBswitch SW 5 SW 4 max_LED[7:0] 3 4 3 4 3 4 3 4 100 5 6 7 8 5 6 7 8 RP11 5K6 RP9 100 RP6 VCC3_3 5 6 7 8 user_PB[3:0] 4 3 2 1 Led_Blue D8 Led_Blue D7 Led_Blue D6 Led_Blue D5 Led_Blue D4 Led_Blue D3 Led_Blue D2 Led_Blue D1 3 user_PB3 user_PB2 user_PB1 user_PB0 3 2 2 LedG power indication LED7 LedR LED6 LedR LED5 LedR LED4 LedG LED3 LedY LED2 LedG LED1 R56 R55 R54 R53 R52 R51 R50 200 200 200 200 200 200 200 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> VCC3_3 flash_CE_nLED pld_CONFIG_DONELED pld_ERRLED pld_LOADLED pld_SAFELED pld_USERLED 10 of 40 LEDs and Buttons 1 Rev 01 A B C D A B C D 1 2 3 4 1 2 3 4 1 2 3 4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 5 1 2 3 4 dacA_D1 dacA_D2 dacA_D3 dacA_D4 33 RP15 33 RP14 33 RP13 33 RP12 dacA_D[14:1] 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DAC904 NC Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 U14 26 20 15 28 18 17 16 22 21 23 27 24 19 4 dacA_IOUT_n DGND AGND PD CLK FSA REFIN N_INT.EXT IOUT IOUT_n BYP +VD +VA BW 1 TP1 0u1 C68 0u1 C62 2K R58 0u1 C63 AGND 0u1 C71 1u C64 10u C65 AVCC5 3 49R9 R59 AGND 10u 2 L13 Ferrite_Bead_33ohm C66 Should be labled IOUT_n in silk screen 0u1 C72 Test_Header 1 dacA_CLK dacA_IOUT_n 1u C67 VCC3_3 1 0_jump 49R9 R60 C69 0u1 C394 1 2 2X1Header 1 2 J14 NOSTUFF J14 AGND 0u1 C73 4 5 6 ADT1_1W T T5 2 Do Not stuff C73 1 2 3 Note C69 was a Capacitor that we determined was not advantagouse to the circuit so it was replaced with a 0ohm jumper. 2 AGND 1 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> J15 1 SMAREC 4 3 3 5 2 4 P 5 S NC 11 of 40 DAC A Rev 01 A B C D A B C 1 2 3 4 1 2 3 4 1 2 3 4 dacB_D5 dacB_D6 dacB_D7 dacB_D8 dacB_D9 dacB_D10 dacB_D11 dacB_D12 dacB_D13 dacB_D14 5 1 2 3 4 dacB_D1 dacB_D2 dacB_D3 dacB_D4 33 RP19 33 RP18 33 RP17 33 RP16 dacB_D[14:1] 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DAC904 NC Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 U15 4 DGND AGND PD CLK FSA REFIN N_INT.EXT IOUT IOUT_n BYP +VD +VA BW 26 20 15 28 18 17 16 22 21 23 27 24 19 1u C74 dacB_CLK 0u1 C83 dacB_IOUT_n VCC3_3 2K R63 0u1 C76 0u1 C82 1u C77 AGND dacB_IOUT_n 0u1 C79 0u1 C75 1 1 TP3 49R9 R64 0u1 0_jump 49R9 R65 C80 Should be labled IOUT_n in silk screen AGND 10u 2 L14 Ferrite_Bead_33ohm C392 C393 3 Test_Header 1 10u C78 AVCC5 1 2 2X1Header 1 2 J16 NOSTUFF J16 2 AGND 0u1 C84 4 5 6 ADT1_1W T T6 J17 1 SMAREC dacB_EXT_GND AGND 1 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> Do Not stuff C84 1 2 3 Note C80 was a Capacitor that we determined was not advantagouse to the circuit so it was replaced with a 0ohm jumper. 2 4 3 3 5 2 D 4 P 5 S NC 12 of DAC B 40 Rev 01 A B C D A B C D 5 5 R68 95R3 dac_CLK_IN2 R72 143 R67 95R3 dac_CLK_IN1 R71 143 4 2 4 6 8 2x4Header 1 3 5 7 J19 VCC3_3 1 3 5 7 dac_PLLCLK2 dac_PLLCLK2_n dac_CLK_IN2 dac_DACCLKIN2 2 4 6 8 2x4Header 1 3 5 7 J18 VCC3_3 1 3 5 7 dac_PLLCLK1 dac_PLLCLK1_n dac_CLK_IN1 dac_DACCLKIN1 4 2 4 6 8 2 4 6 8 143 R73 3 95R3 dac_DACCLKIN1 R69 VCC3_3 dacB_CLK dacA_CLK 3 143 R74 Shunt_jumper Shunt_jumper Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 Sheet 13 1 of 40 DAC Clock Jumper 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 95R3 dac_DACCLKIN2 R70 VCC3_3 S4 S3 2 Rev 01 A B C D A B C D 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 107 106 105 104 102 101 100 99 76 75 74 73 71 70 69 68 66 65 64 63 61 60 59 58 56 55 54 53 51 50 49 48 enet_A1 enet_A2 enet_A3 enet_A4 enet_A5 enet_A6 enet_A7 enet_A8 enet_A9 enet_A10 enet_A11 enet_A12 enet_A13 enet_A14 enet_A15 enet_D0 enet_D1 enet_D2 enet_D3 enet_D4 enet_D5 enet_D6 enet_D7 enet_D8 enet_D9 enet_D10 enet_D11 enet_D12 enet_D13 enet_D14 enet_D15 enet_D16 enet_D17 enet_D18 enet_D19 enet_D20 enet_D21 enet_D22 enet_D23 enet_D24 enet_D25 enet_D26 enet_D27 enet_D28 enet_D29 enet_D30 enet_D31 enet_D[31:0] 5 enet_BE_n[3:0] enet_A[15:1] 30 37 42 38 46 43 29 45 31 32 34 35 36 40 41 enet_AEN enet_RESET enet_ADS_n enet_LCLK enet_IOCHRDY enet_RDYRTN_n enet_SRDY_n enet_INTRQ0 enet_LDEV_n enet_IOR_n enet_IOW _n enet_DATACS_n enet_CYCLE_n enet_W _R_n enet_VLBUS_n 97 96 95 94 enet_BE_n3 enet_BE_n2 enet_BE_n1 enet_BE_n0 RESET ADS# LCLK ARDY RDYRTN# SRDY# INTR0 LDEV# RD# WR# DATACS# CYCLE# W/R# VLBUS# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 AEN BE3# BE2# BE1# BE0# U16 VCC3_3 4 11 16 LAN91C111 4 24 39 52 57 67 72 93 103 108 117 5 1 33 44 62 77 98 110 120 VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PHY MII INTERFACE CSOUT# X25OUT XTAL1 XTAL2 IOS0 IOS1 IOS2 ENEEP ENDO ENDI EESK EECS TXEN100 CRS100 COL100 RXDV RXER MDI MDO MCLK RX25 TX25 TXD3 TXD2 TXD1 TXD0 RXD3 RXD2 RXD1 RXD0 LEDA# LEDB# LNK# LBK CNTRL# RBIAS TPO+ TPOTPI+ TPI- LAN91C111 SERIAL EEPROM 2 47 127 128 3 4 5 6 7 8 9 10 111 119 112 125 126 25 26 27 118 109 113 114 115 116 121 122 123 124 22 23 20 21 28 12 14 15 17 18 RBIAS 11K R81 ENEEP 3 33p C99 LEDLNK_n LEDRX_n Stuff R155 R156 R157 R158 R159 and R160 only when using the MAC Phy instead of the Phy, and resistors R149 R150 R151 R152 R153 and R154 are nostuffed. 3 Y2 25MHz 1 R76 2 VCCA 33p C100 R78 C102 0u001 0u001 0u001 C101 C95 0u001 0u1 C87 TXDP TXDM RXDP RXDM C94 24R9 24R9 49R9 49R9 R77 VCC3_3 R79 R80 24R9 24R9 R75 0u01 C85 VCC3_3 0u001 C103 VCC3_3 0u1 C96 VCC3_3 0u001 C88 1 0u1 C104 0u1 C97 L15 47nH VCCA 2 0u1 C105 0u1 C98 2 0u001 C86 2 RJ45INTLED OCT NC0 TDN TDP TCT RCT RDN RDP RJ1 1u C89 16 0u001 C90 D1 D2 D3 D4 9 0u001 0u1 C92 VCC3_3 C91 10 11 12 10K 0u1 C93 LEDLNK_n 330 R84 10K R83 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> ENEEP enet_IOR_n enet_IOW _n R82 VCC3_3 1 LEDRX_n VCC3_3 PULL-UP/PULL-DOWNS VCC3_3 8 7 3 1 2 5 6 4 14 SMNT1 SMNT0 13 MNT0 MNT1 15 AVDD AVDD AVSS AVSS 13 19 INTERFACE PINS 14 of 40 Ethernet Rev 01 A B C D A B C D 5 5 C140 0u001 C139 0u1 FLASH CAPS VCC3_3 0u1 C141 0u001 C142 VCC3_3 4 4 R87 R86 AM29LV128M OE_n CE_n WE_n RESET_n WP_n.ACC RY_BY_n BYTE_n A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 NC.A23 U17 5K6 5K6 NC NC NC NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15.A1 27 28 30 55 56 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 3 D0 D1 D2 D3 D4 D5 D6 D7 A0 VCC3_3 Flash chip is 16M x 8 for 16Mbytes of flash flash_RW _n flash_CS_n 330 34 32 13 14 16 17 53 flash_OE_n flash_CS_n flash_RW _n flash_RESET_n flash_W P_n flash_RY_BY_n R85 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 D[7:0] A[24:0] 3 2 2 DSP Pro Stratix II 2S180 (Maine Pro) Date: Thursday, August 18, 2005 Size Document Number CustomP06-10217-01 Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 15 of 40 Rev 01 Flash A B C D A B C D 5 5 0_jump 0_jump 0_jump 0_jump R90 R91 R92 R93 TCK TMS TDI TRST 4 0_jump R89 TDO 5K6 R88 VCC3_3 4 3 MICTOR21 MICTOR20 MICTOR19 MICTOR18 MICTOR17 MICTOR16 MICTOR15 MICTOR14 MICTOR22 pld_MICTORCLK MICTOR24 MICTOR23 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 2 VCC3_3 MICTOR11 MICTOR10 MICTOR9 MICTOR8 MICTOR7 MICTOR6 MICTOR5 MICTOR4 MICTOR3 MICTOR2 MICTOR1 MICTOR0 TR_CLK MICTOR13 MICTOR12 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 Sheet 1 of 0u001 0u1 16 C320 C319 VCC3_3 40 Mictor Connector 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Mictor38P 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 MICTOR[24:0] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 J20 44 TOOL Rev 01 A B C D A B C D 5 5 AE32 AE31 AD32 AD31 AB28 AB27 AC32 AC31 AB30 AB29 Y29 Y28 AA30 AA29 AB32 AB31 Y31 Y30 AA32 AA31 W32 W31 V31 V30 flash_A8 flash_A9 flash_A10 flash_A11 flash_A12 flash_A13 flash_A14 flash_A15 flash_A16 flash_A17 flash_A18 flash_A19 flash_A20 flash_A21 flash_A22 flash_A23 flash_A24 flash_W P_n flash_CS_n flash_OE_n flash_RW _n flash_RY_BY_n enet_LCLK enet_RDYRTN_n 4 AF30 AF29 AE30 AE29 AG32 AG31 AF32 AF31 flash_A0 flash_A1 flash_A2 flash_A3 flash_A4 flash_A5 flash_A6 flash_A7 U32 U31 U30 U29 AJ30 AJ29 AH30 AH29 AJ32 AJ31 AG30 AG29 AH32 AH31 flash_D0 flash_D1 flash_D2 flash_D3 flash_D4 flash_D5 flash_D6 flash_D7 4 EP2S180F1020C3 IO.DIFFIO_TX20p IO.DIFFIO_TX20n IO.DIFFIO_TX16p IO.DIFFIO_TX16n IO.DIFFIO_TX17p IO.DIFFIO_TX17n IO.DIFFIO_TX18p IO.DIFFIO_TX18n IO.DIFFIO_TX19p IO.DIFFIO_TX19n IO.DIFFIO_TX12p IO.DIFFIO_TX12n IO.DIFFIO_TX13p IO.DIFFIO_TX13n IO.DIFFIO_TX14p IO.DIFFIO_TX14n IO.DIFFIO_TX15p IO.DIFFIO_TX15n IO.DIFFIO_TX8p IO.DIFFIO_TX8n IO.DIFFIO_TX9p IO.DIFFIO_TX9n IO.DIFFIO_TX10p IO.DIFFIO_TX10n IO.DIFFIO_TX11p IO.DIFFIO_TX11n IO.DIFFIO_TX4p IO.DIFFIO_TX4n IO.DIFFIO_TX5p IO.DIFFIO_TX5n IO.DIFFIO_TX6p IO.DIFFIO_TX6n IO.DIFFIO_TX7p IO.DIFFIO_TX7n IO.DIFFIO_TX0p IO.DIFFIO_TX0n IO.DIFFIO_TX1p IO.DIFFIO_TX1n IO.DIFFIO_TX2p IO.DIFFIO_TX2n IO.DIFFIO_TX3p IO.DIFFIO_TX3n flash_D[7:0] flash_A[24:0] enet_BE_n[3:0] 3 VREFB1N1.VREFB1N1 VREFB1N0.VREFB1N0 VREFB1N2.VREFB1N2 proto2_IO[40:0] IO.CLK2p/DIFFIO_RX_C1p IO.CLK2n/DIFFIO_RX_C1n CLK3p.INPUT CLK3n.INPUT FPLL8CLKp.INPUT FPLL8CLKn.INPUT IO.DIFFIO_RX17p IO.DIFFIO_RX17n IO.DIFFIO_RX18p IO.DIFFIO_RX18n IO.DIFFIO_RX19p IO.DIFFIO_RX19n IO.DIFFIO_RX20p IO.DIFFIO_RX20n IO.DIFFIO_RX13p IO.DIFFIO_RX13n IO.DIFFIO_RX14p IO.DIFFIO_RX14n IO.DIFFIO_RX15p IO.DIFFIO_RX15n IO.DIFFIO_RX16p IO.DIFFIO_RX16n IO.DIFFIO_RX9p IO.DIFFIO_RX9n IO.DIFFIO_RX10p IO.DIFFIO_RX10n IO.DIFFIO_RX11p IO.DIFFIO_RX11n IO.DIFFIO_RX12p IO.DIFFIO_RX12n IO.DIFFIO_RX5p IO.DIFFIO_RX5n IO.DIFFIO_RX6p IO.DIFFIO_RX6n IO.DIFFIO_RX7p IO.DIFFIO_RX7n IO.DIFFIO_RX8p IO.DIFFIO_RX8n IO.DIFFIO_RX1p IO.DIFFIO_RX1n IO.DIFFIO_RX2p IO.DIFFIO_RX2n IO.DIFFIO_RX3p IO.DIFFIO_RX3n IO.DIFFIO_RX4p IO.DIFFIO_RX4n U18A 3 AD28 W30 AG28 U23 U22 W29 W28 V24 V23 V29 V28 U28 U27 AA27 AA26 Y27 Y26 W25 W24 W27 W26 AC27 AC26 AD27 AD26 Y23 Y22 Y25 Y24 AC25 AC24 AB26 AB25 AA25 AA24 AA23 AA22 AE28 AE27 AE26 AE25 AD25 AD24 AB24 AB23 VCC3_3 proto2_IO24 proto2_IO25 proto2_IO16 proto2_IO17 proto2_IO18 proto2_IO19 proto2_IO20 proto2_IO21 proto2_IO22 proto2_IO23 proto2_IO8 proto2_IO9 proto2_IO10 proto2_IO11 proto2_IO12 proto2_IO13 proto2_IO14 proto2_IO15 proto2_IO0 proto2_IO1 proto2_IO2 proto2_IO3 proto2_IO4 proto2_IO5 proto2_IO6 proto2_IO7 enet_AEN enet_IOR_n enet_IOW _n enet_IOCHRDY enet_ADS_n enet_LDEV_n enet_SRDY_n enet_VLBUS_n enet_CYCLE_n enet_W _R_n enet_BE_n0 enet_BE_n1 enet_BE_n2 enet_BE_n3 enet_DATACS_n enet_INTRQ0 2 2 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 17 of 40 PLD Bank 1 Rev 01 A B C D A B C D 5 5 L32 L31 M30 M29 N29 N28 L30 L29 K32 K31 K30 K29 J32 J31 H32 H31 G32 G31 F32 F31 E32 E31 H30 H29 G30 G29 F30 F29 E30 E29 D32 D31 T32 T31 T30 T29 D30 D29 proto1_IO8 proto1_IO9 proto1_IO10 proto1_IO11 proto1_IO12 proto1_IO13 proto1_IO14 proto1_IO15 proto1_IO16 proto1_IO17 proto1_IO18 proto1_IO19 proto1_IO20 proto1_IO21 proto1_IO22 proto1_IO23 proto1_IO24 proto1_IO25 proto1_IO26 proto1_IO27 proto1_IO28 proto1_IO29 proto1_IO30 proto1_IO31 proto1_IO32 proto1_IO33 proto1_IO34 proto1_IO35 proto1_IO36 proto1_IO37 proto1_IO38 proto1_IO39 proto1_CLKOUT 4 proto2_CLKOUT R31 R30 P32 P31 M32 M31 N31 N30 proto1_IO0 proto1_IO1 proto1_IO2 proto1_IO3 proto1_IO4 proto1_IO5 proto1_IO6 proto1_IO7 4 EP2S180F1020C3 proto2_IO[40:0] proto1_IO[40:0] 3 VREFB2N0.VREFB2N0 VREFB2N1.VREFB2N1 VREFB2N2.VREFB2N2 IO.DIFFIO_TX41p IO.DIFFIO_TX41n IO.DIFFIO_TX37p IO.DIFFIO_TX37n IO.DIFFIO_TX38p IO.DIFFIO_TX38n IO.DIFFIO_TX39p IO.DIFFIO_TX39n IO.DIFFIO_TX40p IO.DIFFIO_TX40n IO.DIFFIO_TX33p IO.DIFFIO_TX33n IO.DIFFIO_TX34p IO.DIFFIO_TX34n IO.DIFFIO_TX35p IO.DIFFIO_TX35n IO.DIFFIO_TX36p IO.DIFFIO_TX36n IO.DIFFIO_TX29p IO.DIFFIO_TX29n IO.DIFFIO_TX30p IO.DIFFIO_TX30n IO.DIFFIO_TX31p IO.DIFFIO_TX31n IO.DIFFIO_TX32p IO.DIFFIO_TX32n IO.DIFFIO_TX25p IO.DIFFIO_TX25n IO.DIFFIO_TX26p IO.DIFFIO_TX26n IO.DIFFIO_TX27p IO.DIFFIO_TX27n IO.DIFFIO_TX28p IO.DIFFIO_TX28n IO.DIFFIO_TX21p IO.DIFFIO_TX21n IO.DIFFIO_TX22p IO.DIFFIO_TX22n IO.DIFFIO_TX23p IO.DIFFIO_TX23n IO.DIFFIO_TX24p IO.DIFFIO_TX24n MICTOR[24:0] IO.CLK0p/DIFFIO_RX_C0p IO.CLK0n/DIFFIO_RX_C0n CLK1p.INPUT CLK1n.INPUT FPLL7CLKp.INPUT FPLL7CLKn.INPUT IO.DIFFIO_RX37p IO.DIFFIO_RX37n IO.DIFFIO_RX38p IO.DIFFIO_RX38n IO.DIFFIO_RX39p IO.DIFFIO_RX39n IO.DIFFIO_RX40p IO.DIFFIO_RX40n IO.DIFFIO_RX33p IO.DIFFIO_RX33n IO.DIFFIO_RX34p IO.DIFFIO_RX34n IO.DIFFIO_RX35p IO.DIFFIO_RX35n IO.DIFFIO_RX36p IO.DIFFIO_RX36n IO.DIFFIO_RX29p IO.DIFFIO_RX29n IO.DIFFIO_RX30p IO.DIFFIO_RX30n IO.DIFFIO_RX31p IO.DIFFIO_RX31n IO.DIFFIO_RX32p IO.DIFFIO_RX32n IO.DIFFIO_RX25p IO.DIFFIO_RX25n IO.DIFFIO_RX26p IO.DIFFIO_RX26n IO.DIFFIO_RX27p IO.DIFFIO_RX27n IO.DIFFIO_RX28p IO.DIFFIO_RX28n IO.DIFFIO_RX21p IO.DIFFIO_RX21n IO.DIFFIO_RX22p IO.DIFFIO_RX22n IO.DIFFIO_RX23p IO.DIFFIO_RX23n IO.DIFFIO_RX24p IO.DIFFIO_RX24n U18B PLD Bank 2 3 F28 J28 P30 K25 K24 K27 K26 L24 L23 J27 J26 H28 H27 N23 N22 M25 M24 L26 L25 M23 M22 P29 P28 N27 N26 N25 N24 M27 M26 R23 R22 R27 R26 P25 P24 P27 P26 T23 T22 T28 T27 R29 R28 R25 R24 MICTOR24 TR_CLK VCC3_3 proto2_IO37 proto2_IO38 proto2_IO29 proto2_IO30 proto2_IO31 proto2_IO32 proto2_IO33 proto2_IO34 proto2_IO35 proto2_IO36 33 proto1_IO40 proto1_CARDSEL_n proto2_IO26 proto2_IO27 proto2_IO28 R102 MICTOR16 MICTOR17 MICTOR18 MICTOR19 MICTOR20 MICTOR21 MICTOR22 MICTOR23 MICTOR8 MICTOR9 MICTOR10 MICTOR11 MICTOR12 MICTOR13 MICTOR14 MICTOR15 MICTOR0 MICTOR1 MICTOR2 MICTOR3 MICTOR4 MICTOR5 MICTOR6 MICTOR7 2 proto1_CARDSEL_n pld_MICTORCLK 2 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 18 of 40 Rev 01 A B C D A B C D 5 5 TRST TCK TMS TDI 5K6 R98 VCC3_3 4 evm_A2 evm_A3 evm_A4 evm_A5 evm_A6 evm_A7 evm_A8 evm_A9 evm_A10 evm_A11 evm_A12 evm_A13 evm_A14 evm_A15 evm_A16 evm_A17 evm_A18 evm_A19 evm_A20 evm_A21 evm_D0 evm_D1 evm_D2 evm_D3 evm_D4 evm_D5 evm_D6 evm_D7 evm_D8 evm_D9 evm_D10 evm_D11 evm_D12 evm_D13 evm_D14 evm_D15 evm_D16 evm_D17 evm_D18 evm_D19 evm_D20 evm_D21 evm_D22 evm_D23 evm_D24 evm_D25 evm_D26 evm_D27 4 U18C TRST.TRST TCK.TCK TMS.TMS TDI.TDI IO.DQ10T0 IO.DQ10T1 IO.DQ10T2 IO.DQ10T3 IO.DQ11T0 IO.DQ11T1 IO.DQ11T2 IO.DQ11T3 IO.DQ12T0 IO.DQ12T1 IO.DQ12T2 IO.DQ12T3 IO.DQ13T0 IO.DQ13T1 IO.DQ13T2 IO.DQ13T3 IO.DQ14T0 IO.DQ14T1 IO.DQ14T2 IO.DQ14T3 IO.DQ15T0 IO.DQ15T1 IO.DQ15T2 IO.DQ15T3 IO.DQ16T0 IO.DQ16T1 IO.DQ16T2 IO.DQ16T3 IO.DQ17T0 IO.DQ17T1 IO.DQ17T2 IO.DQ17T3 IO.DQS10T IO.DQS11T IO.DQS12T IO.DQS13T IO.DQS14T IO.DQS15T IO.DQS16T IO.DQS17T IO.DQSn10T IO.DQSn11T IO.DQSn12T IO.DQSn13T IO.DQSn14T IO.DQSn15T IO.DQSn16T IO.DQSn17T EP2S180F1020C3 AK30 AF24 AE24 AL31 B20 E19 C20 E20 A21 C21 A22 C22 D23 D21 F22 F23 A23 C23 C24 A24 A25 A26 D26 C26 E24 C25 E27 E26 A27 A28 D27 C27 B29 A29 D28 E28 D19 B21 D22 B23 B25 D25 B27 C28 D20 B22 E22 B24 B26 E25 B28 C29 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO pld_CONFIG_D[7:0] pld_PGM[2:0] evm_BE_n[3:0] evm_D[31:0] evm_A[21:2] 3 TDO.TDO VREFB3N0.VREFB3N0 VREFB3N1.VREFB3N1 VREFB3N2.VREFB3N2 IO.CLK14p IO.CLK14n IO.CLK15p IO.CLK15n IO.DATA0 IO.DATA1 IO.DATA2 IO.DATA3 IO.DATA4 IO.DATA5 IO.DATA6 IO.DATA7 IO.PGM0 IO.PGM1 IO.PGM2 DCLK.DCLK IO.ASDO nSTATUS.nSTATUS nCE.nCE IO.RDYnBSY IO.nCSO IO.INIT_DONE CONF_DONE.CONF_DONE 3 evm_FSR0 evm_DX0 evm_DR0 pld_DCLK K21 J21 H22 B31 F17 B30 C30 H24 G19 G25 J25 C3 C19 D24 C31 TDO VCC3_3 pld_CONFIG_D0 pld_CONFIG_D1 pld_CONFIG_D2 pld_CONFIG_D3 pld_CONFIG_D4 pld_CONFIG_D5 pld_CONFIG_D6 pld_CONFIG_D7 H19 F20 G23 H23 J23 L22 F24 G24 A17 B17 C17 D17 pld_PGM0 pld_PGM1 pld_PGM2 E17 F19 F18 pld_INIT_DONE pld_CONFIG_DONE pld_STATUS_n evm_ARE_n evm_AOE_n evm_AW E_n evm_ARDY evm_ACE2_n evm_CLKX0 evm_FSX0 evm_CLKR0 evm_D28 evm_D29 evm_D30 evm_D31 evm_BE_n0 evm_BE_n1 evm_BE_n2 evm_BE_n3 K20 K18 L20 H21 J20 J22 G22 K22 L21 G21 L18 J19 H20 L19 K19 G20 PLD Bank 3 2 R94 0_jump TDI TCK TDO TMS RP20 VCC3_3 1K 2 4 6 8 10 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 2 4 6 8 10 R95 2x5Shrouded 1 3 5 7 9 J21 1 Sheet 19 10K 10K of 40 Rev 01 VCC3_3 TRST_PU VCC3_3 male header JTAG connections: pin# jtag 1 TCK 2 GND 3 TDO 4 Vcc 5 TMS 6 Vccio 7 (NC) 8 (NC) 9 TDI 10 GND pld_CONFIG_DONE R97 pld_STATUS_n 10p C106 1 3 5 7 9 1 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 330 R96 Do not stuff R94 TRST 2 8 7 6 5 1 2 3 4 A B C D A B C D 5 5 E13 F13 G13 F15 B14 D14 D13 A14 C4 C5 B5 B6 D7 C7 B8 B9 vga_CLOCK vga_SYNC_n vga_BLANK_n vga_HSYNC vga_VSYNC cpld_USER0 cpld_USER1 cpld_USER2 hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP 4 E11 G10 G11 G12 D12 A11 B11 A12 vga_G0 vga_G1 vga_G2 vga_G3 vga_G4 vga_G5 vga_G6 vga_G7 pld_RECONFIGREQ_n evm_ACE3_n evm_INT2 evm_INT3 F14 E14 C13 B13 F9 E9 C10 C11 F11 F12 C12 B12 D8 E8 F8 F10 A10 B10 D10 D11 vga_R0 vga_R1 vga_R2 vga_R3 vga_R4 vga_R5 vga_R6 vga_R7 hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP B7 E7 E6 A7 C9 A8 C8 A9 B4 D5 E5 A4 A5 D6 C6 A6 vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 pld_LED0 pld_LED1 pld_LED2 pld_LED3 pld_LED4 pld_LED5 pld_LED6 pld_LED7 4 vga_G[7:0] vga_R[7:0] vga_B[7:0] user_PB[3:0] pld_MSEL[3:0] evm_INT[3:0] cpld_USER[2:0] pld_LED[7:0] EP2S180F1020C3 IO.DQS8T IO.DQSn8T IO.DQS9T IO.DQSn9T IO.DQS4T IO.DQSn4T IO.DQS5T IO.DQSn5T IO.DQS6T IO.DQSn6T IO.DQS7T IO.DQSn7T IO.DQS0T IO.DQSn0T IO.DQS1T IO.DQSn1T IO.DQS2T IO.DQSn2T IO.DQS3T IO.DQSn3T IO.DQ8T0 IO.DQ8T1 IO.DQ8T2 IO.DQ8T3 IO.DQ9T0 IO.DQ9T1 IO.DQ9T2 IO.DQ9T3 IO.DQ6T0 IO.DQ6T1 IO.DQ6T2 IO.DQ6T3 IO.DQ7T0 IO.DQ7T1 IO.DQ7T2 IO.DQ7T3 IO.DQ4T0 IO.DQ4T1 IO.DQ4T2 IO.DQ4T3 IO.DQ5T0 IO.DQ5T1 IO.DQ5T2 IO.DQ5T3 IO.DQ2T0 IO.DQ2T1 IO.DQ2T2 IO.DQ2T3 IO.DQ3T0 IO.DQ3T1 IO.DQ3T2 IO.DQ3T3 IO.DQ0T0 IO.DQ0T1 IO.DQ0T2 IO.DQ0T3 IO.DQ1T0 IO.DQ1T1 IO.DQ1T2 IO.DQ1T3 U18D MSEL0.MSEL0 MSEL1.MSEL1 MSEL2.MSEL2 MSEL3.MSEL3 VREFB4N0.VREFB4N0 VREFB4N1.VREFB4N1 VREFB4N2.VREFB4N2 IO.CLK12p IO.CLK12n IO.CLK13p IO.CLK13n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 3 B2 F6 J10 H10 C2 D9 C14 A16 B16 E16 F16 L14 J14 K14 J15 L13 J13 K12 H13 L12 J12 H12 K11 J11 H11 K13 H14 K16 K17 L17 K15 L16 L15 3 R103 pld_MSEL0 pld_MSEL1 pld_MSEL2 pld_MSEL3 VCC3_3 pld_CLKIN1 pld_CLKIN1_n pld_DACCLKIN evm_INT1 33 user_PB0 user_PB1 user_PB2 user_PB3 evm_IACK evm_INUM0 evm_CNTL0 evm_STAT0 evm_DMAC0 evm_CLKOUT2 evm_RESET evm_INT0 DTR1 DCD1 DSR1 RI1 TXD1 CTS1 RXD1 RTS1 pld_CLKOUT PLD Bank 4 2 2 137 137 R106 90R9 R105 VCC3_3 137 R104 90R9 R101 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 90R9 R100 VCC3_3 pld_DACCLKIN pld_CLKIN1 pld_CLKIN1_n R99 VCC3_3 1 20 of 40 Rev 01 A B C D A B C D 5 5 4 4 F1 F2 G3 G4 G1 G2 J3 J4 H1 H2 J1 J2 K3 K4 K1 K2 L3 L4 N4 N5 M3 M4 L1 L2 N2 N3 M1 M2 R2 R3 P1 P2 adcA_D8 adcA_D9 adcA_D10 adcA_D11 adcB_D0 adcB_D1 adcB_D2 adcB_D3 adcB_D4 adcB_D5 adcB_D6 adcB_D7 adcB_D8 adcB_D9 adcB_D10 adcB_D11 adi_D0 adi_D1 adi_D2 adi_D3 adi_D4 adi_D5 adi_D6 adi_D7 adi_D8 adi_D9 adi_D10 adi_D11 adi_D12 adi_D13 adi_D14 adi_D15 T1 T2 T3 T4 D3 D4 D1 D2 E3 E4 E1 E2 F3 F4 adcA_D0 adcA_D1 adcA_D2 adcA_D3 adcA_D4 adcA_D5 adcA_D6 adcA_D7 adcB_D[11:0] adcA_D[11:0] adi_D[33:0] EP2S180F1020C3 IO.CLK10p/DIFFIO_RX_C3p IO.CLK10n/DIFFIO_RX_C3n CLK11p.INPUT CLK11n.INPUT FPLL10CLKp.INPUT FPLL10CLKn.INPUT IO.DIFFIO_RX59p IO.DIFFIO_RX59n IO.DIFFIO_RX60p IO.DIFFIO_RX60n IO.DIFFIO_RX61p IO.DIFFIO_RX61n IO.DIFFIO_RX62p IO.DIFFIO_RX62n IO.DIFFIO_RX55p IO.DIFFIO_RX55n IO.DIFFIO_RX56p IO.DIFFIO_RX56n IO.DIFFIO_RX57p IO.DIFFIO_RX57n IO.DIFFIO_RX58p IO.DIFFIO_RX58n IO.DIFFIO_RX51p IO.DIFFIO_RX51n IO.DIFFIO_RX52p IO.DIFFIO_RX52n IO.DIFFIO_RX53p IO.DIFFIO_RX53n IO.DIFFIO_RX54p IO.DIFFIO_RX54n IO.DIFFIO_RX47p IO.DIFFIO_RX47n IO.DIFFIO_RX48p IO.DIFFIO_RX48n IO.DIFFIO_RX49p IO.DIFFIO_RX49n IO.DIFFIO_RX50p IO.DIFFIO_RX50n IO.DIFFIO_RX43p IO.DIFFIO_RX43n IO.DIFFIO_RX44p IO.DIFFIO_RX44n IO.DIFFIO_RX45p IO.DIFFIO_RX45n IO.DIFFIO_RX46p IO.DIFFIO_RX46n U18E IO.DIFFIO_TX58p IO.DIFFIO_TX58n IO.DIFFIO_TX59p IO.DIFFIO_TX59n IO.DIFFIO_TX60p IO.DIFFIO_TX60n IO.DIFFIO_TX61p IO.DIFFIO_TX61n IO.DIFFIO_TX62p IO.DIFFIO_TX62n IO.DIFFIO_TX54p IO.DIFFIO_TX54n IO.DIFFIO_TX55p IO.DIFFIO_TX55n IO.DIFFIO_TX56p IO.DIFFIO_TX56n IO.DIFFIO_TX57p IO.DIFFIO_TX57n IO.DIFFIO_TX50p IO.DIFFIO_TX50n IO.DIFFIO_TX51p IO.DIFFIO_TX51n IO.DIFFIO_TX52p IO.DIFFIO_TX52n IO.DIFFIO_TX53p IO.DIFFIO_TX53n IO.DIFFIO_TX46p IO.DIFFIO_TX46n IO.DIFFIO_TX47p IO.DIFFIO_TX47n IO.DIFFIO_TX48p IO.DIFFIO_TX48n IO.DIFFIO_TX49p IO.DIFFIO_TX49n IO.DIFFIO_TX42p IO.DIFFIO_TX42n IO.DIFFIO_TX43p IO.DIFFIO_TX43n IO.DIFFIO_TX44p IO.DIFFIO_TX44n IO.DIFFIO_TX45p IO.DIFFIO_TX45n 3 P3 J5 F5 R6 R7 R4 R5 R10 R11 T5 T6 T10 T11 P8 P9 P6 P7 P4 P5 P10 P11 M8 M9 M6 M7 N6 N7 N8 N9 L7 L8 K6 K7 L5 L6 M10 M11 J6 J7 J8 J9 K8 K9 L9 L10 PLD Bank 5 VREFB5N0.VREFB5N0 VREFB5N1.VREFB5N1 VREFB5N2.VREFB5N2 3 VCC3_3 fan_TACH fan_EN_n adi_D32 adi_D33 adi_D24 adi_D25 adi_D26 adi_D27 adi_D28 adi_D29 adi_D30 adi_D31 adi_D16 adi_D17 adi_D18 adi_D19 adi_D20 adi_D21 adi_D22 adi_D23 2 2 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 21 of 40 Rev 01 A B C D A B C D 5 5 pld_CLKFB 137 R108 90R9 R107 VCC3_3 AC1 AC2 AC3 AC4 AD1 AD2 AE1 AE2 AE3 AE4 AF1 AF2 AF3 AF4 AG1 AG2 AG3 AG4 AH1 AH2 AH3 AH4 AJ1 AJ2 cf_IO16 cf_IO17 cf_IO18 cf_IO19 cf_IO20 cf_IO21 cf_IO22 cf_IO23 cf_IO24 cf_IO25 cf_IO26 cf_IO27 cf_IO28 cf_IO29 cf_IO30 audio_LRCIN audio_LRCOUT audio_BCLK audio_CS_n audio_SDIN audio_SCLK audio_MODE audio_DOUT audio_DIN 4 U1 U2 U3 U4 AJ3 AJ4 AA3 AA4 Y4 Y5 AB1 AB2 AB3 AB4 cf_IO8 cf_IO9 cf_IO10 cf_IO11 cf_IO12 cf_IO13 cf_IO14 cf_IO15 pld_CLKFB V2 V3 W1 W2 Y2 Y3 AA1 AA2 cf_IO0 cf_IO1 cf_IO2 cf_IO3 cf_IO4 cf_IO5 cf_IO6 cf_IO7 4 U18F EP2S180F1020C3 IO.DIFFIO_TX83p IO.DIFFIO_TX83n IO.DIFFIO_TX79p IO.DIFFIO_TX79n IO.DIFFIO_TX80p IO.DIFFIO_TX80n IO.DIFFIO_TX81p IO.DIFFIO_TX81n IO.DIFFIO_TX82p IO.DIFFIO_TX82n IO.DIFFIO_TX75p IO.DIFFIO_TX75n IO.DIFFIO_TX76p IO.DIFFIO_TX76n IO.DIFFIO_TX77p IO.DIFFIO_TX77n IO.DIFFIO_TX78p IO.DIFFIO_TX78n IO.DIFFIO_TX71p IO.DIFFIO_TX71n IO.DIFFIO_TX72p IO.DIFFIO_TX72n IO.DIFFIO_TX73p IO.DIFFIO_TX73n IO.DIFFIO_TX74p IO.DIFFIO_TX74n IO.DIFFIO_TX67p IO.DIFFIO_TX67n IO.DIFFIO_TX68p IO.DIFFIO_TX68n IO.DIFFIO_TX69p IO.DIFFIO_TX69n IO.DIFFIO_TX70p IO.DIFFIO_TX70n IO.DIFFIO_TX63p IO.DIFFIO_TX63n IO.DIFFIO_TX64p IO.DIFFIO_TX64n IO.DIFFIO_TX65p IO.DIFFIO_TX65n IO.DIFFIO_TX66p IO.DIFFIO_TX66n dacB_D[14:1] dacA_D[14:1] 3 VREFB6N0.VREFB6N0 VREFB6N1.VREFB6N1 VREFB6N2.VREFB6N2 cf_IO[41:0] IO.CLK8p/DIFFIO_RX_C2p IO.CLK8n/DIFFIO_RX_C2n CLK9p.INPUT CLK9n.INPUT FPLL9CLKp.INPUT FPLL9CLKn.INPUT IO.DIFFIO_RX79p IO.DIFFIO_RX79n IO.DIFFIO_RX80p IO.DIFFIO_RX80n IO.DIFFIO_RX81p IO.DIFFIO_RX81n IO.DIFFIO_RX82p IO.DIFFIO_RX82n IO.DIFFIO_RX75p IO.DIFFIO_RX75n IO.DIFFIO_RX76p IO.DIFFIO_RX76n IO.DIFFIO_RX77p IO.DIFFIO_RX77n IO.DIFFIO_RX78p IO.DIFFIO_RX78n IO.DIFFIO_RX71p IO.DIFFIO_RX71n IO.DIFFIO_RX72p IO.DIFFIO_RX72n IO.DIFFIO_RX73p IO.DIFFIO_RX73n IO.DIFFIO_RX74p IO.DIFFIO_RX74n IO.DIFFIO_RX67p IO.DIFFIO_RX67n IO.DIFFIO_RX68p IO.DIFFIO_RX68n IO.DIFFIO_RX69p IO.DIFFIO_RX69n IO.DIFFIO_RX70p IO.DIFFIO_RX70n IO.DIFFIO_RX63p IO.DIFFIO_RX63n IO.DIFFIO_RX64p IO.DIFFIO_RX64n IO.DIFFIO_RX65p IO.DIFFIO_RX65n IO.DIFFIO_RX66p IO.DIFFIO_RX66n 3 AG5 AD5 W3 AD8 AD9 AC6 AC7 AB7 AB8 AB9 AB10 AC8 AC9 AA10 AA11 AA6 AA7 AD6 AD7 AA8 AA9 Y6 Y7 Y8 Y9 Y10 Y11 AB5 AB6 V4 V5 W8 W9 W6 W7 W4 W5 U5 U6 U10 U11 V9 V10 V6 V7 VCC3_3 cf_IO35 cf_IO36 cf_IO37 cf_IO38 cf_IO39 cf_IO40 cf_IO41 cf_CS_n dacB_D11 dacB_D12 dacB_D13 dacB_D14 cf_IO31 cf_IO32 cf_IO33 cf_IO34 dacB_D3 dacB_D4 dacB_D5 dacB_D6 dacB_D7 dacB_D8 dacB_D9 dacB_D10 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 dacB_D1 dacB_D2 dacA_D1 dacA_D2 dacA_D3 dacA_D4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 2 2 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 22 of 40 PLD Bank 6 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 1 Rev 01 A B C D A B C D 5 5 4 4 AL4 AJ5 AH5 AM4 AG9 AH6 AH7 AH9 AM5 AK6 AJ6 AM6 AM7 AK7 AJ7 AM8 AJ10 AK8 AJ8 AM9 AF12 AG10 AF10 AG12 AJ11 AH11 AL10 AM10 AK12 AJ12 AM11 AM12 AH13 AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AK4 AK5 AG8 AH8 AL5 AL6 AL7 AL8 AK9 AL9 AF11 AG11 AK10 AK11 AL11 AL12 AG14 AH14 AK13 AL13 sdram_DQ0 sdram_DQ1 sdram_DQ2 sdram_DQ3 sdram_DQ4 sdram_DQ5 sdram_DQ6 sdram_DQ7 sdram_DQ8 sdram_DQ9 sdram_DQ10 sdram_DQ11 sdram_DQ12 sdram_DQ13 sdram_DQ14 sdram_DQ15 sdram_DQ16 sdram_DQ17 sdram_DQ18 sdram_DQ19 sdram_DQ20 sdram_DQ21 sdram_DQ22 sdram_DQ23 sdram_DQ24 sdram_DQ25 sdram_DQ26 sdram_DQ27 sdram_DQ28 sdram_DQ29 sdram_DQ30 sdram_DQ31 sdram_DQ32 sdram_DQ33 sdram_DQ34 sdram_DQ35 sdram_DQ36 sdram_DQ37 sdram_DQ38 sdram_DQ39 sdram_RAS_n sdram_DQM0 sdram_DQM1 sdram_DQM2 sdram_DQM3 sdram_CS_n sdram_CKE sdram_CAS_n sdram_W E_n sdram_BA0 sdram_BA1 sram_BE_n0 sram_BE_n1 sram_BE_n2 sram_BE_n3 sram_CS_n sram_OE_n sram_W E_n sdram_DQM4 sdram_DQM5 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 2 <Core Design> Do Not stuff R113 PLL_ENA 330 R113 5K6 R111 VCC3_3 PORSEL Do Not stuff R112 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 VCC3_3 sram_BE_n[3:0] AK14 AJ9 AK2 AM16 AL16 AH16 AG16 IO_PULLUP_n Do Not stuff R109 23 330 of R114 5K6 R112 VCC3_3 330 R110 5K6 R109 VCC3_3 PLD Bank 7 1 Altera Corp. 3 cf_ATASEL_n cf_POW ER cf_PRESENT_n cf_RESET_n sdram_DQM6 sdram_DQM7 AD12 AB11 AC15 AE12 AB12 AC12 AL2 AF8 AK3 AL3 sdram_A8 sdram_A9 sdram_A10 sdram_A11 se_D28 se_D29 se_D30 se_D31 AB15 AC16 AB16 AE13 AC13 AD10 AC11 AE11 PORSEL PLL_ENA IO_PULLUP_n sdram_A0 sdram_A1 sdram_A2 sdram_A3 sdram_A4 sdram_A5 sdram_A6 sdram_A7 AD11 AD13 AB13 AE14 AB14 AC14 AD14 AE10 2 sdram_DQM[7:0] sdram_BA[1:0] sdram_A[11:0] VREFB7N0.VREFB7N0 VREFB7N1.VREFB7N1 VREFB7N2.VREFB7N2 IO.CLK6p IO.CLK6n IO.CLK7p IO.CLK7n PORSEL.PORSEL PLL_ENA.PLL_ENA nIO_PULLUP.nIO_PULLUP nCEO.nCEO sdram_DQ[63:0] se_D[31:0] EP2S180F1020C3 IO.DQS0B IO.DQSn0B IO.DQS1B IO.DQSn1B IO.DQS2B IO.DQSn2B IO.DQS3B IO.DQSn3B IO.DQS4B IO.DQSn4B IO.DQS5B IO.DQSn5B IO.DQS6B IO.DQSn6B IO.DQS7B IO.DQSn7B IO.DQS8B IO.DQSn8B IO.DQS9B IO.DQSn9B IO.DQ0B0 IO.DQ0B1 IO.DQ0B2 IO.DQ0B3 IO.DQ1B0 IO.DQ1B1 IO.DQ1B2 IO.DQ1B3 IO.DQ2B0 IO.DQ2B1 IO.DQ2B2 IO.DQ2B3 IO.DQ3B0 IO.DQ3B1 IO.DQ3B2 IO.DQ3B3 IO.DQ4B0 IO.DQ4B1 IO.DQ4B2 IO.DQ4B3 IO.DQ5B0 IO.DQ5B1 IO.DQ5B2 IO.DQ5B3 IO.DQ6B0 IO.DQ6B1 IO.DQ6B2 IO.DQ6B3 IO.DQ7B0 IO.DQ7B1 IO.DQ7B2 IO.DQ7B3 IO.DQ8B0 IO.DQ8B1 IO.DQ8B2 IO.DQ8B3 IO.DQ9B0 IO.DQ9B1 IO.DQ9B2 IO.DQ9B3 U18G 3 40 Rev 01 A B C D A B C D 5 5 AK20 AJ20 AL21 AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AL26 AL27 AL28 AK28 AK29 se_A9 se_A10 se_A11 se_A12 se_A13 se_A14 se_A15 se_A16 se_A17 se_A18 se_A19 se_D23 se_D24 se_D25 se_D26 se_D27 4 AL20 AH19 AJ19 AH20 AM21 AK21 AJ21 AM22 AJ23 AK22 AG22 AG23 AM23 AK23 AK24 AM24 AK25 AH24 AH26 AG24 AM26 AM25 AJ26 AK26 AM27 AM28 AJ27 AK27 AL29 AM29 AJ28 AH28 sdram_DQ40 sdram_DQ41 sdram_DQ42 sdram_DQ43 sdram_DQ44 sdram_DQ45 sdram_DQ46 sdram_DQ47 sdram_DQ48 sdram_DQ49 sdram_DQ50 sdram_DQ51 sdram_DQ52 sdram_DQ53 sdram_DQ54 sdram_DQ55 sdram_DQ56 sdram_DQ57 sdram_DQ58 sdram_DQ59 sdram_DQ60 sdram_DQ61 sdram_DQ62 sdram_DQ63 se_A1 se_A2 se_A3 se_A4 se_A5 se_A6 se_A7 se_A8 4 IO.CLK4p IO.CLK4n IO.CLK5p IO.CLK5n nCONFIG.nCONFIG IO.RUnLU IO.nWS IO.nRS IO.nCS IO.DEV_OE IO.DEV_CLRn IO.CS IO.CLKUSR VCCSEL.VCCSEL IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB8N0.VREFB8N0 VREFB8N1.VREFB8N1 VREFB8N2.VREFB8N2 proto2_IO[40:0] se_A[19:1] se_D[31:0] sdram_DQ[63:0] EP2S180F1020C3 IO.DQS10B IO.DQSn10B IO.DQS11B IO.DQSn11B IO.DQS12B IO.DQSn12B IO.DQS13B IO.DQSn13B IO.DQS14B IO.DQSn14B IO.DQS15B IO.DQSn15B IO.DQS16B IO.DQSn16B IO.DQS17B IO.DQSn17B IO.DQ10B0 IO.DQ10B1 IO.DQ10B2 IO.DQ10B3 IO.DQ11B0 IO.DQ11B1 IO.DQ11B2 IO.DQ11B3 IO.DQ12B0 IO.DQ12B1 IO.DQ12B2 IO.DQ12B3 IO.DQ13B0 IO.DQ13B1 IO.DQ13B2 IO.DQ13B3 IO.DQ14B0 IO.DQ14B1 IO.DQ14B2 IO.DQ14B3 IO.DQ15B0 IO.DQ15B1 IO.DQ15B2 IO.DQ15B3 IO.DQ16B0 IO.DQ16B1 IO.DQ16B2 IO.DQ16B3 IO.DQ17B0 IO.DQ17B1 IO.DQ17B2 IO.DQ17B3 U18H AC21 AD21 AB21 AE21 AG20 AF21 AD22 AF22 pld_CONFIG_n pld_RU_n_LU pld_CLKIN0 pld_CLKIN0_n proto2_IO39 proto2_IO40 VCC3_3 AM17 AL17 AK17 AJ17 AK31 AJ24 AK19 pld_CLEAR_n AL30 AG17 AE23 AF23 AG18 AH17 AG19 AC22 AD23 AC23 330 R119 proto2_CARDSEL_n PLD Bank 8 se_D16 se_D17 se_D18 se_D19 se_D20 se_D21 se_D22 proto2_CARDSEL_n se_D8 se_D9 se_D10 se_D11 se_D12 se_D13 se_D14 se_D15 AE22 AC17 AE19 AD19 AC18 AB17 AC19 AF19 se_D0 se_D1 se_D2 se_D3 se_D4 se_D5 se_D6 se_D7 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 3 3 1 TP4 2 VIA_TP 1 2 Label this button very clearly with the words. CPU RESET and put a box around the button and text. 1 2 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title pld_CLKIN0_n pld_CLKIN0 1 Sheet 24 pld_CONFIG_n 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> PBswitch 5K6 SW 8 3 4 R117 VCC3_3 1 of 40 5K6 R227 VCC3_3 137 R120 90R9 R118 VCC3_3 137 R116 90R9 R115 VCC3_3 Rev 01 A B C D A B C D 5 5 4 4 L28 AD4 AF28 G28 AD29 P22 AC29 AC30 AD3 J29 J30 L27 W23 N10 N11 F21 P23 W10 W11 W22 AF27 AD30 AE5 AE6 AE9 AF5 AF6 AF14 G14 G27 AG21 AG25 H4 F25 G5 G6 H6 H5 H3 H9 EP2S180F1020C3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC U18J IO.PLL12_OUT0p IO.PLL12_OUT0n IO.PLL12_OUT1p IO.PLL12_OUT1n IO.PLL12_FBp/OUT2p IO.PLL12_FBn/OUT2n IO.PLL11_OUT0p IO.PLL11_OUT0n IO.PLL11_OUT1p IO.PLL11_OUT1n IO.PLL11_FBp/OUT2p IO.PLL11_FBn/OUT2n IO.PLL6_OUT0p IO.PLL6_OUT0n IO.PLL6_OUT1p IO.PLL6_OUT1n IO.PLL6_FBp/OUT2p IO.PLL6_FBn/OUT2n IO.PLL5_OUT0p IO.PLL5_OUT0n IO.PLL5_OUT1p IO.PLL5_OUT1n IO.PLL5_FBp/OUT2p IO.PLL5_FBn/OUT2n 33 R127 3 33 33 R126 B18 C18 D18 E18 A19 B19 R128 33 R125 AK16 AJ16 AJ15 AH15 AL15 AK15 AL18 AK18 AJ18 AH18 AM19 AL19 33 33 33 33 R121 R122 R123 R124 B15 C15 C16 D16 D15 E15 3 audio_CLK adc_PLLCLK2 adc_PLLCLK1 sdram_CLK dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n 2 2 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 25 of 40 Rev 01 PLD Control Signals 1 A B C D A B C D 1 2 3 1x3Header 1 2 3 J36 5 5 1 VCC5 fan_TACH fan_EN_n 20K R226 5K6 R225 10K R224 10K 0u001 R223 VCC3_3 0u1 C408 C409 FDV305N Q7 VCC5 3 2 4 VCC3_3 VCC3_3 4 T26 T25 U26 U8 V8 T8 R8 H16 G16 AE16 AD16 G26 F26 AG27 AF7 AG7 G8 G18 H18 AE17 AD17 Y21 V21 N21 R21 M18 M20 M15 M13 N12 R12 V12 Y12 AA15 AA13 AA18 AA20 AK32 V32 AA28 U21 R32 M28 C32 T21 A18 A30 M17 E21 A15 A3 M16 E12 M5 C1 T12 R1 AK1 U12 V1 AA5 AM3 AM15 AH12 AA16 AM18 AA17 AM30 AH21 N19 N17 R15 R19 Y14 N15 N13 W21 T20 Y16 P18 M21 P20 V14 R13 AA12 R17 Y20 T14 T16 T18 V16 U13 Y18 U17 P16 U19 W19 K10 AC10 V20 K23 W17 W15 P14 W13 V18 U15 VCC1_2 EP2S180F1020C3 GNDA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL3 GNDA_PLL3 GNDA_PLL4 GNDA_PLL4 GNDA_PLL5 GNDA_PLL5 GNDA_PLL6 GNDA_PLL6 GNDA_PLL7 GNDA_PLL7 GNDA_PLL8 GNDA_PLL9 GNDA_PLL9 GNDA_PLL10 GNDA_PLL11 GNDA_PLL11 GNDA_PLL12 GNDA_PLL12 VCCPD1 VCCPD1 VCCPD2 VCCPD2 VCCPD3 VCCPD3 VCCPD4 VCCPD4 VCCPD5 VCCPD5 VCCPD6 VCCPD6 VCCPD7 VCCPD7 VCCPD8 VCCPD8 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT U18I GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND TEMPDIODEp TEMPDIODEn VCCD_PLL1 VCCD_PLL2 VCCD_PLL3 VCCD_PLL4 VCCD_PLL5 VCCD_PLL6 VCCD_PLL7 VCCD_PLL8 VCCD_PLL9 VCCD_PLL10 VCCD_PLL11 VCCD_PLL12 VCCA_PLL1 VCCA_PLL2 VCCA_PLL3 VCCA_PLL4 VCCA_PLL5 VCCA_PLL6 VCCA_PLL7 VCCA_PLL8 VCCA_PLL9 VCCA_PLL10 VCCA_PLL11 VCCA_PLL12 VCC_PLL5_OUT VCC_PLL6_OUT VCC_PLL11_OUT VCC_PLL12_OUT Y17 Y13 W16 W14 W12 Y1 W20 W18 V17 V15 V13 V11 U20 U18 U16 U14 T19 T17 V27 V22 V19 Y32 Y19 R16 Y15 P21 P19 P17 P15 P13 P12 N32 N20 N18 N16 N14 N1 M19 M14 M12 L11 K28 K5 J24 G17 F27 F7 E23 E10 B32 B1 AM31 AM20 AM13 AM2 AL32 AL1 AH27 AH23 AH10 AG6 AF17 AC28 AC5 AB22 AA21 AA19 AA14 A31 A20 A13 A2 T15 T13 T7 R20 R18 R14 AF9 G9 B3 U24 V25 U7 T9 H15 AD15 H25 AF25 AE8 H7 J18 AE18 T24 V26 U9 R9 G15 AE15 H26 AF26 AE7 H8 H17 AF18 J16 AF15 J17 AF16 3 VCCD_PLL VCCA_PLL VCC_PLL5 VCC_PLL6 VCC_PLL11 VCC_PLL12 3 1 TM1 0u1 2 2u2 0u1 2 2u2 0u1 2 2u2 0u1 2 2u2 0u1 2 2u2 1u C130 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u1 C359 C360 C361 C362 C363 C364 C365 C366 VCC1_2 2 VCC3_3 1 0u1 0u1 VCC3_3 0u1 0u1 0u1 0u1 0u1 0u1 0u1 0u001 0u001 C357 C358 VCC3_3 0u1 0u1 Thursday, August 18, 2005 Date: 1 DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size C 10u 26 C192 Sheet 0u1 of 0u1 10u 40 C193 VCC1_2 10u 0u1 C165 VCC3_3 0u1 C329 C330 C331 C332 C333 C334 C335 C336 0u1 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Title PLD Power C321 C322 C323 C324 C325 C326 C327 C328 Altera Corp. <Core Design> 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u1 C347 C348 C349 C350 C351 C352 C353 C354 C355 C356 0u1 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u1 C337 C338 C339 C340 C341 C342 C343 C344 C345 C346 0u1 VCC3_3 0u1 VCC1_2 0u1 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u1 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 0u1 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u001 0u1 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 0u1 VCC3_3 0u1 VCC1_2 0u1 0u1 L21 SMFerrite C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 2u2 VCC1_2 1u C126 VCC1_2 1u C122 VCC3_3 1u C118 VCC3_3 1u C114 VCC3_3 1u C110 VCC3_3 0u1 0u1 1 L20 SMFerrite 1 L19 SMFerrite 1 L18 SMFerrite 1 1 L17 SMFerrite L16 SMFerrite 1 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 0u01 C127 C128 C129 0u01 C123 C124 C125 0u01 C119 C120 C121 0u01 C115 C116 C117 0u01 C111 C112 C113 0u01 C107 C108 C109 2 VCC3_3 VCCD_PLL VCCA_PLL VCC_PLL12 VCC_PLL11 VCC_PLL6 VCC_PLL5 VCC1_2 Test_Header Test_Header TM2 1 1 1 2 Rev 01 A B C D A B C D C278 10u C277 68u Vunreg NOSTUFF C267 68p C267 5 0u1 0u001 470p 5 7 2 100K R143 6 3 5 2 1 9 4 NC ON/OFF Vin U23 POW ER_ON POW ER_ON C270 10K R145 INTVCC1_2 C419 C420 5 0u1 Vout CBoost 3 1 4 13 7 10 15 14 16 11 12 8 Diode_3A D16 0u01 C275 0u1 1 C269 L25 22uH VSENSE1_2 1M4 4R7 R141R142 VCC8OUT C395 PGND ION VIN TG SW BOOST INTVCC BG VFB 4 LM2678_ADJ 6 Feedback LTC1778 GND VRNG ITH PGOOD RUN.SS EXTVCC FCB U21 GND GND 4 8 2 C282 100u 100u R148 C281 1K R147 4u7 C268 5K62 100u C283 4 4 3 0u1 0u001 C400 C401 INTVCC1_2 VCC8 CMDSH2_3 D14 0u22 C260 3 Q5 FDS6680A 5 6 7 8 1 2 3 100 R150 JUMPERS XX1 2 Q6 FDS6680A 5 6 7 8 1 2 3 100u C271 0u1 1 2 1 2 2X1Header 1 2 2X1Header J39 1 2 1 2 1 2 0u001 C273 3 2K 2 100u C262 LT1085_ADJ Vin U22 R146 1K R144 2X1Header J38 J37 C272 VCC8IN 3300p C266 0u001 VSENSE1_2 L24 2u8H 3 2 0u1 C411 C412 Note jumpers should always be installed to connect AGND to DGND uless and external GND sourse is being used. L27 10uH 1 MBRS340 D15 1 68u C259 Vunreg 2 1 2 4 100u C264 0u1 JUMPERS XL28 0u001 C413 C414 0u1 0u001 C415 C416 365 R151 121 R149 2 15u Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title AVCC5 0u1 1 Sheet 27 of 0u001 0u1 40 Rev 01 AGND 0u001 100u C417 C418 C396 C397 C274 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 10u C279 C280 L28 10uH 1 NOSTUFF L28 and replace with a copper wire 100u C265 Altera Corp. <Core Design> ADJ Vout VoutT 100u C263 VCC1_2 Power Connector 1 A B C D A B C NC 1 NC FID3 1 NC FID4 1 1 NC FID6 1 NC FID7 1 NC FID8 1 FBGA1020_heatsink Heatsink XU18 Maine_Board Board FAB 4 1 MT1 3 1 1 1 1 1 1 Antistat_bag XB1 MNTHOLE 1 MT4 3 1 MNTHOLE 1 MT2 1 VCC5 VCC5 5V1 Test_Header 2 VCC3_3 VCC1_2 VCC3_3 VCC1_2 3_3V1 1_2V1 Test_Header Test_Header M8 M7 M9 1_4Screw M2 HexNut HexNut M15 1_2Screw 1_2Screw M20 M12 M11 Nylon_Washer M19 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 Size A DSP Pro Stratix II 2S180 (Maine Pro) Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Title Vunreg 1 M10 1_4Screw M3 VUNREG1 Test_Header 28 1 of 40 Nylon_Washer M4 7_16Standoff 7_16Standoff 7_16Standoff 7_16Standoff 1_4Screw M1 3_3V2 1_2V2 Test_Header Test_Header 1_4Screw M18 5V2 Test_Header Altera Corp. <Core Design> MNTHOLE 1 MT3 GND5 GND6 GND7 GND8 Test_HeaderTest_HeaderTest_HeaderTest_Header MNTHOLE DSP_BRD_ASSY_LABEL XL29 Fiducial_TOP Fiducial_TOP Fiducial_TOP Fiducial_TOP NC FID5 FM1 5 1 FID2 GND9 GND10 GND11 GND12 Test_HeaderTest_HeaderTest_HeaderTest_Header Fiducial_TOP Fiducial_TOP Fiducial_TOP Fiducial_TOP NC FID1 GND1 GND2 GND3 GND4 Test_HeaderTest_HeaderTest_HeaderTest_Header 1 1 D 1 1 1 1 Reset and Test headers 4 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev 01 A B C D A B C D NOSTUFF C255 NOSTUFF C243 1 3 2 470p C246 20K R133 68p 5 C255 470p C258 10K R139 INTVCC3_3 68p C243 INTVCC5 DC_JACK2_5 J22 100K R137 POW ER_ON 100K R131 POW ER_ON - 6 3 5 2 1 9 4 6 3 5 2 1 9 4 LTC1778 GND VRNG ITH PGOOD RUN.SS EXTVCC FCB U20 LTC1778 GND VRNG ITH PGOOD RUN.SS EXTVCC FCB U19 MB1005MS 3 D9 2 4 + PGND ION VIN TG SW BOOST INTVCC BG VFB PGND ION VIN TG SW BOOST INTVCC BG VFB 1 13 7 10 15 14 16 11 12 8 13 7 10 15 14 16 11 12 8 4 4 0u1 C257 VSENSE3_3 1M4 4R7 R135R136 0u1 C245 VSENSE5 1M4 4R7 R129R130 4u7 C256 CMDSH2_3 D12 0u22 C248 4u7 C244 INTVCC3_3 INTVCC5 CMDSH2_3 D10 0u22 C236 4 4 4 4 3 3 Q1 FDS6680A Q2 FDS6680A Q3 FDS6680A Q4 FDS6680A 3300p C254 0u001 VSENSE3_3 3 2 0u1 C427 C428 L23 2u8H MBRS340 D13 1 68u Vunreg 3300p C242 0u001 VSENSE5 3 2 0u1 C422 C423 L22 2u8H C247 MBRS340 D11 1 68u C235 Vunreg 2K R140 6K2 R138 3K74 R134 20K R132 2 100u C250 100u C238 100u C251 100u 100u C253 VCC3_3 100u C241 VCC5 0u001 0u001 0u001 0u1 0u001 C429 C430 0u1 C424 C425 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Document Number P06-10217-01 Size B Title 1 Sheet 29 of 40 Power 5V and 3.3V 1 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. 0u1 C404 C405 0u1 C402 C403 0u1 C237 SW _SPDT SW 9 <Core Design> 100u C252 100u C240 2M R229 Vunreg C239 POW ER_ON 2 1 2 5 5 6 7 8 1 2 3 5 6 7 8 1 2 3 5 6 7 8 1 2 3 5 6 7 8 1 2 3 3 Rev 01 A B C D A B C D 3 4 7 8 11 14 17 18 21 22 proto5_IO10 proto5_IO11 proto5_IO12 proto5_IO13 proto5_IO14 proto5_IO15 proto5_IO16 proto5_IO17 proto5_IO18 proto5_IO19 5 VCC_BUFFER1 VCC3_3 proto5_IO30 proto5_IO31 proto5_IO32 proto5_IO33 proto5_IO34 proto5_IO35 proto5_IO36 proto5_IO37 proto5_IO38 proto5_IO39 proto5_IO20 proto5_IO21 proto5_IO22 proto5_IO23 proto5_IO24 proto5_IO25 proto5_IO26 proto5_IO27 proto5_IO28 proto5_IO29 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U25 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 R158 proto_IO16 R156 proto_IO19 R157 R155 proto_IO22 proto_IO22 R154 proto5_IO[40:0] 4 5K6 5K6 1K 10K 1K proto_IO10 proto_IO11 proto_IO12 proto_IO13 proto_IO14 proto_IO15 proto_IO16 proto_IO17 proto_IO18 proto_IO19 proto_IO[40:0] 1 13 2 5 6 9 10 15 16 19 20 23 proto_IO23 BEABEB- PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC BEABEB- 3 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC U27 24 proto_IO0 proto_IO1 proto_IO2 proto_IO3 proto_IO4 proto_IO5 proto_IO6 proto_IO7 proto_IO8 proto_IO9 VCC_BUFFER1 U26 1 13 2 5 6 9 10 15 16 19 20 23 24 3 PI5C3384 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 4 PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U24 R155 and R157 are stuff options for the IDE determining whether IDE_INTRQ gets a pull down or pull up. R155 should be a nostuff for production. 3 4 7 8 11 14 17 18 21 22 proto5_IO0 proto5_IO1 proto5_IO2 proto5_IO3 proto5_IO4 proto5_IO5 proto5_IO6 proto5_IO7 proto5_IO8 proto5_IO9 5 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 3 4 7 8 11 14 17 18 21 22 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 0u01 C285 0u01 C284 1 13 2 5 6 9 10 15 16 19 20 23 24 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 30 1 of 40 VCC5 1N4001SM D18 RESET_n proto_IO40 CARDSEL_n Sheet VCC5 1N4001SM VCC_BUFFER2 2K21 R153 2K21 R152 D17 Rev 01 Proto1 Buffers 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U28 VCC_BUFFER2 VCC_BUFFER1 Altera Corp. <Core Design> RESET5_n proto5_IO40 CARDSEL5_n proto_IO30 proto_IO31 proto_IO32 proto_IO33 proto_IO34 proto_IO35 proto_IO36 proto_IO37 proto_IO38 proto_IO39 VCC_BUFFER2 proto_IO20 proto_IO21 proto_IO22 proto_IO23 proto_IO24 proto_IO25 proto_IO26 proto_IO27 proto_IO28 proto_IO29 VCC_BUFFER1 2 A B C D A B C D 3 4 7 8 11 14 17 18 21 22 cf5_IO10 cf5_IO11 cf5_IO12 cf5_IO13 cf5_IO14 cf5_IO15 cf5_IO16 cf5_IO17 cf5_IO18 cf5_IO19 5 cf_IO[41:0] cf5_IO[41:0] 3 4 7 8 11 14 17 18 21 22 cf5_IO0 cf5_IO1 cf5_IO2 cf5_IO3 cf5_IO4 cf5_IO5 cf5_IO6 cf5_IO7 cf5_IO8 cf5_IO9 5 VCC_BUFFER3 cf5_IO30 cf5_IO31 cf5_IO32 cf5_IO33 cf5_IO34 cf5_IO35 cf5_IO36 cf5_IO37 cf5_IO38 cf5_IO39 cf5_IO20 cf5_IO21 cf5_IO22 cf5_IO23 cf5_IO24 cf5_IO25 cf5_IO26 cf5_IO27 cf5_IO28 cf5_IO29 VCC 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U30 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BEABEB- PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1 13 2 5 6 9 10 15 16 19 20 23 4 cf5_IO40 cf5_IO41 cf_RESET5_n cf_POWER5 cf_ATASEL5_n cf_PRESENT5_n cf_CS5_n cf_IO10 cf_IO11 cf_IO12 cf_IO13 cf_IO14 cf_IO15 cf_IO16 cf_IO17 cf_IO18 cf_IO19 3 4 7 8 11 14 17 18 21 22 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BEABEBPI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U49 1 13 2 5 6 9 10 15 16 19 20 23 24 BEABEB- 3 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 cf_IO40 cf_IO41 cf_RESET_n cf_POWER cf_ATASEL_n cf_PRESENT_n cf_CS_n VCC_BUFFER4 PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC U32 VCC 24 cf_IO0 cf_IO1 cf_IO2 cf_IO3 cf_IO4 cf_IO5 cf_IO6 cf_IO7 cf_IO8 cf_IO9 VCC_BUFFER3 U31 1 13 2 5 6 9 10 15 16 19 20 23 24 PI5C3384 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 3 PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U29 4 0u01 C310 0u01 C286 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 Sheet 31 2K21 R198 2K21 R159 1 of 40 1N4001SM D26 Rev 01 VCC5 VCC5 1N4001SM D19 Proto1 Buffers 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 VCC_BUFFER4 VCC_BUFFER3 Altera Corp. <Core Design> cf_IO30 cf_IO31 cf_IO32 cf_IO33 cf_IO34 cf_IO35 cf_IO36 cf_IO37 cf_IO38 cf_IO39 VCC_BUFFER4 cf_IO20 cf_IO21 cf_IO22 cf_IO23 cf_IO24 cf_IO25 cf_IO26 cf_IO27 cf_IO28 cf_IO29 VCC_BUFFER3 2 A B C D A B C D cf5_IO38 cf5_IO39 cf5_IO40 cf5_IO41 5 5 6 4 1 2 3 4 RP21 330 FDC6323L R2 Vout1 Vout2 OFF_n R1 Vin U33 compact_flash_DSP2S60 Compact Flash Card F1 750K cf_POWER5 R160 VCC5 5 1 2 3 5K6 R161 0u001 C287 8 7 6 5 4 cf5_IO31 cf5_IO32 cf5_IO33 cf5_IO34 cf5_IO23 cf5_IO21 cf5_IO22 cf5_IO14 cf5_IO12 cf5_IO10 cf5_IO20 cf5_IO38 cf5_IO8 cf5_IO6 cf5_IO4 cf5_IO2 cf5_IO0 cf5_IO24 cf5_IO26 cf_ATASEL5_n cf5_IO28 cf5_IO29 cf5_IO30 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CF_Header 3 Vss CD1# DO3 D11 DO4 D12 DO5 D13 DO6 D14 DO7 D15 CS0# CS1# A10 VS1# ATA_SEL# IORD# AO9 IOWR# AO8 WE# AO7 INTRQ Vcc Vcc AO6 CSEL# AO5 VS2# AO4 RESET# AO3 IORDY AO2 INPACK# AO1 REG# AO0 DASP# DO0 PDIAG# DO1 DO8 DO2 DO9 IOCS16# D10 CD2# Vss CON1 3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0u001 0u001 cf_RESET5_n 10K R163 VCC5 10K cf_PRESENT5_n R162 VCC5 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 cf5_IO[41:0] Sheet 32 1 of 40 Rev 01 Compact Flash Socket 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> cf5_IO18 cf5_IO36 cf5_IO37 cf5_IO25 cf5_IO27 cf5_IO1 cf5_IO3 cf5_IO5 cf5_IO41 cf5_IO39 cf5_IO7 cf5_IO9 cf5_IO11 cf5_IO13 cf5_IO15 cf_CS5_n cf5_IO40 cf5_IO17 cf5_IO16 cf5_IO35 cf5_IO19 C289 C288 2 A B C D A B C D 5 5 OSC OSC CLKIN CLKOUT 2 4 6 8 10 12 14 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 2x10Header 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 2x7Header J25 143 143 4 R168 95R3 95R3 R167 R166 R165 CLKIN 1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 VCC3_3 Vunreg 1 3 5 7 9 11 13 J24 VCC3_3 VCC3_3 proto5_IO40 proto5_IO30 proto5_IO32 proto5_IO34 proto5_IO36 proto5_IO38 4 proto5_IO29 proto5_IO31 proto5_IO33 proto5_IO35 proto5_IO37 proto5_IO39 VCC5 3 proto5_IO[40:0] 3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J23 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C201 0u001 0u001 0u1 C202 0u1 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title Sheet 1 33 1 0u1 C204 VCC5 of CARDSEL5_n R164 10K 40 Rev 01 Protocard 1 VCC3_3 C203 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. proto5_IO26 proto5_IO23 proto5_IO20 proto5_IO1 proto5_IO3 proto5_IO5 proto5_IO7 proto5_IO9 proto5_IO11 proto5_IO13 proto5_IO15 VCC3_3 C200 J24 and J25 Caps 2x20Header <Core Design> proto5_IO16 proto5_IO17 proto5_IO18 proto5_IO19 proto5_IO21 proto5_IO22 proto5_IO24 proto5_IO25 proto5_IO27 proto5_IO28 RESET5_n proto5_IO0 proto5_IO2 proto5_IO4 proto5_IO6 proto5_IO8 proto5_IO10 proto5_IO12 proto5_IO14 2 A B C D A B C D 3 4 7 8 11 14 17 18 21 22 proto5_IO10 proto5_IO11 proto5_IO12 proto5_IO13 proto5_IO14 proto5_IO15 proto5_IO16 proto5_IO17 proto5_IO18 proto5_IO19 5 3 4 7 8 11 14 17 18 21 22 proto5_IO0 proto5_IO1 proto5_IO2 proto5_IO3 proto5_IO4 proto5_IO5 proto5_IO6 proto5_IO7 proto5_IO8 proto5_IO9 5 3 4 7 8 11 14 17 18 21 22 VCC_BUFFER1 24 proto5_IO30 proto5_IO31 proto5_IO32 proto5_IO33 proto5_IO34 proto5_IO35 proto5_IO36 proto5_IO37 proto5_IO38 proto5_IO39 proto5_IO20 proto5_IO21 proto5_IO22 proto5_IO23 proto5_IO24 proto5_IO25 proto5_IO26 proto5_IO27 proto5_IO28 proto5_IO29 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U35 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BEABEB- 1 13 2 5 6 9 10 15 16 19 20 23 proto5_IO40 CARDSEL5_n RESET5_n PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 4 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U38 proto_IO10 proto_IO11 proto_IO12 proto_IO13 proto_IO14 proto_IO15 proto_IO16 proto_IO17 proto_IO18 proto_IO19 1 13 2 5 6 9 10 15 16 19 20 23 proto_IO40 CARDSEL_n RESET_n VCC_BUFFER2 3 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 proto_IO30 proto_IO31 proto_IO32 proto_IO33 proto_IO34 proto_IO35 proto_IO36 proto_IO37 proto_IO38 proto_IO39 VCC_BUFFER2 proto_IO20 proto_IO21 proto_IO22 proto_IO23 proto_IO24 proto_IO25 proto_IO26 proto_IO27 proto_IO28 proto_IO29 VCC_BUFFER1 2 R172 R173 R174 proto_IO19 proto_IO22 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 proto_IO[40:0] proto5_IO[40:0] R175 R171 proto_IO22 0u01 C291 0u01 C290 proto_IO16 1 2K21 R170 2K21 R169 VCC5 1K 1 5K6 5K6 1K of 40 VCC3_3 1N4001SM D21 10K 34 VCC5 1N4001SM D20 Proto2 Buffers proto_IO23 VCC_BUFFER2 VCC_BUFFER1 Altera Corp. <Core Design> R172 and R174 are stuff options for the IDE determining whether IDE_INTRQ gets a pull down or pull up. R172 should be a nostuff for production. BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC U37 VCC 24 proto_IO0 proto_IO1 proto_IO2 proto_IO3 proto_IO4 proto_IO5 proto_IO6 proto_IO7 proto_IO8 proto_IO9 VCC_BUFFER1 U36 1 13 2 5 6 9 10 15 16 19 20 23 24 PI5C3384 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 3 PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U34 4 Rev 01 A B C D A B C D 5 OSC VCC3_3 Vunreg proto5_IO40 proto5_IO30 proto5_IO32 proto5_IO34 proto5_IO36 proto5_IO38 OSC CLKIN CLKOUT 5 1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 143 4 143 R180 95R3 95R3 R179 R178 R177 CLKIN VCC3_3 proto5_IO29 proto5_IO31 proto5_IO33 proto5_IO35 proto5_IO37 proto5_IO39 VCC5 VCC3_3 2x10Header 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 2 4 6 8 10 12 14 2x7Header J28 1 3 5 7 9 11 13 J26 4 proto5_IO[40:0] 3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2x20Header 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J27 C206 0u001 C205 0u001 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 0u1 C208 2 0u1 C209 VCC5 proto5_IO26 proto5_IO23 proto5_IO20 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 10K CARDSEL5_n R176 VCC3_3 35 Proto2 Headers proto5_IO1 proto5_IO3 proto5_IO5 proto5_IO7 proto5_IO9 proto5_IO11 proto5_IO13 proto5_IO15 Altera Corp. <Core Design> 0u1 C207 J26 and J28 VCC3_3 Caps proto5_IO16 proto5_IO17 proto5_IO18 proto5_IO19 proto5_IO21 proto5_IO22 proto5_IO24 proto5_IO25 proto5_IO27 proto5_IO28 RESET5_n proto5_IO0 proto5_IO2 proto5_IO4 proto5_IO6 proto5_IO8 proto5_IO10 proto5_IO12 proto5_IO14 3 1 1 of 40 Rev 01 A B C D A B C D 5 sdram_DQM[7:0] sdram_BA[1:0] sdram_A[11:0] sdram_DQ[63:0] 70 73 30 14 69 57 68 67 sdram_CLK sdram_CKE 16 71 28 59 sdram_DQM0 sdram_DQM1 sdram_DQM2 sdram_DQM3 17 18 19 20 22 23 sdram_BA0 sdram_BA1 sdram_W E_n sdram_CAS_n sdram_RAS_n sdram_CS_n 25 26 27 60 61 62 63 64 65 66 24 21 sdram_A0 sdram_A1 sdram_A2 sdram_A3 sdram_A4 sdram_A5 sdram_A6 sdram_A7 sdram_A8 sdram_A9 sdram_A10 sdram_A11 5 MT48LC4M32B2 NC NC NC NC NC NC CLK CKE WE_n CAS_n RAS_n CS_n DQM0 DQM1 DQM2 DQM3 BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 U39 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 sdram_DQ0 sdram_DQ1 sdram_DQ2 sdram_DQ3 sdram_DQ4 sdram_DQ5 sdram_DQ6 sdram_DQ7 sdram_DQ8 sdram_DQ9 sdram_DQ10 sdram_DQ11 sdram_DQ12 sdram_DQ13 sdram_DQ14 sdram_DQ15 sdram_DQ16 sdram_DQ17 sdram_DQ18 sdram_DQ19 sdram_DQ20 sdram_DQ21 sdram_DQ22 sdram_DQ23 sdram_DQ24 sdram_DQ25 sdram_DQ26 sdram_DQ27 sdram_DQ28 sdram_DQ29 sdram_DQ30 sdram_DQ31 4 sdram_CS_n sdram_RAS_n sdram_CAS_n sdram_CKE sdram_W E_n 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 4 1 2 3 4 5K6 8 7 6 5 5K6 R184 RP22 VCC3_3 3 C369 0u001 0u001 C212 0u001 0u001 C368 C211 68 67 sdram_CLK sdram_CKE 10u 17 18 19 20 sdram_W E_n sdram_CAS_n sdram_RAS_n sdram_CS_n 0u001 C370 0u001 0u001 C215 0u001 C371 0u001 C372 VCC3_3 0u001 C214 VCC3_3 MT48LC4M32B2 NC NC NC NC NC NC CLK CKE WE_n CAS_n RAS_n CS_n DQM0 DQM1 DQM2 DQM3 BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 U40 C213 70 73 30 14 69 57 16 71 28 59 22 23 25 26 27 60 61 62 63 64 65 66 24 21 sdram_DQM4 sdram_DQM5 sdram_DQM6 sdram_DQM7 sdram_BA0 sdram_BA1 sdram_A0 sdram_A1 sdram_A2 sdram_A3 sdram_A4 sdram_A5 sdram_A6 sdram_A7 sdram_A8 sdram_A9 sdram_A10 sdram_A11 C210 3 0u001 C373 0u001 C216 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 0u1 C374 0u1 C217 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 2 0u1 C375 0u1 C218 0u1 C376 0u1 C367 sdram_DQ32 sdram_DQ33 sdram_DQ34 sdram_DQ35 sdram_DQ36 sdram_DQ37 sdram_DQ38 sdram_DQ39 sdram_DQ40 sdram_DQ41 sdram_DQ42 sdram_DQ43 sdram_DQ44 sdram_DQ45 sdram_DQ46 sdram_DQ47 sdram_DQ48 sdram_DQ49 sdram_DQ50 sdram_DQ51 sdram_DQ52 sdram_DQ53 sdram_DQ54 sdram_DQ55 sdram_DQ56 sdram_DQ57 sdram_DQ58 sdram_DQ59 sdram_DQ60 sdram_DQ61 sdram_DQ62 sdram_DQ63 2 0u1 C378 0u1 C224 0u1 C379 0u1 C225 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 0u1 C377 0u1 C223 1 36 of 40 Rev 01 SDRAM A B C D A B C D J29 11 10 5 1 6 2 7 3 8 4 9 5 DB9RF 5 VCC3_3 15 14 13 16 5 6 7 10 12 21 20 18 MAX3237 MBAUD SHDN_n EN_n R1OUTB T1OUT T2OUT T3OUT T4OUT T5OUT R1OUT R2OUT R3OUT U41 4 C1+ C1C2+ C2V+ V- VCC T1IN T2IN T3IN T4IN T5IN R1IN R2IN R3IN 4 28 25 1 3 27 4 26 24 23 22 19 17 8 9 11 1u 1u C294 C295 VCC3_3 1u C293 1u C292 DCD1 DSR1 TXD1 CTS1 RI1 RTS1 RXD1 DTR1 VCC3_3 3 3 TXD1 RXD1 LedG D23 LedG D22 R186 R185 2 200 200 2 VCC3_3 Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 37 of Serial Ports 1 40 Rev 01 A B C D A B C D 5 0u001 0u1 39 40 41 6 sram_BE_n0 sram_BE_n1 sram_OE_n 0u1 C196 0u001 C197 VCC3_3 5K6 4 17 sram_WE_n R189 SRAM U35 U36 C195 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 4 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VCC3_3 sram_CS_n C194 VCC3_3 5 U43 NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 28 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 sram_WE_n sram_OE_n sram_BE_n[3:0] D[31:0] A[19:2] sram_OE_n sram_CS_n sram_BE_n2 sram_BE_n3 sram_WE_n A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 2 3 41 6 39 40 17 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 U44 IDT71V416S OE_n CS_n BLE_n BHE_n WE_n A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title Sheet NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> One bank of 256K x 32 SRAM (two 256K x 16 parts in parallel) = 1Mbyte of SRAM IDT71V416S OE_n CS_n BLE_n BHE_n WE_n A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 3 38 28 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 1 1 of D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 40 Rev 01 SRAM A B C D A B C D 5 5 C381 0u1 C380 0u1 0u1 C382 VCC5 evm_CLKOUT2 evm_DMAC0 evm_CNTL0 evm_STAT0 evm_INT3 evm_INUM0 evm_IACK evm_INT1 evm_DR0 evm_DX0 0u1 C383 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 Periferal 0u001 C384 0u001 C385 4 0u001 C386 12V GND 5V GND 5V NC NC NC NC 3.3V CLKXO FSXO GND CLKRO FSRO GND CLKX2 FSX2 GND CLKR2 FSR2 GND TOUT0 NC TOUT1 GND EXT_INT4 NC NC RESET GND CNTL1 STAT1 EXT_INT6 ACE3_n NC NC DC_DET_n GND GND 40X2TFM_CONN -12V GND 5V GND 5V NC NC NC NC 3.3V CLKS0 DX0 GND NC DR0 GND CLKS2 DX2 GND NC DR2 GND TINP0 EXT_INT5 TINP1 GND NC NC NC NC GND CNTL0 STAT0 EXT_INT7 NC NC NC GND ECLKOUT GND J31 4 0u001 C387 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 0u1 C388 330 0u1 0u001 C390 VCC3_3 C389 R228 evm_INT2 evm_RESET evm_INT0 evm_CLKR0 evm_FSR0 evm_CLKX0 evm_FSX0 0u001 C391 evm_A[21:2] evm_INT[3:0] evm_AW E_n evm_ARDY evm_ACE2_n evm_D6 evm_D4 evm_D2 evm_D0 evm_D14 evm_D12 evm_D10 evm_D8 evm_D22 evm_D20 evm_D18 evm_D16 evm_D30 evm_D28 evm_D26 evm_D24 evm_A4 evm_A2 evm_BE_n2 evm_BE_n0 evm_A12 evm_A10 evm_A8 evm_A6 evm_A20 evm_A18 evm_A16 evm_A14 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 40X2TFM_CONN 5V EA20 EA18 EA16 EA14 GND EA12 EA10 EA8 EA6 5V EA4 EA2 BE2_n BE0_n GND ED30 ED28 ED26 ED24 3.3V ED22 ED20 ED18 ED16 GND ED14 ED12 ED10 ED8 GND ED6 ED4 ED2 ED0 GND AWE_n ARDY ACE2_n GND J33 5V EA21 EA19 EA17 EA15 GND EA13 EA11 EA9 EA7 5V EA5 EA3 BE3_n BE1_n GND ED31 ED29 ED27 ED25 3.3V ED23 ED21 ED19 ED17 GND ED15 ED13 ED11 ED9 GND ED7 ED5 ED3 ED1 GND ARE_n AOE_n ACE_n GND 3.00" apart 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 evm_ARE_n evm_AOE_n evm_ACE3_n evm_D7 evm_D5 evm_D3 evm_D1 evm_D15 evm_D13 evm_D11 evm_D9 evm_D23 evm_D21 evm_D19 evm_D17 evm_D31 evm_D29 evm_D27 evm_D25 evm_A5 evm_A3 evm_BE_n3 evm_BE_n1 evm_A13 evm_A11 evm_A9 evm_A7 evm_A21 evm_A19 evm_A17 evm_A15 3 2 1 TI EVM Connector Document Number P06-10217-01 Thursday, August 18, 2005 Date: DSP Pro Stratix II 2S180 (Maine Pro) Size B Title 1 Sheet 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> These connectors reference the TI 6416 board evm_BE_n[3:0] evm_D[31:0] 3 Memory 39 of 40 Rev 01 A B C D A B C 5 FMS3818 IO_B IO_G IO_R G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 C307 0u1 C306 0u1 VCC3_3 29 32 33 2 3 4 5 6 7 8 9 vga_G0 vga_G1 vga_G2 vga_G3 vga_G4 vga_G5 vga_G6 vga_G7 vga_BLUE vga_GREEN vga_RED 40 41 42 43 44 45 46 47 vga_R0 vga_R1 vga_R2 vga_R3 vga_R4 vga_R5 vga_R6 vga_R7 B0 B1 B2 B3 B4 B5 B6 B7 U45 0u1 C308 2u2 C309 NC NC NC NC VDD_D GND GND GND GND GND GND GND GND VDD_A VDD_A V_REF COMP R_REF CLK SYNC_n BLANK_n 4 13 24 25 37 12 48 39 38 28 27 15 14 1 31 30 35 34 36 26 11 10 4 R190 10u 0u1 0u01 3 vga_G[7:0] vga_R[7:0] vga_B[7:0] vga_VSYNC vga_HSYNC C305 C304 0u1 0u1 VCC3_3 C303 33 NOSTUFF R192 R192 C301 C302 0u1 18 C300 R191 330 vga_CLOCK vga_SYNC_n vga_BLANK_n 3 3 VCC3_3 5 4 GND DB15RA 6 11 7 12 8 13 9 14 10 15 J35 GND 3 Thursday, August 18, 2005 Date: 2 Document Number P06-10217-01 AC2 U48 3 VGA 5 75 Sheet 40 75 1 of 75 R197 40 Rev 01 vga_BLUE 3 R196 vga_GREEN 2 R195 vga_RED 4 D A B C MMBD2 1 DSP Pro Stratix II 2S180 (Maine Pro) Size A Title 1 U47MMBD3004BRM AC2 AC1 6 Transient Supression 110 Cooper Street, Suite 201, Santa Cruz, CA, 95060 Altera Corp. <Core Design> 33 33 R194 R193 6 2 U46MMBD3004BRM AC2 AC1 C1 C2 A1 A2 1 2 5 4 C1 C2 A1 A2 1 2 D 16 17 18 19 20 21 22 23 vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 5 16 17 2 C1 A1 1