A B C D E 8 100-0310202-C1 110-0310202-C1 120-0310202-C1 130-0310202-C1 140-0310202-C1 150-0310202-C1 160-0310202-C1 170-0310202-C1 180-0310202-C1 210-0310202-C1 220-0310202-C1 320-0310202-C1 Digital Ground PLL Ground DAC Ground ADC Ground 7 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. PLL DAC ADC 2. 894 Parts, 63 Library Parts, 874 Nets, 4299 Pins 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework NOTES: 6 6 5 System Block Diagram 5 4 4 C A B REV 3 3 04/04/2006 01/26/2005 02/17/2005 DATE 1,16 --------- 2 DESCRIPTION 1 DAC Channel B Video DAC AIC23 Audio Codec Buttons, Switches, LEDs SRAM, TI EVM Connectors Altera Daughter Card & Mictor Connector Cyclone II Power and Decoupling Digital Power Supplies Analog Power Supplies ----- 15 16 17 18 19 20 21 22 23 Date: Size B 2 Tuesday, August 15, 2006 Sheet 1 1 of 150-0310202-C1 (6XX-40023R ) Document Number Cyclone II DSP Board Title 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 ----- DAC Channel A 14 ----- ADC Channel B 13 25 ADC Channel A 12 24 Cyclone II Configuration Circuitry Cyclone II Banks 7 & 8 7 11 Cyclone II Banks 5 & 6 6 DDR2 Termination Cyclone II Banks 3 & 4 5 10 Cyclone II Banks 1 & 2 4 9 Clock Circuitry 3 DDR2 DIMM FPGA Package I/O Diagram & Design Notes 2 8 Title, Notes, Block Diagram, Revision History 1 DESCRIPTION Fixed ground connections on AIC23 audio codec (U11). Released for Protoype Production Fixed clock buffer U27 pinout. Fixed SSRAM U22 pinout to remove rework. Fixed EVM_CE2/CE3 short on TI EVM Interface. Fixed VTT Regulator U8 decoupling by adding ceramic output caps. PAGE PAGES C Rev A B C D E A B C D E Leaving 1.2V-connected I/O pins as outputs driving GND causes high I/O current and increased temperature which can lead to device damage if left over a long period of time. --- W ARNING --DO NOT DRIVE UNUSED I/O TO GND IN QUARTUS Some I/O pins are connected to 1.2V and GND. These are the additional VCC and GND pins of the larger 2C50 and 2C70. 7 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 3. PCB Supports 2C70 - 2C50 - 2C70 Migration 2. No additional I/O of 2C70 or 2C50 used as the 2C70 has the fewest I/O of the group due to additional VCCINT,GND, and VREF pins on the larger 2C50 and 2C70 devices. FPGA Schematic Symbol Breakdown: (a) Bank1 - I/O (b) Bank2 - I/O (c) Bank3 - I/O (d) Bank4 - I/O (e) Bank5 - I/O (f) Bank6 - I/O (g) Bank7 - I/O (h) Bank8 - I/O (i) Configuration (j) Clocks (k) VCCint, GND (l) VCCio, GND 8 1. Notes: 3 BANK 5 5 DDR2 DIMM DATA LANES, ADDRESS Pushbuttons 4 DDR2 DIMM DATA LANES, CNTL, CLOCK Pushbuttons Dipswitch BANK 7 VCCIO = 1.8V BANK 8 2 1 Date: 2 Sheet 2 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Size B 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Shared Bus DAC Channel 1 DAC Channel 2 Video DAC DAC Channel 1 DAC Channel 2 Video DAC VCCIO = 1.8V BANK 6 VCCIO = 3.3V BANK 1 VCCIO = 3.3V Shared Bus DAC Channel 2 DDR2 DIMM DATA LANES ADC Channel 1 ADC Channel 2 VCCIO = 3.3V DDR2 DIMM DATA LANES ADC Channel 2 BANK 4 VCCIO = 1.8V BANK 3 VCCIO = 1.8V (2C70 Device Shown) 3 Proto Bus Video DAC DAC Channel 1 6 4 FPGA Package Top View 5 VCCIO = 3.3V BANK 2 6 C Rev A B C D E A B C D E 1 2 3 8 PIN1-PIN2 PIN2-PIN3 5 8 3X1 SMA_TO_DAC_CLK R241 143R,3.3V 1% R240 95.3R, 1% R239 143R,3.3V 1% 8 7 6 CLK_OSC CLK_SMA R125 49.9 1 R252 143R, 1% R251 95.3R, 1% R248 143R, 1% R247 95.3R, 1% 7 10 9 8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VDD VDD ICS552-02 GND GND INA INB SELA OE U16 0.1uF 1.0uf CLK_SEL 16 CLK_EN R121 10.0K, 1% 3.3V_CLK C306 C74 L9 BLM21PG331SN1 0.01uf C305 6 3 4 5 6 11 12 13 14 R129 R128 R127 R126 CLK_OSC_ADCA_R CLK_OSC_ADCB_R CLK_OSC_DACA_R CLK_OSC_DACB_R R253 49.9 3X2 1 3 5 J36 2 4 6 3X2 1 3 5 J35 2 4 6 SHUNT3 881545-2 3X2 1 3 5 J34 5 SHUNT4 881545-2 2 4 6 Channel B DAC Clock Select CLK_OSC_DACB FPGA_TO_DAC_CLK SMA_TO_DAC_CLK R250 49.9 2 4 6 Channel A DAC Clock Select CLK_OSC_DACA FPGA_TO_DAC_CLK SMA_TO_DAC_CLK R249 49.9 3X2 1 3 5 J37 SHUNT5 881545-2 DACB_ENC DACA_ENC ADCB_ENC ADCA_ENC 33.2R, 1% 33.2R, 1% 33.2R, 1% 33.2R, 1% C399 0.01uf C400 0.1uF 3.3V SHUNT6 4 0.1uF C397 SY10EPT28L 3.3V 1 2 3 0.01uf C398 VCC IN_LVPECL OUT_LVTTL IN_LVPECL_n IN_LVTTL OUT_LVPECL GND OUT_LVPECL_n U28 SY10EPT28L 1Y VCC 2Y 3.3V 6 5 4 3.3V 0.1uF C390 0.01uf C387 3 R259 82R R260 130R 3 DACB_CLK_R DACA_CLK_R R261 82R R262 130R 3.3V EP2C70F672C6N CLK8_B4 CLK9_B4 CLK10_B3 CLK11_B3 CLK12_B7 CLK13_B7 CLK14_B8 CLK15_B8 R42 R39 3.3V V21 V20 E5 F6 F21 F20 AA7 AA6 Channel B ADC Sample Clock 14 DACB_CLK 33.2R, 1% Channel B DAC Sample Clock 13 DACA_CLK Channel A DAC Sample Clock 12 ADC_B_CLK_P 12 ADC_B_CLK_N R235 82R 14 DAC_B_D4 14 DAC_B_D3 17 USER_LED0 19 PROTO_IO3 15 VGA_VSYNC 17 USER_LED2 17 USER_LED7 17 USER_LED6 Channel A ADC Sample Clock 11 ADC_A_CLK_P 11 ADC_A_CLK_N R236 130R 33.2R, 1% 3.3V 2 1 Date: Size B 2 Sheet 3 150-0310202-C1 Tuesday, August 15, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 R245 82R R237 130R PLL4_OUTp_B6 PLL4_OUTn_B6 PLL3_OUTp_B2 PLL3_OUTn_B2 PLL2_OUTp_B5 PLL2_OUTn_B5 PLL1_OUTp_B1 PLL1_OUTn_B1 CYCLONE II, CLOCKS CLK0_B2 CLK1_B2 CLK2_B1 CLK3_B1 CLK4_B5 CLK5_B5 CLK6_B6 CLK7_B6 U12J 3.3V B13 A13 C13 D13 AE14 AF14 AD13 AC13 N2 N1 P2 P1 N25 N26 P25 P26 SN74LVC2G34DBV 1A GND 2A U27 1 2 3 4 1 2 3 4 3.3V AUDIO_DOUT 16 ADC_A_DCLK 11 ADC_B_DCLK 12 ADC_A_D7 11 USER_PB3 17 DIMM_SYNC_CLK 7 PROTO_CLKOUT 19 USER_DIPSW 0 17 EVM_CLKOUT2 18 EVM_INUM0 18 CLKIN_BOT EVM_IACK 18 EVM_RESET 18 EVM_AREn 18 CLKIN_TOP VCC IN_LVPECL OUT_LVTTL IN_LVPECL_n IN_LVTTL OUT_LVPECL GND OUT_LVPECL_n U29 881545-2 8 7 6 5 8 7 6 5 33.2R, 1% CLKIN_TOP 33.2R, 1% CLKIN_BOT 33.2R, 1% PROTO_CLK_OSC 19 Channel B ADC Clock Select CLK_OSC_ADCB FPGA_TO_ADC_CLK SMA_TO_ADC_CLK R246 49.9 CLK_OSC_ADCA FPGA_TO_ADC_CLK SMA_TO_ADC_CLK 4 Cyclone II Clocking 5 Channel A ADC Clock Select R122 R123 R124 CLKIN_TOP_R CLKIN_BOT_R PROTO_CLK_OSC_R 2 3.3V_CLK 15 (1) On-Board OSC (2) Custom OSC (3) SMA Input High-Speed Clock Source 3.3V 3.3V 3.3V R238 95.3R, 1% Copyright (c) 2005, Altera Corporation. All Rights Reserved. 1 LTI-SASF54GT DAC Clock SMA FPGA_TO_DAC_CLK 4 3.3V SMA_TO_ADC_CLK DAC Clock (from FPGA) 1 LTI-SASF54GT 7 1 2 3 3.3V J19 FPGA_TO_ADC_CLK 4 ADC Clock SMA J26 3 Oscillator SMA Input SMA Input 1 OUT VCC OSC_Socket GND EN Custom OSC 4 1 J20 J17 LTI-SASF54GT J27 OUT 4 Dual footprint with SMT and socketed oscillator ADC Clock (from FPGA) SHUNT2 881545-2 SHUNT1 881545-2 GND VCC 100Mhz 1.0uf C79 On-Board OSC 2 EN Y1 0.01uf 0.1uF 1 C85 C84 BLM21PG331SN1 3.3V_OSCB R134 10.0K, 1% L11 PIN1-PIN2 100MHz CLK PIN2-PIN3 Socket CLK 3X1 J18 3.3V 5 4 3 2 5 4 3 2 5 4 3 2 R130 10.0K, 1% C Rev A B C D E A B C D E 3,6,10,17 3,6,14 13 16 VGA_BLANKn 15 VGA_SYNCn 15 ADC_SDATA 11,12 AUDIO_LRCOUT 16 AUDIO_LRCIN AUDIO_BCLK 16 AUDIO_SCLK 16 AUDIO_MODE 16 AUDIO_CLK 16 AUDIO_SDIN 16 ADC_B_OE 12 DAC_A_D[13..0] FPGA_TO_DAC_CLK 3 ADC_A_OE 11 DAC_B_D[13..0] FPGA_TO_ADC_CLK 3 DIG_LSB_A 17 DIG_LSB_C 17 DIG_LSB_D 17 DIG_LSB_E 17 DIG_LSB_G 17 DIG_LSB_DP 17 DIG_MSB_B 17 DIG_MSB_D 17 DIG_MSB_E 17 DIG_MSB_F 17 DIG_MSB_DP 17 USER_LED[7..0] VGA_CLK 15 VGA_B[7..0] 15 VGA_G[7..0] 15 VGA_R[7..0] 6,15 PROTO_CARDSELn 19 PROTO_IO[40..0] 3,19 7 AB4 AC1 AC2 AC3 AD2 AD3 AE2 AE3 P6 P7 R2 R4 R5 R6 R7 R8 T2 T3 T4 T6 USER_LED5 VGA_B0 DIG_LSB_G USER_LED4 AUDIO_SDIN DAC_A_D3 VGA_SYNCn DAC_A_D2 DAC_A_D13 DIG_LSB_DP ADC_B_OE AUDIO_SCLK DAC_A_D12 VGA_G4 VGA_G2 DAC_A_D5 FPGA_TO_ADC_CLK VGA_CLK VGA_G6 AB1 AB2 AB3 8 7 AA1 AA2 AA3 AA4 AA5 DAC_A_D0 AUDIO_LRCOUT AUDIO_CLK 1.2V VCCIO = 3.3V 6 0 VREF 2 GND 4 VCCINT CYCLONE II, BANK 1 6 EP2C70F672C6N IO_21 IO_22 IO_23 IO_24 IO_25 IO_26 IO_27 IO_28 IO_29 IO_30 IO_11 IO_12 IO_13 IO_14 IO_15 IO_16 IO_17 IO_18 IO_19 IO_20 IO_8 IO_9 IO_10 IO_1 IO_2 IO_3 IO_4 IO_5 U12A These pins are connected to VCCINT on 2C70. DAC_A_D1 AUDIO_MODE DIG_LSB_C VGA_G5 DAC_A_D7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 8 4 IO_456 IO_457 IO_459 IO_58 IO_59 IO_60 IO_51 IO_52 IO_53 IO_54 IO_55 IO_56 IO_41 IO_42 IO_43 IO_44 IO_45 IO_46 IO_47 IO_48 IO_49 IO_50 IO_31 IO_32 IO_33 IO_34 IO_35 IO_36 IO_37 IO_38 IO_39 IO_40 P3 P4 R3 Y3 Y4 Y5 W1 W2 W3 W4 W6 Y1 U7 U9 U10 V1 V2 V3 V4 V5 V6 V7 T7 T8 T9 T10 U1 U2 U3 U4 U5 U6 DAC_A_D10 VGA_R6 VGA_G0 FPGA_TO_DAC_CLK DAC_A_D6 DIG_MSB_D VGA_B5 VGA_B3 VGA_B1 AUDIO_LRCIN VGA_G1 ADC_SDATA DIG_LSB_D PROTO_CARDSELn DIG_MSB_DP VGA_G7 DAC_A_D8 DAC_A_D9 DIG_LSB_E DAC_A_D11 DIG_MSB_F VGA_B7 DAC_A_D4 VGA_B6 VGA_G3 VGA_BLANKn DIG_MSB_B 5 These pins are GND pins on 2C70. 1.2V These pins are connected to VCCINT on 2C70. 4 CYCLONE II BANKS 1 & 2 5 B2 3 N9 L6 J5 J6 J7 J8 L10 These pins are GND pins on 2C70. PROTO_IO4 PROTO_IO0 PROTO_IO37 PROTO_IO31 PROTO_IO7 F7 G1 G2 G3 G4 G5 F2 F3 F4 PROTO_IO13 AUDIO_BCLK PROTO_IO9 ADC_A_OE PROTO_IO16 PROTO_IO27 PROTO_IO11 PROTO_IO10 PROTO_IO8 F1 C2 C3 D1 D2 E1 E2 PROTO_IO15 PROTO_IO12 PROTO_IO40 PROTO_IO14 PROTO_IO29 DIG_MSB_E PROTO_IO28 VGA_B2 3 IO_458 IO_111 IO_101 IO_102 IO_103 IO_104 IO_105 IO_106 IO_107 IO_108 IO_109 IO_110 IO_91 IO_92 IO_93 IO_94 IO_95 IO_96 IO_97 IO_98 IO_99 IO_100 IO_87 IO_88 IO_89 IO_90 IO_81 IO_82 P9 M5 PROTO_IO25 PROTO_IO35 PROTO_IO22 PROTO_IO30 PROTO_IO36 PROTO_IO5 K3 K4 L2 L3 L4 L7 L9 M2 M3 M4 These pins are GND pins on 2C70. DAC_B_D1 PROTO_IO24 PROTO_IO23 DAC_B_D0 PROTO_IO18 VGA_B4 PROTO_IO26 PROTO_IO34 PROTO_IO19 PROTO_IO20 PROTO_IO17 PROTO_IO33 PROTO_IO21 DIG_LSB_A PROTO_IO32 PROTO_IO38 PROTO_IO6 PROTO_IO39 PROTO_IO2 PROTO_IO1 H1 H2 H3 H4 J1 J2 J3 J4 K1 K2 K5 K6 K7 K8 G6 H6 1.2V These pins are connected to VCCINT on 2C70. 1 Date: Size B 2 Sheet 4 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 0 VREF 3 GND 1 VCCINT CYCLONE II, BANK 2 VCCIO = 3.3V EP2C70F672C6N IO_474 IO_470 IO_450 IO_451 IO_452 IO_453 IO_454 IO_75 IO_76 IO_77 IO_78 IO_79 IO_80 IO_71 IO_72 IO_73 IO_70 IO_63 IO_64 IO_65 IO_66 IO_67 IO_68 IO_57 U12B 2 C Rev A B C D E A B C D E ADC_B_SEN 12 ADC_A_SEN 11 3.3V USER_RESETn 17,19 3,7,17 3,10,11 12 USER_DIPSW [7:0] ADC_B_OVR 12 ADC_B_D[13..0] ADC_A_OVR 11 ADC_A_D[13..0] DIMM_ODT_R1 7,9 DIMM_ODT_R0 7,9 DIMM_CKE_R1 7,9 DIMM_CKE_R0 7,9 DIMM_CSn_R1 7,9 DIMM_CSn_R0 7,9 DIMM_W En_R 7,9 DIMM_CASn_R 7,9 DIMM_RASn_R 7,9 DIMM_DM[8..0] 7,8,9 DIMM_BA_R[2..0] 7,9 DIMM_A_R[15..0] 7,9 DIMM_DQS[8..0] 7,8,9 DIMM_DQ[71..0] 7,8,9 R233 1K 3.3V 7 R258 1K 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 1.8V driving 3.3V logic must be driven as open-drain 8 6 DIMM_DQ32 DIMM_DQ42 DIMM_DQ64 DIMM_DQ43 DIMM_DM6 DIMM_DQ44 D5 D10 D11 E8 E10 F11 F12 G9 G11 G12 C6 C10 C11 C12 ADC_A_D1 DIMM_DQ45 ADC_A_D5 DIMM_DQS5 A10 A4 A5 A6 A8 A9 B4 B5 B6 B9 B10 B11 B12 C4 VREF DIMM_DM5 DIMM_DQ40 DIMM_DQ52 ADC_A_D6 DIMM_DQ65 DIMM_DQ41 DIMM_DM8 DIMM_DQ70 ADC_B_OVR ADC_A_D3 ADC_A_D4 DIMM_DQ69 DIMM_DQ66 DIMM_DQS8 6 VCCIO = 1.8V 4 VREF 6 GND 4 VCCINT EP2C70F672C6N IO_131 IO_132 IO_133 IO_134 IO_135 IO_136 IO_137 IO_138 IO_139 IO_140 IO_127 IO_128 IO_129 IO_130 IO_121 IO_122 IO_123 IO_124 IO_125 IO_112 IO_113 IO_114 IO_115 IO_116 IO_117 IO_118 IO_119 IO_120 5 IO_161 IO_162 IO_163 IO_164 IO_165 IO_151 IO_152 IO_153 IO_154 IO_155 IO_156 IO_157 IO_158 IO_159 IO_160 IO_141 IO_142 IO_143 IO_144 IO_145 IO_146 IO_147 IO_148 IO_149 IO_150 CYCLONE II, BANK 3 U12C 4 D6 D7 F10 F9 G10 C9 D12 D8 D9 E12 J11 J14 A7 B7 C7 H8 H10 H11 H12 J9 J10 J13 K9 B8 C8 1.2V DIMM_DM4 DIMM_DQ67 DIMM_DQ37 DIMM_DQ68 DIMM_DQ36 DIMM_DQ38 ADC_A_D2 DIMM_DQ71 DIMM_DQ39 DIMM_DQ46 DIMM_DQ33 DIMM_DQ35 DIMM_DQ47 DIMM_DQS4 DIMM_DQ34 4 CYCLONE II BANKS 3 & 4 5 D14 D15 D16 D17 D18 D19 D20 D21 E15 E18 3 ADC_B_D1 ADC_B_D2 ADC_B_SEN ADC_B_D13 ADC_B_D12 DIMM_DQ60 ADC_B_D10 DIMM_DQ49 ADC_A_OVR A21 A22 A23 B14 B15 B16 B17 B18 B19 B20 A14 A17 A18 A19 A20 B21 B22 B23 C15 C16 C17 C19 C21 C22 C23 VREF ADC_B_D7 ADC_A_D8 ADC_A_D11 DIMM_DQ55 DIMM_DM7 DIMM_DQS7 ADC_B_D3 USER_DIPSW 2 ADC_A_D12 USER_DIPSW 3 ADC_A_D9 ADC_A_D13 ADC_A_D10 DIMM_DQS6 DIMM_DQ54 DIMM_DQ50 DIMM_DQ57 ADC_A_SEN ADC_B_D4 ADC_B_D5 USER_RESETn DIMM_DQ61 DIMM_DQ56 USER_DIPSW 1 ADC_B_D6 3 VCCIO = 1.8V IO_221 IO_211 IO_212 IO_213 IO_214 IO_215 IO_216 IO_217 IO_218 IO_219 IO_220 IO_201 IO_202 IO_203 IO_204 IO_205 IO_206 IO_207 IO_208 IO_209 IO_210 K17 G16 G17 G18 H15 H16 H17 J16 J17 J18 K16 E20 F13 F14 F15 F16 F17 F18 G13 G14 G15 VREF 1.2V DIMM_DQ58 UNUSED I/O ADC_B_D9 DIMM_DQ48 DIMM_DQ62 DIMM_DQ63 ADC_B_D0 ADC_B_D8 DIMM_DQ53 DIMM_DQ51 DIMM_DQ59 ADC_B_D11 1 Date: Size B 2 Sheet 5 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 2 VREF 5 GND 4 VCCINT EP2C70F672C6N IO_191 IO_192 IO_193 IO_194 IO_195 IO_196 IO_197 IO_198 IO_199 IO_200 IO_181 IO_182 IO_183 IO_184 IO_185 IO_186 IO_187 IO_188 IO_189 IO_190 IO_171 IO_172 IO_173 IO_174 IO_175 IO_176 IO_177 IO_178 IO_179 IO_180 IO_166 IO_167 IO_168 IO_169 IO_170 CYCLONE II, BANK 4 U12D 2 C Rev A B C D E A B C D E 4,13 3,4,14 16 3,4,10,17 PROTO_CLKIN 19 SRAM_CLK 18 EPCS_USER_CSn 10 ADC_B_SEN 5,12 ADC_SCLK 11,12 ADC_RESET 11,12 DIG_LSB_F 17 DIG_LSB_B 17 DIG_MSB_G 17 DIG_MSB_C 17 DIG_MSB_A 17 VGA_B[7..0] 4,15 VGA_R[7..0] 4,15 VGA_HSYNC 15 EVM_RESET 3,18 AUDIO_DIN AUDIO_CSn 16 USER_LED[7..0] EVM_FSR0 18 EVM_CLKR0 18 EVM_FSX0 18 EVM_CLKX0 18 EVM_ARDY 18 EVM_OEn 18 EVM_DR0 18 EVM_AW En 18 EVM_DMAC0 18 EVM_STAT0 18 EVM_CNTL0 18 EVM_DX0 18 EVM_CEn[3..2] 10,18 EVM_INT[3..0] 18 EVM_BEn[3..0] 18 EVM_D[31..0] 18 EVM_A[21..2] 18 DAC_B_D[13..0] DAC_A_D[13..0] 7 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 8 EVM_D12 EVM_D14 EVM_D16 EVM_D18 EVM_D20 EVM_D22 EVM_CEn2 EVM_A15 EVM_A11 VGA_HSYNC EVM_D24 EVM_D26 EVM_A19 EVM_DR0 EVM_FSR0 AUDIO_DIN EVM_CLKR0 EVM_A17 6 J22 J23 J24 J25 J26 K18 K19 K21 K22 K23 G25 G26 H19 H21 H23 H24 H25 H26 J20 J21 F23 F24 F25 F26 G21 G23 G24 E26 EVM_A4 EVM_BEn0 EVM_CLKX0 EVM_BEn2 EVM_A21 EVM_DX0 EVM_D28 EVM_D30 B24 B25 C24 C25 D23 D25 E22 E24 E25 DAC_B_D5 EVM_A20 EVM_A18 EVM_A16 EVM_A14 EVM_A12 USER_LED3 EVM_A6 EVM_A2 1.2V 6 0 VREF 2 GND 2 VCCINT CYCLONE II, BANK 5 VCCIO = 3.3V EP2C70F672C6N IO_251 IO_252 IO_253 IO_254 IO_255 IO_256 IO_257 IO_258 IO_259 IO_260 IO_241 IO_242 IO_243 IO_244 IO_245 IO_246 IO_247 IO_248 IO_249 IO_250 IO_234 IO_235 IO_236 IO_237 IO_238 IO_239 IO_240 IO_231 IO_222 IO_223 IO_224 IO_225 IO_226 IO_227 IO_228 IO_229 IO_230 U12E 4 5 IO_447 IO_448 IO_449 IO_281 IO_271 IO_272 IO_273 IO_274 IO_275 IO_276 IO_277 IO_278 IO_279 IO_280 IO_261 IO_262 IO_263 IO_264 IO_265 IO_266 IO_267 IO_268 IO_269 IO_270 D26 E23 G22 P18 M20 M21 M22 M23 M24 M25 N18 N20 N23 N24 K24 K25 K26 L19 L20 L21 L23 L24 L25 M19 EVM_A10 EVM_A8 EVM_FSX0 4 EVM_D4 EVM_D31 EVM_DMAC0 EVM_D6 EVM_CNTL0 EVM_INT0 EVM_BEn1 EVM_BEn3 EVM_INT1 EVM_A13 EVM_A9 EVM_A7 EVM_D8 EVM_STAT0 EVM_D10 EVM_INT3 EVM_A3 EVM_A5 EVM_D2 CYCLONE II BANKS 5 & 6 5 EVM_OEn VGA_R3 EVM_D23 VGA_R1 DAC_B_D6 ADC_RESET EVM_D25 SRAM_CLK 3 PROTO_CLKIN DAC_B_D7 EVM_D27 EVM_INT2 ADC_SCLK VGA_R2 EVM_D9 EVM_D5 EVM_D7 DIG_MSB_C EVM_D29 EVM_D1 EVM_D3 VGA_R4 AUDIO_CSn 3 1.2V AA23 R24 R25 T17 T18 T19 T20 T21 T22 T23 T24 P17 P23 P24 R17 R19 R20 AC26 AD24 AD25 AA24 AA25 AA26 AB23 AB24 AB25 AB26 AC23 AC25 VCCIO = 3.3V IO_331 IO_332 IO_333 IO_334 IO_335 IO_336 IO_321 IO_322 IO_323 IO_324 IO_325 IO_326 IO_327 IO_328 IO_329 IO_330 IO_311 IO_312 IO_313 IO_314 IO_315 IO_316 IO_317 IO_318 Y21 Y22 Y23 Y24 Y25 Y26 V22 V23 V24 V25 V26 W21 W23 W24 W25 W26 T25 U20 U21 U22 U23 U24 U25 U26 DIG_MSB_A VGA_R0 EPCS_USER_CSn DAC_B_D8 VGA_R7 EVM_D11 EVM_D0 EVM_AW En DAC_B_D9 DAC_B_D12 EVM_D17 DIG_MSB_G EVM_ARDY EVM_D13 DAC_B_D10 DAC_B_D11 DAC_B_D13 DAC_B_D2 VGA_R5 EVM_D15 DIG_LSB_F EVM_D19 DIG_LSB_B EVM_D21 1 Date: Size B 2 Sheet 6 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 0 VREF 2 GND 4 VCCINT CYCLONE II, BANK 6 EP2C70F672C6N IO_460 IO_301 IO_302 IO_303 IO_304 IO_305 IO_306 IO_307 IO_308 IO_309 IO_310 IO_295 IO_296 IO_297 IO_298 IO_299 IO_300 IO_291 IO_292 IO_293 IO_282 IO_283 IO_284 IO_285 IO_286 IO_287 IO_288 IO_289 IO_290 U12F 2 C Rev A B C D E A B C D E 8 3,5,17 3 7 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. DIMM_SYNC_CLK PROTO_CLKIN 6,19 USER_DIPSW [7:0] USER_PB[3..0] 3,17 DIMM_RESETn 8 DIMM_SCL 8 DIMM_SDA 8 DIMM_CK_N[2..0] DIMM_CK_P[2..0] 8 DIMM_ODT_R1 9 DIMM_ODT_R0 9 DIMM_CKE_R1 9 DIMM_CKE_R0 9 DIMM_CSn_R1 9 DIMM_CSn_R0 9 DIMM_W En_R 9 DIMM_CASn_R 9 DIMM_RASn_R 9 DIMM_DM[8..0] 5,8,9 DIMM_BA_R[2..0] 9 DIMM_A_R[15..0] 9 DIMM_DQS[8..0] 5,8,9 DIMM_DQ[71..0] 5,8,9 8 AA17 AA18 AB15 AB18 AB20 AB21 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AD15 AD16 AD17 AD19 AD21 AD22 AD23 AE15 AE16 AE17 AE18 AE19 AE20 AE21 DIMM_W En_R DIMM_SCL DIMM_BA_R2 DIMM_CSn_R1 DIMM_CK_P1 DIMM_SYNC_CLK DIMM_DQ10 DIMM_DM0 DIMM_DQ1 USER_PB0 DIMM_CKE_R1 USER_DIPSW 5 DIMM_CK_P0 DIMM_CASn_R UNUSED I/O DIMM_DQ7 DIMM_DQ5 DIMM_CK_N0 DIMM_CK_N1 DIMM_CK_P2 DIMM_RESETn DIMM_DQS1 USER_PB1 DIMM_DQ2 USER_DIPSW 6 USER_DIPSW 7 DIMM_RASn_R DIMM_CKE_R0 VCCIO = 1.8V 2 VREF 4 GND 5 VCCINT EP2C70F672C6N IO_361 IO_362 IO_363 IO_364 IO_365 IO_366 IO_367 IO_368 IO_369 IO_370 IO_351 IO_352 IO_353 IO_354 IO_355 IO_356 IO_357 IO_358 IO_359 IO_360 IO_344 IO_345 IO_346 IO_347 IO_348 IO_349 IO_350 IO_341 IO_342 IO_337 IO_338 IO_339 IO_340 J11 DIMM_SYNC_CLK 6 (secondary use) 5 SMA for External Clock Input / Eye Diagram Output 1 LTI-SASF54GT IO_455 IO_391 IO_392 IO_381 IO_382 IO_383 IO_384 IO_385 IO_386 IO_387 IO_388 IO_389 IO_390 IO_371 IO_372 IO_373 IO_374 IO_375 IO_376 IO_377 IO_378 IO_379 IO_380 CYCLONE II, BANK 7 U12G 5 4 0.1uF C201 DIMM_CK_N2 AA20 R102 56 DIMM_DQ4 DIMM_BA_R0 Y16 Y18 VTT DIMM_DQ12 DIMM_DQ13 DIMM_DQ8 4 USER_PB2 DIMM_ODT_R1 DIMM_DQ3 DIMM_DQ6 DIMM_DQS0 DIMM_SDA DIMM_ODT_R0 DIMM_CSn_R0 DIMM_BA_R1 U18 V17 V18 W15 W16 W17 W19 Y13 Y14 Y15 AE22 AE23 AF17 AF18 AF19 AF20 AF21 AF22 AF23 U17 1.2V CYCLONE II BANKS 7 & 8 Resynchronization Feedback Clock DIMM_DQ9 DIMM_DQ0 AA13 AA14 AA15 AA16 VREF DIMM_DQ14 6 5 4 3 2 DIMM_A_R2 DIMM_A_R5 DIMM_DM3 DIMM_DQ17 DIMM_DQ21 DIMM_DQ11 DIMM_A_R0 DIMM_A_R10 DIMM_DQ26 DIMM_DQ27 3 AD6 AD7 AD8 AD10 AD11 AD12 AE4 AE5 AE6 AE7 AD5 DIMM_A_R8 DIMM_DQ16 DIMM_A_R1 DIMM_DM2 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AA9 AA10 AA11 AA12 AB8 AB10 AB12 VREF DIMM_A_R14 DIMM_A_R6 DIMM_DQ31 DIMM_DQ25 DIMM_DQ29 DIMM_DM1 DIMM_A_R7 DIMM_DQ24 DIMM_DQ20 3 VCCIO = 1.8V IO_461 IO_462 IO_441 IO_442 IO_443 IO_444 IO_445 IO_446 IO_431 IO_432 IO_433 IO_434 IO_435 IO_436 IO_437 IO_438 IO_439 IO_440 IO_421 IO_422 IO_423 IO_424 IO_425 IO_426 IO_427 IO_428 IO_429 IO_430 DIMM_A_R3 DIMM_DQ28 DIMM_A_R12 DIMM_A_R11 DIMM_DQS3 AD4 AE8 DIMM_DQ23 DIMM_DQ22 DIMM_A_R15 DIMM_DQ19 DIMM_DQ18 DIMM_A_R9 DIMM_DQ15 DIMM_DQS2 USER_DIPSW 4 DIMM_A_R4 DIMM_DQ30 DIMM_A_R13 UNUSED I/O W10 W11 W12 Y10 Y11 Y12 AF9 AF10 AF13 U12 V9 V10 V11 V13 V14 W8 AE9 AE10 AE11 AE12 AE13 AF4 AF5 AF6 AF7 AF8 1.2V 1 Date: Size B 2 Sheet 7 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 VREF 7 GND 4 VCCINT EP2C70F672C6N IO_411 IO_412 IO_413 IO_414 IO_415 IO_416 IO_417 IO_418 IO_419 IO_420 IO_410 IO_401 IO_402 IO_403 IO_404 IO_405 IO_406 IO_407 IO_408 IO_393 IO_394 IO_395 IO_396 IO_397 IO_398 IO_399 CYCLONE II, BANK 8 U12H 2 C Rev A B C D E A B C D E 1.8V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 J8A DIMM_CASn DIMM_W En DIMM_CSn0 DIMM_CSn1 9 DIMM_CASn 9 DIMM_W En 9 DIMM_CSn0 9 DIMM_CSn1 DIMM_CKE1 DIMM_ODT0 9 DIMM_CKE1 9 DIMM_ODT0 TP1 Place near DIMM back-side on component side of PCB 54101-G05-01LF 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 0.1uF C55 MT8HTF3264AY-40E 54101-G05-01LF DIMM_RESETn 7 DIMM_RESETn TP2 DIMM_SCL 7 DIMM_SCL VTT DIMM_SDA 7 DIMM_SDA XJ8 DIMM_ODT1 9 DIMM_ODT1 DUAL INLINE MEMORY MODULE DIMM_CKE0 9 DIMM_CKE0 7 DIMM_CK_N[2..0] 7 DIMM_CK_P[2..0] DIMM_RASn 9 DIMM_RASn 6 DIMM_A5 DIMM_A11 DIMM_A7 DIMM_BA2 DIMM_CKE0 DIMM_DQ66 DIMM_DQ67 DIMM_DQS8 DIMM_DQ64 DIMM_DQ65 DIMM_DQ26 DIMM_DQ27 DIMM_DQS3 DIMM_DQ24 DIMM_DQ25 DIMM_DQ18 DIMM_DQ19 DIMM_DQS2 DIMM_DQ16 DIMM_DQ17 DIMM_DQ10 DIMM_DQ11 DIMM_RESETn DIMM_DQS1 DIMM_DQ8 DIMM_DQ9 DIMM_DQ2 DIMM_DQ3 DIMM_DQS0 DIMM_DQ0 DIMM_DQ1 DDR2 DIMM VSS34 DQ4 DQ5 VSS35 DM0/DQS_P9 NC/DQS_N9 VSS36 DQ6 DQ7 VSS37 DQ12 DQ13 VSS38 DM1/DQS_P10 NC/DQS_N10 VSS39 CK_P1/RFU CK_N1/RFU VSS40 DQ14 DQ15 VSS41 DQ20 DQ21 VSS42 DM2/DQS_P11 NC/DQS_N11 VSS43 DQ22 DQ23 VSS44 DQ28 DQ29 VSS45 DM3/DQS_P12 NC/DQS_N12 VSS46 DQ30 DQ31 VSS47 CB4 CB5 VSS48 DM8/DQS_P17 NC/DQS_N17 VSS49 CB6 CB7 VSS50 VDDQ7 CKE1 VDD5 A15 A14 VDDQ8 A12 A9 VDD6 A8 A6 DIMM_A[15..0] VREF VSS1 DQ0 DQ1 VSS2 DQS_N0 DQS_P0 VSS3 DQ2 DQ3 VSS4 DQ8 DQ9 VSS5 DQS_N1 DQS_P1 VSS6 RESETn NC1 VSS7 DQ10 DQ11 VSS8 DQ16 DQ17 VSS9 DQS_N2 DQS_P2 VSS10 DQ18 DQ19 VSS11 DQ24 DQ25 VSS12 DQS_N3 DQS_P3 VSS13 DQ26 DQ27 VSS14 CB0 CB1 VSS15 DQS_N8 DQS_P8 VSS16 CB2 CB3 VSS17 VDDQ1 CKE0 VDD1 BA2/A16 RC0 VDDQ2 A11 A7 VDD2 A5 DIMM_BA[2..0] 9 DIMM_A[15..0] DIMM_DQ[71..0] 9 DIMM_BA[2..0] DIMM_DM[8..0] 5,7,9 DIMM_DQ[71..0] VREF 5 4 5 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 1.8V DIMM_A8 DIMM_A6 DIMM_A12 DIMM_A9 DIMM_A15 DIMM_A14 DIMM_CKE1 DIMM_DQ70 DIMM_DQ71 DIMM_DM8 DIMM_DQ68 DIMM_DQ69 DIMM_DQ30 DIMM_DQ31 DIMM_DM3 DIMM_DQ28 DIMM_DQ29 DIMM_DQ22 DIMM_DQ23 DIMM_DM2 DIMM_DQ20 DIMM_DQ21 DIMM_DQ14 DIMM_DQ15 DIMM_CK_P1 DIMM_CK_N1 DIMM_DM1 DIMM_DQ12 DIMM_DQ13 DIMM_DQ6 DIMM_DQ7 DIMM_DM0 DIMM_DQ4 DIMM_DQ5 4 1.8V R91 R89 10.0K, 1%10.0K, 1% DDR2 SDRAM DIMM DIMM_DQS[8..0] 6 5,7,9 DIMM_DM[8..0] 7 5,7,9 DIMM_DQS[8..0] 8 1.8V 3 DIMM_SDA DIMM_SCL DIMM_DQ58 DIMM_DQ59 DIMM_DQS7 DIMM_DQ56 DIMM_DQ57 DIMM_DQ50 DIMM_DQ51 DIMM_DQS6 DIMM_DQ48 DIMM_DQ49 DIMM_DQ42 DIMM_DQ43 DIMM_DQS5 DIMM_DQ40 DIMM_DQ41 DIMM_DQ34 DIMM_DQ35 DIMM_DQS4 DIMM_DQ32 DIMM_DQ33 DIMM_CSn1 DIMM_ODT1 DIMM_W En DIMM_CASn DIMM_A10 DIMM_BA0 DIMM_A2 DIMM_A4 3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 61 62 63 64 CK_P0 CK_N0 VDD8 A0 VDD9 BA1 VDDQ10 RASn Sn0 VDDQ11 ODT0 A13 VDD10 VSS51 DQ36 DQ37 VSS52 DM4/DQS_P13 NC/DQS_N13 VSS53 DQ38 DQ39 VSS54 DQ44 DQ45 VSS55 DM5/DQS_P14 NC/DQS_N14 VSS56 DQ46 DQ47 VSS57 DQ52 DQ53 VSS58 CK_P2/RFU CK_N2/RFU VSS59 DM6/DQS_P15 NC/DQS_N15 VSS60 DQ54 DQ55 VSS61 DQ60 DQ61 VSS62 DM7/DQS_P16 NC/DQS_N16 VSS63 DQ62 DQ63 VSS64 VDDSPD SA0 SA1 KEY VDDQ9 A3 A1 VDD7 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 181 182 183 184 1.8V DIMM_DQ62 DIMM_DQ63 DIMM_DM7 DIMM_DQ60 DIMM_DQ61 DIMM_DQ54 DIMM_DQ55 DIMM_DM6 DIMM_CK_P2 DIMM_CK_N2 DIMM_DQ52 DIMM_DQ53 DIMM_DQ46 DIMM_DQ47 DIMM_DM5 DIMM_DQ44 DIMM_DQ45 DIMM_DQ38 DIMM_DQ39 DIMM_DM4 DIMM_DQ36 DIMM_DQ37 DIMM_ODT0 DIMM_A13 DIMM_RASn DIMM_CSn0 DIMM_BA1 DIMM_A0 DIMM_CK_P0 DIMM_CK_N0 DIMM_A3 DIMM_A1 1 Date: Size B 2 Sheet 8 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 DDR2 DIMM VSS18 VSS19 VDD4 NC2 VDD5 A10/AP BA0 VDDQ4 WEn CASn VDDQ5 Sn1 ODT1 VDDQ6 VSS20 DQ32 DQ33 VSS21 DQS_N4 DQS_P4 VSS22 DQ34 DQ35 VSS23 DQ40 DQ41 VSS24 DQS_N5 DQS_P5 VSS25 DQ42 DQ43 VSS26 DQ48 DQ49 VSS27 SA2 NC/TEST VSS28 DQS_N6 DQS_P6 VSS29 DQ50 DQ51 VSS30 DQ56 DQ57 VSS31 DQS_N7 DQS_P7 VSS32 DQ58 DQ59 VSS33 SDA SCL A4 VDDQ3 A2 VDD3 J8B 2 C Rev A B C D E A B C D E DIMM_ODT0 DIMM_ODT1 8 DIMM_ODT0 8 DIMM_ODT1 7 RN20C RN21F RN21E RN21G RN21H RN21D RN23D RN21C RN23E RN22G RN22C RN23A RN22B RN22F RN22E RN22D RN22H RN23F RN23H RN23B RN23G RN22A RN21A RN21B DIMM_A_R9 DIMM_A_R11 DIMM_A_R8 DIMM_A_R5 DIMM_A_R6 DIMM_A_R7 DIMM_A_R3 DIMM_A_R4 DIMM_A_R10 DIMM_A_R2 DIMM_A_R1 DIMM_A_R0 DIMM_A_R15 DIMM_A_R14 DIMM_A_R13 DIMM_A_R12 DIMM_CKE_R0 DIMM_BA_R2 DIMM_BA_R1 DIMM_BA_R0 DIMM_CKE_R1 DIMM_RASn_R DIMM_W En_R DIMM_CASn_R DIMM_CSn_R0 DIMM_CSn_R1 DIMM_ODT_R0 DIMM_ODT_R1 8 6 8 2 7 1 1 2 5 7 3 1 2 6 5 4 3 6 5 7 8 4 4 3 1 2 3 8 7 5 6 4 9 11 9 15 10 16 16 15 12 10 14 16 15 11 12 13 14 11 12 10 9 13 13 14 16 15 14 9 10 12 11 13 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 DIMM_W En DIMM_CASn DIMM_CSn0 DIMM_CSn1 DIMM_ODT0 DIMM_ODT1 DIMM_A13 DIMM_A12 DIMM_CKE0 DIMM_BA2 DIMM_BA1 DIMM_BA0 DIMM_CKE1 DIMM_RASn DIMM_A3 DIMM_A4 DIMM_A10 DIMM_A2 DIMM_A1 DIMM_A0 DIMM_A15 DIMM_A14 DIMM_A9 DIMM_A11 DIMM_A8 DIMM_A5 DIMM_A6 DIMM_A7 8 7 DIMM_DQ0 DIMM_DQ4 DIMM_DQS0 DIMM_DQ3 DIMM_DQ1 DIMM_DQ7 DIMM_DQ6 DIMM_DQ5 DIMM_DQ71 DIMM_DQ64 VTT C194 0.01uf 0.01uf 0.01uf 0.01uf C272 C294 C307 RN32D RN32F RN32G RN30D RN30C RN32H RN34A RN34E RN24H RN33A RN24F RN24G RN24A RN33D RN24B RN24D DIMM_DQ65 DIMM_DQ2 DIMM_DQ69 DIMM_DQ68 DIMM_DQ67 DIMM_DM0 DIMM_DQ70 DIMM_DM8 RN29C RN27E RN27G RN29D RN25E RN25H RN25F RN25D RN31F RN29H RN27H RN27C RN27D RN29B RN29A RN27F RN31B RN31A RN31D RN29F RN31E RN31C RN29G RN29E RN33G RN33H RN33C RN31G RN33F RN31H RN33B RN33E 0.01uf C195 0.01uf C260 4 6 7 4 3 8 1 5 8 1 6 7 1 4 2 4 1 3 2 1 7 2 5 3 3 5 7 4 5 8 6 4 6 8 8 3 4 2 1 6 2 1 4 6 5 3 7 5 7 8 3 7 6 8 2 5 R18 R15 RN27A RN25C RN25B RN25A RN25G RN27B RN24E RN24C DIMM_DQ55 DIMM_DQ54 DIMM_DQS6 DIMM_DQ52 DIMM_DQ53 DIMM_DM6 DIMM_DQ58 DIMM_DQS7 6 6 0.01uf VTT C196 0.01uf VTT C324 13 11 10 13 14 9 16 12 9 16 11 10 16 13 15 13 16 14 15 16 10 15 12 14 14 12 10 13 12 9 11 13 11 9 9 14 13 15 16 11 15 16 13 11 12 14 10 12 10 9 14 10 11 9 15 12 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 DIMM_DQ56 DIMM_DQ59 DIMM_DQ63 DIMM_DQ57 DIMM_DQ61 DIMM_DM7 DIMM_DQ60 DIMM_DQ62 DIMM_DQ46 DIMM_DQ43 DIMM_DQ47 DIMM_DM5 DIMM_DQ49 DIMM_DQ51 DIMM_DQ50 DIMM_DQ48 DIMM_DQ38 DIMM_DM4 DIMM_DQ40 DIMM_DQ41 DIMM_DQS5 DIMM_DQ45 DIMM_DQ42 DIMM_DQ44 DIMM_DQ32 DIMM_DQ33 DIMM_DQ34 DIMM_DQS4 DIMM_DQ35 DIMM_DQ39 DIMM_DQ36 DIMM_DQ37 RN34G RN34B RN34C RN34H RN32A RN34F RN32B RN34D RN30G RN30E RN30H RN28B RN30A RN32C RN32E RN30B RN26B RN26D RN28D RN28C RN28A RN28E RN30F RN28F RN26F RN26E RN26A RN26C RN28H RN28G RN26G RN26H 7 2 3 8 1 6 2 4 7 5 8 2 1 3 5 2 2 4 4 3 1 5 6 6 6 5 1 3 8 7 7 8 10 15 14 9 16 11 15 13 10 12 9 15 16 14 12 15 15 13 13 14 16 12 11 11 11 12 16 14 9 10 10 9 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 VTT 56 56 56 56 56 56 56 56 0.01uf C197 0.01uf 0.01uf C200 0.01uf 0.01uf C198 0.01uf 0.01uf C202 0.01uf 5 0.01uf VTT C204 0.01uf 0.01uf C203 0.01uf C271 2.2uf C209 VTT C207 2.2uf C192 C206 2.2uf 2.2uf C205 C362 C254 C193 VTT RN24, RN25, RN26, RN27, RN28, RN29, RN30, RN31, RN32, RN33, RN34, R15, R18 The following resistors can be installed for Class II Termination: C199 VTT 4 0.01uf VTT C224 0.01uf C304 RN18H RN18G RN18F RN18E RN18D RN18C RN18B RN18A DIMM_DQ2 DIMM_DQ3 DIMM_DQ12 DIMM_DQ13 DIMM_DQ8 DIMM_DQ9 DIMM_DM1 DIMM_DQS1 0.01uf C282 0.01uf 0.01uf 4 RN12H RN12G RN12F RN12E RN12D RN12C RN12B RN12A DIMM_A9 DIMM_A11 DIMM_A7 DIMM_A8 DIMM_A6 DIMM_A5 DIMM_A4 DIMM_A3 C354 RN13H RN13G RN13F RN13E RN13C RN13B RN13D RN13A DIMM_DQ66 DIMM_DQ67 DIMM_CKE1 DIMM_CKE0 DIMM_A15 DIMM_A14 DIMM_BA2 DIMM_A12 C318 RN14H RN14G RN14F RN14E RN14D RN14C RN14A RN14B RN15H RN15F RN15G RN15E RN15D RN15B RN15C RN15A DIMM_DQ24 DIMM_DQ25 DIMM_DM3 DIMM_DQS3 DIMM_DQ30 DIMM_DQ31 DIMM_DQ26 DIMM_DQ27 DIMM_DQ68 DIMM_DQ69 DIMM_DQ64 DIMM_DQ65 DIMM_DM8 DIMM_DQS8 DIMM_DQ70 DIMM_DQ71 RN16H RN16G RN16E RN16D RN16F RN16C RN16B RN16A DIMM_DM2 DIMM_DQS2 DIMM_DQ22 DIMM_DQ23 DIMM_DQ18 DIMM_DQ19 DIMM_DQ28 DIMM_DQ29 RN17H RN17F RN17G RN17E RN17C RN17B RN17D RN17A RN19H RN19G RN19F RN19D RN19E RN19C RN19B RN19A DIMM_DQ4 DIMM_DQ5 DIMM_DQ0 DIMM_DQ1 DIMM_DM0 DIMM_DQS0 DIMM_DQ6 DIMM_DQ7 DIMM_DQ14 DIMM_DQ15 DIMM_DQ10 DIMM_DQ11 DIMM_DQ20 DIMM_DQ21 DIMM_DQ16 DIMM_DQ17 3 8 7 6 5 4 3 2 1 8 7 6 5 3 2 4 1 8 7 6 5 4 3 1 2 8 6 7 5 4 2 3 1 8 7 5 4 6 3 2 1 8 6 7 5 3 2 4 1 8 7 6 5 4 3 2 1 8 7 6 4 5 3 2 1 9 10 11 12 13 14 15 16 9 10 11 12 14 15 13 16 9 10 11 12 13 14 16 15 9 11 10 12 13 15 14 16 9 10 12 13 11 14 15 16 9 11 10 12 14 15 13 16 9 10 11 12 13 14 15 16 9 10 11 13 12 14 15 16 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 VTT 3 DIMM_DM7 DIMM_DQS7 DIMM_DQ62 DIMM_DQ63 DIMM_DQ58 DIMM_DQ59 DIMM_DQ54 DIMM_DQ55 DIMM_DQ50 DIMM_DQ51 DIMM_DQ60 DIMM_DQ61 DIMM_DQ56 DIMM_DQ57 DIMM_DQ42 DIMM_DQ43 DIMM_DQ52 DIMM_DQ53 DIMM_DQ48 DIMM_DQ49 DIMM_DM6 DIMM_DQS6 DIMM_DQ44 DIMM_DQ45 DIMM_DQ40 DIMM_DQ41 DIMM_DM5 DIMM_DQS5 DIMM_DQ46 DIMM_DQ47 DIMM_DQ32 DIMM_DQ33 DIMM_DM4 DIMM_DQS4 DIMM_DQ38 DIMM_DQ39 DIMM_DQ34 DIMM_DQ35 DIMM_W En DIMM_CASn DIMM_ODT0 DIMM_A13 DIMM_CSn1 DIMM_ODT1 DIMM_DQ36 DIMM_DQ37 DIMM_A1 DIMM_A2 DIMM_A0 DIMM_BA1 DIMM_A10 DIMM_BA0 DIMM_RASn DIMM_CSn0 RN5H RN5G RN5E RN5D RN5F RN5C RN5B RN5A RN6H RN6F RN6G RN6E RN6C RN6B RN6D RN6A RN7H RN7G RN7F RN7E RN7D RN7C RN7B RN7A RN8G RN8H RN8F RN8D RN8E RN8C RN8B RN8A RN9H RN9G RN9F RN9E RN9D RN9C RN9B RN9A RN10H RN10G RN10F RN10D RN10E RN10C RN10A RN10B RN11H RN11G RN11F RN11D RN11E RN11C RN11B RN11A DIMM-Side Termination Resistors DDR2 SDRAM DIMM Terminations 5 Cyclone II-Side Termination Resistors DIMM_DQ29 DIMM_DQ26 DIMM_DQ27 DIMM_DQ31 DIMM_DQ25 DIMM_DQ28 DIMM_DQS8 DIMM_DQ66 DIMM_DQ16 DIMM_DQ18 DIMM_DQS2 DIMM_DQ20 DIMM_DM3 DIMM_DQ24 DIMM_DQS3 DIMM_DQ30 DIMM_DQ12 DIMM_DQ14 DIMM_DM2 DIMM_DQ19 DIMM_DQ23 DIMM_DQ21 DIMM_DQ17 DIMM_DQ22 DIMM_DM1 DIMM_DQS1 DIMM_DQ13 DIMM_DQ11 DIMM_DQ8 DIMM_DQ9 DIMM_DQ10 DIMM_DQ15 VTT Copyright (c) 2005, Altera Corporation. All Rights Reserved. RN20A RN20B RN23C RN20H RN20G RN20E RN20F RN20D Cyclone II-Side Termination Resistors DIMM_CKE0 DIMM_CKE1 DIMM_BA[2..0] 8 DIMM_BA[2..0] 8 DIMM_CKE0 8 DIMM_CKE1 DIMM_A[15..0] 8 DIMM_A[15..0] DIMM_CSn0 DIMM_CSn1 DIMM_ODT_R0 DIMM_ODT_R1 7 DIMM_ODT_R0 7 DIMM_ODT_R1 8 DIMM_CSn0 8 DIMM_CSn1 DIMM_CKE_R0 DIMM_CKE_R1 7 DIMM_CKE_R0 7 DIMM_CKE_R1 DIMM_RASn DIMM_CASn DIMM_W En DIMM_CSn_R0 DIMM_CSn_R1 7 DIMM_CSn_R0 7 DIMM_CSn_R1 8 DIMM_RASn 8 DIMM_CASn 8 DIMM_W En DIMM_RASn_R DIMM_CASn_R DIMM_W En_R DIMM_BA_R[2..0] 7 DIMM_BA_R[2..0] 7 DIMM_RASn_R 7 DIMM_CASn_R 7 DIMM_W En_R DIMM_A_R[15..0] 7 DIMM_A_R[15..0] DIMM_DM[8..0] DIMM_DQS[8..0] 5,7,8 DIMM_DQS[8..0] 5,7,8 DIMM_DM[8..0] DIMM_DQ[71..0] 5,7,8 DIMM_DQ[71..0] 8 8 7 5 4 6 3 2 1 8 6 7 5 3 2 4 1 8 7 6 5 4 3 2 1 7 8 6 4 5 3 2 1 8 7 6 5 4 3 2 1 8 7 6 4 5 3 1 2 8 7 6 4 5 3 2 1 VTT VTT 0.1uf x 4 8 7 6 5 0.1uf x 4 8 7 6 5 0.1uf x 4 8 7 6 5 0.1uf x 4 8 7 6 5 CN1 1 2 3 4 CN26 0.1uf x 4 1 8 2 7 3 6 4 5 0.1uf x 4 8 7 6 5 CN21 0.1uf x 4 1 8 2 7 3 6 4 5 CN23 0.1uf x 4 1 8 2 7 3 6 4 5 CN17 0.1uf x 4 1 8 2 7 3 6 4 5 CN24 0.1uf x 4 1 8 2 7 3 6 4 5 CN22 0.1uf x 4 1 8 2 7 3 6 4 5 CN25 0.1uf x 4 1 8 2 7 3 6 4 5 CN8 1 2 3 4 CN3 1 2 3 4 CN11 0.1uf x 4 1 8 2 7 3 6 4 5 VTT CN18 0.1uf x 4 1 8 2 7 3 6 4 5 CN15 0.1uf x 4 1 8 2 7 3 6 4 5 CN19 0.1uf x 4 1 8 2 7 3 6 4 5 CN20 0.1uf x 4 1 8 2 7 3 6 4 5 CN2 1 2 3 4 CN9 1 2 3 4 CN16 0.1uf x 4 1 8 2 7 3 6 4 5 VTT 0.1uf x 4 8 7 6 5 0.1uf x 4 8 7 6 5 0.1uf x 4 8 7 6 5 CN7 1 2 3 4 0.1uF C65 0.1uf x 4 8 7 6 5 CN13 0.1uf x 4 1 8 2 7 3 6 4 5 CN12 0.1uf x 4 1 8 2 7 3 6 4 5 CN14 0.1uf x 4 1 8 2 7 3 6 4 5 CN4 1 2 3 4 CN5 1 2 3 4 CN10 0.1uf x 4 1 8 2 7 3 6 4 5 CN6 1 2 3 4 DIMM Memory Decoupling 1 Date: 2 Sheet 9 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Size B 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 Title 9 10 12 13 11 14 15 16 9 11 10 12 14 15 13 16 9 10 11 12 13 14 15 16 10 9 11 13 12 14 15 16 9 10 11 12 13 14 15 16 9 10 11 13 12 14 16 15 9 10 11 13 12 14 15 16 2 C Rev A B C D E A B C D E 2X5_SH 2 4 6 8 10 J9 1 3 5 7 9 R82 1K R88 1K JTAG_CONN_TDO JTAG_TCK JTAG_CONN_TDI JTAG_TMS R92 1K 7 EP2C_MSEL0 EP2C_MSEL1 EP2C_CEn R132 1K 2X5 1 3 5 7 9 J13 2 4 6 8 10 2 4 6 8 10 R131 R104 1K 1K R33 IS NOT INSTALLED 1 3 5 7 9 3.3V EP2C_CEn EP2C_CSOn 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 3.3V EP2C_DCLK EP2C_CONFIG_DONE EP2C_B_CONFIGn EP2C_DATA0 EP2C_ASDO 3.3V SURFACE MOUNT ACTIVE SERIAL HEADER 3.3V 3.3V RIGHT ANGLE JTAG HEADER 8 100R, 1% 6 10.0K, 1% EPCS_SAFE_CSn 10.0K, 1% EPCS_USER_CSn JTAG_TCK JTAG_TMS JTAG_CONN_TDO JTAG_CONN_TDI R157 R165 19 19 19 19 100pf C409 R273 6 3.3V P20 P21 R107 R57 R133 R110 EVM_CEn3 18 EP2C_MSEL0 EP2C_MSEL1 N4 M6 L8 M8 M7 AE25 JTAG_TCK JTAG_TMS JTAG_CONN_TDO JTAG_CONN_TDI EP2C_CEN 4 5 10.0K, 1% 332R, 1% 10.0K, 1% 10.0K, 1% CLKUSR DEV_CLRn nSTATUS CONF_DONE nCONFIG nCEO DCLK DATA0 nCSO ASDO B3 C5 R22 R23 N7 EP2C_STATUSn EP2C_CONFIG_DONE EP2C_CONFIGn EP2C_DCLK EP2C_DATA0 EP2C_CSOn EP2C_ASDO 4 17 USER_LED1 11 ADC_A_D0 AE24 N6 N3 D3 E3 EP2C_CONFIGn EP2C_CONFIG_DONE EP2C_STATUSn EP2C_B_CONFIGn EP2C70F672C6N INIT_DONE MSEL0 MSEL1 nCE TCK TMS TDI TDO CYCLONE II, CONFIG U12I U35 3 3 1 3 EP2C_B_CONFIGn BAW 56LT1G 2 SYS_RESETn CONFIGURATION CIRCUITRY 5 NC8 NC7 NC6 NC5 GND VCC1 VCC2 VCC3 EPCS64 NC1 NC2 NC3 NC4 DCLK DATA nCS ASDI Green_LED D10 3 4 5 6 16 8 7 15 U36 USER EPCS NC8 NC7 NC6 NC5 GND VCC1 VCC2 VCC3 EPCS64 NC1 NC2 NC3 NC4 DCLK DATA nCS ASDI J29 14 13 12 11 10 1 2 9 14 13 12 11 10 1 2 9 881545-2 SHUNT7 3.3V 3.3V 1 Date: Size B 2 Sheet 10 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 EP2C_CONFIG_DONE EP2C_DCLK EP2C_DATA0 EPCS_USER_CSn EP2C_ASDO SYS_RESETn 17 3 4 5 6 16 8 7 15 U17 SAFE EPCS 3X1 EPCS_SAFE_CSn 1 EP2C_CSOn 2 EPCS_USER_CSn 3 EPCS SELECT EP2C_DCLK EP2C_DATA0 EPCS_SAFE_CSn EP2C_ASDO 6 EPCS_USER_CSn 2 A C C Rev A B C D E A B C D E ADC_A_IN TC4_1W + 6 6 4 8 S 1 2 3 ADC_A_CM ADC A DECOUPLING CAPS TC4_1W + T2 4 P ANALOG POWER 3 2 1 T3 RN35A RN35B RN35C RN35D RN35E RN35F RN35G RN35H ADC_A_D7 ADC_A_D6 ADC_A_D5 ADC_A_D4 ADC_A_D3 ADC_A_D2 ADC_A_D1 ADC_A_D0 ADC CHANNEL A RN36A RN36B RN36C RN36D RN36E RN36F RN36G RN36H ADC_A_D13 ADC_A_D12 ADC_A_D11 ADC_A_D10 ADC_A_D9 ADC_A_D8 6 7 6 ADC 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 R40 R41 24.9, 1% C139 R38 24.9, 1% R37 C117 1R 0.1uF 0.1uF 0.01uf C166 C378 C129 1R ADC 0.01uf EXB-2HV330JV ADC_A_R_D7 ADC_A_R_D6 EXB-2HV330JV ADC_A_R_D5 EXB-2HV330JV EXB-2HV330JV ADC_A_R_D4 ADC_A_R_D3 EXB-2HV330JV EXB-2HV330JV ADC_A_R_D2 ADC_A_R_D1 EXB-2HV330JV ADC_A_R_D0 EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV ADC_A_R_D13 ADC_A_R_D12 EXB-2HV330JV EXB-2HV330JV ADC_A_R_D11 ADC_A_R_D10 EXB-2HV330JV ADC_A_R_D9 EXB-2HV330JV EXB-2HV330JV ADC_A_R_D8 DIGITAL POWER 10uF 3.3V ADC 0.01uf C136 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 C384 C381 C380 C377 C116 C115 C114 C113 C145 C142 C141 C140 ADC R200 Do Not Install 49.9 1 LTI-SASF54GT 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 10uF C146 VCCA_ADC J32 ADC_A_DCLK 3 ADC_A_D[13..0] 3,5,10 ADC_A_OE 4 ADC_A_OVR 5 ADC_RESET 6,12 ADC_A_CLK_P 3 ADC_A_CLK_N 3 5 4 3 2 4 5 0.001uf C109 10pf 0.1uF C118 3.3V CLKBUF ADC_A_INP C135 ADC_A_INM 4 ADC_A_D1 ADC_A_D0 ADC_A_IREF ADC_A_REFM ADC_A_REFP R33 R34 ADC 1R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1R 1R DRGND SCLK SDATA SEN AVDD AGND AVDD AGND AVDD CLKP CLKM AGND AGND AGND AVDD AGND U26 ADC_A_OVR VCCA_ADC R271 C144 0.01uf ADC_A_CM ADC_A_INP ADC_A_INM ADC_A_CLK_N ADC_A_CLK_P C143 0.01uf ADC_SCLK ADC_SDATA ADC_A_SEN ADC Channel A 5 3 ADS5500 3 R201 R202 R30 ADC_A_R_D13 ADC_A_R_D12 ADC_A_R_D11 ADC_A_R_D10 10.0K, 1% 10.0K, 1% 56K C124 C125 0.1uF 0.1uF ADC_A_DFS 1 3 5 7 4X2 1 3 5 7 J30 2 4 6 8 2 4 6 8 ADC_RESET ADC_A_OE ADC_A_DFS ADC_A_R_D3 ADC_A_R_D2 ADC_A_R_D1 ADC_A_R_D0 ADC_A_DCLK 1 3.3V Date: Size B 2 Sheet 11 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 C Rev R166 1.00K, 1% R167 1.00K, 1% R168 1.00K, 1% Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 SHUNT8 881545-2 Data Output Format 2's Complement data valid falling edge Straight Binary data valid falling edge 2's Complement data valid rising edge Straight Binary data valid rising edge ADC Pin 1-2 Pin 3-4 Pin 5-6 Pin 7-8 ADC_A_IREF ADC_A_REFM ADC_A_REFP VCCA_ADC VCCA_ADC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 J30 Position ADC 2 DRGND D3 D2 D1 D0 CLKOUT DRGND OE DFS AVDD AGND AVDD AGND RESET AVDD AVDD 3.3V ADC CHANNEL A ADC_A_R_D9 ADC_A_R_D8 ADC_A_R_D7 ADC_A_R_D6 ADC_A_R_D5 ADC_A_R_D4 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAD_GND OVR D13 D12 D11 D10 DRGND DRVDD DRGND D9 D8 D7 D6 D5 D4 DRGND DRVDD CM AGND INP INM AGND AVDD AGND AVDD AGND AVDD AGND AVDD REFP REFM IREF AGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ADC_SCLK 6,12 ADC_SDATA 4,12 ADC_A_SEN 5 S 8 P A B C D E A B C D E C173 ADC_B_IN T6 TC4_1W + 4 8 S 1 2 3 4 5 6 7 8 1 2 3 ADC_B_CM ADC B DECOUPLING CAPS TC4_1W + 6 6 ANALOG POWER 3 2 1 T5 4 P ADC_B_D7 ADC_B_D6 ADC_B_D5 ADC_B_D4 ADC_B_D3 ADC_B_D2 ADC_B_D1 ADC_B_D0 1 2 3 4 5 6 7 8 6 3.3V ADC 7 6 ADC 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R54 10uF C155 0.1uF 0.1uF 0.01uf C386 C159 C394 24.9, 1% ADC 5 5 0.1uF C153 3.3V CLKBUF ADC_B_INP 0.001uf C161 10pf C162 ADC_B_INM 4 ADC_SCLK ADC_SDATA ADC_B_SEN ADC_B_CLK_N 4 ADC_B_D1 ADC_B_D0 ADC_B_IREF ADC_B_REFM ADC_B_REFP ADC_B_CM ADC_B_INP ADC_B_INM C171 0.01uf ADC_B_CLK_P C170 0.01uf ADC Channel B 24.9, 1% 0.01uf DIGITAL POWER 0.01uf R55 24.9, 1% C165 R53 24.9, 1% R52 EXB-2HV330JV ADC_B_R_D7 ADC_B_R_D6 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D5 ADC_B_R_D4 EXB-2HV330JV ADC_B_R_D3 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D2 ADC_B_R_D1 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D0 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D13 EXB-2HV330JV ADC_B_R_D12 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D11 ADC_B_R_D10 EXB-2HV330JV EXB-2HV330JV ADC_B_R_D9 ADC_B_R_D8 EXB-2HV330JV C163 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 C149 C150 C151 C152 C172 C169 C168 C167 C396 C402 C403 C406 ADC R254 Do Not Install 49.9 1 RN37A RN37B RN37C RN37D RN37E RN37F RN37G RN37H ADC_B_D13 ADC_B_D12 ADC_B_D11 ADC_B_D10 ADC_B_D9 ADC_B_D8 ADC CHANNEL B RN40A RN40B RN40C RN40D RN40E RN40F RN40G RN40H 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 10uF VCCA_ADC J44 LTI-SASF54GT ADC_B_DCLK 3 ADC_B_D[13..0] 5 ADC_B_OE 4 ADC_B_OVR 5 ADC_RESET 6,11 ADC_B_CLK_P 3 ADC_B_CLK_N 3 5 4 3 2 R50 R51 R272 ADC 1R 1R 1R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRGND SCLK SDATA SEN AVDD AGND AVDD AGND AVDD CLKP CLKM AGND AGND AGND AVDD AGND U31 ADC_B_OVR VCCA_ADC 3 ADS5500 3 R56 R58 R49 ADC_B_R_D13 ADC_B_R_D12 ADC_B_R_D11 ADC_B_R_D10 10.0K, 1% 10.0K, 1% 56K C157 C160 0.1uF 0.1uF ADC_B_DFS 1 3 5 7 4X2 1 3 5 7 J38 2 4 6 8 2 4 6 8 ADC_RESET ADC_B_OE ADC_B_DFS ADC_B_R_D3 ADC_B_R_D2 ADC_B_R_D1 ADC_B_R_D0 ADC_B_DCLK 1 3.3V Date: Size B 2 Sheet 12 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 C Rev R242 1.00K, 1% R243 1.00K, 1% R244 1.00K, 1% Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 SHUNT9 881545-2 Data Output Format 2's Complement data valid falling edge Straight Binary data valid falling edge 2's Complement data valid rising edge Straight Binary data valid rising edge ADC VCCA_ADC Pin 1-2 Pin 3-4 Pin 5-6 Pin 7-8 ADC_B_IREF ADC_B_REFM ADC_B_REFP VCCA_ADC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 J38 Position ADC 2 DRGND D3 D2 D1 D0 CLKOUT DRGND OE DFS AVDD AGND AVDD AGND RESET AVDD AVDD 3.3V ADC CHANNEL B ADC_B_R_D9 ADC_B_R_D8 ADC_B_R_D7 ADC_B_R_D6 ADC_B_R_D5 ADC_B_R_D4 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAD_GND OVR D13 D12 D11 D10 DRGND DRVDD DRGND D9 D8 D7 D6 D5 D4 DRGND DRVDD CM AGND INP INM AGND AVDD AGND AVDD AGND AVDD AGND AVDD REFP REFM IREF AGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ADC_SCLK 6,11 ADC_SDATA 4,11 ADC_B_SEN 5 S 8 P A B C D E A B C D E DACA_CLK DAC_A_D[13..0] RN1A RN1B RN1C RN1D RN1E RN1F RN1G RN1H DAC_A_D5 DAC_A_D4 DAC_A_D3 DAC_A_D2 DAC_A_D1 DAC_A_D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 EXB-2HV330JV 15 EXB-2HV330JV 14 EXB-2HV330JV 13 EXB-2HV330JV 12 EXB-2HV330JV 11 EXB-2HV330JV 10 EXB-2HV330JV 9 EXB-2HV330JV 16 EXB-2HV330JV 15 EXB-2HV330JV 14 EXB-2HV330JV 13 EXB-2HV330JV 12 EXB-2HV330JV 11 EXB-2HV330JV 10 EXB-2HV330JV 9 EXB-2HV330JV R_DAC_A_D13 R_DAC_A_D12 R_DAC_A_D11 R_DAC_A_D10 R_DAC_A_D9 R_DAC_A_D8 R_DAC_A_D7 R_DAC_A_D6 R_DAC_A_D5 R_DAC_A_D4 R_DAC_A_D3 R_DAC_A_D2 R_DAC_A_D1 R_DAC_A_D0 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. RN2A RN2B RN2C RN2D RN2E RN2F RN2G RN2H PLACE NEXT TO CYCLONE II DAC_A_D13 DAC_A_D12 DAC_A_D11 DAC_A_D10 DAC_A_D9 DAC_A_D8 DAC_A_D7 DAC_A_D6 3 DACA_CLK 4 DAC_A_D[13..0] 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DAC904 NC Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 U25 6 3.3V 15 0.1uF 5 R25 2K 0.1uF DAC 0.1uF C130 10uF 54101-G05-01LF TP4 DACA_CLK 28 18 17 16 C382 1 0.01uf 0.1uF 0.1uF 1.0uf C123 4 2 DAC 4 R31 49.9 DAC 0.1uF C375 R35 49.9 VCCA_DAC L25 Ferrite_Bead_330hm C379 C383 C385 C388 C119 DAC_A_IOUTp DAC_A_IOUTn 26 20 5 DAC CHANNEL A 22 21 23 0.001uf C137 DAC_A_IOUTn DGND AGND PD CLK FSA REFIN N_INT.EXT IOUT IOUT_n BYP 27 24 19 0.01uf 1.0uf +VD +VA BW C405 C389 6 10uF C376 VCCA_DAC 3 3 DAC 0.1uF C126 1 2 T1 DAC_A_OUT 1 J31 LTI-SASF54GT DAC 1 Date: Size B 2 Sheet 13 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 <Variant Name> 4 5 3 ADT1_1W T6 2 2 3 4 5 7 P 8 S NC C Rev A B C D E A B C D E DACB_CLK DAC_B_D[13..0] RN3A RN3B RN3C RN3D RN3E RN3F RN3G RN3H DAC_B_D5 DAC_B_D4 DAC_B_D3 DAC_B_D2 DAC_B_D1 DAC_B_D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV EXB-2HV330JV R_DAC_B_D13 R_DAC_B_D12 R_DAC_B_D11 R_DAC_B_D10 R_DAC_B_D9 R_DAC_B_D8 R_DAC_B_D7 R_DAC_B_D6 R_DAC_B_D5 R_DAC_B_D4 R_DAC_B_D3 R_DAC_B_D2 R_DAC_B_D1 R_DAC_B_D0 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. RN4A RN4B RN4C RN4D RN4E RN4F RN4G RN4H PLACE NEXT TO CYCLONE II DAC_B_D13 DAC_B_D12 DAC_B_D11 DAC_B_D10 DAC_B_D9 DAC_B_D8 DAC_B_D7 DAC_B_D6 3 DACB_CLK 3,4,6 DAC_B_D[13..0] 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DAC904 NC Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 U30 6 26 20 15 0.1uF R46 2K 5 0.1uF DAC 0.1uF C158 10uF 54101-G05-01LF TP3 28 18 17 16 C401 1 0.01uf 0.1uF 0.1uF 1.0uf C154 4 2 DAC 4 R47 49.9 DAC R48 49.9 0.1uF C391 10uF C392 VCCA_DAC VCCA_DAC L26 Ferrite_Bead_330hm C393 C395 C404 C407 C147 DACB_CLK 22 21 23 DAC_B_IOUTn DGND AGND PD CLK FSA REFIN N_INT.EXT IOUT IOUT_n BYP 0.001uf C164 3.3V 5 DAC CHANNEL B DAC_B_OUTp DAC_B_IOUTn 27 24 19 0.01uf 1.0uf +VD +VA BW C102 C408 6 3 3 DAC 0.1uF C156 1 2 T4 1 J43 LTI-SASF54GT DAC 1 Date: Size B 2 Sheet 14 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 <Variant Name> 4 5 3 ADT1_1W T6 DAC_B_OUT 2 2 3 4 5 7 P 8 S NC C Rev A B C D E 2 3 4 5 6 7 8 9 VGA_G0 VGA_G1 VGA_G2 VGA_G3 VGA_G4 VGA_G5 VGA_G6 VGA_G7 8 7 6 0.1uF 0.1uF 0.1uF C374 13 24 25 37 12 48 39 38 28 27 15 14 1 31 30 35 2.2uf C83 0.1uF C363 3 VGA_VSYNC 5 10uF C86 3.3V R147 33.2R, 1% 3.3V 6 VGA_HSYNC 0.01uf C367 0.1uF 0.1uF R159 18R C368 0.1uF C371 332R, 1% C372 R155 36 34 VGA_CLK VGA_SYNCn VGA_BLANKn 26 11 10 4 33.2R, 1% R135 VGA_VSYNC 6 6 11 7 12 8 13 9 14 10 15 GND GND MMBD3004BRM AC2 AC1 33.2R, 1% R143 3 U37 3.3V VGA_HSYNC VGA_CLK 4 VGA_SYNCn 4 VGA_BLANKn 4 5 1 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 R144 R151 R156 75.0R, 1%75.0R, 1%75.0R, 1% VGA_BLUE 3 4 VGA_GREEN 2 3 AC2 VGA_RED 3 MMBD2004S U39 2 1 6 MMBD3004BRM AC2 AC1 DB15FRA J21 3 U38 Transient Supression 3 Rev C D E Date: Size B 2 Sheet 15 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 C A C364 C365 3.3V NC NC NC NC VDD_D GND GND GND GND GND GND GND GND VDD_A VDD_A V_REF COMP R_REF CLK SYNC_n BLANK_n VIDEO DAC 4 A FMS3818 IO_B IO_G IO_R G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 B2 B3 B4 B5 B6 B7 U21 5 B 29 32 33 40 41 42 43 44 45 46 47 VGA_R0 VGA_R1 VGA_R2 VGA_R3 VGA_R4 VGA_R5 VGA_R6 VGA_R7 VGA_BLUE VGA_GREEN VGA_RED 16 17 18 19 20 21 22 23 VGA_B0 VGA_B1 VGA_B2 VGA_B3 VGA_B4 VGA_B5 VGA_B6 VGA_B7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. VGA_G[7..0] VGA_R[7..0] VGA_B[7..0] 6 B C D 4 VGA_G[7..0] 4,6 VGA_R[7..0] 4 VGA_B[7..0] 7 5 4 C1 C2 A1 A2 1 2 E 8 16 17 5 4 C1 C2 A1 A2 1 2 2 C1 A1 1 A B C D E 5 4 3 2 1 5 4 3 2 1 SJ_3515N J16 5 4 3 2 1 8 7 100R, 1% C255 R117 47.5K 1% C66 6 C218 C219 5 220uF 220uF 100R, 1% C227 C73 R116 47.5K 1% R114 47.5K 1% R108 R113 R103 4.70K, 1% BLM21P221SN L23 1 2 R109 47.5K 1% R93 4.70K, 1% 4.70K, 1% 4.70K, 1% 5 4 10 9 LALINEOUT 12 RALINEOUT 13 0.47uf LLINEOUT 17 18 20 19 0.47uf RLINEOUT 0.47uf LLINEIN 0.47uf RLINEIN AIC23 4 LHPOUT RHPOUT LOUT ROUT MICBIAS MICIN LLINEIN RLINEIN U11 AIC23 AUDIO CODEC BLM21P221SN L24 1 2 BLM21P221SN L21 1 2 BLM21P221SN L22 1 2 R94 BLM21P221SN L19 1 2 Line Out R99 6 BLM21P221SN L20 1 2 Line In Amplified Line Out SJ_3515N J14 SJ_3515N J10 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 8 DGND BVDD DVDD HPGND HPVDD AGND VMID AVDD BCLK CS_n SDIN SCLK MODE DOUT DIN LRCIN LRCOUT CLKOUT XTO XTI.MCLK 28 1 27 11 8 15 16 14 3 21 23 24 22 6 4 5 7 2 26 25 3 3 10uF C46 0.1uF C220 0.1uF 0.001uf 10uF C49 3.3V C58 C59 1 2 10uF C57 L7 120ohm, 800mA 3.3V R13 R12 R14 4.70K, 1% 4.70K, 1% 4.70K, 1% 3.3V 1 Date: Size B 2 Sheet 16 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 0.001uf C52 0.1uF C48 3.3V_AUDIO AUDIO_CLK 4 AUDIO_BCLK 4 AUDIO_CSn 6 AUDIO_SDIN 4 AUDIO_SCLK 4 AUDIO_MODE 4 AUDIO_DOUT 3 AUDIO_DIN 6 AUDIO_LRCIN 4 AUDIO_LRCOUT 4 AUDIO_SDIN AUDIO_SCLK AUDIO_MODE 2 C Rev A B C D E A B C D E DIG_LSB_A DIG_LSB_B DIG_LSB_C DIG_LSB_D DIG_LSB_E DIG_LSB_F DIG_LSB_G DIG_LSB_DP 4 6 4 4 4 6 4 4 16 15 14 13 12 11 10 9 RN39A RN39E RN41A RN41G RN41E RN39D RN41B RN41D RN39B RN39F RN39H RN41H RN41F RN39C RN39G RN41C 1 5 1 7 5 4 2 4 2 6 8 8 6 3 7 3 SPST8 Grayhill 76SB08S S1 3,4,6,10 1 2 3 4 5 6 7 8 8 7 16 12 16 10 12 13 15 13 15 11 9 9 11 14 10 14 3.3V EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV EXB-2HV221JV USER_DIPSW 0 USER_DIPSW 1 USER_DIPSW 2 USER_DIPSW 3 USER_DIPSW 4 USER_DIPSW 5 USER_DIPSW 6 USER_DIPSW 7 USER_DIPSW [7:0] USER_LED[7..0] USER_RESETn 5,19 SYS_RESETn 10 USER_PB[3..0] 3,7 DIG_LSB_A DIG_LSB_B DIG_LSB_C DIG_LSB_D DIG_LSB_E DIG_LSB_F DIG_LSB_G DIG_LSB_DP DIG_MSB_A DIG_MSB_B DIG_MSB_C DIG_MSB_D DIG_MSB_E DIG_MSB_F DIG_MSB_G DIG_MSB_DP 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 3,5,7 USER_DIPSW [7:0] USER_LED[7..0] USER_RESETn SYS_RESETn USER_PB[3..0] DIG_MSB_A DIG_MSB_B DIG_MSB_C DIG_MSB_D DIG_MSB_E DIG_MSB_F DIG_MSB_G DIG_MSB_DP 6 4 6 4 4 4 6 4 8 6 EXB-2HV103JV EXB-2HV103JV 3.3V SEVEN SEGMENT DISPLAY B 6 1 7Segment_Display 7 DP 3 G 2 F 4 E 5 D 8 C 9 B U33 10 A 3.3V 5 5 USER_LED0 USER_LED1 USER_LED2 USER_LED3 USER_LED4 USER_LED5 USER_LED6 USER_LED7 USER IO SEVEN SEGMENT DISPLAY A 6 1 7Segment_Display 7 DP 3 G 2 F 4 E 5 D 8 C 9 B U32 10 A 7-Segment Displays 6 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 RN38H RN38G RN38F RN38E RN38D RN38C RN38B RN38A 2 USER_RESETn SW 6 PBSwitch 2 1 4 USER_PB3 1 PBSwitch USER_PB2 SW 2 PBSwitch 2 USER_PB1 USER_PB0 SYS_RESETn A A A A A A A A 3.3V SW 3 PBSwitch 2 SW 4 PBSwitch 2 PBSwitch SW 5 2 SW 7 LEDY LEDY D2 LEDY D3 LEDY D4 LEDY D5 LEDY D6 LEDY D7 LEDY D8 D9 1 1 1 1 Pushbutton Switches C C C C C C C C R264 R265 R266 R267 R268 R269 R270 USER_LED_RES1 USER_LED_RES2 USER_LED_RES3 USER_LED_RES4 USER_LED_RES5 USER_LED_RES6 USER_LED_RES7 EXB-2HV103JV 3 R263 3 USER_LED_RES0 EXB-2HV103JV User LEDs 4 16 13 14 11 10 9 15 12 1 4 3 6 7 8 2 5 RN42A RN42D RN42C RN42F RN42G RN42H RN42B RN42E 3.3V 56 56 56 56 56 56 56 56 STANDOFF2 STANDOFF3 STANDOFF4 1 SCREW 2 SCREW 3 SCREW 4 RoHS Label XL2 Antistat_bag XB1 Date: Size B 2 Sheet 17 150-0310202-C1 Tuesday, August 15, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 ASSY LABEL XL1 SCREW 4_40_9_5mm SCREW 4_40_9_5mm SCREW 4_40_9_5mm SCREW 4_40_9_5mm SCREW 1 STANDOFF_1inch4_40 STANDOFF_1inch4_40 STANDOFF_1inch4_40 STANDOFF_1inch4_40 STANDOFF1 Board Mounting Hardware 2 C Rev A B C D E A B C D E R199 R145 R148 R146 R158 R182 R214 R181 R213 EVM_AW En EVM_CNTL0 EVM_STAT0 EVM_DMAC0 EVM_CEn2 EVM_BEn0 EVM_BEn1 EVM_BEn2 EVM_BEn3 3.3V R161 22 R149 22 R150 22 3.3V 3.3V 3.3V 90 17 67 40 15 41 65 91 66 14 16 31 64 86 89 88 87 83 85 84 98 97 92 93 94 95 96 37 36 35 34 33 32 42 43 44 45 46 47 48 49 50 81 82 99 100 38 39 R163 22 R164 22 SRAM_MODE SRAM_ZZ SRAM_OEn SRAM_CLK_R SRAM_GW n SRAM_BW En SRAM_ADVn SRAM_ADSCn SRAM_ADSPn SRAM_CEn1 SRAM_CE2 SRAM_CEn3 SRAM_BEn0 SRAM_BEn1 SRAM_BEn2 SRAM_BEn3 SRAM_A0 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_A5 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A10 SRAM_A11 SRAM_A12 SRAM_A13 SRAM_A14 SRAM_A15 SRAM_A16 SRAM_A17 SRAM_A18 SRAM_A19 SRAM_A20 3.3V R160 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 7 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. SRAM_MODE SRAM_GW n SRAM_CE2 SRAM_CEn3 R231 R152 R210 R178 R180 R212 R179 R211 R162 R172 R204 R171 R203 R208 R175 R207 R174 R206 R173 R205 R177 R209 R176 EVM_OEn SRAM_CLK EVM_A7 EVM_A6 EVM_A2 EVM_A3 EVM_A4 EVM_A5 EVM_A10 EVM_A18 EVM_A19 EVM_A20 EVM_A21 EVM_A11 EVM_A12 EVM_A13 EVM_A14 EVM_A15 EVM_A16 EVM_A17 EVM_A8 EVM_A9 8 R153 22 R154 22 CY7C1360C VSS VSS VSS VSS VDD VDD VDD VDD NC NC NC MODE ZZ OE_n CLK GW_n BWE_n ADV_n ADSC_n ADSP_n CE1_n CE2 CE3_n BWA_n BWB_n BWC_n BWD_n A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 NC/A19 NC/A20 U22 5 21 26 10 55 60 71 76 Always Enabled (VCC) ZZ = 6 Always Enabled (jumper GND) CEn3 = Always Enabled (GND) CE2 = GWn = Global Write Disable (VCC) MODE = Linear Burst (GND) 5 PIN1-PIN2 PIN2-PIN3 SHUNT10 3X1 J24 1 2 3 0.001uf C366 SSRAM Sleep SSRAM Run EVM_D30 EVM_D28 EVM_D26 EVM_D24 EVM_D22 EVM_D20 EVM_D18 EVM_D16 EVM_D14 EVM_D12 EVM_D10 EVM_D8 EVM_D6 EVM_D4 EVM_D2 EVM_D0 EVM_D17 EVM_D19 EVM_D21 EVM_D23 EVM_D25 EVM_D27 EVM_D29 EVM_D31 EVM_D1 EVM_D3 EVM_D5 EVM_D7 EVM_D9 EVM_D11 EVM_D13 EVM_D15 881545-2 1K 1K 1K 1K SRAM_DQP0 R136 SRAM_DQP1 R137 SRAM_DQP2 R170 SRAM_DQP3 R169 51 80 1 30 3.3V 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196 R197 R198 R222 R221 R220 R219 R218 R217 R216 R215 R230 R229 R228 R227 R226 R225 R224 R223 SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D20 SRAM_D21 SRAM_D22 SRAM_D23 SRAM_D24 SRAM_D25 SRAM_D26 SRAM_D27 SRAM_D28 SRAM_D29 SRAM_D30 SRAM_D31 77 70 4 11 20 27 54 61 4 0.1uF C369 4 0.1uF C370 SRAM_ZZ R138 10.0K, 1% 0.001uf C373 3.3V 3.3V EVM_CLKOUT2 EVM_DMAC0 EVM_CNTL0 EVM_STAT0 EVM_INT3 EVM_INUM0 EVM_IACK EVM_INT1 EVM_DR0 EVM_DX0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 12V GND 5V_5 GND 5V_9 NC_11 NC_13 NC_15 NC_17 3.3V_19 CLKXO FSXO GND CLKRO FSRO GND CLKX2 FSX2 GND CLKR2 FSR2 GND TOUT0 NC_47 TOUT1 GND EXT_INT4 NC_55 NC_57 RESET GND CNTL1 STAT1 EXT_INT6 ACE3_n NC_71 NC_73 DC_DET_n GND GND 40X2TFM_CONN -12V GND 5V_6 GND 5V_10 NC_12 NC_14 NC_16 NC_18 3.3V_20 CLKS0 DX0 GND NC_28 DR0 GND CLKS2 DX2 GND NC_40 DR2 GND TINP0 EXT_INT5 TINP1 GND NC_54 NC_56 NC_58 NC_60 GND CNTL0 STAT0 EXT_INT7 NC_70 NC_72 NC_74 GND ECLKOUT GND J45 SSRAM, TI EVM Connectors 5 52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 Default SRAM Settings VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPA DQPB DQPC DQPD DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQC16 DQC17 DQC18 DQC19 DQC20 DQC21 DQC22 DQC23 DQD24 DQD25 DQD26 DQD27 DQD28 DQD29 DQD30 DQD31 6 EVM_CLKX0 EVM_FSX0 3 6 EVM_FSR0 6 EVM_CLKR0 6 EVM_FSX0 6 EVM_CLKX0 6 EVM_INT[3..0] 6 EVM_D[31..0] 6 EVM_A[21..2] 6 EVM_BEn[3..0] 332R, 1% R105 EVM_INT2 EVM_RESET EVM_INT0 EVM_CLKR0 EVM_FSR0 6,10 EVM_CEn[3..2] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 5V_1 EA21 EA19 EA17 EA15 GND EA13 EA11 EA9 EA7 5V_21 EA5 EA3 BE3_n BE1_n GND ED31 ED29 ED27 ED25 3.3V_41 ED23 ED21 ED19 ED17 GND ED15 ED13 ED11 ED9 GND ED7 ED5 ED3 ED1 GND ARE_n AOE_n ACE_n GND 6 EVM_ARDY 6 EVM_DR0 3 EVM_AREn 6 EVM_OEn 6 EVM_AW En 3 EVM_RESET 3 EVM_CLKOUT2 6 EVM_DMAC0 6 EVM_STAT0 6 EVM_CNTL0 3 EVM_INUM0 3 EVM_IACK 6 EVM_DX0 6 SRAM_CLK 40X2TFM_CONN 5V_2 EA20 EA18 EA16 EA14 GND EA12 EA10 EA8 EA6 5V_22 EA4 EA2 BE2_n BE0_n GND ED30 ED28 ED26 ED24 3.3V_42 ED22 ED20 ED18 ED16 GND ED14 ED12 ED10 ED8 GND ED6 ED4 ED2 ED0 GND AWE_n ARDY ACE2_n GND J46 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 EVM_IACK EVM_DX0 SRAM_CLK EVM_AREn EVM_OEn EVM_CEn3 EVM_D7 EVM_D5 EVM_D3 EVM_D1 EVM_D15 EVM_D13 EVM_D11 EVM_D9 EVM_D23 EVM_D21 EVM_D19 EVM_D17 EVM_D31 EVM_D29 EVM_D27 EVM_D25 EVM_A5 EVM_A3 EVM_BEn3 EVM_BEn1 EVM_A13 EVM_A11 EVM_A9 EVM_A7 EVM_A21 EVM_A19 EVM_A17 EVM_A15 EVM_ARDY EVM_DR0 EVM_AREn EVM_OEn EVM_AW En EVM_RESET EVM_CLKOUT2 EVM_DMAC0 EVM_STAT0 EVM_CNTL0 EVM_INUM0 1 Date: Size B 2 Sheet 18 150-0310202-C1 Tuesday, August 15, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 EVM_FSR0 EVM_CLKR0 EVM_FSX0 EVM_CLKX0 EVM_INT[3..0] EVM_D[31..0] EVM_A[21..2] EVM_BEn[3..0] EVM_CEn[3..2] EVM_AW En EVM_ARDY EVM_CEn2 EVM_D6 EVM_D4 EVM_D2 EVM_D0 EVM_D14 EVM_D12 EVM_D10 EVM_D8 EVM_D22 EVM_D20 EVM_D18 EVM_D16 EVM_D30 EVM_D28 EVM_D26 EVM_D24 EVM_A4 EVM_A2 EVM_BEn2 EVM_BEn0 EVM_A12 EVM_A10 EVM_A8 EVM_A6 EVM_A20 EVM_A18 EVM_A16 EVM_A14 2 C Rev A B C D E A B C D E 0 0 DC_IN 2X10 1 3 5 7 9 11 13 15 17 19 J23 2X7 1 3 5 7 9 11 13 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 PROTO_IO21 PROTO_IO20 PROTO_IO19 PROTO_IO18 PROTO_IO17 PROTO_IO16 PROTO_IO15 PROTO_IO14 PROTO_IO22 PROTO_CLKOUT PROTO_IO24 PROTO_IO23 USER_RESETn 8 7 0 0 0 0 R97 0 3.3V 3.3V MICTOR_TCK MICTOR_TMS MICTOR_TDI MICTOR_TRST (n/c) MICTOR_TDO MICTOR_PLDCLK 3.3V R140 143R, 1% PROTO_RESETn R142 143R, 1% 0.1uF Mictor38P 5VDC GND CLKE D15E D14E D13E D12E D11E D10E D9E D8E D7E D6E D5E D4E D3E D2E D1E D0E J12 R96 4.70K, 1% 6 0.1uF C357 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 0.1uF C359 5V 0.1uF C91 B_PROTO_IO26 B_PROTO_CARDSELn B_PROTO_IO23 B_PROTO_IO20 B_PROTO_IO1 B_PROTO_IO3 B_PROTO_IO5 B_PROTO_IO7 B_PROTO_IO9 B_PROTO_IO11 B_PROTO_IO13 B_PROTO_IO15 Mictor Connector 0.1uF C360 20X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J15 SCL SDA CLKO D15O D14O D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O GND1 GND2 GND3 GND4 GND5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 39 40 41 42 43 4 3.3V R115 10.0K, 1% 0.001uf 0.1uF 5 C221 C222 3.3V B_PROTO_IO10 B_PROTO_IO11 B_PROTO_IO12 B_PROTO_IO13 B_PROTO_IO14 B_PROTO_IO15 B_PROTO_IO16 B_PROTO_IO17 B_PROTO_IO18 B_PROTO_IO19 B_PROTO_IO0 B_PROTO_IO1 B_PROTO_IO2 B_PROTO_IO3 B_PROTO_IO4 B_PROTO_IO5 B_PROTO_IO6 B_PROTO_IO7 B_PROTO_IO8 B_PROTO_IO9 4 3.3V B_PROTO_RESETn B_PROTO_IO40 B_PROTO_CARDSELn MICTOR_TR_CLK R106 0 PROTO_CLKOUT PROTO_IO13 PROTO_IO12 MICTOR_PW R1 R111 0 MICTOR_PW R2 R112 0 PROTO_IO11 PROTO_IO10 PROTO_IO9 PROTO_IO8 PROTO_IO7 PROTO_IO6 PROTO_IO5 PROTO_IO4 PROTO_IO3 PROTO_IO2 PROTO_IO1 PROTO_IO0 (pinned out for FS2 hardware trace module) C358 3.3V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 0.1uF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 5 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 BEABEB- BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC 3 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U19 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U14 3 2 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 BEABEB- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 VCC R118 R119 PROTO_IO22 PROTO_IO16 R120 60v 5V PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U18 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BEABEBPI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC 3.3V PROTO_IO30 PROTO_IO31 PROTO_IO32 PROTO_IO33 PROTO_IO34 PROTO_IO35 PROTO_IO36 PROTO_IO37 PROTO_IO38 PROTO_IO39 PROTO_IO20 PROTO_IO21 PROTO_IO22 PROTO_IO23 PROTO_IO24 PROTO_IO25 PROTO_IO26 PROTO_IO27 PROTO_IO28 PROTO_IO29 4.70K, 1% 4.70K, 1% 1K D13 1 13 2 5 6 9 10 15 16 19 20 23 24 1 13 2 5 6 9 10 15 16 19 20 23 24 1 Date: Size B 2 Sheet 19 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 <Variant Name> 3 4 7 8 11 14 17 18 21 22 3 4 7 8 11 14 17 18 21 22 U15 PROTO_IO19 4.3V B_PROTO_IO30 B_PROTO_IO31 B_PROTO_IO32 B_PROTO_IO33 B_PROTO_IO34 B_PROTO_IO35 B_PROTO_IO36 B_PROTO_IO37 B_PROTO_IO38 B_PROTO_IO39 B_PROTO_IO20 B_PROTO_IO21 B_PROTO_IO22 B_PROTO_IO23 B_PROTO_IO24 B_PROTO_IO25 B_PROTO_IO26 B_PROTO_IO27 B_PROTO_IO28 B_PROTO_IO29 PROTO_RESETn PROTO_IO40 PROTO_CARDSELn PROTO_IO10 PROTO_IO11 PROTO_IO12 PROTO_IO13 PROTO_IO14 PROTO_IO15 PROTO_IO16 PROTO_IO17 PROTO_IO18 PROTO_IO19 PROTO_IO0 PROTO_IO1 PROTO_IO2 PROTO_IO3 PROTO_IO4 PROTO_IO5 PROTO_IO6 PROTO_IO7 PROTO_IO8 PROTO_IO9 (for 5V compatibility) Altera Daughter Card Voltage Limiters PI5C3384 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U13 Altera Daughter Card, Mictor Connector C361 B_PROTO_IO16 B_PROTO_IO17 B_PROTO_IO18 B_PROTO_IO19 B_PROTO_IO21 B_PROTO_IO22 B_PROTO_IO24 B_PROTO_IO25 B_PROTO_IO27 B_PROTO_IO28 B_PROTO_RESETn B_PROTO_IO0 B_PROTO_IO2 B_PROTO_IO4 B_PROTO_IO6 B_PROTO_IO8 B_PROTO_IO10 B_PROTO_IO12 B_PROTO_IO14 R141 R139 95.3R, 1% 95.3R, 1% B_PROTO_IO29 B_PROTO_IO31 B_PROTO_IO33 B_PROTO_IO35 B_PROTO_IO37 B_PROTO_IO39 0 R100 R98 R101 6 Altera Daughter Card R95 R19 PROTO_CLKIN PROTO_CLK_OSC PROTO_CLKOUT PROTO_CARDSELn PROTO_IO[40..0] 1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 J22 PROTO_3_3V_5V 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 10 JTAG_TCK 10 JTAG_TMS 10 JTAG_CONN_TDO 10 JTAG_CONN_TDI 5,17 USER_RESETn PROTO_CLKIN PROTO_CLK_OSC PROTO_CLKOUT PROTO_CARDSELn 3,4 PROTO_IO[40..0] 3.3V B_PROTO_IO40 B_PROTO_IO30 B_PROTO_IO32 B_PROTO_IO34 B_PROTO_IO36 B_PROTO_IO38 NOT INSTALLED R20 INSTALLED R21 8 PROTO_CLK_OSC PROTO_CLKIN PROTO_CLKOUT 6 3 3 4 3.3V 5V C Rev A B C D E A B C D E 1 1 1 1 Y7 H20 H7 Y20 L10 60ohm, 6A L8 60ohm, 6A L14 60ohm, 6A 2 2 2 2 0.1uF 2.2uf 0.1uF 2.2uf 0.1uF 2.2uf 0.1uF 2.2uf PLL C88 C87 PLL C70 C69 PLL C94 C93 PLL C60 C54 EP2C70F672C6N VCCD_PLL1 VCCD_PLL2 VCCD_PLL3 VCCD_PLL4 VCCA_PLL1 VCCA_PLL2 VCCA_PLL3 VCCA_PLL4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 0.01uf C89 0.01uf C71 0.01uf C95 0.01uf C61 8 7 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 Y8 F19 F8 Y19 W7 G20 G7 W20 Y6 E21 E4 AA21 AB6 AB9 AB13 AF3 AF11 V12 W9 AB14 AB17 AB22 AD20 AF16 AF24 V15 W18 AA22 AD26 P22 R18 T26 V19 C26 F22 J19 L26 M18 N22 0.001uf C92 VCCA_PLL4 0.001uf C72 VCCA_PLL3 0.001uf C97 VCCA_PLL2 0.001uf C63 VCCA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL3 GNDA_PLL4 GNDD_PLL1 GNDD_PLL2 GNDD_PLL3 GNDD_PLL4 GNDG_PLL1 GNDG_PLL2 GNDG_PLL3 GNDG_PLL4 CYCLONE II, IO POWER VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 U12L 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 1.2V 1.2V 1.2V 1.2V 1.2V AA8 G19 G8 AA19 A16 A24 C20 D22 E14 E17 H18 J15 A3 A11 E6 E9 E13 H9 J12 C1 F5 L1 M9 N5 AB5 AD1 P5 R9 T1 V8 L4 60ohm, 6A 3.3V VCCA_PLL1 VCCA_PLL2 VCCA_PLL3 VCCA_PLL4 1.8V 8 PLL 3.3V 1 1 1 1 6 L12 60ohm, 6A L13 60ohm, 6A L6 60ohm, 6A L5 60ohm, 6A PLL 1.8V 6 2 2 2 2 1.2V 4 A2 A12 A15 A25 B1 B26 C14 C18 D4 D24 E7 E11 E19 H5 H13 H14 H22 K20 AB7 AB11 AC4 AB16 AB19 AF2 E16 AD14 K10 K11 K12 K13 K14 K15 L11 L16 L17 L18 M10 M11 M16 M17 N10 N17 P10 R10 R11 R16 T11 T16 U11 U13 U14 U15 U16 V16 EP2C70F672C6N GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 5 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CYCLONE II, POWER U12K T13 T14 T15 U8 U19 W5 W13 W14 W22 Y9 Y17 AF12 AF15 AF25 AE26 N15 N16 N19 P8 P11 P12 P13 P14 P15 P16 P19 R1 R12 R13 R14 R15 R21 R26 T5 T12 AD9 AD18 AE1 L5 L12 L13 L14 L15 L22 M1 M12 M13 M14 M15 M26 N8 N11 N12 N13 N14 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C301 1.2V 0.1uF C244 1.2V 0.1uF C340 1.2V 0.1uF C270 0.1uF C300 0.1uF C246 0.1uF C347 0.1uF C264 0.1uF 0.1uF 1.2V C292 10uF 47uf 10V Tantalum C50 C280 1.2V + C98 0.1uF 0.1uF 1.8V C351 C256 1.8V C285 C286 1.8V C311 47uf 10V Tantalum C78 10uF C322 1.8V + C99 0.1uF 0.1uF 3.3V C251 C330 3.3V C245 C231 3.3V Cyclone II Power & Decoupling 5 NC01 NC02 NC03 AC24 N21 Y2 1 2 1 2 0.1uF C295 0.1uF C239 0.1uF C348 0.1uF C259 0.1uF C298 2.2uf C42 0.1uF C331 0.1uF C290 0.1uF C299 2.2uf C56 0.1uF C346 0.1uF C313 3 0.1uF C283 0.1uF C240 0.1uF C241 0.1uF C275 0.1uF C302 2.2uf C41 0.1uF C250 0.1uF C291 0.1uF C281 2.2uf C75 0.1uF C335 0.1uF C237 3 0.1uF 1.8V C216 0.1uF C325 0.1uF C277 2.2uf C110 0.1uF C266 0.1uF C343 2.2uf C100 0.1uF C321 0.1uF C338 2.2uf C76 0.1uF C215 0.1uF C319 0.1uF C265 2.2uf C51 0.1uF C308 0.1uF C258 2.2uf C68 0.1uF C296 0.1uF C326 0.1uF C278 0.1uF C249 0.1uF C350 0.1uF C310 0.1uF C339 0.1uF C267 0.1uF C342 0.1uF C233 0.1uF C287 0.1uF C345 0.1uF C261 0.1uF C341 0.1uF C243 0.1uF C288 0.1uF C303 2.2uf C43 0.1uF C279 0.1uF C217 2.2uf 3.3V C107 0.1uF 3.3V C268 0.1uF C349 0.1uF C257 0.1uF C230 0.1uF C235 0.1uF C297 0.1uF C312 2.2uf C53 2.2uf C82 0.1uF C320 0.1uF C236 0.1uF C336 0.1uF C317 (32 + 25) 2.2uf 1.8V C47 0.1uF C284 0.1uF C229 (30) 2.2uf C67 0.1uF C263 0.1uF C332 (23) 2.2uf 1.2V C64 0.1uF 1.2V C314 0.1uF 1.2V C238 0.1uF 1.2V C337 0.1uF 1.2V C323 0.1uF 1.8V C274 0.1uF 1.8V C329 2.2uf C106 0.1uF C315 0.1uF 3.3V C316 1 2.2uf C77 0.1uF C309 0.1uF C247 0.1uF C276 0.1uF C333 0.1uF C262 0.1uF C293 0.1uF C234 Date: Size B 2 Sheet 20 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 0.1uF C273 0.1uF C344 0.1uF C232 0.1uF C289 0.1uF C334 1.2V VCCINT BYPASS CAPS 2.2uf C81 2.2uf C62 0.1uF C269 0.1uF C248 1.8V VCCIO BYPASS CAPS 2.2uf C80 0.1uF C228 0.1uF C242 3.3V VCCIO BYPASS CAPS 2 C Rev A B C D E A B C D E J7 3X1 1 2 3 6V C35 22uf 1.0uf C38 SW 1 DC_IN 5 6 4 2 3 1 R74 10R 1.8V C14 + 22uf U10 ENABLE 2 3 1 1.8V 8 7 VOUT GND ADJ 6 5 4 4 2 1M C39 0.01uf 180uf 22pf 1M 1.8V F1 6 R16 1K R17 1K 5 4 D11 5V 1.0uf C36 1.8V_TG_R 1.0uf VREF 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uf 0.01uf 0.01uf 0.01uf 5 1 0 1 R69 3.3V_TG 0.1uf C24 R10 10.0K, 1% 0 MBR0530 D12 R7 10.0K, 1% R1 2 10uF C182 C327 C328 C353 C252 C225 C226 C352 C253 10uF C188 1.2V 1.2V (3A) 5V 5V (1A) C184 2 R3 10R 4 1 2 3 U5 5 6 7 8 SI4392DY-e3 3 6 7 9 10 10R 4 5 6 7 8 VTTREF S3 S5 VIN 4 3 VTT VTTSNS C21 10uf 3 5 10uf C18 1.8V_SW 3.3V_SW TPS51100DGQ VLDOIN 2 VDDQSNS 1 5 6 7 8 U4 1 2 3 SI4392DY-e3 U8 1.8V_TG R72 1.8V_BG U1 1 2 3 SI4392DY-e3 U3 30 5 6 7 8 1.0uf SI4392DY-e3 MBR0530 29 3.3V_SW _R 28 3.3V_BG 27 C186 22pf DC_IN 26 R70 12.4K, 1% 25 4 24 DC_IN_R DC_IN R71 12.4K, 1% 23 VREG5 C187 22pf 22 1 2 3 21 20 19 1.8V_SW _R 18 17 C185 16 TPS51020DBT INV1 VBST1 COMP1 OUT1_U SSTRT1 LL1 SKIPn OUT1_D VO1_VDDQ OUTGND1 DDRn TRIP1 GND VIN REF_X TRIP2_SNS ENBL1 VREG5 ENBL2 REG5_IN VO2 OUTGND2 PGOOD OUT2_D SSTRT2 LL2 COMP2 OUT2_U INV2 VBST2 U2 3.3V_TG_R Digital Power Supplies 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C45 C189 VREF 180uf 10uF C1 1.2V J5 BANANA_JACK_RED 0.1uf C7 R4 0.1R,1% Fuse_Block_7AMP 5V R67 51.1K, 1% 3300p C183 3.3V_SHDN 1.8V_SHDN DC_IN vreg5 51.1K, 1% R68 3300p C181 Fuse_Block_7AMP R6 1.15K, 1% R9 3.32K, 1% F5 22pf C179 0.01uf R65 88.7K, 1% C175 R61 6 C177 0.01uf C178 0.1uf C174 R60 R64 34.0K, 1% 1.2VOUT C4 4.53K, 1% 100K, 1% D1 LEDB VOUT UC382TD GND VIN VB U7 4.53K, 1% R73 1.00K, 1% ADJUST 470pf R66 R77 10R DC_IN REG104GA-A 5V 5 1 100K, 1% R63 3.3V_SHDN 1.8V_SHDN VIN R62 C180 10V 10V Tantalum Tantalum C90 + 5V_EN R11 10.0K, 1% 1.8V_FB R78 10R SW _SLIDE-4P2T 11 12 10 8 9 7 R75 10R 470pf R59 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 10uF 5V Typically No Shunt (Enabled) PIN1-PIN2 ENABLE PIN2-PIN3 DISABLE 0.1uf C44 6V R76 10R 6V_SHDN 22 Main Power Switch C176 7 A C 3.3V_FB 1 2 GND GND 6 3 C5 10uF 10uf C19 DC_IN C8 10uF C25 + C223 10uF + 3.3V VTT 1.8V (7A) C28 C29 22uf 10uF 10V Tantalum 0.9V (3A Sink/Src) C356 10uF VTT J6 BANANA_JACK_RED + 1.8V J3 BANANA_JACK_RED C27 180uf J1 Date: Size B 2 Sheet 21 150-0310202-C1 Tuesday, August 15, 2006 Document Number Cyclone II DSP Board Title 1 of 22 C Rev 9V - 20V DC Input (40W) RAPC712X 2 1 3 C33 + 22uf C32 10V Tantalum 10uF Fuse_Block_7AMP C355 C208 10uF10uF C15 22uf 10V Tantalum DC_IN 180uf C34 Fuse_Block_7AMP + C10 47uf 10V 10V Tantalum Tantalum F2 C17 10uF C20 47uf 10V Tantalum C12 22uf + 1.8V_FB 10R C13 + 22uf C23 10V Tantalum 10uF F3 3.3V (7A) J4 BANANA_JACK_RED 1 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 10uF 3.3V_FB F4Fuse_Block_7AMP 1.8V C30 180uf 10uh 1 10uf 0.1uf L12 R2 C191 C3 180uf C31 10uh 1 DC_IN_R L22 C22 10uf DC_IN 2 1 2 1 2 8 1 2 PGND GND GND 4 8 11 1 2 1 2 1 2 1 2 1 2 A B C D E A B C D R90 SHUNT13 + 220uF C101 10uH 1 1.0uf + 0.1uF C112 PIN1-PIN2 ENABLE PIN2-PIN3 DISABLE 10V 1.0uf C108 3X1 J28 3X1 0.1uF J25 C105 1 2 3 1 2 3 10.0K, 1% C104 R87 3900pf R86 PIN1-PIN2 ENABLE PIN2-PIN3 DISABLE 10V C214 Tantalum 220uF C103 10uH 1 49.9 Tantalum 881545-2 SHUNT11 881545-2 L16 2 6V L15 2 6V 6V 8 7 Copyright (c) 2005, Altera Corporation. All Rights Reserved. 6V 6V 6V 7 VCCA_ADC_EN R23 10.0K, 1% R84 5 1 5 1 REG104GA-A ADJUST VOUT 6 C121 0.01uf VCCA_DAC_OUT R83 R81 191K, 1% 0 4 2 C122 0.01uf C211 0.01uf DAC 5 C111 ADC R27 0.1R,1% 10uF R29 1.33K, 1% R28 2K DAC R234 2.15K,1% 881545-2 ADC 15 1 7 8 2 4 5 6V_SHDN 6 R8 68.1K,1% R26 R24 3.32K, 1% 0.1R,1% SHUNT12 VCCA_ADC_OUT DAC 5 4 10uF C120 L18 2 R36 L17 2 R32 0 1.0uf C133 10uH 1 0 1.0uf ADC DAC 6V_LDRV 10 9 4 ADC 1.0uf C128 DAC 1.0uf C127 6V_BOOST 6V_SW 21 6V_HDRV 14 12 F7 F6 8.25K,1% R5 16 13 C132 10uH 1 1.0uf 1.0uf 6V_SHDN C40 LDRV PGND BOOST SW ILIM HDRV TPS40055PW P C210 KFF VFB COMP RT SYNC SGND SS VIN U9 DC_IN Analog Power Supplies PIN1-PIN2 5V PIN2-PIN3 3.3V R232 J33 1.15K, 1% 3X1 4 2 VCCA_DAC Voltage Select Jumper ENABLE VIN U24 VOUT ADJUST REG104GA-A ENABLE VIN U23 68pf 15.0K, C213 1% 8200pf C212 R85 1.33K, 1% VCCA_DAC_EN R22 10.0K, 1% 681R, 1% 6 BP5 GND BP10 3 17 11 E 1 2 0 0.1uf R80 0 C131 DAC DAC 0.1uf 3 ADC Fuse_Block_7AMP VCCA_ADC C134 4 ADC 3 L32 0.1uf C6 C148 0.01uf VCCA_DAC (1A) C138 0.01uf ADC DAC 39uh 1 10uf C2 2 R43 R44 ADC_GND DAC_GND R255 R256 R257 R45 + C26 C96 6V 0 0 0 0 0 0 47uf 47uf 10uf 10V 10V Tantalum Tantalum + C11 6V 6V (1.5A) 47uf 10V Tantalum + C37 DC_IN DAC_GND ADC Date: Size B 2 Sheet 22 150-0310202-C1 Sunday, August 13, 2006 Document Number Cyclone II DSP Board Title 1 of 22 C Rev ADC_GND J41 BANANA_JACK_BLACK DAC J40 BANANA_JACK_BLACK GND J2 BANANA_JACK_BLACK 1 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 VCCA_ADC (1A) VCCA_ADC J42 BANANA_JACK_RED 0.1uf 1 U6B 5 6 SI9936BDY-e3 2 U6A 7 8 SI9936BDY-e3 VCCA_DAC J39 BANANA_JACK_RED R79 C190 Fuse_Block_7AMP VCCA_DAC 100pf C16 3 1 2 8 1 2 GND GND 6 3 GND GND 6 3 1 2 3 1 2 1 2 A B C D E