ALTGX Transceiver Setup Guide for Stratix IV Devices

1. ALTGX Transceiver Setup Guide for
Stratix IV Devices
January 2014
SIV53001-4.4
SIV53001-4.4
This chapter describes the options you can choose in the ALTGX MegaWizard™
Plug-In Manager in the Quartus® II software to configure Stratix® IV GX and GT
devices in different functional modes.
The MegaWizard Plug-In Manager in the Quartus II software creates or modifies
design files that contain custom megafunction variations that can then be instantiated
in a design file. You can use the MegaWizard Plug-In Manager to set the ALTGX
megafunction features in the design. The ALTGX megafunction allows you to
configure one or more transceiver channels. You can select the physical coding
sublayer (PCS) and physical medium attachment (PMA) functional blocks depending
on your transceiver configuration.
This chapter contains the following sections:
■
“Parameter Settings” on page 1–4
■
“Reconfiguration Settings” on page 1–28
■
“Protocol Settings” on page 1–36
Start the MegaWizard Plug-In Manager using one of the following methods:
■
From the Tools menu, select MegaWizard Plug-In Manager.
■
When working in the Block Editor, click MegaWizard Plug-In Manager in the
Symbol dialog box (Edit menu).
■
Start the standalone version of the MegaWizard Plug-In Manager by typing the
following command at the command prompt: qmegawiz.
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semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
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Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014
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1–2
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Figure 1–1 shows the first page of the MegaWizard Plug-In Manager. To generate an
ALTGX custom megafunction variation, select Create a new custom megafunction
variation.
Figure 1–1. MegaWizard Plug-In Manager (Page 1)
Figure 1–2 shows the second page of the MegaWizard Plug-In Manager.
To use the MegaWizard Plug-In Manager to configure a Stratix IV device, follow these
steps:
1. Select Stratix IV as the device family.
2. Select either VHDL or Verilog HDL depending on the type of output files you
want to create.
3. Select the ALTGX megafunction under the I/O section of the available
megafunctions.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
1–3
4. Name the output file, then Browse to the folder you want to save your file in and
click Next. The General screen of the ALTGX MegaWizard Plug-In Manager opens
(Figure 1–3).
Figure 1–2. MegaWizard Plug-In Manager (Page 2)
January 2014
1
All reset and control signals are active high unless otherwise mentioned.
1
All output ports are synchronous to the data path unless otherwise specified.
1
Throughout this chapter, the various functional modes and their settings are
explained for Stratix IV GX and GT devices.
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–4
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Parameter Settings
This section describes the options available on the individual pages of the ALTGX
MegaWizard Plug-In Manager for the Parameter Settings. The MegaWizard Plug-In
Manager provides a warning if any of the settings you choose are illegal.
General Screen for the Parameter Settings
Figure 1–3 shows the General screen of the ALTGX MegaWizard Plug-In Manager for
the Parameter Settings.
Figure 1–3. MegaWizard Plug-In Manager—ALTGX (General Screen for the Parameter Settings)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–5
Table 1–1 lists the available functional modes and their options on the General screen
of the MegaWizard Plug-In Manager. Depending on your configuration, you will
select one of the following functional modes:
■
Basic
■
Basic (PMA Direct)
■
Deterministic Latency
■
GIGE
■
(OIF) CEI Phy Interface
■
PCI Express® (PCIe)
■
SDI
■
Serial RapidIO®
■
SONET/SDH
■
XAUI
If you select Basic (PMA Direct) mode, all the channels are configured with only the
PMA blocks. These channels are called PMA-only channels throughout this chapter.
The PMA-only channels include:
■
Regular transceiver channels with PMA blocks only
■
CMU channels (clock multiplier unit phase-locked loops [CMU PLLs]
configured as additional transceiver channels with PMA blocks only)
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 1 of 11)
ALTGX Setting
Description
Select GX or GT based on the Stratix IV device used in
your design.
Which device variation will you
be using?
Select the speed grade of your device. The available
speed grades for the Stratix IV GX device are 2, 2×, 3,
and 4. The available speed grades for the Stratix IV GT
device are 1, 2 and 3.
Reference
DC and Switching
Characteristics for Stratix IV
Devices chapter.
Determines the specific protocol under which the
transceiver operates. For a specific mode, you must
select the desired protocol from the following list:
Which protocol will you be
using?
January 2014
Altera Corporation
■
(OIF) CEI PHY Interface
■
SDI
■
SONET/SDH
■
XAUI
■
Basic
■
Basic (PMA Direct)
■
Deterministic Latency
■
GIGE
■
PCIe
■
Serial RapidIO
Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 2 of 11)
ALTGX Setting
Description
Reference
Basic
In Basic mode, the subprotocols are diagnostic modes.
The available options are as follows:
■
None—This is the normal operation of the transceiver.
■
×4—In this mode, all four channels within the
transceiver block are clocked from its central clock
divider block to minimize transmitter
channel-to-channel skew.
■
×8—In this mode, all eight channels in two
transceiver blocks are clocked from the central clock
divider of the master transceiver block to minimize
transmitter channel-to-channel skew.
■
BIST—This subprotocol is applicable only for
Receiver and Transmitter operation mode. This mode
loops the parallel data from the built-in self test (BIST)
(non-PRBS) back to the BIST verifier in the receiver
path. Parallel loopback is allowed only in Basic
double-width mode.
■
PRBS—This subprotocol is applicable only for
Receiver and Transmitter operation mode.This is
another Serial Loopback mode but with the
pseudo-random binary sequence (PRBS) BIST block
active. The PRBS pattern depends on the
serializer/deserializer (SERDES) factor.
Which subprotocol will you be
using?
“Basic Functional Mode”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Basic (PMA Direct)
■
None—This is the normal mode of operation in which
each channel is treated independently.
■
XN—In this mode, the “N” in XN represents the
number of channels in the bonded configuration. All
N channels are clocked by the same transmit clock
from the central clock divider block to minimize
transmitter channel-to-channel skew.
“Basic PMA Direct Functional
Mode” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Deterministic Latency
■
■
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
×1—In this mode, you can have up to two configured
channels per transceiver block. Each channel uses one
CMU PLL and its feedback path to compensate for the
uncertain latency.
×4—In this mode, you can have up to four configured
channels per transceiver block. All channels use one
CMU PLL per block and its feedback path to
compensate for the uncertain latency.
“Deterministic Latency Mode”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–7
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 3 of 11)
ALTGX Setting
Description
Reference
PCIe
In PCIe mode, there are six subprotocols:
Which subprotocol will you be
using?
■
Gen1 ×1—The transceiver is configured as a
single-lane PCIe link for a 2.5 Gbps data rate.
■
Gen1 ×4—The transceiver is configured as a four-lane
PCIe link for a data rate of 2.5 Gbps.
■
Gen1 ×8—The transceiver is configured as an
eight-lane PCIe link for a data rate of 2.5 Gbps.
■
Gen2 ×1—The transceiver is configured as a
single-lane PCIe link for a 5.0 Gbps data rate.
■
Gen2 ×4—The transceiver is configured as a four-lane
PCIe link for a data rate of 5.0 Gbps.
■
Gen2 ×8—The transceiver is configured as an
eight-lane PCIe link for a data rate of 5.0 Gbps.
“PCIe Mode” in the
Transceiver Architecture in
Stratix IV Devices chapter.
SDI
In SDI mode, the two available subprotocols are:
■
3G—third-generation (3 Gbps) SDI at 2967 Mbps or
2970 Mbps.
■
HD—high-definition SDI at 1483.5 Mbps or
1485 Mbps.
“SDI Mode” in the Transceiver
Architecture in Stratix IV
Devices chapter.
SONET/SDH
In SONET/SDH mode, the three available subprotocols
and their data rates are:
■
OC-12—622 Mbps
■
OC-48—2488.32 Mbps
■
OC-96—4976.64 Mbps
“SONET/SDH Mode” in the
Transceiver Architecture in
Stratix IV Devices chapter.
Deterministic Latency
GIGE
(OIF) CEI PHY Interface
Enforce default settings for
this protocol.
PCIe
—
SONET/SDH
XAUI
If you select this option, all mode-specific ports and
settings are used.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–8
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 4 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
Deterministic Latency
SDI
Serial RapidIO
SONET/SDH
—
The available operation modes are Receiver only,
Transmitter only, and Receiver and Transmitter.
What is the operation mode?
For Basic (PMA Direct) xN mode, the available operation
modes are Transmitter only and Receiver and
Transmitter. However, if you set the subprotocol to None,
the available operation modes are Receiver only,
Transmitter only, and Receiver and Transmitter.
GIGE
The available operation modes are Transmitter only, and
Receiver and Transmitter.
—
PCIe
XAUI
—
Only Receiver and Transmitter mode is allowed.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–9
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 5 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
Deterministic Latency
SDI
—
Serial RapidIO
The number of channels required with the same
configuration. This option determines how many
identical channels this ALTGX instance contains.
GIGE
(OIF) CEI PHY Interface
SONET/SDH
What is the number of
channels?
—
This option allows you to select how many channels this
ALTGX instance contains. In these modes, the number of
channels increments by one.
PCIe
This is the number of channels required with the same
configuration.
■
In a ×4 subprotocol, the number of channels
increments by 4.
■
In a ×8 subprotocol, the number of channels
increment by 8.
—
XAUI
This option allows you to select how many identical
channels this ALTGX instance contains. In XAUI mode,
the number of channels increments by 4.
January 2014
Altera Corporation
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Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 6 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
Deterministic Latency
This option sets the transceiver data path width.
■
Single-width—This mode operates from 600 Mbps to
3.75 Gbps.
■
Double-width—This mode operates from 1 Gbps to
8.5 Gbps.
“Basic Single-Width Mode
Configurations” and “Basic
Double-Width Mode
Configurations” sections in the
Transceiver Architecture in
Stratix IV Devices chapter.
GIGE
PCIe
SDI
Serial RapidIO
What is the deserializer block
width?
—
XAUI
These modes only operate in single-width mode.
Double-width mode is not allowed.
(OIF) CEI PHY Interface
The (OIF) CEI PHY Interface mode only operates in
double-width mode. Single-width mode is not allowed.
—
SONET/SDH
This option allows you to set the transceiver data path
width.
■
■
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
Single-width—Selected automatically in OC-12 and
OC-48 configurations. The transceiver data path width
is 8 bits.
—
Double-width—Selected automatically in OC-96
configurations. The transceiver data path width is
16 bits.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–11
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 7 of 11)
ALTGX Setting
Description
Reference
Basic
Deterministic Latency
This option determines the FPGA fabric-Transceiver
interface width.
■
Single-width mode—Selecting 8 or 10 bits bypasses
the byte serializer/deserializer. Selecting 16 or 20 bits
uses the byte serializer/deserializer.
■
Double-width mode—Selecting 16 or 20 bits
bypasses the byte serializer/deserializer. Selecting 32
or 40 bits uses the byte serializer/deserializer.
Basic (PMA Direct)
This option determines the FPGA fabric-Transceiver
interface width.
■
Single-width mode—You can select 8 or 10 bits.
■
Double-width mode— You can select 16 or 20 bits.
GIGE
This option determines the FPGA fabric-Transceiver
interface width. In GIGE mode, only 8 bits are allowed.
What is the channel width?
(OIF) CEI PHY Interface
This option selects the FPGA fabric-Transceiver width. In
(OIF) CEI PHY Interface mode, only 32 bits are allowed.
“Byte Serializer” and “Byte
Deserializer” sections in the
Transceiver Architecture in
Stratix IV Devices chapter.
PCIe
This option determines the FPGA fabric-Transceiver
interface width.
■
In PCIe Gen1 (2.5 Gbps) mode, 8 and 16 bits are
allowed.
■
In PCIe Gen2 (5 Gbps) mode, only 16 bits are allowed.
SDI
This option determines the FPGA fabric-Transceiver
interface width:
■
HD mode—10-bit and 20-bit channel widths are
allowed.
■
3G mode—only 20-bit channel width is allowed.
■
10-bit configuration—the byte serializer is not used.
■
20-bit configuration—the byte serializer is used.
Serial RapidIO
The channel width is fixed to 16 in Serial RapidIO mode.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–12
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 8 of 11)
ALTGX Setting
Description
Reference
SONET/SDH
This option selects the FPGA fabric-Transceiver interface
width. Depending on your subprotocol selection, choose
one of the following:
What is the channel width?
■
8 bits for OC-12 mode
■
16 bits for OC-48 mode
■
32 bits for OC-96 mode
“Byte Serializer” and “Byte
Deserializer” sections in the
Transceiver Architecture in
Stratix IV Devices chapter.
XAUI
XAUI mode only operates in single-width mode.
Basic
Basic (PMA Direct)
You can select one of the following options:
■
What would you like to base
the setting on?
■
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
Data rate—Selecting this option allows you to enter
the transceiver channel serial data rate. Based on the
value you enter, the ALTGX MegaWizard Plug-In
Manager populates the input reference clock
frequency options in the What is the input clock
frequency? field. The ALTGX MegaWizard Plug-In
Manager determines these input reference clock
frequencies depending on the available multiplier
settings.
—
Input clock frequency—Selecting this option allows
you to enter your input clock frequency. Based on the
value you enter, the ALTGX MegaWizard Plug-In
Manager populates the data rate options in the What
is the effective data rate? field. The ALTGX
MegaWizard Plug-In Manager determines these data
rate options depending on the available multipler
settings.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–13
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 9 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
Deterministic Latency
■
■
If you select the Data Rate option in the What would
you like to base the setting on? field, the ALTGX
MegaWizard Plug-In Manager allows you to specify
the effective serial data rate value in this field.
—
If you select the Input Clock Frequency option in the
What would you like to base the setting on? field, the
ALTGX MegaWizard Plug-In Manager displays the list
of effective serial data rates in this field.
GIGE
This option is not available in GIGE mode. The
transceiver channel serial data rate is fixed to 1250 Mbps
in this mode.
—
(OIF) CEI PHY Interface
The allowed effective data rate is between 3125 Mbps
and 6500 Mbps. Enter the transceiver channel’s serial
data rate in this field.
—
PCIe
This option is not available in PCIe mode. The defaults
What is the effective data rate? are:
■ 2500 Mbps for PCIe Gen1 mode.
■
—
5000 Mbps for PCIe Gen 2 mode.
SDI
The effective data rate is fixed at:
■
2967 Mbps or 2970 Mbps in 3G mode.
■
1483.5 Mbps or 1485 Mbps in HD mode.
—
Serial RapidIO
Enter one of these three data rates in this option:
■
1250 Mbps.
■
2500 Mbps.
■
3125 Mbps.
—
SONET/SDH
The effective data rate is fixed at:
■
622 Mbps in OC-12 mode.
■
2488.32 Mbps in OC-48 mode.
■
—
4976 Mbps in OC-96 mode.
XAUI
The effective data rate can be from 3125 Mbps to
3750 Mbps.
January 2014
Altera Corporation
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Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 10 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
■
If you select the Input Clock Frequency option in the
What would you like to base the setting on? field, the
ALTGX MegaWizard Plug-In Manager allows you to
specify the input reference clock frequency in this
field.
■
If you select the Data Rate option in the What would
you like to base the setting on? field, the ALTGX
MegaWizard Plug-In Manager displays the list of input
reference clock frequencies in this field.
Deterministic Latency
GIGE
(OIF) CEI PHY Interface
SDI
SONET/SDH
What is the input clock
frequency?
Based on the effective data rate value in the What is the
effective data rate? field, the ALTGX MegaWizard
Plug-In Manager determines the input reference clock
frequencies depending on the available multiplier
settings.
“Input Reference Clocking”
section in the Transceiver
Clocking in Stratix IV Devices
chapter.
PCIe
This option is not available in PCIe mode. The input
reference clock frequency is fixed to 100 MHz in PCIe
mode.
Serial RapidIO
This option provides the available input reference clock
frequencies depending on whether your effective serial
data rate is 1250 Mbps, 2500 Mbps, or 3125 Mbps and
the available multiplier settings.
XAUI
This option provides the available input reference clock
frequencies depending on whether your effective serial
data rate is 3125 Mbps or 3750 Mbps and the available
multiplier settings.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–15
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 11 of 11)
ALTGX Setting
Description
Reference
Basic
Basic (PMA Direct)
The ALTGX MegaWizard Plug-In Manager provides you
the base data rate options for the CMU/advanced
technology extended (ATX) PLL and receiver clock data
recovery (CDR).
—
If you select a value in this field that is greater than the
value in the What is the effective data rate? field, the
ALTGX MegaWizard Plug-In Manager enables the
appropriate local clock divider values. The local divider is
present in the receiver channels.
GIGE
This option is not available in this mode because the data
rate is fixed. The ALTGX MegaWizard Plug-In Manager
provides you the base data rate options for the CMU PLL
and receiver CDR.
—
(OIF) CEI PHY Interface
Specify base data rate.
Serial RapidIO
XAUI
—
This option is not available in these modes. The ALTGX
MegaWizard Plug-In Manager provides you the base data
rate options for the CMU PLL and receiver CDR.
PCIe
For Gen1 ×1, an optional base data rate of either 2500 or
5000 Mbps is available.
—
SDI
This option is not available this mode as the data rate is
fixed in 3G and HD modes. The ALTGX MegaWizard
Plug-In Manager provides you the base data rate options
for the CMU PLL and receiver CDR.
—
SONET/SDH
This option is not available in this mode as the data rates
are fixed in OC-12, OC-48, and OC-96 modes. The ALTGX
MegaWizard Plug-In Manager provides you the base data
rate options for the CMU PLL and receiver CDR in this
option.
January 2014
Altera Corporation
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Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–16
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
PLL/Ports Screen for the Parameter Settings
Figure 1–4 shows the PLL/Ports screen of the ALTGX MegaWizard Plug-In Manager
for the Parameter Settings.
Figure 1–4. MegaWizard Plug-In Manager—ALTGX (PLL/Ports Screen)
Table 1–2 lists the available options on the PLL/ports screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 1 of 3)
ALTGX Setting
Description
Train receiver clock and data
recovery (CDR) from
pll_inclk.
If you select this option, the input reference clock to
the CMU PLL trains the receiver CDR.
Use ATX Transmitter PLL
This option is only available for certain data rates.
Refer to the DC and Switching Characteristics for
Stratix IV Devices chapter for the supported data
rates.
This option enables the auxiliary transmitter PLL.
This is a low-jitter PLL that resides between the
transceiver blocks and can be used as a transmitter
PLL.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
Reference
Table 1-77 in the Transceiver
Architecture in Stratix IV Devices
chapter.
“Auxiliary Transmit (ATX) PLL Block”
section in the Transceiver Architecture
in Stratix IV Devices, the Transceiver
Clocking in Stratix IV Devices chapter,
and the DC and Switching
Characteristics for Stratix IV Devices
section.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–17
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 2 of 3)
ALTGX Setting
Description
Reference
Enable PLL phase frequency
detector (PFD) feedback to
compensate latency
uncertainty in tx_dataout
and tx_clkout paths
relative to the reference
clock.
This option applies only when you select
Deterministic Latency functional mode.
“CMU PLL Feedback” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
What is the TX PLL
bandwidth mode?
The available options are Auto, Low, Medium, and
High. Select the appropriate option based on your
system requirements.
“PLL Bandwidth Setting” section in
the Transceiver Architecture in Stratix
IV Devices chapter and the DC and
Switching Characteristics for Stratix
IV Devices section.
What is the receiver CDR
bandwidth mode?
The available options are Auto, Low, Medium, and
High. Select the appropriate option based on your
system requirements.
“Clock and Data Recovery Unit”
section in the Transceiver Architecture
in Stratix IV Devices chapter and the
DC and Switching Characteristics for
Stratix IV Devices section.
What is the acceptable PPM
threshold between the
receiver CDR VCO and the
receiver input reference
clock?
In Automatic Lock mode, the CDR remains in
Lock-to-Data (LTD) mode as long as the parts per
million (PPM) difference between the CDR VCO
output clock and the input reference clock is less
than the PPM value that you set in this option. If the
PPM difference is greater than the PPM value that
you set in this option, the CDR switches to
Lock-to-Reference (LTR) mode.
“Automatic Lock Mode” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
The range of values available in this option is
±62.5 ppm to ±1000 ppm. (1)
Optional Ports
Create a gxb_powerdown
port to power down the
transceiver block.
When asserted, this signal powers down the entire
transceiver block. If none of the channels are
instantiated in a transceiver block, the Quartus II
software automatically powers down the entire
transceiver block.
“User Reset and Power Down
Signals” section in the Reset Control
and Power Down in Stratix IV Devices
chapter.
Create a pll_powerdown
port to power down the TX
PLL.
Each transceiver block has two CMU PLLs. Each
CMU/ATX PLL has a dedicated power down signal
called pll_powerdown. This signal powers down
the CMU/ATX PLL.
“User Reset and Power Down
Signals” section in the Reset Control
and Power Down in Stratix IV Devices
chapter.
Create a rx_analogreset
port for the analog portion of
the receiver.
January 2014
Altera Corporation
The receiver analog reset port is available in
Receiver only and Receiver and Transmitter
operation modes. This resets part of the analog
portion of the receiver CDR in the receiver channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
“User Reset and Power Down
Signals” in the Reset Control and
Power Down in Stratix IV Devices
chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–18
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 3 of 3)
ALTGX Setting
Create a rx_digitalreset
port for the digital portion of
the receiver.
Create a tx_digitalreset
port for the digital portion of
the transmitter.
Description
Reference
The receiver digital reset port is available in
Receiver only and Receiver and Transmitter
operation modes. This resets the PCS portion of the
receiver channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
The transmitter digital reset port is available in
Transmitter only and Receiver and Transmitter
operation modes. This resets the PCS portion of the
transmitter channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
“User Reset and Power Down
Signals” section in the Reset Control
and Power Down in Stratix IV Devices
chapter.
“User Reset and Power Down
Signals” section in the Reset Control
and Power Down in Stratix IV Devices
chapter.
Create a pll_locked port to
indicate PLL is in lock with
the reference input clock.
Each CMU/ATX PLL has a dedicated pll_locked
signal that is fed to the FPGA fabric to indicate
when the PLL is locked to the input reference clock.
“Transceiver Reset Sequences”
section in the Reset Control and
Power Down in Stratix IV Devices
chapter.
Create an
rx_locktorefclk port to
lock the RX CDR to the
reference clock.
When this signal is asserted high, the LTR/LTD
controller forces the receiver CDR to lock to the
phase and frequency of the input reference clock.
(1), (2)
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
Create an rx_locktodata
port to lock the RX CDR to
the received data.
When this signal is asserted high, the LTR/LTD
controller forces the receiver CDR to lock to the
received data. (1), (2)
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
Create an rx_pll_locked
port to indicate RX CDR is
locked to the input reference
clock.
Create an rx_freqlocked
port to indicate RX CDR is
locked to the received data.
■
■
In LTR mode, this signal is asserted high to
indicate that the receiver CDR has locked to the
phase and frequency of the input reference
clock.
In LTD mode, this signal has no significance.
“Lock-to-Reference (LTR) Mode”
section in the Transceiver Architecture
in Stratix IV Devices chapter.
(1)
This signal is asserted high to indicate that the
receiver CDR has switched from LTR to LTD mode.
This signal has relevance only in Automatic Lock
mode and may be required to control the
transceiver resets, as described in the User Reset
and Power Down Signals section in the Reset
Control and Power Down in Stratix IV Devices
chapter. (1)
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
Notes to Table 1–2:
(1) LTR mode is lock-to-reference mode and LTD mode is lock-to-data mode.
(2) When rx_locktorefclk and rx_locktodata are both asserted high, rx_locktodata takes precedence over rx_locktorefclk, forcing
the CDR to lock to the received data. When both these signals are de-asserted, the LTR/LTD controller is configured in Automatic Lock mode.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–19
Ports/Calibration Screen for the Parameter Settings
Figure 1–5 shows the Ports/Calibration screen of the ALTGX MegaWizard Plug-In
Manager for the Parameter Settings.
Figure 1–5. MegaWizard Plug-In Manager—ALTGX (Ports/Calibration Screen)
Table 1–3 lists the available options on the Ports/Calibration screen of the
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
Unless indicated otherwise, the options apply to all functional modes.
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 1 of 3)
ALTGX Setting
Description
Reference
Optional Ports/Controls
Create an rx_signaldetect port to
indicate data input signal detection.
This port is only available in Basic
and PCIe mode.
“Signal Threshold Detection Circuitry”
section in the Transceiver Architecture in
Stratix IV Devices chapter.
Enable TX Phase Comp FIFO in register
mode.
This option is only available in
Deterministic Latency mode.
“Deterministic Latency” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
Create an
rx_phase_comp_fifo_error output
port.
This output port indicates a Receiver
Phase Compensation FIFO overflow
or under-run condition.
“Receiver Phase Compensation FIFO Error
Flag” section in the Transceiver
Architecture in Stratix IV Devices chapter.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–20
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 2 of 3)
ALTGX Setting
Description
Reference
Create a
tx_phase_comp_fifo_error output
port.
This output port indicates a
Transmitter Phase Compensation
FIFO overflow or under-run
condition.
“TX Phase Compensation FIFO Status
Signal” section in the Transceiver
Architecture in Stratix IV Devices chapter.
Create an rx_coreclk port to connect
to the read clock of the RX phase
compensation FIFO.
You can clock the parallel output data
from the receiver using this optional
input port. This port allows you to
clock the read side of the Receiver
Phase Compensation FIFO with a
user-provided clock (FPGA fabric
clock, FPGA fabric-Transceiver
interface clock, or input reference
clock).
“FPGA Fabric-Transceiver Interface
Clocking” section in the Transceiver
Clocking in Stratix IV Devices chapter.
Create a tx_coreclk port to connect
to the write clock of the TX phase
compensation FIFO.
You can clock the parallel transmitter
data generated in the FPGA fabric
using this optional input port. This
port allows you to clock the write
side of the Transmitter Phase
Compensation FIFO with a
user-provided clock (FPGA fabric
clock, FPGA fabric-Transceiver
interface clock, or input reference
clock).
“FPGA Fabric-Transceiver Interface
Clocking” section in the Transceiver
Clocking in Stratix IV Devices chapter.
Create a tx_forceelecidle input
port
In Basic and PCIe modes, this
optional input signal places the
transmitter buffer in the electrical
idle state.
“Transceiver Channel Architecture” section
in the Transceiver Architecture in Stratix IV
Devices chapter.
Use calibration block.
The calibration block is always
enabled.
“Calibration Blocks” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–21
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 3 of 3)
ALTGX Setting
Description
Create an active high
cal_blk_powerdown to power down
the calibration block.
Asserting this signal high powers
down the calibration block. A
high-to-low transition on this signal
restarts calibration.
Reference
“Input Signals to the Calibration Block”
section in the Transceiver Architecture in
Stratix IV Devices chapter.
The options available for selection
are based on what you specify in the
Specify base data rate option:
What is the Analog Power (VCCA_L/R)?
■
3.3 V—Available up to 11.3 Gbps
for Stratix IV GT devices only.
■
3.0 V—Available up to 8.5 Gbps.
■
2.5 V—Available up to 4.25 Gbps.
■
AUTO—The ALTGX MegaWizard
Plug-In Manager automatically
sets VCCA_L/R to 2.5 V for the VCO
data rates less than 4.25 Gbps.
“General Requirements to Combine
Channels” section in the Configuring
Multiple Protocols and Data Rates in
Stratix IV Devices chapter.
or
VCCA_L/R to 3.0 V for the VCO data
rates greater than 4.25 Gbps.
It is up to you to connect the correct
voltage supply to the VCCA_L/R pins on
the board.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–22
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Loopback Screen for the Parameter Settings
Figure 1–6 shows the Loopback screen of the ALTGX MegaWizard Plug-In Manager
for the Parameter Settings.
Figure 1–6. MegaWizard Plug-In Manager—ALTGX (Loopback Screen)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–23
Table 1–4 lists the available options on the Loopback screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–4. MegaWizard Plug-In Manager Options (Lpbk Screen)
ALTGX Setting
Description
Reference
There are two options available:
■
No loopback—This is the default mode.
■
Serial loopback—If you select serial loopback, the
rx_seriallpbken port is available to control the serial
loopback feature dynamically.
Which loopback option
would you like?
■
1'b1—enables serial loopback
■
1'b0—disables serial loopback
“Serial Loopback” section in
the Transceiver Architecture
in Stratix IV Devices
chapter.
This signal is asynchronous to the receiver datapath.
There are three options available:
■
No reverse loopback—This is the default mode.
■
Reverse Serial loopback (pre-CDR)—This is the
loopback before the receiver’s CDR block to the
transmitter buffer. The receiver path in PCS is active but
the transmitter side is not.
■
Reverse Serial loopback—This is a loopback after the
receiver’s CDR block to the transmitter buffer. The receiver
path in PCS is active but the transmitter side is not.
Which reverse loopback
option would you like?
January 2014
Altera Corporation
“Loopback Modes” section
in the Transceiver
Architecture in Stratix IV
Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–24
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
RX Analog Screen for the Parameter Settings
Figure 1–7 shows the RX Analog screen of the ALTGX MegaWizard Plug-In Manager
for the Parameter Settings.
Figure 1–7. MegaWizard Plug-In Manager—ALTGX (RX Analog Screen)
Table 1–5 lists the available options on the RX Analog screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–5. MegaWizard Plug-In Manager Options (RX Analog Screen) (Part 1 of 2)
ALTGX Setting
Enable static equalizer
control.
Description
This option enables the static equalizer
settings.
Reference
“Programmable Equalization and DC Gain”
section in the Transceiver Architecture in Stratix
IV Devices chapter and the DC and Switching
Characteristics for Stratix IV Devices section.
This DC gain option has five settings:
What is the DC gain?
■
0 – 0 dB
■
1 – 3 dB
■
2 – 6 dB
■
3 – 9 dB
■
4 – 12 dB
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
“Programmable Equalization and DC Gain”
section in the Transceiver Architecture in Stratix
IV Devices chapter.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–25
Table 1–5. MegaWizard Plug-In Manager Options (RX Analog Screen) (Part 2 of 2)
ALTGX Setting
Description
Reference
What is the receiver common
mode voltage (RX VCM)?
The receiver common mode voltage is
programmable to 0.82 V or 1.1 V.
“Receiver Channel Datapath” section in the
Transceiver Architecture in Stratix IV Devices
chapter.
Force signal detection.
In PCIe mode, this option disables the
signal threshold detect circuit for the
receiver CDR. The receiver CDR no
longer depends on the signal detect
criterion to switch from LTR to LTD
mode.
“Signal Threshold Detection Circuitry” section
in the Transceiver Architecture in Stratix IV
Devices chapter.
Use this option in PCIe or Basic mode
with the 8B/10B block enabled and the
rx_signaldetect port selected to
determine the threshold level for the
signal detect circuit.
What is the signal detect
threshold?
■
PIPE mode—The levels are fixed.
■
Basic mode—A range of values
depending on the data rate are
available. The levels will be
determined after characterization.
The ALTGX settings have the following
threshold voltages (Vth):
setting 8: 50 mV
setting 7: 45 mV
setting 6: 40 mV
setting 5: 35 mV
setting 4: 30 mV
setting 3: 25 mV
setting 2: 20 mV
setting 1: 15 mV
“Signal Threshold Detection Circuitry” section
in the Transceiver Architecture in Stratix IV
Devices chapter.
The rx_signaldetect status signal is
asserted when the receiver peak-to-peak
differential input voltage VID (diff p-p) is
higher than Vth multiplied by 4.
Use external receiver
termination.
Select this option if you want to use an
external termination resistor instead of
differential on-chip termination (OCT). If
checked, this option turns off the
receiver OCT.
This option allows you to select the
receiver differential termination value.
The settings allowed are:
What is the receiver
termination resistance?
January 2014
Altera Corporation
■
85 
■
100 
■
120 
■
150.
“Programmable Differential On-Chip
Termination” section in the Transceiver
Architecture in Stratix IV Devices chapter.
“Programmable Differential On-Chip
Termination” section in the Transceiver
Architecture in Stratix IV Devices chapter, and
the DC and Switching Characteristics for Stratix
IV Devices section.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–26
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
TX Analog Screen for the Parameter Settings
Figure 1–8 shows the TX Analog screen of the ALTGX MegaWizard Plug-In Manager
for the Parameter Settings.
Figure 1–8. MegaWizard Plug-In Manager—ALTGX (TX Analog Screen)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
1–27
Table 1–6 lists the available options on the TX Analog screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–6. MegaWizard Plug-In Manager Options (TX Analog Screen) (Part 1 of 2)
ALTGX Setting
Description
Reference
The options available for selection are based on
what you enter in the What is the effective data
rate? option.
What is the transmitter buffer
power (VCCH)?
■
1.4 V—Available up to 8.5 Gbps.
■
1.5 V is available up to 6.5 Gbps (not available
for Stratix IV GT).
■
AUTO—The ALTGX MegaWizard Plug-In
Manager automatically sets VCCH to 1.5 V for
the effective data rates less than 6.5 Gbps
“Programmable Transmit Output
Buffer Power (VCCH)” section in the
Transceiver Architecture in Stratix IV
Devices chapter.
or
VCCH to 1.4 V for effective data rates greater
than 6.5 Gbps.
It is up to you to connect the correct voltage
supply to the VCCH pins on the board.
What is the transmitter
The transmitter common mode voltage is fixed to
common mode voltage (VCM)? 0.65 V.
“Transmitter Output Buffer” in the
Transceiver Architecture in Stratix IV
Devices chapter and the DC and
Switching Characteristics for Stratix IV
Devices section.
This option is available if you want to use an
external termination resistor instead of the
differential OCT. Checking this option turns off the
transmitter differential OCT.
“Programmable Transmitter
Termination” section in the Transceiver
Architecture in Stratix IV Devices
chapter and the DC and Switching
Characteristics for Stratix IV Devices
section.
This option selects the transmitter differential
termination value. The settings allowed are 85 
100 , 120 , and 150 .
“Programmable Transmitter
Termination” section in the Transceiver
Architecture in Stratix IV Devices
chapter and the DC and Switching
Characteristics for Stratix IV Devices
section.
What is the voltage output
differential (VOD) control
setting?
This option selects the VOD of the transmitter
buffer. The available VOD settings change based
on the transmitter termination resistance value.
“Programmable Output Differential
Voltage” section in the Transceiver
Architecture in Stratix IV Devices
chapter and the DC and Switching
Characteristics for Stratix IV Devices
section.
What is the pre-emphasis first
post-tap setting (% of VOD)?
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap.
“Programmable Pre-Emphasis”
section in the Transceiver Architecture
in Stratix IV Devices chapter.
Use external transmitter
termination.
Select the transmitter
termination resistance.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–28
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
Table 1–6. MegaWizard Plug-In Manager Options (TX Analog Screen) (Part 2 of 2)
ALTGX Setting
Description
Reference
What is the pre-emphasis
pre-tap setting (% of VOD)?
This option sets the amount of pre-emphasis on
the transmitter buffer using pre-tap.
“Programmable Pre-Emphasis”
section in the Transceiver Architecture
in Stratix IV Devices chapter.
What is the pre-emphasis
second post-tap setting (% of
VOD)?
This option sets the amount of pre-emphasis on
the transmitter buffer using second post-tap.
“Programmable Pre-Emphasis”
section in the Transceiver Architecture
in Stratix IV Devices chapter.
Reconfiguration Settings
This section describes the various dynamic reconfiguration modes and settings for
Stratix IV GX and GT transceivers.
In Reconfiguration Settings, when you enable the Enable Channel and Transmitter
PLL reconfiguration option, the following screens become available:
■
Modes
■
Transmitter PLLs
■
Clocking/Interface
The following sections describe these screens and their corresponding settings.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
1–29
Modes Screen for the Reconfiguration Settings
Figure 1–9 shows the Modes screen, listing the various dynamic reconfiguration
modes available.
Figure 1–9. MegaWizard Plug-In Manager—Reconfiguration Settings
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–30
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
Table 1–7 lists the different options available in the Modes screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–7. MegaWizard Plug-In Manager Options (Modes Screen) (Part 1 of 2)
ALTGX Setting
Description
Reference
Dynamic Reconfiguration Settings
The different dynamic reconfiguration modes available are
listed in the Reconfiguration Settings screen. Based on
which portion of the transceiver you want to reconfigure,
select the corresponding options and connect the
ALTGX_RECONFIG instance to the ALTGX instance.
■
■
What do you want to be able
to dynamically reconfigure in
the transceiver?
Analog controls (VOD, Pre-emphasis, and Manual
Equalization and EyeQ)—Enable this option to dynamically
reconfigure the PMA control settings similar to VOD,
pre-emphasis, manual equalization, DC gain, and EyeQ.
Enable adaptive equalizer control—Selecting this option
enables the Adaptive Equalization (AEQ) hardware and
provides the following additional ports:
■
aeq_togxb[]
■
aeq_fromgxb[]
These ports provide the interface between the receiver
channel and the dynamic reconfiguration controller.
■
“Dynamic Reconfiguration
Modes Implementation”
section, “PMA Controls
Reconfiguration Mode
Details” section, “Enabling
the AEQ Control Logic and
AEQ Hardware” section, and
the “Offset Cancellation
Feature” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Offset cancellation for receiver channels—This option is
enabled by default for Receiver only and Receiver and
Transmitter configurations. It is not available for
Transmitter only configurations.
Ensure that you connect a dynamic reconfiguration
controller to all the transceiver channels in the design.
You must enable this option to reconfigure one of the
following: Transmitter local divider block, CMU PLL,
Transceiver channel, or Both the CMU PLL and transceiver
channel.
Enable Channel and
Transmitter PLL
Reconfiguration
■
Channel Interface—This option allows channel interface
reconfiguration.
■
Use alternate CMU Transmitter PLL—This option sets up
the alternate PLL so that the transceiver channel can
optionally select between the output of the main and
alternate transmitter PLL.
Use additional CMU/ATX Transmitter PLLs from outside
the Transceiver Block—This option allows you to select a
maximum of four transmitter PLLs. For example, you can
select the ATX PLL as the main PLL and three additional
PLLs.
■
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
“Transceiver Channel
Reconfiguration Modes
Details” section, “FPGA
Fabric-Transceiver Channel
Interface Selection” section,
“Transceiver Channel
Reconfiguration Modes
Details” section. and the
“Multi-PLL Settings”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
How many additional PLLs are used?—You can have a
maximum of two PLLs outside the transceiver block.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
1–31
Table 1–7. MegaWizard Plug-In Manager Options (Modes Screen) (Part 2 of 2)
ALTGX Setting
Description
Reference
How many input clocks are
used?
Enter the number of input clocks available for selection for
the transmitter PLLs and receiver PLL. You have a choice of
up to 10 input clock sources (clock 1, clock 2, and so on).
“Guidelines for Specifying
the Input Reference Clocks”
section in the Dynamic
Reconfiguration in Stratix
IV Devices chapter.
What is the starting channel
number?
You must set the starting channel number of the first ALTGX
instance controlled by the dynamic reconfiguration controller
to 0. Set the starting channel number of the consecutive
ALTGX instances controlled by the same dynamic
reconfiguration controller, if any, in the next available
multiples of 4.
“Logical Channel
Addressing while
Reconfiguring the PMA
Controls” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Transmitter PLL Settings
Depending on the number of additional PLLs you select in the How many additional
PLLs are used? option in Reconfiguration Settings, the corresponding PLL screens
become available.
Each of these PLL screens have the same settings available for selection. Table 1–8 lists
each of these settings.
1
January 2014
The Main PLL is the PLL you configure in the General screen. Therefore, some of the
options are already enabled or disabled for this PLL. Some of the options differ when
compared with the additional transmitter PLLs.
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–32
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
Figure 1–10 shows the options available on the Main PLL screen of the ALTGX
MegaWizard Plug-In Manager.
Figure 1–10. MegaWizard Plug-In Manager Options—Main PLL Screen
Table 1–8 lists the available options on the Main PLL screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 1 of 3)
ALTGX Setting
Description
Reference
Main Tx PLL/Rx PLL Settings
“Selecting the PLL Logical
Reference Index for
Additional PLLs” and the
“Multi-PLL Settings”
sections in the Dynamic
Reconfiguration in Stratix
IV Devices chapter.
Use central clock divider to
drive the transmitter
channels using ×4/×N lines
If this option is enabled, the transmitter PLL is outside the
transceiver block. If this option is disabled, the transmitter
PLL is one of the CMU PLLs within the same transceiver
block.
What is the PLL logical
reference index (used in
reconfiguration)?
“Selecting the PLL Logical
Reference Index for
Additional PLLs” and
The PLL logical reference index is selected based on the
location of the alternate PLL. If the Use central clock divider “Selecting the Logical
to drive the transmitter channels using ×4/×N lines option is Reference Index of the CMU
unchecked this must be 0 or 1, otherwise this must be 2 or 3. PLL” sections in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
1–33
Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 2 of 3)
ALTGX Setting
Description
Reference
What is the selected input
clock source for the Rx/Tx
PLLs?
Assign identification numbers to all input reference clocks
that are used by the transmitter PLLs in their corresponding
PLL screens. You can set up a maximum of 10 input
reference clocks and assign identification numbers from 1 to
10.
“Guidelines for Specifying
the Input Reference Clocks”
section in the Dynamic
Reconfiguration in Stratix
IV Devices chapter.
What is the protocol to be
reconfigured to?
Select the desired functional mode here, if you intend to
dynamically reconfigure the transceiver channel to a different
functional mode using the alternate transmitter PLL.
“Channel Reconfiguration
with Transmitter PLL Select
Mode Details” in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
This option is not available for Basic, (OIF) CEI PHY
Interface, Serial RapidIO, GIGE, and XAUI functional modes.
What is the subprotocol to be
reconfigured to?
This option is available for the following protocols and
subprotocols:
—
■
Protocol = PCIe; Subprotocols = Gen 1 and Gen 2
■
Protocol = SDI; Subprotocols = 3G and HD
■
Protocol = SONET/SDH; Subprotocols = OC12, OC48, and
OC96
This option is available only for Basic mode.You can select
one of the following options for the alternate transmitter PLL:
■
Input clock frequency—Selecting this option allows you
to enter your input clock frequency. Based on the value
you enter, the ALTGX MegaWizard Plug-In Manager
populates the data rate options in the What is the effective
data rate? field. The ALTGX MegaWizard Plug-In Manager
determines these data rate options depending on the
available multiplier settings.
■
Data rate—Selecting this option allows you to enter the
transceiver channel serial data rate. Based on the value
you enter, the ALTGX MegaWizard Plug-In Manager
populates the input reference clock frequency options in
the What is the input clock frequency? field. The ALTGX
MegaWizard Plug-In Manager determines these input
reference clock frequencies depending on the available
multiplier settings.
What would you like to base
the setting on?
—
These settings are to dynamically reconfigure the transceiver
channel to listen to the alternate transmitter PLL.
■
What is the data rate?
■
January 2014
Altera Corporation
If you select the data rate option in the What would you
like to base the setting on? field, the ALTGX MegaWizard
Plug-In Manager allows you to specify the effective serial
data rate value in this field.
—
If you select the input clock frequency option in the What
would you like to base the setting on? field, the ALTGX
MegaWizard Plug-In Manager displays the list of effective
serial data rates in this field.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–34
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 3 of 3)
ALTGX Setting
Description
Reference
These settings are to dynamically reconfigure the transceiver
channel to listen to the alternate transmitter PLL.
■
What is the input clock
frequency?
■
If you select the input clock frequency option in the What
would you like to base the setting on? field, the ALTGX
MegaWizard Plug-In Manager displays the list of effective
serial data rates in this field.
If you select the data rate option in the What would you
like to base the setting on? field, the ALTGX MegaWizard
Plug-In Manager allows you to specify the effective serial
data rate value in this field.
“CMU PLL Reconfiguration
Mode Details” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
What is the PLL bandwith
mode?
The available options are Auto, Low, Medium, and High.
Select the appropriate option based on your system
requirements.
“PLL Bandwidth Setting”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create powerdown port to
power down the PLL.
Each transceiver block has two CMU PLLs. Each CMU/ATX
PLL has a dedicated power down signal called
pll_powerdown. This signal powers down the CMU PLL.
“User Reset and
Power-Down Signals”
section in the Reset Control
and Power Down in Stratix
IV Devices chapter.
Create locked port to indicate
that the PLL is in lock with
the reference clock.
Each CMU/ATX PLL has a dedicated pll_locked signal that
is fed to the FPGA fabric to indicate when the PLL is locked to
the input reference clock.
“User Reset and
Power-Down Signals”
section in the Reset Control
and Power Down in Stratix
IV Devices chapter.
Use Auxiliary Transmitter
(ATX) PLL (available only if
central clock divider is used)
This option is only available for certain data rates. Refer to the
DC and Switching Characteristics for Stratix IV Devices
chapter for the supported data rates.
This option enables the auxiliary transmitter PLL. This is a
low-jitter PLL that resides between the transceiver blocks and
can be used as a transmitter PLL.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
“Auxiliary Transmit (ATX)
PLL Block” section in the
Transceiver Architecture in
Stratix IV Devices chapter
and the DC and Switching
Characteristics for Stratix IV
Devices section.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
1–35
Clocking/Interface Screen for the Reconfiguration Settings
Figure 1–11 shows the Clocking/Interface screen of the ALTGX MegaWizard Plug-In
Manager for the Reconfiguration settings.
Figure 1–11. MegaWizard Plug-In Manager Options (Clocking/Interface Screen)
Table 1–9 lists the available options on the Clocking/Interface screen of the
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
1
This screen is not available for Basic (PMA Direct) ×1 and xN configurations.
Table 1–9. MegaWizard Plug-In Manager Options (Clocking/Interface Screen) (Part 1 of 2)
ALTGX Setting
Description
Reference
Dynamic Reconfiguration Channel Internal and Interface Settings
Select one of the following available options:
How should the receivers be
clocked?
January 2014
Altera Corporation
■
Share a single transmitter core clock between receivers
■
Use the respective channel transmitter core clocks
■
Use the respective channel receiver core clocks
“Clocking/Interface
Options” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–36
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–9. MegaWizard Plug-In Manager Options (Clocking/Interface Screen) (Part 2 of 2)
ALTGX Setting
Description
Reference
Select one of the following available options:
How should the transmitters
be clocked?
■
Share a single transmitter core clock between
transmitters
■
Use the respective channel transmitter core clocks
“Clocking/Interface
Options” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Create an 'rx_revbitorderwa'
input port to use receiver
enable bit reversal
This optional input port allows you to dynamically reverse the
bit order at the output of the receiver word aligner.
“Word Aligner” section in
the Transceiver Architecture
in Stratix IV Devices
chapter.
Check a control box to use
the corresponding control
port.
You can select various control and status signals depending
on what protocol(s) you intend to dynamically reconfigure
the transceiver channel to.
“FPGA Fabric-Transceiver
Channel Interface
Selection” section in the
Dynamic Reconfiguration in
Stratix IV Devices chapter.
Protocol Settings
This section describes the various screens available to set up the PCS blocks of the
Stratix IV transceiver.
1
Protocol Settings are not available for Basic (PMA Direct) functional mode.
Based on the protocol you select in the General screen of Parameter Settings, the
screens listed in Table 1–10 become available.
Table 1–10. Protocol Settings
Protocol Settings Screens
Protocols
8B/10B
Word Aligner
Rate match/Byte order
Y(Basic/8B10B)
Y
Y
Y Det. Latency/8B10B)
Y
—
Y SDI/8B10B)
Y
—
Y Serial RapidIO/8B10B)
Y
Y
Basic
Deterministic Latency
SDI
Serial RapidIO
The following sections describe these screens and the available settings for each of
them.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–37
8B10B Screen for the Protocol Settings
Figure 1–12 shows the 8B10B screen of the MegaWizard Plug-In Manager for the
Protocol Settings.
Figure 1–12. MegaWizard Plug-In Manager—ALTGX (8B10B Screen)
Table 1–11 lists the available options on the 8B10B screen of the MegaWizard Plug-In
Manager for your ALTGX custom megafunction variation.
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 1 of 3)
ALTGX Setting
Description
Reference
Enable low latency PCS mode.
This option disables all the PCS blocks except the
Transmitter/Receiver Phase Comp FIFO and optional
byte serializer/de-serializer.
“Low Latency PCS Datapath”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Enable 8B/10B
decoder/encoder.
This option is available if the channel width is 8-bits,
16-bits, or 32-bits.
“8B/10B Decoder” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
8B/10B encoder force disparity control:
Create a tx_forcedisp to
enable Force disparity and use
tx_dispval to code up the
incoming word using positive
or negative disparity.
January 2014
Altera Corporation
■
■
When asserted high—forces the 8B/10B encoder to
encode the data on the tx_datain port with a
positive or negative disparity depending on the
tx_dispval signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port according
to the 8B/10B running disparity rules.
“8B/10B Encoder” and
“Transceiver Port Lists” sections
in the Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–38
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 2 of 3)
ALTGX Setting
Description
Reference
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is a
data or control code group on this port.
Create an rx_ctrldetect
port to indicate 8B/10B
decoder has detected a control
code.
If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the
IEEE802.3 specification, this signal is driven high.
“8B/10B Decoder” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
If the received 10-bit code group is a data code group
(/Dx.y/), this signal is driven low.
The signal width is 1, 2, and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric and indicates an
8B/10B code group violation.
Create an rx_errdetect port
to indicate 8B/10B decoder
has detected an error code.
This signal is asserted high if the received 10-bit code
group has a code violation or disparity error. It is used
along with the rx_disperr signal to differentiate
between a code violation error and/or a disparity error.
“8B/10B Decoder” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
The signal width is 1, 2 and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric.
Create an rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error.
This signal is asserted high if the received 10-bit code
or data group has a disparity error. When this signal
goes high, rx_errdetect is also asserted high.
“8B/10B Decoder” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
The signal width is 1, 2, and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
Create an rx_runningdisp
port to indicate the current
running disparity of the 8B10B
decoded byte.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric to indicate the
current running disparity of the 8B/10B decoded byte.
“8B/10B Decoder” section of
Table 1-77 in the Transceiver
Architecture in Stratix IV Devices
chapter.
Flip receiver output data bits.
This option reverses the bit order of the parallel
receiver data at a byte level at the output of the
receiver phase compensation FIFO. For example, if the
16-bit parallel receiver data at the output of the
receiver phase compensation FIFO is
'10111100 10101101' (16'hBCAD), enabling this
option reverses the data on rx_dataout port to
'00111101 10110101' (16'h3DB5).
—
This option reverses the bit order of the parallel
transmitter data at a byte level at the input of the
transmitter phase compensation FIFO. For example, if
the 16-bit parallel transmitter data at the tx_datain
Flip transmitter input data bits.
port is '10111100 10101101' (16'hBCAD), enabling
this option reverses the input data to the transmitter
phase compensation FIFO to
'00111101 10110101' (16'h3DB5).
—
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–39
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 3 of 3)
ALTGX Setting
Description
Reference
Enabling this option in:
Enable transmitter bit reversal.
■
Single-width mode—the 8-bit D[7:0] or 10-bit
D[9:0] data at the input of the serializer gets
rewired to D[0:7] or D[0:9], respectively.
■
Double-width mode—the 16-bit D[15:0] or 20-bit
D[19:0] data at the input of the serializer gets
rewired to D[0:15] or D[0:19], respectively.
“Transmitter Bit Reversal” section
in the Transceiver Architecture in
Stratix IV Devices chapter.
For example, if the 8-bit parallel data at the input of the
serializer is '00111101', enabling this option reverses
this serializer input data to '10111100.'
Create a tx_invpolarity
port to allow Transmitter
polarity inversion.
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this option
when the positive and negative signals of the
differential output from the transmitter (tx_dataout)
are erroneously swapped on the board.
You can only select this option when you use the
Create tx_bitslipboundary
Transmitter only or Receiver and Transmitter
select port to control the
operation mode. This option enables the
number of words slipped in
tx_bitslipboundaryselect input to control the
the TX bitslipper.
number of bits slipped in the TX bitslipper.
January 2014
Altera Corporation
“Transmitter Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
—
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–40
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Word Aligner Screen for the Protocol Settings
Figure 1–13 shows the Word Aligner screen of the MegaWizard Plug-In Manager for
the Protocol Settings.
Figure 1–13. MegaWizard Plug-In Manager—ALTGX (Word Aligner Screen)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–41
Table 1–12 lists the available options on the Word Aligner screen of the MegaWizard
Plug-In Manager for your ALTGX custom megafunction variation.
1
The word aligner and rate matcher operations and patterns are pre-configured for
PCIe, GIGE, and XAUI modes, and cannot be altered.
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 1 of 4)
ALTGX Setting
Use manual word alignment
mode.
Description
Reference
Enabling this option sets the word aligner in Manual
Alignment mode. In Manual Alignment mode, the
word aligner operation is controlled by the input signal
rx_enapatternalign.
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture in Stratix
IV Devices chapter.
Two options are available in manual mode:
When should the word aligner
realign?
■
Realign continuously while the
rx_enapatternalign signal is high.
■
Realign at the rising edge of the
rx_enapatternalign signal.
This option sets the word aligner in Bit-Slip mode.
Enabling this option creates an input signal
rx_bitslip to control the word aligner. At every
rising edge of the rx_bitslip signal, the bit slip
circuitry slips one bit into the received data stream,
effectively shifting the word boundary by one bit.
Use manual bitslipping mode.
SDI
Because word alignment and framing occur after
de-scrambling, the word aligner in the receiver data
path is not useful in SDI systems. Altera recommends
driving the ALTGX rx_bitslip signal low to prevent
the word aligner from inserting bits in the received
data stream.
Use the Automatic
synchronization state machine
mode.
This option sets the word aligner in Automatic
Synchronization State Machine mode. This mode is
available only in Single-width mode for 8B/10B
encoded data:
■
10-bit PCS-PMA Interface where the 8B/10B
encoder is enabled
or
■
January 2014
Altera Corporation
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture in Stratix
IV Devices chapter.
“Word Aligner” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
10-bit PCS-PMA Interface where the 8B/10B is
disabled but the data is already 8B/10B encoded
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–42
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 2 of 4)
ALTGX Setting
Description
Reference
Use this option in Automatic Synchronization State
Machine mode to indicate the number of consecutive
valid words that it must receive between erroneous
words to reduce the error count by one. The
rx_syncstatus stays high as long as the error count
is less than the programmed error count.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Number of bad data words
before loss of synch state.
Use this option in Automatic Synchronization State
Machine mode to indicate the number of bad data
words (error count) that it must receive to lose
synchronization. The loss-of-synch is indicated by the
rx_syncstatus signal going low.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Number of valid patterns
before synch state is reached.
Use this option in Automatic Synchronization State
Machine mode to indicate the number of word
alignment patterns that it must receive without
intermediate erroneous code groups to achieve
synchronization. The rx_syncstatus signal is driven
high to indicate that synchronization has been
achieved.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Number of consecutive valid
words before synch state is
reached.
This option sets the word alignment pattern length.
The available choices depend on the following
conditions:
■
Whether the data is 8B/10B encoded or not
■
Which mode is used in Single-width mode:
What is the word alignment
pattern length?
■
What is the word alignment
pattern?
■
for 8-bit PCS-PMA Interface (8B/10B encoder
disabled), only 16 bits are allowed.
■
for 10-bit PCS-PMA, 7 and 10 bits are allowed.
Which mode is used in Double-width mode:
■
for 16-bit PCS-PMA Interface (8B/10B encoder
disabled), 8, 16, and 32 bits are allowed.
■
for 20-bit PCS-PMA Interface, 7, 10, and 20 bits
are allowed.
Enter the word alignment pattern in MSB to LSB order
with MSB at the left most bit position. The length of
the alignment pattern is based on the What is the
word alignment pattern length? option. The word
aligner restores the word boundary by looking for the
pattern that you enter here. For example, if you want to
set the word alignment pattern to /K28.5/:
■
You must enter the word alignment pattern
length: 10.
■
You must enter the word alignment pattern:
0101111100 (17C).
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
“Word Aligner in Single-Width
Mode” and “Word Aligner in
Double-Width Mode” sections in
the Transceiver Architecture in
Stratix IV Devices chapter.
“Word Aligner in Single-Width
Mode” and “Word Aligner in
Double-Width Mode” sections in
the Transceiver Architecture in
Stratix IV Devices chapter.
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–43
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 3 of 4)
ALTGX Setting
Flip word alignment pattern
bits.
Description
Reference
When this option is enabled, the ALTGX MegaWizard
Plug-In Manager flips the bit order of the pattern that
you enter in the What is the word alignment pattern?
option and uses the flipped version as the word
alignment pattern. For example, if you enter
'0101111100' (17C) as the word alignment pattern
and enable this option, the word aligner uses
'0011111010' as the word alignment pattern.
—
This option creates the output signal rx_rlv. Enabling
this option also activates the run-length violation
circuit. If the number of continuous 1s and 0s exceeds
the number that you set in this option, the run-length
violation circuit asserts the rx_rlv signal. The
rx_rlv signal is asynchronous to the receiver data
path and is asserted for a minimum of two recovered
clock cycles in Single-width mode. Similarly, it is
asserted for a minimum of three recovered clock
cycles in Double-width mode.
Enable run-length violation
checking with a run length of:
The run length limits are as follows:
■
■
Single-width mode:
■
8-bit and 16-bit channel width: 4 to 128 in
increments of four
■
10-bit and 20-bit channel width: 5 to 160 in
increments of five
“Programmable Run Length
Violation Detection” section in the
Transceiver Architecture in Stratix
IV Devices chapter.
Double-width mode:
■
16-bit and 32-bit channel width: 8 to 512 in
increments of eight
■
20-bit and 40-bit channel width: 10 to 640 in
increments of 10
Enable word aligner output
reverse bit ordering.
In manual bit-slip mode, this option creates an input
port rx_revbitorderwa to dynamically reverse the
bit order at the output of the receiver word aligner.
“Receiver Bit Reversal” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Create an rx_syncstatus
output port for pattern
detector and word aligner.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that
synchronization has been achieved. This signal is
synchronous with the parallel receiver data on the
rx_dataout port. This signal is not available in
bit-slip mode. Signal width is 1, 2, and 4 bits for a
channel width of 8-bits/10-bits, 16-bits/20-bits, and
32-bits/40-bits, respectively.
Table 1-77, “Word Aligner in
Single-Width Mode” and “Word
Aligner in Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV Devices
chapter.
Create an
rx_patterndetect port to
indicate pattern detected.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. Signal width is 1, 2, and 4
bits for a channel width of 8-bits/10-bits,
16-bits/20-bits, and 32-bits/40-bits, respectively.
Table 1-77 and “Word Aligner in
Single-Width Mode” and “Word
Aligner in Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV Devices
chapter.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–44
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 4 of 4)
ALTGX Setting
Create an rx_invpolarity
port to enable word aligner
polarity inversion.
Description
Reference
This optional port allows you to dynamically reverse
the polarity of every bit of the received data at the
input of the word aligner. Use this option when the
positive and negative signals of the differential input to
the receiver (rx_datain) are erroneously swapped on
the board.
“Receiver Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
This is an optional input port that is available only in
the double-width mode. It creates an
rx_revbyteorderwa port to dynamically swap the
MSByte and LSByte of the data at the output of the
word aligner in the receiver data path. Enabling this
Create an
option compensates for the erroneous swapping of
rx_revbyteorderwa to
enable Receiver symbol swap. bytes at the upstream transmitter and corrects the
data received by the downstream systems.
“Receiver Byte Reversal in Basic
Double-Width Modes” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
For example, if the 16-bit output of the word aligner is
0B0A, asserting the rx_revbyteorderwa signal
swaps the two bytes so the output becomes 0A0B.
Create
rx_bitslipboundaryselec
tout port to indicate the
number of bits slipped in the
word aligner.
This option is available for selection only when you are
in Receiver only or Receiver and Transmitter
operation mode. This option enables the
rx_bitslipboundaryselectout output to indicate
the number of bits slipped in the word aligner.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
—
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–45
Rate Match/Byte Order Screen for the Protocol Settings
Figure 1–14 shows the Rate Match/Byte Order screen of the MegaWizard Plug-In
Manager for the Protocol Settings.
Figure 1–14. MegaWizard Plug-In Manager—ALTGX (Rate Match/Byte Order Screen)
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–46
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–13 lists the available options on the Rate Match/Byte Order screen of the
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 1 of 3)
ALTGX Setting
Description
This option enables the rate match (clock rate
compensation) FIFO. The rate match block consists
of a 20-word deep FIFO. Depending on the PPM
difference, the rate match FIFO controls insertion and
deletion of skip characters based on the 20-bit rate
match pattern you enter in the What is the 20-bit rate
match pattern1? and What is the 20-bit rate match
pattern2? options.
To enable this block:
Enable rate match FIFO.
■
The transceiver channel must have both the
transmitter and the receiver channels instantiated.
You must select the Receiver and Transmitter
option in the What is the operation mode? field in
the General screen.
■
You must also enable the 8B/10B encoder/decoder
in the 8B10B screen.
Reference
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
The rate match block is capable of compensating up
to ±300 PPM difference between the upstream
transmitter clock and the local receiver’s input
reference clock.
What is the 20-bit rate match
pattern1? (usually used for +ve
disparity pattern)
Enter a 10-bit skip pattern and a 10-bit control
pattern. In the skip pattern field, you must choose a
10-bit code group that has neutral disparity. When
the rate matcher receives the 10-bit control pattern
followed by the 10-bit skip pattern, it inserts or
deletes the 10-bit skip pattern as necessary to avoid
rate match FIFO overflow or underflow conditions. (1)
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
What is the 20-bit rate match
pattern2? (usually used for -ve
disparity pattern)
Enter a 10-bit skip pattern and a 10-bit control
pattern. In the skip pattern field, you must choose a
10-bit code group that has neutral disparity. When
the rate matcher receives the 10-bit control pattern
followed by the 10-bit skip pattern, it inserts or
deletes the 10-bit skip pattern as necessary to avoid
rate match FIFO overflow or underflow conditions. (1)
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create the rx_rmfifofull port to
indicate when the rate match FIFO is
full.
This option creates the output port rx_rmfifofull
when you enable the Enable Rate Match FIFO option.
It is a status flag that the rate match block forwards
to the FPGA fabric. It indicates when the rate match
FIFO block is full (20 words). This signal remains
high as long as the FIFO is full. It is asynchronous to
the receiver data path.
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–47
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 2 of 3)
ALTGX Setting
Description
Reference
Create the rx_rmfifoempty port to
indicate when the rate match FIFO is
empty.
This option creates the output port rx_rmfifoempty
when you enable the Enable Rate Match FIFO option.
It is a status flag that the rate match block forwards
to the FPGA fabric. It indicates when the rate match
FIFO block is empty (5 words full). This signal
remains high as long as the FIFO is empty. It is
asynchronous to the receiver data path.
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create the
rx_rmfifodatainserted port to
indicate when data is inserted in the
rate match FIFO.
This option creates the output port
rx_rmfifodatainserted flag when you enable the
Enable Rate Match FIFO option. It is a status flag
that the rate match block forwards to the FPGA fabric.
This indicates the insertion of skip patterns. For every
deletion, this signal is high for one parallel clock
cycle.
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create the rx_rmfifodatadeleted
port to indicate when data is deleted
in the rate match FIFO.
This option creates the output port
rx_rmfifodatadeleted flag when you enable the
Enable Rate Match FIFO option. It is a status flag
that the rate match block forwards to the FPGA fabric.
This indicates the deletion of skip patterns. For every
insertion, this signal is high for one parallel clock
cycle.
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the Transceiver
Architecture in Stratix IV
Devices chapter.
Enable insertion or deletion of
consecutive characters or ordered
sets
This option enables the back-to-back insertion or
deletion of skip characters in the rate match FIFO.
This option is available for selection in Single-width
mode. It is enabled by default in Double-width mode.
—
This option enables the byte ordering block. It is
available in both Single-width and Double-width
modes. It is available only when the channel width is:
Enable byte ordering block.
■
16-bits/20-bits in Single-width mode
■
32-bits/40-bits in Double-width mode
As soon as the byte ordering block sees the rising
edge of the appropriate signal, it compares the
LSByte coming out of the byte deserializer with the
byte ordering pattern. If they do not match, the byte
ordering block inserts the pad character that you
enter in the What is the byte ordering pad pattern?
option such that the byte ordering pattern is seen in
the LSByte position. Inserting this pad character
enables the byte ordering block to restore the correct
byte order.
“Byte Ordering Block”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
What do you want the byte ordering
to be based on?
This option is available only when the byte ordering
block is enabled. This option allows you to trigger the
byte ordering block on the rising edge of either the
rx_syncstatus signal or the user-controlled
rx_enabyteord signal from the FPGA fabric.
“Byte Ordering Block”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
What is the byte ordering pattern?
This option is available only when the byte ordering
block is enabled. Enter the 10-bit pattern that the byte
ordering block must place in the LSByte position of
the receiver parallel data on the rx_dataout port.
“Byte Ordering Block”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–48
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 3 of 3)
ALTGX Setting
What is the byte ordering pad
pattern?
Description
When the byte ordering block does not find the byte
ordering pattern in the LSByte position of the data
coming out of the byte deseriazlier, it inserts this byte
ordering pad pattern such that the byte ordering
pattern is seen in the LSByte position of the receiver
parallel data on the rx_dataout port. Inserting this
pad character enables the byte ordering block to
restore the correct byte order.
Reference
“Byte Ordering Block”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Note to Table 1–13:
(1) If you want the rate matcher to insert or delete both the positive and negative disparities of the 20-bit rate matching pattern, enter the positive
disparity as pattern1 and negative disparity as pattern2.
Protocol Settings Screen for GIGE and XAUI
Figure 1–15 shows the Protocol Settings screen for the GIGE and XAUI modes of the
MegaWizard Plug-In Manager.
Figure 1–15. MegaWizard Plug-In Manager—ALTGX (Protocol Settings Screen—GIGE and XAUI)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–49
Table 1–14 lists the available options for the GIGE and XAUI modes in the Protocol
Settings screen of the MegaWizard Plug-In Manager for your ALTGX custom
megafunction variation.
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 1 of 3)
ALTGX Setting
Enable run-length violation
checking with a run length of __.
Description
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s
and 0s exceeds the number that you set in this
option, the run-length violation circuit asserts the
rx_rlv signal. The rx_rlv signal is
asynchronous to the receiver data path and is
asserted for a minimum of two recovered clock
cycles.
Reference
“Programmable Run Length
Violation Detection” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
The run length limits are five to 160 in increments
of five.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
This is an output status signal that the word
aligner forwards to the FPGA fabric to indicate
that synchronization has been achieved. This
signal is synchronous with the parallel receiver
data on the rx_dataout port. Receiver
synchronization is indicated on the
rx_syncstatus port of each channel.
Table 1-33 and the “Word
Aligner” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create an rx_patterndetect port
to indicate pattern detected.
This is an output status signal that the word
aligner forwards to the FPGA fabric to indicate
that the word alignment pattern programmed has
been detected in the current word boundary.
Table 1-33 and the “Word
Aligner” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create an rx_invpolarity port to
enable word aligner polarity
inversion.
This optional port allows you to dynamically
reverse the polarity of every bit of the received
data at the input of the word aligner. Use this
option when the positive and negative signals of
the differential input to the receiver (rx_datain)
are erroneously swapped on the board.
“Receiver Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Create an rx_ctrldetect port to
indicate 8B/10B decoder has
detected a control code.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is
a data or control code group on this port. If the
received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in
IEEE802.3 specification, this signal is driven high.
If the received 10-bit code group is a data code
group (/Dx.y/), this signal is driven low.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create an rx_errdetect port to
indicate 8B/10B decoder has
detected an error code.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates an 8B/10B code group violation. It is
asserted high if the received 10-bit code group
has a code violation or disparity error. It is used
along with the rx_disperr signal to differentiate
between a code violation error and/or a disparity
error.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–50
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 2 of 3)
ALTGX Setting
Create an rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error.
Description
Reference
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric.This signal is
asserted high if the received 10-bit code or data
group has a disparity error. When this signal goes
high, rx_errdetect also is asserted high.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
This optional port allows you to dynamically
reverse the polarity of every bit of the data word
fed to the serializer in the transmitter data path.
Create a tx_invpolarity port to
Use this option when the positive and negative
allow Transmitter polarity inversion.
signals of the differential output from the
transmitter (tx_dataout) are erroneously
swapped on the board.
“Transmitter Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV Devices
chapter.
Create an rx_runningdisp port to
indicate the current running
disparity of the 8B/10B decoded
byte.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
is asserted high when the current running
disparity of the 8B/10B decoded byte is negative.
This signal is low when the current running
disparity of the 8B/10B decoded byte is positive.
Create an rx_rmfifofull port to
indicate when the rate match FIFO
is full.
This option creates the output port
rx_rmfifofull. It is a status flag that the rate
match block forwards to the FPGA fabric. This
indicates when the rate match FIFO block is full
(20 words). This signal remains high as long as
the FIFO is full and is asynchronous to the
receiver data path.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Create an rx_rmfifoempty port to
indicate when the rate match FIFO
is empty.
This option creates the output port
rx_rmfifoempty. It is a status flag that the rate
match block forwards to the FPGA fabric. This
indicates when the rate match FIFO block is empty
(five words). This signal remains high as long as
the FIFO is empty and is asynchronous to the
receiver data path.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Create an
rx_rmfifodatainserted port to
indicate when data is inserted in the
rate match FIFO.
This option creates the output port
rx_rmfifodatainserted flag. It is a status flag
that the rate match block forwards to the FPGA
fabric. The rx_rmfifodatainserted flag is
asserted when a rate match pattern byte is
inserted to compensate for the PPM difference in
reference clock frequencies between the
upstream transmitter and the local receiver.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
This option creates the output port
rx_rmfifodatadeleted. It is a status flag that
the rate match block forwards to the FPGA fabric.
Create an rx_rmfifodatadeleted
The rx_rmfifodatadeleted flag is asserted
port to indicate when data is deleted
when a rate match pattern byte is deleted to
in the rate match FIFO.
compensate for the PPM difference in reference
clock frequencies between the upstream
transmitter and the local receiver.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
—
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–51
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 3 of 3)
ALTGX Setting
Description
Reference
Enable transmitter bit reversal.
Enabling this option reverses every bit of the
10-bit parallel data at the input of the serializer.
The 10-bit input to the serializer D[9:0] is
reversed to D[0:9].
“8B/10B Encoder” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
What is the word alignment pattern
length?
This option sets the word alignment pattern
length. The available choices are 7 and 10 for the
GIGE and XAUI modes. The default setting for this
option is 10.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Protocol Settings Screen for the (OIF) CEI Phy Interface
Table 1–15 lists the available options for the (OIF) CEI Phy Interface mode in the
Protocol Settings screen of the MegaWizard Plug-In Manager for your ALTGX custom
megafunction variation.
Table 1–15. MegaWizard Plug-In Manager Options (Protocol Settings - [OIF] CEI PHY Interface)
ALTGX Setting
Enable run-length violation checking
with a run length of __.
Description
Reference
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path and is asserted for a minimum of
two recovered clock cycles.
“Programmable Run Length
Violation Detection” section in
the Transceiver Architecture
in Stratix IV Devices chapter.
For a 32-bit channel width, the run length limits are
8 to 512 in increments of eight.
January 2014
Altera Corporation
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–52
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Protocol Settings Screen for PCIe
Figure 1–16 shows the PCIe 1 screen for Protocol Settings of the MegaWizard Plug-In
Manager.
Figure 1–16. MegaWizard Plug-In Manager—ALTGX (PCIe 1 Screen)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–53
Table 1–16 lists the available options on the PCIe 1 screen of the MegaWizard Plug-In
Manager for your ALTGX custom megafunction variation.
Table 1–16. MegaWizard Plug-In Manager Options (PCIe 1) (Part 1 of 2)
ALTGX Setting
Enable low latency synchronous
PCIe.
Enable run-length violation checking
with a run length of __.
Description
Reference
This option puts the rate match FIFO into low latency
mode, which forces the system into a 0 ppm mode.
Ensure that there is a 0 ppm difference between the
upstream transmitter’s and the local receiver’s input
reference clocks.
“Rate Match (Clock Rate
Compensation) FIFO” section
in the Transceiver
Architecture in Stratix IV
Devices chapter.
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path.
“Programmable Run Length
Violation Detection” section in
the Transceiver Architecture
in Stratix IV Devices chapter.
For both 8-bit and 16-bit channel widths, the run
length limits are 5 to 160 in increments of five.
Enable fast recovery mode.
“Fast Recovery Mode” section
in the Transceiver
Architecture in Stratix IV
Devices chapter.
This option enables the CDR control block. When
this block is enabled, the rx_locktodata and
rx_locktorefclk signals are disabled.
Enable the electrical idle inference module by
selecting this option. In PCIe mode, the PCS has an
optional electrical idle inference module designed to
implement the electrical idle inference conditions
specified in PCIe base specification 2.0.
Enable electrical idle inference
functionality.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
January 2014
Altera Corporation
Enabling this option creates the
rx_elecidleinfersel[2:0] input signal. The
electrical idle Inference module infers electrical idle
depending on the logic level driven on the
rx_elecidleinfersel[2:0] input signal. For the
electrical idle Inference module to correctly infer an
electrical idle condition in each LTSSM sub-state,
you must drive the rx_elecidleinfersel[2:0]
signal appropriately.
The ALTGX MegaWizard Plug-In Manager
automatically configures the word aligner in
Automatic Synchronization State Machine mode for
PCIe mode. This is an output status signal that the
word aligner forwards to the FPGA fabric to indicate
that synchronization has been achieved. This signal
is synchronous with the parallel receiver data on the
rx_dataout port. The signal width is 1 and 2 bits
for a channel width of 8 bits and 16 bits,
respectively.
“Electrical Idle Inference”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Table 1-29 and “Automatic
Synchronization State
Machine Mode Word Aligner
with 10-bit PMA-PCS
Interface Mode” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–54
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–16. MegaWizard Plug-In Manager Options (PCIe 1) (Part 2 of 2)
ALTGX Setting
Create an rx_patterndetect
output port to indicate pattern
detected.
Description
Reference
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. The signal width is 1 and
2 bits for a channel width of 8 bits and 16 bits,
respectively.
“Automatic Synchronization
State Machine Mode Word
Aligner with 10-bit PMA-PCS
Interface Mode” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is a
data or control code group on this port.
Create an rx_ctrldetect port to
indicate 8B/10B decoder has
detected a control code.
If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the
IEEE802.3 specification, this signal is driven high. If
the received 10-bit code group is a data code group
(/Dx.y/), this signal is driven low. The signal width is
1 and 2 bits for a channel width of 8 bits and 16 bits,
respectively.
“8B/10B Decoder” section in
the Transceiver Architecture
in Stratix IV Devices chapter.
Create a tx_detectrxloop input
port as Receiver detect or loopback
enable, depending on the power
state.
Depending on the power-down mode, asserting this
signal enables either the receiver detect operation or
Loopback mode. (1)
“Receiver Detection” and
“PCIe Reverse Parallel
Loopback” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create a tx_forceelecidle input
port to force the Transmitter to send
Electrical Idle signals.
Enabling this port sets the transmitter buffer in
electrical idle mode. This port is available in all PCIe
power-down modes and has a specific use in each
mode. (1)
“Transmitter Buffer Electrical
Idle” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
A high level on this port forces the associated
parallel transmitter data on the tx_datain port to
be transmitted with negative current running
disparity.
■
For 8-bit transceiver channel width
configurations, you must drive
tx_forcedispcompliance[1:0] high in the
same parallel clock cycle as the first /K28.5/ of
the compliance pattern on the tx_datain port.
■
For 16-bit transceiver channel width
configurations, you must drive only the LSB of
tx_forcedispcompliance[1:0]high in the
same parallel clock cycle as /K28.5/D21.5/ of the
compliance pattern on the tx_datain port.
Create a
tx_forcedispcompliance input
port to force negative running
disparity.
Create a tx_invpolarity port to
allow Transmitter polarity inversion.
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this option
when the positive and negative signals of the
differential output from the transmitter
(tx_dataout) are erroneously swapped on the
board.
“Compliance Pattern
Transmission Support”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
“Transmitter Polarity
Inversion” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Note to Table 1–16:
(1) Refer to the table 'Power States and Functions Allowed in Each Power State' in the PIPE Interface section in the Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–55
Figure 1–17 shows the PCIe 2 screen of Protocol Settings for the MegaWizard Plug-In
Manager.
Figure 1–17. MegaWizard Plug-In Manager—ALTGX (PCIe 2 Screen)
Table 1–17 lists the available options on the PCIe 2 screen of the MegaWizard Plug-In
Manager for your ALTGX custom megafunction variation.
Table 1–17. MegaWizard Plug-In Manager Options (PCIe 2 Screen) (Part 1 of 2)
ALTGX Setting
Description
Reference
Create a pipestatus output port
for PIPE interface status signal.
The PCIe interface block receives status signals
from the transceiver channel PCS and PMA blocks
and encodes the status on a 3-bit output signal
(pipestatus[2:0]) that is forwarded to the FPGA
fabric.
“Receiver Status” section and
Table 1-53 in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create a pipedatavalid output
port to indicate valid data from the
receiver.
This is an output status port that indicates the
receiver parallel data on the rx_dataout port is
valid.
January 2014
Altera Corporation
—
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–56
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–17. MegaWizard Plug-In Manager Options (PCIe 2 Screen) (Part 2 of 2)
ALTGX Setting
Description
Reference
Enabling this option creates the pipeelecidle
output status port that is forwarded to the FPGA
fabric.
■
Create a pipeelecidle output port
for Electrical Idle detect status
signal.
■
If you select Enable Electrical Idle Inference
Module, the pipeelecidle signal is driven high
when the electrical idle inference module infers
an electrical idle condition depending on the logic
driven on the rx_elecidleinfersel[2:0]
port. Otherwise, it is driven low.
If you do not select Enable Electrical Idle
Inference Module, the rx_signaldetect
output signal from the signal threshold detection
circuitry is inverted and driven on the
pipeelecidle port.
“Electrical Idle Inference”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
The pipeelecidle signal is asynchronous to the
receiver data path.
Create a pipephydonestatus
output port to indicate PIPE
completed power state transitions.
This is an output status signal forwarded to the
FPGA fabric. The completion of various PHY
functions; for example, receiver detection, power
state transition, clock switch, and rate switch, are
indicated on this pipephydonestatus signal by
driving this signal high for one parallel clock cycle.
“PCIe Mode” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create a pipe8b10binvpolarity
port to enable polarity inversion in
PIPE.
This optional port allows you to dynamically reverse
every bit of the received data at the input of the
8B/10B decoder.
“PCIe Mode” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
Create a powerdn input port for
PIPE powerdown directive.
Enabling this option creates an input control port
powerdn[1:0] for each transceiver channel.
“Power State Management”
section and Table 1-51 in the
Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–57
Protocol Settings Screen for SONET/SDH
Figure 1–18 shows the SONET/SDH screen for Protocol Settings of the MegaWizard
Plug-In Manager.
Figure 1–18. MegaWizard Plug-In Manager—ALTGX (Protocol Settings—SONET/SDH)
Table 1–18 lists the available options on the SONET/SDH screen for Protocol Settings
of the MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
Table 1–18. MegaWizard Plug-In Manager Options (SONET/SDH Screen) (Part 1 of 3)
ALTGX Setting
When should the word aligner
realign?
Description
This option is not available in SONET/SDH mode. In
SONET/SDH mode, the word aligner operates in
Manual Alignment mode. By default, the ALTGX
MegaWizard Plug-In Manager sets the behavior of
the word aligner such that re-alignment occurs when
there is a rising edge of the rx_enapatternalign
input signal in this mode.
This option sets the length of the word alignment
pattern. The following options are available:
What is the word alignment
pattern length?
January 2014
Altera Corporation
Reference
■
OC-12—only 16-bit pattern is allowed.
■
OC-48—only 16-bit pattern is allowed.
■
OC-96—16-bit and 32-bit patterns are allowed.
“Word Aligner” section in the
Transceiver Architecture in
Stratix IV Devices chapter.
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–58
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–18. MegaWizard Plug-In Manager Options (SONET/SDH Screen) (Part 2 of 3)
ALTGX Setting
Description
What is the word alignment
pattern?
Enter the word alignment pattern. By default, the
pattern that appears in the MegaWizard Plug-In
Manager is '0001010001101111' (16'h146F).
Flip word alignment pattern bits.
This option is enabled in the MegaWizard Plug-In
Manager by default. This option reverses the order
of the alignment pattern at a bit level to support
MSB-to-LSB transmission in SONET/SDH mode.
The ALTGX MegaWizard Plug-In Manager flips the
bit order of the default word alignment pattern
'0001010001101111 '(16'h146F) and uses the
flipped version '1111011000101000' (16'hF628) as
the word alignment pattern.
What do you want the byte
ordering to be based on?
This option allows you to trigger the byte ordering
block either on the rising edge of the
rx_syncstatus signal or the user-controlled
rx_enabyteord signal from the FPGA fabric. The
byte ordering block is enabled only in OC-48 mode.
Enable run-length violation
checking with a run length of.
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path and is asserted for a minimum of
two recovered clock cycles in OC-12 and OC-48
modes. Similarly, it is asserted for a minimum of
three recovered clock cycles in the OC-96 mode.
Reference
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the Transceiver Architecture in
Stratix IV Devices chapter.
—
“Byte Ordering Block” section
in the Transceiver Architecture
in Stratix IV Devices chapter.
“Programmable Run Length
Violation Detection” section in
the Transceiver Architecture in
Stratix IV Devices chapter.
For the OC-12 and OC-48 modes, the run length
limits are 4 to 128 in increments of four. For the
OC-96 mode, the run length limits are 5 to 160 in
increments of five.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that
synchronization has been achieved. This signal is
synchronous with the parallel receiver data on the
rx_dataout port. The signal width is 1 bit, 2 bits,
and 4 bits for a channel width of 8 bits, 16 bits, and
32 bits, respectively.
Table 1-77 and “Word Aligner”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create an rx_patterndetect
port to indicate pattern detected.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. The signal width is 1 bit,
2 bits, and 4 bits for a channel width of 8 bits,
16 bits, and 32 bits, respectively.
Table 1-33 and “Word Aligner”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–59
Table 1–18. MegaWizard Plug-In Manager Options (SONET/SDH Screen) (Part 3 of 3)
ALTGX Setting
Description
Reference
Create a rx_invpolarity port to
enable word aligner polarity
inversion.
This optional port allows you to dynamically reverse
the polarity of every bit of the received data at the
input of the word aligner. Use this option when the
positive and negative signals of the differential input
to the receiver (rx_datain) are erroneously
swapped on the board.
“Receiver Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
Create a tx_invpolarity port to
allow Transmitter polarity
inversion.
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this
option when the positive and negative signals of the
differential output from the transmitter
(tx_dataout) are erroneously swapped on the
board.
“Transmitter Polarity Inversion”
section in the Transceiver
Architecture in Stratix IV
Devices chapter.
This option reverses the bit order of the parallel
receiver data at a byte level at the output of the
receiver phase compensation FIFO to support
MSB-to-LSB transmission in SONET/SDH mode.
Flip receiver output data bits.
Flip transmitter input data bits.
January 2014
Altera Corporation
For example, if the 16-bit parallel receiver data at the
output of the receiver phase compensation FIFO is
'10111100 10101101' (16'hBCAD), enabling this
option reverses the data on the rx_dataout port to
'00111101 10110101' (16'h3DB5).
This option reverses the bit order of the parallel
transmitter data at a byte level at the input of the
transmitter phase compensation FIFO to support
MSB-to-LSB transmission protocols in SONET/SDH
mode.
For example, if the 16-bit parallel transmitter data at
the tx_datain port is '10111100 10101101'
(16'hBCAD), enabling this option reverses the input
data to the transmitter phase compensation FIFO to
'00111101 10110101' (16'h3DB5).
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the Transceiver Architecture in
Stratix IV Devices chapter.
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the Transceiver Architecture in
Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–60
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
EDA Screen
Figure 1–19 shows the EDA screen of the MegaWizard Plug-In Manager. The
Generate Netlist option generates a netlist for the third party EDA synthesis tool to
estimate timing and resource utilization for the ALTGX instance.
Figure 1–19. MegaWizard Plug-In Manager—ALTGX (EDA Screen)
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
1–61
Summary Screen
Figure 1–20 shows the Summary screen of the MegaWizard Plug-In Manager. You can
select optional files on this page. After you make your selections, click Finish to
generate the files.
Figure 1–20. MegaWizard Plug-In Manager—ALTGX (Summary Screen)
Document Revision History
Table 1–19 lists the revision history for this chapter.
Table 1–19. Document Revision History (Part 1 of 2)
Date
Version
January 2014
4.4
September 2012
4.3
December 2011
4.2
January 2014
Altera Corporation
Changes
■
Updated Table 1–5.
■
Updated Table 1–1 to close FB #65275.
■
Updated Table 1–12 to close FB #37243.
Updated Table 1–1.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
1–62
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–19. Document Revision History (Part 2 of 2)
Date
February 2011
November 2009
June 2009
March 2009
November 2008
Version
4.1
4.0
3.1
3.0
2.0
Changes
■
Updated Table 1–1, Table 1–3, Table 1–7, and Table 1–17.
■
Updated chapter title.
■
Minor text edits.
■
Applied new template.
■
Added Deterministic Latency protocol information.
■
Added AEQ information.
■
Updated PLL setting information.
■
Consolidated Parameter Settings information (Table 1–1 to Table 1–6).
■
Consolidated Reconfiguration Settings information (Table 1–7 to Table 1–9).
■
Consolidated Protocol Settings information (Table 1–10 to Table 1–18).
■
Minor text edits.
■
Updated Table 1–9, Table 1–29 and Table 1–35.
■
Updated Figure 1–10.
■
Added introductory sentences to improve search ability.
■
Minor text edits.
■
Updated the figures to match the software changes.
■
Removed the 'Deterministic Latency' subprotocol from Basic functional mode.
■
Removed the various clock frequencies from the Reconfig Clks screen for all the
applicable functional modes.
■
Updated Table 1–1, Table 1–6, and Table 1–11.
■
Updated Figure 1–8.
■
Added Reconfig Clks and Reconfig 2 sections.
■
Added the “Use ATX Transmitter PLL” setting.
■
Changed the “Which device speed grade will you be using?” setting to the “Which device
variation will you be using” setting.
June 2008
1.1
Minor text edit.
May 2008
1.0
Initial release.
Stratix IV Device Handbook
Volume 3: Transceiver Configuration Guide
January 2014 Altera Corporation