Using TriMatrix Embedded Memory Blocks in Straix & Stratix

14. TriMatrix Embedded
Memory Blocks in
Stratix & Stratix GX Devices
S52003-3.3
Introduction
Stratix® and Stratix GX devices feature the TriMatrix™ memory
structure, composed of three sizes of embedded RAM blocks. TriMatrix
memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit
M-RAM blocks, each of which is configurable to support a wide range of
features. Offering up to 10 Mbits of RAM and up to 12 terabits per second
of device memory bandwidth, the TriMatrix memory structure makes the
Stratix and Stratix GX families ideal for memory-intensive applications.
TriMatrix
Memory
TriMatrix memory structures can implement a wide variety of complex
memory functions. For example, use the small M512 blocks for first-in
first-out (FIFO) functions and clock domain buffering where memory
bandwidth is critical. The M4K blocks are an ideal size for applications
requiring medium-sized memory, such as asynchronous transfer mode
(ATM) cell processing. M-RAM blocks enhance programmable logic
device (PLD) memory capabilities for large buffering applications, such
as internet protocol (IP) packet buffering and system cache.
TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift-register, ROM, and FIFO mode. The
TriMatrix memory architecture also includes advanced features and
capabilities, such as byte enable support, parity-bit support, and mixedport width support. This chapter describes the various TriMatrix memory
modes and features.
Table 14–1 summarizes the features supported by the three sizes of
TriMatrix memory.
f
Altera Corporation
July 2005
For more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
14–1
TriMatrix Memory
Table 14–1. Summary of TriMatrix Memory Features
Feature
Performance
Total RAM bits (including parity bits)
Configurations
Parity bits
M512 Block
M4K Block
M-RAM Block
319 MHz
290 MHz
287 MHz
576
4,608
589,824
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
v
v
v
v
v
Byte enable
Single-port memory
v
v
v
Simple dual-port memory
v
v
v
v
v
True dual-port memory
Embedded shift register
v
v
ROM
v
v
FIFO buffer
v
v
v
Simple dual-port mixed width support
v
v
v
v
v
True dual-port mixed width support
v
Memory initialization file (.mif)
v
Mixed-clock mode
v
v
v
Power-up condition
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Input and output
registers (1)
Input and output
registers (2)
Output registers
Same-port read-during-write
New data available at
positive clock edge
New data available at
positive clock edge
New data available at
positive clock edge
Mixed-port read-during-write
Outputs set to
unknown or old data
Outputs set to
unknown or old data
Unknown output
Notes to Table 14–1:
(1)
(2)
The rden register on the M512 memory block does not have a clear port.
On the M4K block, asserting the clear port of the rden and byte enable registers drives the output of these registers
high.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
The extremely high memory bandwidth of the Stratix and Stratix GX
device families is a result of increased memory capacity and speed.
Table 14–2 shows the memory capacity for TriMatrix memory blocks in
each Stratix device. Table 14–3 shows the memory capacity for TriMatrix
memory blocks in each Stratix GX device.
Table 14–2. TriMatrix Memory Distribution in Stratix Devices
Device
M512
M4K
Columns/Blocks Columns/Blocks
EP1S10
4 / 94
EP1S20
EP1S25
M-RAM
Blocks
Total RAM Bits
2 / 60
1
920,448
6 / 194
2 / 82
2
1,669,248
6 / 224
3 / 138
2
1,944,576
EP1S30
7 / 295
3 / 171
4
3,317,184
EP1S40
8 / 384
3 / 183
4
3,423,744
EP1S60
10 / 574
4 / 292
6
5,215,104
EP1S80
11 / 767
4 / 364
9
7,427,520
Table 14–3. TriMatrix Memory Distribution in Stratix GX Devices
Device
M512
M4K
Columns/Blocks Columns/Blocks
M-RAM
Blocks
Total RAM Bits
EP1SGX10
4 / 94
2 / 60
1
920,448
EP1SGX25
6 / 224
3 / 138
2
1,944,576
EP1SGX40
8 / 384
3 / 183
4
3,423,744
Clear Signals
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Parity Bit Support
The memory blocks support a parity bit for each byte. Parity bits are in
addition to the amount of memory in each RAM block. For example, the
M512 block has 576 bits, 64 of which are optionally used for parity bit
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TriMatrix Memory
storage. The parity bit, along with logic implemented in logic elements
(LEs), can implement parity checking for error detection to ensure data
integrity. Parity-size data words can also store user-specified control bits.
Byte Enable Support
In the M4K and M-RAM blocks, byte enables can mask the input data so
that only specific bytes of data are written. The unwritten bytes retain the
previous written value. The write enable signals (wren), in conjunction
with the byte enable signals (byteena), controls the RAM block’s write
operations. The default value for the byteena signals is high (enabled),
in which case writing is controlled only by the wren signals.
Asserting the clear port of the byte enable registers drives the byte enable
signals to their default high level.
M4K Blocks
M4K blocks support byte writes when the write port has a data width of
16, 18, 32, or 36 bits. Table 14–4 summarizes the byte selection.
Table 14–4. Byte Enable for M4K Blocks Notes (1), (2)
byteena
datain × 18
datain × 36
[0] = 1
[8..0]
[8..0]
[1] = 1
[17..9]
[17..9]
[2] = 1
–
[26..18]
[3] = 1
–
[35..27]
Notes to Table 14–4:
(1)
(2)
Any combination of byte enables is possible.
Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32
modes.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
M-RAM Blocks
M-RAM blocks support byte enables for the × 16, × 18, × 32, × 36, × 64, and
× 72 modes. In the × 128 or × 144 simple dual-port mode, the two sets of
byteena signals (byteena_a and byteena_b) combine to form the
necessary 16 byte enables. Tables 14–5 and 14–6 summarize the byte
selection.
Table 14–5. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena
datain × 18
datain × 36
datain × 72
[0] = 1
[8..0]
[8..0]
[8..0]
[1] = 1
[17..9]
[17..9]
[17..9]
[2] = 1
–
[26..18]
[26..18]
[3] = 1
–
[35..27]
[35..27]
[4] = 1
–
–
[44..36]
[5] = 1
–
–
[53..45]
[6] = 1
–
–
[62..54]
[7] = 1
–
–
[71..63]
Notes to Table 14–5:
(1)
(2)
Any combination of byte enables is possible.
Byte enables can be used in the same manner with 8-bit words, that is, in × 16, × 32,
and × 64 modes.
Table 14–6. M-RAM Combined Byte Selection for × 144 Mode (Part 1 of 2),
Notes (1), (2)
byteena_a
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July 2005
datain × 144
[0] = 1
[8..0]
[1] = 1
[17..9]
[2] = 1
[26..18]
[3] = 1
[35..27]
[4] = 1
[44..36]
[5] = 1
[53..45]
[6] = 1
[62..54]
[7] = 1
[71..63]
[8] = 1
[80..72]
[9] = 1
[89..81]
[10] = 1
[98..90]
[11] = 1
[107..99]
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TriMatrix Memory
Table 14–6. M-RAM Combined Byte Selection for × 144 Mode (Part 2 of 2),
Notes (1), (2)
byteena_a
datain × 144
[12] = 1
[116..108]
[13] = 1
[125..117]
[14] = 1
[134..126]
[15] = 1
[143..135]
Notes to Table 14–6:
(1)
(2)
Any combination of byte enables is possible.
Byte enables can be used in the same manner with 8-bit words, i.e., in × 16, × 32,
× 64, and × 128 modes.
Byte Enable Functional Waveform
Figure 14–1 shows how both the wren and the byteena signals control
the write operations of the RAM.
Figure 14–1. Byte Enable Functional Waveform Note (1)
inclock
wren
a0
address
an
data_in
XXXX
byteena
XX
contents at a0
contents at a1
a2
a0
a1
ABCD
10
a2
XXXX
01
11
FFFF
XX
ABFF
FFFF
FFCD
FFFF
contents at a2
asynch_data_out
a1
doutn
ABXX
ABCD
XXCD
ABCD
ABFF
FFCD
ABCD
Note to Figure 14–1:
(1)
For more information on simulation output when a read-during-write occurs at the same address location, see
“Read-During-Write Operation at the Same Address” on page 14–25.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Using TriMatrix
Memory
f
The TriMatrix memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. All TriMatrix memory blocks are pipelined, meaning that
all inputs are registered, but outputs are either registered or
combinatorial. TriMatrix memory can emulate a flow-through memory
by using combinatorial outputs.
For more information, see AN 210: Converting Memory from Asynchronous
to Synchronous for Stratix & Stratix GX Designs.
Depending on the TriMatrix memory block type, the memory can have
various modes, including:
■
■
■
■
■
■
Single-port
Simple dual-port
True dual-port (bidirectional dual-port)
Shift-register
ROM
FIFO
Implementing Single-Port Mode
Single-port mode supports non-simultaneous reads and writes.
Figure 14–2 shows the single-port memory configuration for TriMatrix
memory. All memory block types support the single-port mode.
Figure 14–2. Single-Port Memory Note (1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to Figure 14–2:
(1)
Two single-port memory blocks can be implemented in a single M4K block.
M4K memory blocks can also be divided in half and used for two
independent single-port RAM blocks. The Altera Quartus II software
automatically uses this single-port memory packing when running low
on memory resources. To force two single-port memories into one M4K
block, first ensure that each of the two independent RAM blocks is equal
to or less than half the size of the M4K block. Second, assign both singleport RAMs to the same M4K block.
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Using TriMatrix Memory
In the single-port RAM configuration, the outputs can only be in
read-during-write mode, which means that during the write operation,
data written to the RAM flows through to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle it was written on. For more information about
read-during-write mode, see “Read-During-Write Operation at the Same
Address” on page 14–25.
Figure 14–3 shows timing waveforms for read and write operations in
single-port mode.
Figure 14–3. Single-Port Timing Waveforms
in clock
wren
address
an-1
an
data_in
din-1
din
synch_data_out
asynch_data_out
a0
din-2
din
din-1
din
din-1
a1
a2
dout0
dout0
dout1
a3
dout1
a4
a5
a6
din4
din5
din6
dout2
dout2
dout3
dout3
din4
din4
din5
Implementing Simple Dual-Port Mode
Simple dual-port memory supports a simultaneous read and write.
Figure 14–4 shows the simple dual-port memory configuration for
TriMatrix memory. All memory block types support this configuration.
Figure 14–4. Simple Dual-Port Memory Note (1)
Dual-Port Memory
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Note to Figure 14–4:
(1)
Simple dual-port RAM supports read/write clock mode in addition to the
input/output clock mode shown.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
TriMatrix memory supports mixed-width configurations, allowing
different read and write port widths. When using mixed-width mode, the
LSB is written to or read from first. For example, take a RAM that is set up
in mixed-width mode with write data width ×8 and read data width ×2.
If a binary 00000001 is written to write dress 0, the following is read out
of the ×2 output side:
Read Address
×2 data
00
01(LSB of ×8 data)
01
00
10
00
11
00(MSB of ×8 data)
Tables 14–7 to 14–9 show the mixed width configurations for the M512,
M4K, and M-RAM blocks, respectively.
Table 14–7. M512 Block Mixed-Width Configurations (Simple Dual-Port Mode)
Write Port
Read Port
512 × 1
256 × 2
128 × 4
64 × 8
32 × 16
v
v
v
v
v
v
v
512 × 1
256 × 2
v
v
v
128 × 4
v
v
v
64 × 8
v
v
32 × 16
v
v
64 × 9
32 × 18
v
v
v
v
64 × 9
v
32 × 18
v
Table 14–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Write Port
Read Port
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16
128 × 32 512 × 9 256 × 18
4K × 1
v
v
v
v
v
v
2K × 2
v
v
v
v
v
v
1K × 4
v
v
v
v
v
v
512 × 8
v
v
v
v
v
v
256 × 16
v
v
v
v
v
v
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128 × 36
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Using TriMatrix Memory
Table 14–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Write Port
Read Port
128 × 32
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16
v
v
v
v
v
128 × 32 512 × 9 256 × 18
128 × 36
v
512 × 9
v
v
v
256 × 18
v
v
v
128 × 36
v
v
v
Table 14–9. M-RAM Block Mixed-Width Configurations (Simple Dual-Port Mode)
Write Port
Read Port
64K × 9
32K × 18
16K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
16K × 36
v
v
v
v
8K × 72
v
v
v
v
4K × 144
4K × 144
v
M512 blocks support serializer and deserializer (SERDES) applications.
By using the mixed-width support in combination with double data rate
(DDR) I/O standards, the block can function as a SERDES to support lowspeed serial I/O standards using global or regional clocks.
f
For more information on Stratix device I/O structure see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1.
For more information on Stratix GX device I/O structure see the
Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
In simple dual-port mode, the M512 and M4K blocks have one write
enable and one read enable signal. The M512 does not support a clear port
on the rden register. On the M4K block, asserting the clear port of the
rden register drives rden high, which allows the read operation to occur.
When the read enable is deactivated, the current data is retained at the
output ports. If the read enable is activated during a write operation with
the same address location selected, the simple dual-port RAM output is
either unknown or can be set to output the old data stored at the memory
address. For more information, see “Read-During-Write Operation at the
Same Address” on page 14–25.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
M-RAM blocks have one write enable signal in simple dual-port mode. To
perform a write operation, the write enable is held high. The M-RAM
block is always enabled for read operation. If the read address and the
write address select the same address location during a write operation,
the M-RAM block output is unknown.
Figure 14–5 shows timing waveforms for read and write operations in
simple dual-port mode.
Figure 14–5. Simple Dual-Port Timing Waveforms Note (1)
wrclock
wren
wraddress
an-1
an
data_in
din-1
din
a0
a1
a2
a3
a4
a5
a6
din4
din5
din6
rdclock
rden
rdaddress
synch_data_out
asynch_data_out
bn
doutn-2
doutn-1
b1
b0
doutn-1
doutn
b2
doutn
b3
dout0
dout0
Note to Figure 14–5:
(1)
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
Implementing True Dual-Port Mode
M4K and M-RAM blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies. Figure 14–6 shows the
true dual-port memory configuration for TriMatrix memory.
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Using TriMatrix Memory
Figure 14–6. True Dual-Port Memory Note (1)
A
B
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
Note to Figure 14–6:
(1)
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
The widest bit configuration of the M4K and M-RAM blocks in true dualport mode is 256 × 16-bit (× 18-bit with parity) and 8K × 64-bit (× 72-bit
with parity), respectively. The 128 × 32-bit (× 36-bit with parity)
configuration of the M4K block and the 4K × 128-bit (× 144-bit with parity)
configuration of the M-RAM block are unavailable because the number of
output drivers is equivalent to the maximum bit width of the respective
memory block. Because true dual-port RAM has outputs on two ports,
the maximum width of the true dual-port RAM equals half of the total
number of output drivers. Tables 14–10 and 14–11 list the possible M4K
RAM block and M-RAM block configurations, respectively.
Table 14–10. M4K Block Mixed-Port Width Configurations (True Dual-Port)
Port B
Port A
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
4K × 1
v
v
v
v
v
2K × 2
v
v
v
v
v
1K × 4
v
v
v
v
v
512 × 8
v
v
v
v
v
256 × 16
v
v
v
v
v
512 × 9
v
v
256 × 18
v
v
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Table 14–11. M-RAM Block Mixed-Port Width Configurations (True DualPort)
Port B
Port A
64K × 9
32K × 18
16K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
16K × 36
v
v
v
v
8K × 72
v
v
v
v
In true dual-port configuration, the RAM outputs can only be configured
for read-during-write mode. This means that during write operation,
data being written to the A or B port of the RAM flows through to the A
or B outputs, respectively. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle it was
written on. For waveforms and information on mixed-port read-duringwrite mode, see “Read-During-Write Operation at the Same Address” on
page 14–25.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location. Data is written on the rising edge of the write
clock for the M-RAM block. For a valid write operation to the same
address of the M-RAM block, the rising edge of the write clock for port A
must occur following the maximum write cycle time interval after the
rising edge of the write clock for port B. Since data is written into the
M512 and M4K blocks at the falling edge of the write clock, the rising
edge of the write clock for port A should occur following half of the
maximum write cycle time interval after the falling edge of the write clock
for port B. If this timing is not met, the data stored in that particular
address is invalid.
f
See the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of
the Stratix GX Device Handbook, Volume 1 for the maximum synchronous
write cycle time.
Figure 14–7 shows true dual-port timing waveforms for write operation
at port A and read operation at port B.
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Stratix GX Device Handbook, Volume 2
Using TriMatrix Memory
Figure 14–7. True Dual-Port Timing Waveforms
A_clk
A_wren
A_address
A_data_in
an-1
an
din-1
din
A_synch_data_out
din-2
A_asynch_data_out
a0
din
din-1
din
din-1
a1
a2
dout0
dout1
dout1
dout0
a3
a4
a5
a6
din4
din5
din6
dout2
dout2
din4
dout3
dout3
din5
din4
B_clk
B_wren
B_address
B_synch_data_out
B_asynch_data_out
bn
doutn-2
doutn-1
b1
b0
doutn-1
dout0
doutn
dout0
doutn
b2
b3
dout1
dout2
dout1
Implementing Shift-Register Mode
Embedded memory block configurations can implement shift registers
for digital signal processing (DSP) applications, such as finite impulse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP applications require local data storage, traditionally
implemented with standard flip-flops that can quickly consume many
logic cells for large shift registers. A more efficient alternative is to use
embedded memory as a shift register block, which saves logic cell and
routing resources and provides a more efficient implementation.
The size of a (w × m × n) shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n). The size
of a (w × m × n) shift register must be less than or equal to the maximum
number of memory bits in the respective block: 576 bits for the M512
block and 4,608 bits for the M4K block. In addition, the size of w × n must
be less than or equal to the maximum width of the respective block: 18
bits for the M512 block and 36 bits for the M4K block. If a larger shift
register is required, the memory blocks can be cascaded together.
1
M-RAM blocks do not support the shift-register mode.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift-register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 14–8 shows the
TriMatrix memory block in the shift-register mode.
Figure 14–8. Shift-Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
w
w
m-Bit Shift Register
w
w
n Number
of Taps
m-Bit Shift Register
w
w
m-Bit Shift Register
w
w
Implementing ROM Mode
The M512 and the M4K blocks support ROM mode. Use a memory
initialization file (.mif) to initialize the ROM contents of M512 and M4K
blocks. The M-RAM block does not support ROM mode.
All Stratix memory configurations must have synchronous inputs;
therefore, the address lines of the ROM are registered. The outputs can be
registered or combinatorial. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
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Clock Modes
Implementing FIFO Buffers
While the small M512 memory blocks are ideal for designs with many
shallow FIFO buffers, all three memory sizes support FIFO mode.
All memory configurations have synchronous inputs; however, the FIFO
buffer outputs are always combinatorial. Simultaneous read and write
from an empty FIFO is not supported.
Clock Modes
Depending on the TriMatrix memory mode, independent, input/output,
read/write, and/or single-port clock modes are available. Table 14–12
shows the clock modes supported by the TriMatrix memory modes.
Table 14–12. TriMatrix Memory Clock Modes
Clocking Mode
True-Dual Port
Mode
Independent
v
Input/output
v
Read/write
Single-port
Simple DualPort Mode
Single-Port
Mode
v
v
v
Independent Clock Mode
The TriMatrix memory blocks can implement independent clock mode
for true dual-port memory. In this mode, a separate clock is available for
each port (A and B). Clock A controls all registers on the port A side,
while clock B controls all registers on the port B side. Each port also
supports independent clock enables and asynchronous clear signals for
port A and B registers. Figure 14–9 shows a TriMatrix memory block in
independent clock mode.
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July 2005
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
clockB
clkenB
wrenB
addressB[ ]
D
ENA
D
D
Q
ENA
ENA
Q
Q
ENA
D
Q
ENA
ENA
D
clockA
clkenA
wrenA
addressA[ ]
byteenaA[ ]
dataA[ ]
8
D
8 LAB Row Clocks
Q
Write
Pulse
Generator
D
Data Out
Address A
Write/Read
Enable
qA[ ]
qB[ ]
Q
Data Out
Write/Read
Enable
Address B
Byte Enable B
Byte Enable A
B
Data In
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
A
Data In
ENA
Write
Pulse
Generator
Q
D
ENA
Q
D
ENA
Q
D
Q
ENA
8
dataB[ ]
byteenaB[ ]
Figure 14–9. Independent Clock Mode Note (1), (2)
Note to Figure 14–9:
(1)
(2)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
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July 2005
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Stratix GX Device Handbook, Volume 2
Clock Modes
Input/Output Clock Mode
The TriMatrix memory blocks can implement input/output clock mode
for true and simple dual-port memory. On each of the two ports, A and B,
one clock controls all registers for inputs into the memory block: data
input, wren, and address. The other clock controls the block’s data output
registers. Each memory block port also supports independent clock
enables and asynchronous clear signals for input and output registers.
Figures 14–10 and 14–11 show the memory block in input/output clock
mode for true and simple dual-port modes, respectively.
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Altera Corporation
July 2005
(1)
Altera Corporation
July 2005
clockA
clkenA
wrenA
addressA[ ]
byteenaA[ ]
dataA[ ]
8
ENA
D
ENA
D
ENA
D
ENA
D
8 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Address A
ENA
D
A
qA[ ]
Data In
B
qB[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
ENA
D
ENA
D
ENA
D
ENA
D
8
clockB
clkenB
wrenB
addressB[ ]
byteenaB[ ]
dataB[ ]
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 14–10. Input/Output Clock Mode in True Dual-Port Mode Note (1)
Note to Figure 14–10:
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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Stratix GX Device Handbook, Volume 2
Clock Modes
All registers shown have asynchronous clear ports, except when using
the M-RAM. M-RAM blocks have asynchronous clear ports on their
output registers only.
Figure 14–11. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3), (4)
8 LAB Row
Clocks
Memory Block
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
8
data[ ]
D
Q
ENA
Data In
address[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
D
Q
ENA
Read Enable
D
Q
ENA
To MultiTrack
Interconnect
rden
wren
outclken
inclken
D
Q
ENA
wrclock
Write
Pulse
Generator
Write Enable
rdclock
Notes to Figure 14–11:
(1)
(2)
(3)
(4)
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
For more information on the MultiTrack™ interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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July 2005
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Read/Write Clock Mode
The TriMatrix memory blocks can implement read/write clock mode for
simple dual-port memory. This mode can use up to two clocks. The write
clock controls the block’s data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 14–12 shows a memory block in read/write clock mode.
Altera Corporation
July 2005
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Stratix GX Device Handbook, Volume 2
Clock Modes
Figure 14–12. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3)
8 LAB Row
Clocks
Memory Block
256 × 16
512 × 8
1,024 × 4
Data In
2,048 × 2
4,096 × 1
8
data[ ]
D
Q
ENA
Data Out
address[ ]
D
Q
ENA
Read Address
wraddress[ ]
D
Q
ENA
Write Address
byteena[ ]
D
Q
ENA
Byte Enable
D
Q
ENA
To MultiTrack
Interconnect
rden
D
Q
ENA
wren
Read
Pulse
Generator
Read Enable
rdclocken
wrclocken
D
Q
ENA
wrclock
Write
Pulse
Generator
Write Enable
rdclock
Notes to Figure 14–12:
(1)
(2)
(3)
For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Single-Port Mode
The TriMatrix memory blocks can implement single-port clock mode for
single-port memory mode. Single-port mode is used when simultaneous
reads and writes are not required. See Figure 14–13. A single block in a
memory block can support up to two single-port mode RAM blocks in
M4K blocks.
Figure 14–13. Single-Port Mode Notes (1), (2), (3)
8 LAB Row
Clocks
RAM/ROM
256 × 16
512 × 8
1,024 × 4
Data In
2,048 × 2
4,096 × 1
8
data[ ]
D
Q
ENA
Data Out
address[ ]
D
Q
ENA
Address
D
Q
ENA
To MultiTrack
Interconnect
wren
Write Enable
outclken
inclken
inclock
D
Q
ENA
Write
Pulse
Generator
outclock
Notes to Figure 14–13:
(1)
(2)
(3)
For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Designing With
TriMatrix
Memory
Altera Corporation
July 2005
When instantiating TriMatrix memory you must understand the various
features that set it apart from other memory architectures. The following
sections describe some of the important attributes and functionality of
TriMatrix memory.
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Stratix GX Device Handbook, Volume 2
Designing With TriMatrix Memory
f
For information on the difference between APEX-style memory and
TriMatrix memory, see the Transitioning APEX Designs to Stratix Devices
chapter.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks using the most efficient size
combinations. The memory can also be manually assigned to a specific
block size or a mixture of block sizes. Table 14–1 on page 14–2 is a guide
for selecting a TriMatrix memory block size based on supported features.
1
f
Violating the setup or hold time on the address registers could
corrupt the memory contents. This applies to both read and
write operations.
For more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
1
Violating the setup or hold time on the address registers could
corrupt the memory contents. This applies to both read and
write operations.
Pipeline & Flow-Through Modes
TriMatrix memory architecture implements synchronous (pipelined)
RAM by registering both the input and output signals to the RAM block.
All TriMatrix memory inputs are registered providing synchronous write
cycles. In synchronous operation, RAM generates its own self-timed
strobe write enable (wren) signal derived from the global or regional
clock. In contrast, a circuit using asynchronous RAM must generate the
RAM wren signal while ensuring its data and address signals meet setup
and hold time specifications relative to the wren signal. The output
registers can be bypassed.
In an asynchronous memory neither the input nor the output is
registered. While Stratix and Stratix GX devices do not support
asynchronous memory, they do support a flow-through read where the
output data is available during the clock cycle when the read address is
driven into it. Flow-through reading is possible in the simple and true
dual-port modes of the M512 and M4K blocks by clocking the read enable
and read address registers on the negative clock edge and bypassing the
output registers.
f
For more information, see AN 210: Converting Memory from Asynchronous
to Synchronous for Stratix & Stratix GX Devices.
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July 2005
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Power-up Conditions & Memory Initialization
Upon power-up, TriMatrix memory is in an idle state. The M512 and M4K
block outputs always power-up to zero, regardless of whether the output
registers are used or bypassed. Even if a memory initialization file is used
to pre-load the contents of the RAM block, the outputs still power-up
cleared. For example, if address 0 is pre-initialized to FF, the M512 and
M4K blocks power-up with the output at 00.
M-RAM blocks do not support memory initialization files; therefore, they
cannot be pre-loaded with data upon power-up. M-RAM blocks
combinatorial outputs and memory controls always power-up to an
unknown state. If M-RAM block outputs are registered, the registers
power-up cleared. The undefined output appears one clock cycle later.
The output remains undefined until a read operation is performed on an
address that has been written to.
Read-DuringWrite Operation
at the Same
Address
The following two sections describe the functionality of the various RAM
configurations when reading from an address during a write operation at
that same address. There are two types of read-during-write operations:
same-port and mixed-port. Figure 14–14 illustrates the difference in data
flow between same-port and mixed-port read-during-write.
Figure 14–14. Read-During-Write Data Flow
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle it was written on. This behavior is valid on all memoryblock sizes. See Figure 14–15 for a sample functional waveform.
Altera Corporation
July 2005
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Stratix GX Device Handbook, Volume 2
Read-During-Write Operation at the Same Address
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown. (See Figure 14–1 on
page 14–6.) The non-masked bytes are read out as shown in Figure 14–15.
Figure 14–15. Same-Port Read-During-Write Functionality Note (1)
inclock
data_in
A
B
wren
data_out Old
A
Note to Figure 14–15:
(1)
Outputs are not registered.
Mixed-Port Read-During-Write Mode
This mode is used when a RAM in simple or true dual-port mode has one
port reading and the other port writing to the same address location with
the same clock.
The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512
and M4K memory blocks determines whether to output the old data at
the address or a “don’t care” value. Setting this parameter to OLD_DATA
outputs the old data at that address. Setting this parameter to DONT_CARE
outputs a “don’t care” or unknown value. See Figures 14–16 and 14–17 for
sample functional waveforms showing this operation. These figures
assume that the outputs are not registered.
The DONT_CARE setting allows memory implementation in any TriMatrix
memory block. The OLD_DATA setting restricts memory implementation
to only M512 or M4K memory blocks. Selecting DONT_CARE gives the
compiler more flexibility when placing memory functions into TriMatrix
memory.
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TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 14–16. Mixed-Port Read-During-Write: OLD_DATA
inclock
addressA and
addressB
Port A
data_in
Address Q
A
B
Port A
wren
Port B
wren
Port B
data_out
Old
A
B
For mixed-port read-during-write operation of the same address location
of a M-RAM block, the RAM outputs are unknown, as shown in
Figure 14–17.
Figure 14–17. Mixed-Port Read-During-Write: DONT_CARE
inclock
addressA and
addressB
Port A
data_in
Address Q
A
B
Port A
wren
Port B
wren
Port B
data_out
Unknown
B
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value will be unknown during
a mixed-port read-during-write operation.
Conclusion
Altera Corporation
July 2005
TriMatrix memory, an enhanced RAM architecture with extremely high
memory bandwidth in Stratix and Stratix GX devices, gives advanced
control of memory applications with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode.
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Conclusion
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July 2005