I/O Features in Cyclone IV Devices

6. I/O Features in Cyclone IV Devices
May 2013
CYIV-51006-2.6
CYIV-51006-2.6
This chapter describes the I/O and high speed I/O capabilities and features offered in
Cyclone® IV devices.
The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O
standards in many low-cost applications, and the significant increase in required I/O
performance. Altera’s objective is to create a device that accommodates your key
board design needs with ease and flexibility.
The I/O flexibility of Cyclone IV devices is increased from the previous generation
low-cost FPGAs by allowing all I/O standards to be selected on all I/O banks.
Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The
Cyclone IV devices support LVDS, BLVDS, RSDS, mini-LVDS, and PPDS. The
transceiver reference clocks and the existing general-purpose I/O (GPIO) clock input
features also support the LVDS I/O standards.
The Quartus® II software completes the solution with powerful pin planning features
that allow you to plan and optimize I/O system designs even before the design files
are available.
This chapter includes the following sections:
■
“Cyclone IV I/O Elements” on page 6–2
■
“I/O Element Features” on page 6–3
■
“OCT Support” on page 6–6
■
“I/O Standards” on page 6–11
■
“Termination Scheme for I/O Standards” on page 6–13
■
“I/O Banks” on page 6–16
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone IV Device Handbook,
Volume 1
May 2013
Feedback Subscribe
6–2
Chapter 6: I/O Features in Cyclone IV Devices
Cyclone IV I/O Elements
■
“Pad Placement and DC Guidelines” on page 6–23
■
“Clock Pins Functionality” on page 6–23
■
“High-Speed I/O Interface” on page 6–24
■
“High-Speed I/O Standards Support” on page 6–28
■
“True Differential Output Buffer Feature” on page 6–35
■
“High-Speed I/O Timing” on page 6–36
■
“Design Guidelines” on page 6–37
■
“Software Overview” on page 6–38
Cyclone IV I/O Elements
Cyclone IV I/O elements (IOEs) contain a bidirectional I/O buffer and five registers
for registering input, output, output-enable signals, and complete embedded
bidirectional single-data rate transfer. I/O pins support various single-ended and
differential I/O standards.
The IOE contains one input register, two output registers, and two output-enable (OE)
registers. The two output registers and two OE registers are used for DDR
applications. You can use input registers for fast setup times and output registers for
fast clock-to-output times. Additionally, you can use OE registers for fast
clock-to-output enable timing. You can use IOEs for input, output, or bidirectional
data paths.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Element Features
6–3
Figure 6–1 shows the Cyclone IV devices IOE structure for single data rate (SDR)
operation.
Figure 6–1. Cyclone IV IOEs in a Bidirectional I/O Configuration for SDR Mode
io_clk[5..0]
Column
or Row
Interconnect
OE
OE Register
clkout
D
VCCIO
Q
Optional
PCI Clamp
ENA
ACLR
/PRN
VCCIO
oe_out
Programmable
Pull-Up
Resistor
aclr/prn
Chip-Wide Reset
Output
Pin Delay
Output Register
D
sclr/
preset
(1)
Current Strength Control
Open-Drain Out
Slew Rate Control
Q
ENA
ACLR
/PRN
data_in1
data_in0
D
clkin
oe_in
Q
Input Pin to
Input Register
Delay
or Input Pin to
Logic Array
Delay
Bus Hold
ENA
ACLR
/PRN
Input Register
Note to Figure 6–1:
(1) Tri-state control is not available for outputs configured with true differential I/O standards.
I/O Element Features
The Cyclone IV IOE offers a range of programmable features for an I/O pin. These
features increase the flexibility of I/O utilization and provide a way to reduce the
usage of external discrete components, such as pull-up resistors and diodes.
Programmable Current Strength
The output buffer for each Cyclone IV I/O pin has a programmable current strength
control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I
and II, HSTL-15 Class I and II, and HSTL-12 Class I and II I/O standards have several
levels of current strength that you can control.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–4
Chapter 6: I/O Features in Cyclone IV Devices
I/O Element Features
Table 6–2 on page 6–7 shows the possible settings for I/O standards with current
strength control. These programmable current strength settings are a valuable tool in
helping decrease the effects of simultaneously switching outputs (SSO) in conjunction
with reducing system noise. The supported settings ensure that the device driver
meets the specifications for IOH and IOL of the corresponding I/O standard.
1
When you use programmable current strength, on-chip series termination (RS OCT) is
not available.
Slew Rate Control
The output buffer for each Cyclone IV I/O pin provides optional programmable
output slew-rate control. Table 6–2 on page 6–7 shows the possible slew rate option
and the Quartus II default slew rate setting. However, these fast transitions may
introduce noise transients in the system. A slower slew rate reduces system noise, but
adds a nominal delay to rising and falling edges. Because each I/O pin has an
individual slew-rate control, you can specify the slew rate on a pin-by-pin basis. The
slew-rate control affects both the rising and falling edges. Slew rate control is available
for single-ended I/O standards with current strength of 8 mA or higher.
1
You cannot use the programmable slew rate feature when using OCT with calibration.
1
You cannot use the programmable slew rate feature when using the 3.0-V PCI,
3.0-V PCI-X, 3.3-V LVTTL, or 3.3-V LVCMOS I/O standards. Only the fast slew rate
(default) setting is available.
Open-Drain Output
Cyclone IV devices provide an optional open-drain (equivalent to an open-collector)
output for each I/O pin. This open-drain output enables the device to provide
system-level control signals (for example, interrupt and write enable signals) that are
asserted by multiple devices in your system.
Bus Hold
Each Cyclone IV device user I/O pin provides an optional bus-hold feature. The
bus-hold circuitry holds the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not necessary to hold a signal
level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input threshold
voltage in which noise can cause unintended high-frequency switching. You can select
this feature individually for each I/O pin. The bus-hold output drives no higher than
VCCIO to prevent overdriving signals.
1
If you enable the bus-hold feature, the device cannot use the programmable pull-up
option. Disable the bus-hold feature when the I/O pin is configured for differential
signals. Bus-hold circuitry is not available on dedicated clock pins.
Bus-hold circuitry is only active after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Element Features
6–5
f For the specific sustaining current for each VCCIO voltage level driven through the
resistor and for the overdrive current used to identify the next driven input level, refer
to the Cyclone IV Device Datasheet chapter.
Programmable Pull-Up Resistor
Each Cyclone IV device I/O pin provides an optional programmable pull-up resistor
while in user mode. If you enable this feature for an I/O pin, the pull-up resistor
holds the output to the VCCIO level of the output pin’s bank.
1
If you enable the programmable pull-up resistor, the device cannot use the bus-hold
feature. Programmable pull-up resistors are not supported on the dedicated
configuration, JTAG, and dedicated clock pins.
1
When the optional DEV_OE signal drives low, all I/O pins remains tri-stated even with
the programmable pull-up option enabled.
Programmable Delay
The Cyclone IV IOE includes programmable delays to ensure zero hold times,
minimize setup times, increase clock-to-output times, and delay the clock input
signal.
A path in which a pin directly drives a register may require a programmable delay to
ensure zero hold time, whereas a path in which a pin drives a register through
combinational logic may not require the delay. Programmable delays minimize setup
time. The Quartus II Compiler can program these delays to automatically minimize
setup time while providing a zero hold time. Programmable delays can increase the
register-to-pin delays for output registers. Each dual-purpose clock input pin
provides a programmable delay to the global clock networks.
Table 6–1 shows the programmable delays for Cyclone IV devices.
Table 6–1. Cyclone IV Devices Programmable Delay Chain
Programmable Delay
Quartus II Logic Option
Input pin-to-logic array delay
Input delay from pin to internal cells
Input pin-to-input register delay
Input delay from pin to input register
Output pin delay
Delay from output register to output pin
Dual-purpose clock input pin
delay
Input delay from dual-purpose clock pin to fan-out destinations
There are two paths in the IOE for an input to reach the logic array. Each of the two
paths can have a different delay. This allows you to adjust delays from the pin to the
internal logic element (LE) registers that reside in two different areas of the device.
You must set the two combinational input delays with the input delay from pin to
internal cells logic option in the Quartus II software for each path. If the pin uses the
input register, one of the delays is disregarded and the delay is set with the input
delay from pin to input register logic option in the Quartus II software.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–6
Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
The IOE registers in each I/O block share the same source for the preset or clear
features. You can program preset or clear for each individual IOE, but you cannot use
both features simultaneously. You can also program the registers to power-up high or
low after configuration is complete. If programmed to power-up low, an
asynchronous clear can control the registers. If programmed to power-up high, an
asynchronous preset can control the registers. This feature prevents the inadvertent
activation of the active-low input of another device upon power-up. If one register in
an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if
they require preset or clear. Additionally, a synchronous reset signal is available for
the IOE registers.
f For more information about the input and output pin delay settings, refer to the Area
and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
PCI-Clamp Diode
Cyclone IV devices provide an optional PCI-clamp diode enabled input and output
for each I/O pin. Dual-purpose configuration pins support the diode in user mode if
the specific pins are not used as configuration pins for the selected configuration
scheme. For example, if you are using the active serial (AS) configuration scheme, you
cannot use the clamp diode on the ASDO and nCSO pins in user mode. Dedicated
configuration pins do not support the on-chip diode.
The PCI-clamp diode is available for the following I/O standards:
■
3.3-V LVTTL
■
3.3-V LVCMOS
■
3.0-V LVTTL
■
3.0-V LVCMOS
■
2.5-V LVTTL/LVCMOS
■
PCI
■
PCI-X
If the input I/O standard is one of the listed standards, the PCI-clamp diode is
enabled by default in the Quartus II software.
OCT Support
Cyclone IV devices feature OCT to provide I/O impedance matching and termination
capabilities. OCT helps prevent reflections and maintain signal integrity while
minimizing the need for external resistors in high pin-count ball grid array (BGA)
packages. Cyclone IV devices provide I/O driver on-chip impedance matching and
RS OCT for single-ended outputs and bidirectional pins.
1
When using RS OCT, programmable current strength is not available.
There are two ways to implement OCT in Cyclone IV devices:
■
OCT with calibration
■
OCT without calibration
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
6–7
Table 6–2 lists the I/O standards that support impedance matching and series
termination.
Table 6–2. Cyclone IV Device I/O Features Support (Part 1 of 2)
IOH/IOL Current Strength
Setting (mA) (1), (9)
I/O Standard
RS OCT with
Calibration
Setting, Ohm ()
RS OCT Without
Calibration
Setting, Ohm ()
Cyclone
IV E I/O
Banks
Support
Cyclone
IV GX I/O
Banks
Support
Slew
Rate
Option
(6)
PCIclamp
Diode
Support
Column I/O
Row I/O
Column
I/O
Row
I/O (8)
Column
I/O
Row
I/O (8)
4,8
4,8
—
—
—
—
—
v
2
2
—
—
—
—
—
v
3.0-V LVTTL
4,8,12,16
4,8,12,16
50,25
50,25
50,25
50,25
3.0-V LVCMOS
4,8,12,16
4,8,12,16
50,25
50,25
50,25
50,25
3.0-V PCI/PCI-X
—
—
—
—
—
—
2.5-V
LVTTL/LVCMOS
4,8,12,16
4,8,12,16
50,25
50,25
50,25
50,25
3.3-V LVTTL
3.3-V LVCMOS
0,1,2
—
3,4,5,6,
7,8,9
v
v
v
v
1.8-V
LVTTL/LVCMOS
2,4,6,8,10,12,1 2,4,6,8,10,12,1
6
6
50,25
50,25
50,25
50,25
—
1.5-V LVCMOS
2,4,6,8,10,12,1 2,4,6,8,10,12,1
6
6
50,25
50,25
50,25
50,25
—
1,2,3,4,
5,6,7,8
4,5,6,7,
8
1.2-V LVCMOS
2,4,6,8,10,12
2,4,6,8,10
50,25
50
50,25
50
SSTL-2 Class I
8,12
8,12
50
50
50
50
SSTL-2 Class II
16
16
25
25
25
25
SSTL-18 Class I
8,10,12
8,10,12
50
50
50
50
SSTL-18 Class II
12,16
12,16
25
25
25
25
HSTL-18 Class I
8,10,12
8,10,12
50
50
50
50
HSTL-18 Class II
16
16
25
25
25
25
—
HSTL-15 Class I
8,10,12
8,10,12
50
50
50
50
—
HSTL-15 Class II
16
16
25
25
25
25
—
HSTL-12 Class I
8,10,12
8,10
50
50
50
50
HSTL-12 Class II
14
—
25
—
25
—
Differential SSTL-2
Class I (2), (7)
8,12
8,12
50
50
50
50
—
Differential SSTL-2
Class II (2), (7)
16
16
25
25
25
25
—
Differential SSTL18 (2), (7)
8,10,12
—
50
—
50
—
Differential HSTL18 (2), (7)
8,10,12
—
50
—
50
—
—
Differential HSTL15 (2), (7)
8,10,12
—
50
—
50
—
—
Differential HSTL12 (2), (7)
8,10,12
—
50
—
50
—
May 2013
Altera Corporation
—
—
0,1,2
—
—
—
3,4,5,6,
7,8,9
3,4,7,8
1,2,3,4,
5,6,7,8
3,4,7,8
—
4,5,6,7,
8
—
4,7,8
—
3,4,5,6,
7,8
0,1,2
4,7,8
Cyclone IV Device Handbook,
Volume 1
—
—
6–8
Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
Table 6–2. Cyclone IV Device I/O Features Support (Part 2 of 2)
IOH/IOL Current Strength
Setting (mA) (1), (9)
I/O Standard
BLVDS
RS OCT with
Calibration
Setting, Ohm ()
RS OCT Without
Calibration
Setting, Ohm ()
Column I/O
Row I/O
Column
I/O
Row
I/O (8)
Column
I/O
Row
I/O (8)
8,12,16
8,12,16
—
—
—
—
LVDS
(3)
—
—
—
—
—
—
PPDS
(3), (4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RSDS and miniLVDS (3), (4)
Differential LVPECL
(5)
Cyclone
IV E I/O
Banks
Support
Cyclone
IV GX I/O
Banks
Support
3,4,5,6,
7,8
1,2,3,4,
5,6,7,8
Slew
Rate
Option
(6)
PCIclamp
Diode
Support
0,1,2
—
—
—
—
—
—
—
—
—
5,6
3,4,5,6,
7,8
Notes to Table 6–2:
(1) The default current strength setting in the Quartus II software is 50- OCT without calibration for all non-voltage reference and HSTL/SSTL Class I I/O standards.
The default setting is 25- OCT without calibration for HSTL/SSTL Class II I/O standards.
(2) The differential SSTL-18 and SSTL-2, differential HSTL-18, HSTL-15, and HSTL-12 I/O standards are supported only on clock input pins and PLL output clock pins.
(3) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only for Cyclone IV E devices and right
I/O banks 5 and 6 only for Cyclone IV GX devices. Differential outputs in column I/O banks require an external resistor network.
(4) This I/O standard is supported for outputs only.
(5) This I/O standard is supported for clock inputs only
(6) The default Quartus II slew rate setting is in bold; 2 for all I/O standards that supports slew rate option.
(7) Differential SSTL-18, differential HSTL-18, HSTL-15, and HSTL-12 I/O standards do not support Class II output.
(8) Cyclone IV GX devices only support right I/O pins.
(9) Altera not only offers current strength that meets the industrial standard specification but also other additional current strengths.
1
For more details about the differential I/O standards supported in Cyclone IV I/O
banks, refer to “High-Speed I/O Interface” on page 6–24.
On-Chip Series Termination with Calibration
Cyclone IV devices support RS OCT with calibration in the top, bottom, and right I/O
banks. The RS OCT calibration circuit compares the total impedance of the I/O buffer
to the external 25- ±1% or 50- ±1% resistors connected to the RUP and RDN pins, and
dynamically adjusts the I/O buffer impedance until they match (as shown in
Figure 6–2).
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
6–9
The RS shown in Figure 6–2 is the intrinsic impedance of the transistors that make up
the I/O buffer.
Figure 6–2. Cyclone IV Devices RS OCT with Calibration
Cyclone IV Device Family
Driver Series Termination
Receiving
Device
VCCIO
RS
ZO
RS
GND
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in each of I/O banks 2, 4, 5, and 7 for Cyclone IV E devices
and I/O banks 4, 5, and 7 for Cyclone IV GX devices. Each calibration block supports
each side of the I/O banks. Because there are two I/O banks sharing the same
calibration block, both banks must have the same VCCIO if both banks enable OCT
calibration. If two related banks have different VCCIO, only the bank in which the
calibration block resides can enable OCT calibration.
Figure 6–10 on page 6–18 shows the top-level view of the OCT calibration blocks
placement.
Each calibration block comes with a pair of RUP and RDN pins. When used for
calibration, the RUP pin is connected to VCCIO through an external 25- ±1% or
50- ±1% resistor for an RS OCT value of 25  or 50  , respectively. The RDN pin is
connected to GND through an external 25- ±1% or 50- ±1% resistor for an RS OCT
value of 25  or 50  , respectively. The external resistors are compared with the
internal resistance using comparators. The resultant outputs of the comparators are
used by the OCT calibration block to dynamically adjust buffer impedance.
1
May 2013
During calibration, the resistance of the RUP and RDN pins varies.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–10
Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
Figure 6–3 shows the external calibration resistors setup on the RUP and RDN pins and
the associated OCT calibration circuitry.
Figure 6–3. Cyclone IV Devices RS OCT with Calibration Setup
Cyclone IV Device Family OCT with
Calibration with RUP and RDN pins
VCCIO
External
Calibration
Resistor
RUP
OCT
Calibration
Circuitry
VCCIO
RDN
External
Calibration
Resistor
GND
RUP and RDN pins go to a tri-state condition when calibration is completed or not
running. These two pins are dual-purpose I/Os and function as regular I/Os if you
do not use the calibration circuit.
On-Chip Series Termination Without Calibration
Cyclone IV devices support driver impedance matching to match the impedance of
the transmission line, which is typically 25 or 50 . When used with the output
drivers, OCT sets the output driver impedance to 25 or 50 . Cyclone IV devices also
support I/O driver series termination (RS = 50 ) for SSTL-2 and SSTL-18.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Standards
6–11
Figure 6–4 shows the single-ended I/O standards for OCT without calibration. The RS
shown is the intrinsic transistor impedance.
Figure 6–4. Cyclone IV Devices RS OCT Without Calibration
Cyclone IV Device
Driver Series Termination
Receiving
Device
VCCIO
RS
ZO
RS
GND
All I/O banks and I/O pins support impedance matching and series termination.
Dedicated configuration pins and JTAG pins do not support impedance matching or
series termination.
RS OCT is supported on any I/O bank. VCCIO and VREF must be compatible for all I/O
pins to enable RS OCT in a given I/O bank. I/O standards that support different RS
values can reside in the same I/O bank as long as their VCCIO and VREF do not conflict.
Impedance matching is implemented using the capabilities of the output driver and is
subject to a certain degree of variation, depending on the process, voltage, and
temperature.
f For more information about tolerance specification, refer to the Cyclone IV Device
Datasheet chapter.
I/O Standards
Cyclone IV devices support multiple single-ended and differential I/O standards.
Cyclone IV devices support 3.3-, 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-V I/O standards.
Table 6–3 summarizes I/O standards supported by Cyclone IV devices and which
I/O pins support them.
Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 1 of 3)
VCCIO Level (in V)
I/O Standard
3.3-V LVTTL,
3.3-V LVCMOS
3.0-V LVTTL,
3.0-V LVCMOS
May 2013
Type
Standard
Support
(2)
Single-ended
JESD8-B
(2)
Single-ended
JESD8-B
Altera Corporation
Input
3.3/3.0/2.5
(3)
3.3/3.0/2.5
(3)
Row I/O Pins (1)
Column I/O Pins
Output
CLK,
DQS
PLL_OUT
User
I/O
Pins
CLK,
DQS
User I/O
Pins
3.3
v
v
v
v
v
3.0
v
v
v
v
v
Cyclone IV Device Handbook,
Volume 1
6–12
Chapter 6: I/O Features in Cyclone IV Devices
I/O Standards
Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 2 of 3)
VCCIO Level (in V)
I/O Standard
Type
Standard
Support
Row I/O Pins (1)
Column I/O Pins
Output
CLK,
DQS
PLL_OUT
User
I/O
Pins
CLK,
DQS
User I/O
Pins
(3)
2.5
v
v
v
v
v
Input
2.5-V LVTTL /
LVCMOS
Single-ended
JESD8-5
1.8-V LVTTL /
LVCMOS
Single-ended
JESD8-7
1.8/1.5 (3)
1.8
v
v
v
v
v
1.5-V LVCMOS
Single-ended
JESD8-11
1.8/1.5 (3)
1.5
v
v
v
v
v
Single-ended
JESD8-12A
1.2
1.2
v
v
v
v
v
SSTL-2 Class I,
SSTL-2 Class II
voltagereferenced
JESD8-9A
2.5
2.5
v
v
v
v
v
SSTL-18 Class I,
SSTL-18 Class II
voltagereferenced
JESD815
1.8
1.8
v
v
v
v
v
HSTL-18 Class I,
HSTL-18 Class II
voltagereferenced
JESD8-6
1.8
1.8
v
v
v
v
v
HSTL-15 Class I,
HSTL-15 Class II
voltagereferenced
JESD8-6
1.5
1.5
v
v
v
v
v
HSTL-12 Class I
voltagereferenced
JESD8-16A
1.2
1.2
v
v
v
v
v
voltagereferenced
JESD8-16A
1.2
1.2
v
v
v
—
—
—
3.0
3.0
v
v
v
v
v
1.2-V LVCMOS
(4)
HSTL-12 Class II
(9)
PCI and PCI-X
Single-ended
Differential SSTL-2
Class I or Class II
Differential
Differential SSTL-18
Class I or Class II
Differential
Differential HSTL-18
Class I or Class II
Differential
Differential HSTL-15
Class I or Class II
Differential
Differential HSTL-12
Class I or Class II
Differential
(5)
(5)
(5)
(5)
(5)
JESD8-9A
JESD815
JESD8-6
JESD8-6
JESD8-16A
3.3/3.0/2.5
—
2.5
—
v
—
—
—
2.5
—
v
—
—
v
—
—
1.8
—
v
—
—
—
1.8
—
v
—
—
v
—
—
1.8
—
v
—
—
—
1.8
—
v
—
—
v
—
—
1.5
—
v
—
—
—
1.5
—
v
—
—
v
—
—
1.2
—
v
—
—
—
1.2
—
v
—
—
v
—
PPDS
(6)
Differential
—
—
2.5
—
v
v
—
v
LVDS
(10)
Differential
ANSI/TIA/
EIA-644
2.5
2.5
v
v
v
v
v
Differential
—
—
2.5
—
v
v
—
v
Differential
—
2.5
2.5
—
—
v
—
v
RSDS and
mini-LVDS
BLVDS
(8)
(6)
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
Termination Scheme for I/O Standards
6–13
Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 3 of 3)
VCCIO Level (in V)
I/O Standard
LVPECL
(7)
Type
Differential
Row I/O Pins (1)
Column I/O Pins
Standard
Support
Input
Output
CLK,
DQS
PLL_OUT
User
I/O
Pins
CLK,
DQS
User I/O
Pins
—
2.5
—
v
—
—
v
—
Notes to Table 6–3:
(1) Cyclone IV GX devices only support right I/O pins.
(2) The PCI-clamp diode must be enabled for 3.3-V/3.0-V LVTTL/LVCMOS.
(3) The Cyclone IV architecture supports the MultiVolt I/O interface feature that allows Cyclone IV devices in all packages to interface with I/O
systems that have different supply voltages.
(4) Cyclone IV GX devices do not support 1.2-V VCCIO in banks 3 and 9. I/O pins in bank 9 are dual-purpose I/O pins that are used as configuration
or GPIO pins. Configuration scheme is not support at 1.2 V, therefore bank 9 can not be powered up at 1.2-V VCCIO.
(5) Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Differential HSTL and SSTL
inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. Differential HSTL and SSTL are only
supported on CLK pins.
(6) PPDS, mini-LVDS, and RSDS are only supported on output pins.
(7) LVPECL is only supported on clock inputs.
(8) Bus LVDS (BLVDS) output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input
buffer.
(9) 1.2-V HSTL input is supported at both column and row I/Os regardless of Class I or Class II.
(10) True LVDS, RSDS, and mini-LVDS I/O standards are supported in left and right I/O pins, while emulated LVDS, RSDS, and mini-LVDS I/O
standards are supported in the top, bottom, and right I/O pins.
Cyclone IV devices support PCI and PCI-X I/O standards at 3.0-V VCCIO. The 3.0-V
PCI and PCI-X I/O are fully compatible for direct interfacing with 3.3-V PCI systems
without requiring any additional components. The 3.0-V PCI and PCI-X outputs meet
the VIH and VIL requirements of 3.3-V PCI and PCI-X inputs with sufficient noise
margin.
f For more information about the 3.3/3.0/2.5-V LVTTL & LVCMOS multivolt I/O
support, refer to AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V
LVTTL/LVCMOS I/O Systems.
Termination Scheme for I/O Standards
This section describes recommended termination schemes for voltage-referenced and
differential I/O standards.
The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS, 1.8-V
LVTTL and LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, 3.0-V PCI, and PCI-X
I/O standards do not specify a recommended termination scheme per the JEDEC
standard
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–14
Chapter 6: I/O Features in Cyclone IV Devices
Termination Scheme for I/O Standards
Voltage-Referenced I/O Standard Termination
Voltage-referenced I/O standards require an input reference voltage (VREF) and a
termination voltage (VTT). The reference voltage of the receiving device tracks the
termination voltage of the transmitting device, as shown in Figure 6–5 and Figure 6–6.
Figure 6–5. Cyclone IV Devices HSTL I/O Standard Termination
HSTL Class I
Termination
HSTL Class II
VTT
50 Ω
External
On-Board
Termination
VTT
50 Ω
50 Ω
VREF
Receiver
VTT
Cyclone IV Device
Family Series OCT
50 Ω
50 Ω
50 Ω
VREF
Transmitter
OCT with
and without
Calibration
VTT
Transmitter
Cyclone IV Device
Family Series OCT
25 Ω
50 Ω
Receiver
VTT
VTT
50 Ω
50 Ω
VREF
50 Ω
50 Ω
VREF
Transmitter
Receiver
Transmitter
Receiver
Figure 6–6. Cyclone IV Devices SSTL I/O Standard Termination
Termination
SSTL Class I
SSTL Class II
VTT
25 Ω
External
On-Board
Termination
VTT
50 Ω
50 Ω
25 Ω
50 Ω
VREF
Transmitter
Receiver
Cyclone IV Device
Family Series OCT
50 Ω
50 Ω
OCT with
and without
Calibration
50 Ω
Cyclone IV Device Handbook,
Volume 1
50 Ω
VREF
Receiver
VTT
50 Ω
VTT
50 Ω
50 Ω
VREF
Transmitter
50 Ω
Transmitter
Cyclone IV Device
Family Series OCT
25 Ω
VTT
VTT
VREF
Receiver
Transmitter
Receiver
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
Termination Scheme for I/O Standards
6–15
Differential I/O Standard Termination
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus (refer to Figure 6–7 and Figure 6–8).
Cyclone IV devices support differential SSTL-2 and SSTL-18, differential HSTL-18,
HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential LVPECL.
Figure 6–7. Cyclone IV Devices Differential HSTL I/O Standard Class I and Class II Interface and Termination
Termination
Differential HSTL Class I
VTT
50 Ω
External
On-Board
Termination
Differential HSTL Class II
VTT
VTT VTT
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
VTT
Cyclone IV Device
Family Series OCT
50 Ω
OCT
VTT VTT
50 Ω
Transmitter
Receiver
VTT
VTT
Cyclone IV Device
Family Series OCT
25 Ω
50 Ω
VTT
50 Ω
VTT
50 Ω
50Ω
50 Ω
50 Ω
50 Ω
50 Ω
Transmitter
Receiver
50 Ω
VTT
50 Ω
Transmitter
Receiver
Figure 6–8. Cyclone IV Devices Differential SSTL I/O Standard Class I and Class II Interface and Termination
Termination
Differential SSTL Class I
VTT
50 Ω
25 Ω
External
On-Board
Termination
Differential SSTL Class II
VTT VTT
VTT
50 Ω
50 Ω
VTT VTT
50 Ω
25 Ω
25 Ω
25 Ω
VTT
Cyclone IV Device
Family Series OCT
50 Ω
OCT
Transmitter
50 Ω
Transmitter
VTT
Receiver
VTT
Cyclone IV Device
Family Series OCT
25 Ω
50 Ω
VTT
50 Ω
VTT
50 Ω
50Ω
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
50 Ω
50 Ω
50Ω
Receiver
50 Ω
50 Ω
50 Ω
Transmitter
(1)
Transmitter
VTT
50 Ω
Receiver
Note to Figure 6–8:
(1) Only Differential SSTL-2 I/O standard supports Class II output.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–16
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
I/O Banks
I/O pins on Cyclone IV devices are grouped together into I/O banks. Each bank has a
separate power bus.
Cyclone IV E devices have eight I/O banks, as shown in Figure 6–9. Each device I/O
pin is associated with one I/O bank. All single-ended I/O standards are supported in
all banks except HSTL-12 Class II, which is only supported in column I/O banks. All
differential I/O standards are supported in all banks. The only exception is HSTL-12
Class II, which is only supported in column I/O banks.
Cyclone IV GX devices have up to ten I/O banks and two configuration banks, as
shown in Figure 6–10 on page 6–18 and Figure 6–11 on page 6–19. The Cyclone IV GX
configuration I/O bank contains three user I/O pins that can be used as normal user
I/O pins if they are not used in configuration modes. Each device I/O pin is
associated with one I/O bank. All single-ended I/O standards are supported except
HSTL-12 Class II, which is only supported in column I/O banks. All differential I/O
standards are supported in top, bottom, and right I/O banks. The only exception is
HSTL-12 Class II, which is only supported in column I/O banks.
The entire left side of the Cyclone IV GX devices contain dedicated high-speed
transceiver blocks for high speed serial interface applications. There are a total of 2, 4,
and 8 transceiver channels for Cyclone IV GX devices, depending on the density and
package of the device. For more information about the transceiver channels
supported, refer to Figure 6–10 on page 6–18 and Figure 6–11 on page 6–19.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
6–17
Figure 6–9 shows the overview of Cyclone IV E I/O banks.
Figure 6–9. Cyclone IV E I/O Banks
(1), (2)
I/O Bank 8
I/O Bank 7
I/O Bank 3
I/O bank with
calibration block
I/O bank without
calibration block
I/O Bank 5
I/O Bank 2
I/O Bank 1
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
Bus LVDS (7)
LVPECL (3)
SSTL-2 class I and II
SSTL-18 CLass I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II (4)
Differential SSTL-2 (5)
Differential SSTL-18 (5)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
Differential HSTL-12 (6)
I/O Bank 6
All I/O Banks Support:
Calibration block
coverage
I/O Bank 4
Notes to Figure 6–9:
(1) This is a top view of the silicon die. This is only a graphical representation. For exact pin locations, refer to the pin list and the Quartus II software.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only. External resistors
are needed for the differential outputs in column I/O banks.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output pins.
(4) The HSTL-12 Class II is supported in column I/O banks 3, 4, 7, and 8 only.
(5) The differential SSTL-18 and SSTL-2, differential HSTL-18, and HSTL-15 I/O standards are supported only on clock input pins and phase-locked
loops (PLLs) output clock pins. Differential SSTL-18, differential HSTL-18, and HSTL-15 I/O standards do not support Class II output.
(6) The differential HSTL-12 I/O standard is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 Class II is supported
only in column I/O banks 3, 4, 7, and 8.
(7) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses true LVDS input buffer.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–18
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
Figure 6–10 and Figure 6–11 show the overview of Cyclone IV GX I/O banks.
Figure 6–10. Cyclone IV GX I/O Banks for EP4CGX15, EP4CGX22, and EP4CGX30 (1),
(2), (9)
Configuration pins
VCCIO8
VCC_CLKIN8A
VCCIO7
I/O Bank 9
(11)
I/O Bank 8
I/O Bank
8A (10)
I/O Bank 7
Right, Top, and Bottom Banks Support:
I/O Bank 3
VCCIO3
Configuration pins
I/O Bank
3A (10)
VCC_CLKIN3A
I/O Bank
3B (12)
VCC_CLKIN3B
I/O Bank 6
VCCIO6
I/O bank with
calibration block
I/O bank without
calibration block
I/O Bank 5
PCIe hard IP x1, x2, and x4
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
Bus LVDS (7)
LVPECL (3)
SSTL-2 class I and II
SSTL-18 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II (4)
Differential SSTL-2 (5)
Differential SSTL-18 (5)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
Differential HSTL-12 (6)
3.0-V PCI/PCI-X (8)
Channel 0
Channel 1
Channel 2
Channel 3
Configuration
pins
VCCIO9
Calibration block
coverage
VCCIO5
I/O Bank 4
VCCIO4
Notes to Figure 6–10:
(1) This is a top view of the silicon die. For exact pin locations, refer to the pin list and the Quartus II software. Channels 2 and 3 are not available in
EP4CGX15 and F169 package type in EP4CGX22 and EP4CGX30 devices.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 5 and 6 only. External resistors are
needed for the differential outputs in column I/O banks.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output pins.
(4) The HSTL-12 Class II is supported in column I/O banks 4, 7, and 8.
(5) The differential SSTL-18 and SSTL-2, differential HSTL-18, and HSTL-15 I/O standards are supported only on clock input pins and phase-locked
loops (PLLs) output clock pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and
HSTL-12 I/O standards.
(6) The differential HSTL-12 I/O standard is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 Class II is supported
only in column I/O banks 4, 7, and 8.
(7) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses the LVDS input buffer.
(8) The PCI-X I/O standard does not meet the IV curve requirement at the linear region.
(9) The OCT block is located in the shaded banks 4, 5, and 7.
(10) There are two dedicated clock input I/O banks (I/O bank 3A and I/O bank 8A) that can be used for either high-speed serial interface (HSSI) input
reference clock pins or clock input pins.
(11) There are dual-purpose I/O pins in bank 9. If input pins with VREF I/O standards are used on these dual-purpose I/O pins during user mode, they
share the VREF pin in bank 8.These dual-purpose IO pins in bank 9 when used in user mode also support RS OCT without calibration and they
share the OCT block with bank 8.
(12) There are four dedicated clock input in I/O bank 3B for the EP4CGX30F484 device that can be used for either HSSI input reference clock pins or
clock input pins.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
6–19
Figure 6–11. Cyclone IV GX I/O Banks for EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 (1),
VCCIO9 VCC_CLKIN8B VCCIO8 VCC_CLKIN8A
I/O Bank 9
I/O Bank
I/O Bank 8B
I/O Bank 8
8A (10)
(10), (11)
Ch3
PCIe hard IP x1, x2, and x4
Config I/O Bank 3B
I/O Bank
I/O Bank 3
(10), (11)
pins
3A (10)
VCCIO3
VCC_CLKIN3B VCCIO3 VCC_CLKIN3A
I/O Bank 6
Ch2
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
Bus LVDS (7)
LVPECL (3)
SSTL-2 class I and II
SSTL-18 CLass I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II (4)
Differential SSTL-2 (5)
Differential SSTL-18 (5)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
Differential HSTL-12 (6)
3.0-V PCI/PCI-X (8)
Ch1
GXBL1
I/O Bank 7
Right, Top, and Bottom Banks Support:
Ch0
Ch3
Ch2
GXBL0
Ch1
Ch0
VCCIO7
VCCIO6
I/O bank with
calibration block
I/O bank without
calibration block
I/O Bank 5
Configuration
pins
(2), (9)
Calibration block
coverage
VCCIO5
I/O Bank 4
VCCIO4
Notes to Figure 6–11:
(1) This is a top view of the silicon die. For exact pin locations, refer to the pin list and the Quartus II software.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 5 and 6 only. External resistors are
needed for the differential outputs in column I/O banks.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output pins.
(4) The HSTL-12 Class II is supported in column I/O banks 4, 7, and 8.
(5) The differential SSTL-18 and SSTL-2, differential HSTL-18, and HSTL-15 I/O standards are supported only on clock input pins and phase-locked
loops (PLLs) output clock pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and
HSTL-12 I/O standards.
(6) The differential HSTL-12 I/O standard is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 Class II is supported
only in column I/O banks 4, 7, and 8.
(7) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses the LVDS input buffer.
(8) The PCI-X I/O standard does not meet the IV curve requirement at the linear region.
(9) The OCT block is located in the shaded banks 4, 5, and 7.
(10) The dedicated clock input I/O banks 3A, 3B, 8A, and 8B can be used either for HSSI input reference clock pins or clock input pins.
(11) Single-ended clock input support is available for dedicated clock input I/O banks 3B and 8B.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
1
6–20
Cyclone IV Device Handbook,
Volume 1
Each Cyclone IV I/O bank has a VREF bus to accommodate voltage-referenced I/O standards. Each VREF pin is the reference
source for its VREF group. If you use a VREF group for voltage-referenced I/O standards, connect the VREF pin for that group to
the appropriate voltage level. If you do not use all the VREF groups in the I/O bank for voltage-referenced I/O standards, you
can use the VREF pin in the unused voltage-referenced groups as regular I/O pins. For example, if you have SSTL-2 Class I
input pins in I/O bank 1 and they are all placed in the VREFB1N[0] group, VREFB1N[0] must be powered with 1.25 V, and the
remaining VREFB1N[1..3] pins (if available) are used as I/O pins. If multiple VREF groups are used in the same I/O bank, the
VREF pins must all be powered by the same voltage level because the VREF pins are shorted together within the same I/O bank.
When VREF pins are used as regular I/Os, they have higher pin capacitance than regular user I/O pins. This has an impact on
the timing if the pins are used as inputs and outputs.
f For more information about VREF pin capacitance, refer to the pin capacitance section in the Cyclone IV Device Datasheet chapter.
f For information about how to identify VREF groups, refer to the Cyclone IV Device Pin-Out files or the Quartus II Pin Planner
tool.
Table 6–4 and Table 6–5 summarize the number of VREF pins in each I/O bank for the Cyclone IV device family.
EP4CE115
164-MBGA
256-MBGA
256-UBGA
256-FBGA
484-FBGA
144-EQPF
256-UBGA
256-FBGA
324-FBGA
484-FBGA
780-FBGA
324-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-FBGA
780-FBGA
EP4CE75
144-EQPF
EP4CE55
256-FBGA
EP4CE40
256-UBGA
EP4CE30
144-EQPF
EP4CE22
256-FBGA
EP4CE15
256-UBGA
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
2
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
3
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
4
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
5
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
6
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
7
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
I/O
Bank
(1)
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
144-EQPF
Device
EP4CE6
EP4CE10
Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices (Part 1 of 2)
EP4CE115
164-MBGA
256-MBGA
256-UBGA
256-FBGA
484-FBGA
144-EQPF
256-UBGA
256-FBGA
324-FBGA
484-FBGA
780-FBGA
324-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-FBGA
780-FBGA
EP4CE75
144-EQPF
EP4CE55
256-FBGA
EP4CE40
256-UBGA
EP4CE30
144-EQPF
EP4CE22
256-FBGA
EP4CE15
EP4CE10
EP4CE6
256-UBGA
(1)
144-EQPF
Device
Altera Corporation
I/O
Bank
(Part 2 of 2)
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
4
4
4
4
4
4
4
2
2
2
3
3
3
3
3
8
Note to Table 6–4:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
May 2013
Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices
Table 6–5. Number of VREF Pins Per I/O Bank for Cyclone IV GX Devices
3
1
1
1
3
3
3
3
3
4
1
1
1
3
3
3
3
3
5
1
1
1
3
3
3
3
3
6
1
1
1
3
3
3
3
3
7
1
1
1
3
3
3
3
3
8 (2)
1
1
1
3
3
3
3
3
896-FBGA
672-FBGA
484-FBGA
4CGX150
896-FBGA
672-FBGA
4CGX110
484-FBGA
672-FBGA
4CGX75
484-FBGA
672-FBGA
484-FBGA
4CGX50
484-FBGA
324-FBGA
4CGX30
169-FBGA
324-FBGA
4CGX22
169-FBGA
(1)
169-FBGA
I/O Bank
4CGX15
148- QFN
Device
Notes to Table 6–5:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
Each Cyclone IV I/O bank has its own VCCIO pins. Each I/O bank can support only one VCCIO setting from among 1.2, 1.5, 1.8,
2.5, 3.0, or 3.3 V. Any number of supported single-ended or differential standards can be simultaneously supported in a single
I/O bank, as long as they use the same VCCIO levels for input and output pins.
6–21
Cyclone IV Device Handbook,
Volume 1
(2) Bank 9 does not have VREF pin. If input pins with VREF I/O standards are used in bank 9 during user mode, it shares the VREF pin in bank 8.
6–22
Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
When designing LVTTL/LVCMOS inputs with Cyclone IV devices, refer to the
following guidelines:
■
All pins accept input voltage (VI) up to a maximum limit (3.6 V), as stated in the
recommended operating conditions provided in the Cyclone IV Device Datasheet
chapter.
■
Whenever the input level is higher than the bank VCCIO, expect higher leakage
current.
■
The LVTTL/LVCMOS I/O standard input pins can only meet the VIH and VIL
levels according to bank voltage level.
Voltage-referenced standards are supported in an I/O bank using any number of
single-ended or differential standards, as long as they use the same VREF and VCCIO
values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your
Cyclone IV devices, I/O pins using these standards—because they require different
VREF values—must be in different banks from each other. However, the same I/O
bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to 2.5 V and the VREF
set to 1.25 V.
1
When using Cyclone IV devices as a receiver in 3.3-, 3.0-, or 2.5-V LVTTL/LVCMOS
systems, you are responsible for managing overshoot or undershoot to stay in the
absolute maximum ratings and the recommended operating conditions, provided in
the Cyclone IV Device Datasheet chapter.
1
The PCI clamping diode is enabled by default in the Quartus II software for input
signals with bank VCCIO at 2.5, 3.0, or 3.3 V.
High-Speed Differential Interfaces
Cyclone IV devices can send and receive data through LVDS signals. For the LVDS
transmitter and receiver, the input and output pins of Cyclone IV devices support
serialization and deserialization through internal logic.
The BLVDS extends the benefits of LVDS to multipoint applications such as
bidirectional backplanes. The loading effect and the need to terminate the bus at both
ends for multipoint applications require BLVDS to drive out a higher current than
LVDS to produce a comparable voltage swing. All the I/O banks of Cyclone IV
devices support BLVDS for user I/O pins.
The RSDS and mini-LVDS standards are derivatives of the LVDS standard. The RSDS
and mini-LVDS I/O standards are similar in electrical characteristics to LVDS, but
have a smaller voltage swing and therefore provide increased power benefits and
reduced electromagnetic interference (EMI).
The PPDS standard is the next generation of the RSDS standard introduced by
National Semiconductor Corporation. Cyclone IV devices meet the National
Semiconductor Corporation PPDS Interface Specification and support the PPDS
standard for outputs only. All the I/O banks of Cyclone IV devices support the PPDS
standard for output pins only.
The LVDS standard does not require an input reference voltage, but it does require a
100- termination resistor between the two signals at the input buffer. An external
resistor network is required on the transmitter side for the top and bottom I/O banks.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
Pad Placement and DC Guidelines
6–23
External Memory Interfacing
Cyclone IV devices support I/O standards required to interface with a broad range of
external memory interfaces, such as DDR SDRAM, DDR2 SDRAM, and QDR II
SRAM.
f For more information about Cyclone IV devices external memory interface support,
refer to the External Memory Interfaces in Cyclone IV Devices chapter.
Pad Placement and DC Guidelines
You can use the Quartus II software to validate your pad and pin placement.
Pad Placement
Altera recommends that you create a Quartus II design, enter your device I/O
assignments and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules depend on device
density, package, I/O assignments, voltage assignments and other factors that are not
fully described in this chapter.
f For more information about how the Quartus II software checks I/O restrictions, refer
to the I/O Management chapter in volume 2 of the Quartus II Handbook.
DC Guidelines
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Clock Pins Functionality
Cyclone IV clock pins have multiple purposes, as per listed:
May 2013
■
CLK pins—Input support for single-ended and voltage-referenced standards. For
I/O standard support, refer to Table 6–3 on page 6–11.
■
DIFFCLK pins—Input support for differential standards. For I/O standard support,
refer to Table 6–3 on page 6–11. When used as DIFFCLK pins, DC or AC coupling
can be used depending on the interface requirements and external termination is
required. For more information, refer to “High-Speed I/O Standards Support” on
page 6–28.
■
REFCLK pins—Input support for high speed differential reference clocks used by
the transceivers in Cyclone IV GX devices. For I/O support, coupling, and
termination requirements, refer to Table 6–10 on page 6–29.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–24
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
High-Speed I/O Interface
Cyclone IV E I/Os are separated into eight I/O banks, as shown in Figure 6–9 on
page 6–17. Cyclone IV GX I/Os are separated into six user I/O banks with the left
side of the device as the transceiver block, as shown in Figure 6–10 on page 6–18. Each
bank has an independent power supply. True output drivers for LVDS, RSDS,
mini-LVDS, and PPDS are on the right I/O banks. On the Cyclone IV E row I/O banks
and the Cyclone IV GX right I/O banks, some of the differential pin pairs (p and n
pins) of the true output drivers are not located on adjacent pins. In these cases, a
power pin is located between the p and n pins. These I/O standards are also
supported on all I/O banks using two single-ended output with the second output
programmed as inverted, and an external resistor network. True input buffers for
these I/O standards are supported on the top, bottom, and right I/O banks except for
I/O bank 9.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
6–25
Table 6–6 and Table 6–7 summarize which I/O banks support these I/O standards in
the Cyclone IV device family.
Table 6–6. Differential I/O Standards Supported in Cyclone IV E I/O Banks
Differential I/O Standards
LVDS
RSDS
mini-LVDS
PPDS
BLVDS
LVPECL
(1)
(2)
I/O Bank Location
External Resistor
Network at Transmitter
1,2,5,6
Not Required
All
Three Resistors
1,2,5,6
Not Required
3,4,7,8
Three Resistors
All
Single Resistor
1,2,5,6
Not Required
All
Three Resistors
1,2,5,6
Not Required
All
Three Resistors
All
All
Transmitter (TX)
Receiver (RX)
v
v
v
—
v
—
v
—
Single Resistor
v
v
—
—
v
All
—
v
v
Differential SSTL-18
(3)
All
—
v
v
Differential HSTL-18
(3)
All
—
v
v
Differential HSTL-15
(3)
All
—
v
v
Differential HSTL-12
(3), (4)
All
—
v
v
Differential SSTL-2
(3)
Notes to Table 6–6:
(1) Transmitter and Receiver fMAX depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(4) Differential HSTL-12 Class II is supported only in column I/O banks.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–26
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks
Differential I/O Standards
LVDS
RSDS
mini-LVDS
PPDS
BLVDS
LVPECL
(1)
(2)
I/O Bank Location
External Resistor
Network at
Transmitter
Transmitter (TX)
Receiver (RX)
v
v
v
—
v
—
v
—
5,6
Not Required
3,4,5,6,7,8
Three Resistors
5,6
Not Required
3,4,7,8
Three Resistors
3,4,5,6,7,8
Single Resistor
5,6
Not Required
3,4,5,6,7,8
Three Resistors
5,6
Not Required
3,4,5,6,7,8
Three Resistors
3,4,5,6,7,8
Single Resistor
v
v
3,4,5,6,7,8
—
—
v
3,4,5,6,7,8
—
v
v
Differential SSTL-18
(3)
3,4,5,6,7,8
—
v
v
Differential HSTL-18
(3)
3,4,5,6,7,8
—
v
v
Differential HSTL-15
(3)
3,4,5,6,7,8
—
v
v
Differential HSTL-12
(3)
4,5,6,7,8
—
v
v
Differential SSTL-2
(3)
Notes to Table 6–7:
(1) Transmitter and Receiver fMAX depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
You can use I/O pins and internal logic to implement a high-speed differential
interface in Cyclone IV devices. Cyclone IV devices do not contain dedicated
serialization or deserialization circuitry. Therefore, shift registers, internal
phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel
conversions on incoming data and parallel-to-serial conversion on outgoing data. The
differential interface data serializers and deserializers (SERDES) are automatically
constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS
megafunction.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
EP4CE115
144-EQPF
164-MBGA
256-MBGA
256-UBGA
256-FBGA
484-FBGA
144-EQPF
256-UBGA
256-FBGA
324-FBGA
484-FBGA
780-FBGA
324-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-UBGA
484-FBGA
780-FBGA
484-FBGA
780-FBGA
EP4CE75
256-FBGA
EP4CE55
256-UBGA
EP4CE40
144-EQPF
EP4CE30
256-FBGA
EP4CE22
256-UBGA
EP4CE15
EP4CE10
EP4CE6
144-EQPF
Device
Numbers of Differential
Channels (1), (2)
Altera Corporation
Table 6–8. Cyclone IV E I/O and Differential Channel Count
User
I/O (3)
91
179
179
91
179
179
81
89
165
165
165
343
79
153
153
193
328
532
193
328
328
532
324
324
374
292
292
426
280
528
User I/O
Banks
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6)
8
23
23
8
23
23
6
8
21
21
21
67
7
20
20
30
60
112
30
60
60
112
62
62
70
54
54
79
50
103
Emulated
LVDS (5), (
13
43
43
13
43
43
12
13
32
32
32
70
10
32
32
38
64
112
38
64
64
112
70
70
90
56
56
99
53
127
LVDS (4), (
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
May 2013
Table 6–8 and Table 6–9 summarize the total number of supported row and column differential channels in the Cyclone IV
device family.
6)
Notes to Table 6–8:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) For differential pad placement guidelines, refer to “Pad Placement” on page 6–23.
(3) The I/O pin count includes all GPIOs, dedicated clock pins, and dual-purpose configuration pins. Dedicated configuration pins are not included in the pin count.
(4) The true LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in row I/O banks 1, 2, 5, and 6.
(5) The emulated LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in column I/O banks 3, 4, 7, and 8.
6–27
Cyclone IV Device Handbook,
Volume 1
(6) LVDS input and output buffers are sharing the same p and n pins. One LVDS I/O channel can only be either transmitter or receiver at a time.
6–28
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
Table 6–9. Cyclone IV GX I/O, Differential, and XCVRs Channel Count
9 (4)
9 (4)
9 (4)
9 (4)
9 (4)
LVDS
(7), (9)
896-FBGA
9 (4)
672-FBGA
User I/O
banks
484-FBGA
150
896-FBGA
72
672-FBGA
150
484-FBGA
72
4CGX150
672-FBGA
324-FBGA
72
4CGX110
484-FBGA
169-FBGA
72
4CGX75
672-FBGA
324-FBGA
User I/O (3)
(1), (2)
4CGX50
484-FBGA
169-FBGA
4CGX30
169-FBGA
4CGX22
148- QFN
Numbers of
Differential
Channels
4CGX15
484-FBGA
Device
290
290
310
290
310
270
393
475
270
393
475
11
11
11
11
11
11
11
11
11
11
(5)
(5),
(5),
(5),
(5),
(5),
(5),
(5),
(5),
(5),
(5),
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
11
9
9
9
16
9
16
45
45
51
45
51
38
52
63
38
52
63
Emulated
LVDS (8), (9)
16
16
16
48
16
48
85
85
89
85
89
82
129
157
82
129
157
XCVRs
2
2
2
4
2
4
4
4
8
4
8
4
8
8
4
8
8
Notes to Table 6–9:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as outputs only.
(2) For differential pad placement guidelines, refer to “Pad Placement” on page 6–23.
(3) The I/O pin count includes all GPIOs, dedicated clock pins, and dual-purpose configuration pins. Transceivers pins and dedicated configuration pins are not
included in the pin count.
(4) Includes one configuration I/O bank and two dedicated clock input I/O banks for HSSI input reference clock.
(5) Includes one configuration I/O bank and four dedicated clock input I/O banks for HSSI input reference clock.
(6) Single-ended clock input support is available for dedicated clock input I/O banks 3B (pins CLKIO20 and CLKIO22) and 8B (pins CLKIO17 and CLKIO19).
(7) The true LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in right I/O banks 5 and 6.
(8) The emulated LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in column I/O banks 3, 4, 7, and 8.
(9) LVDS input and output buffers are sharing the same p and n pins. One LVDS I/O channel can only be either transmitter or receiver at a time.
High-Speed I/O Standards Support
This section provides information about the high-speed I/O standards and the HSSI
input reference clock supported in Cyclone IV devices.
High Speed Serial Interface (HSSI) Input Reference Clock Support
Cyclone IV GX devices support the same I/O features for GPIOs with additional new
features where current I/O banks 3A and 8A consist of dual-purpose clock input pins
(CLKIN) and 3B and 8B consist of dedicated CLKIN that can be used to support the highspeed transceiver input reference clock (REFCLK) features on top of the
general-purpose clock input function.
The EP4CGX15, EP4CGX22, and EP4CGX30 devices contain two pairs of
CLKIN/REFCLK pins located in I/O banks 3A and 8A. I/O banks 3B and 8B are not
available in EP4CGX15, EP4CGX22, and EP4CGX30 devices. The EP4CGX50,
EP4CGX75, EP4CGX110, and EP4CGX150 devices have a total of four pairs of
CLKIN/REFCLK pins located in I/O banks 3A, 3B, 8A, and 8B. I/O banks 3B and 8B can
also support single-ended clock inputs. For more information about the CLKIN/REFCLK
pin location, refer to Figure 6–10 on page 6–18 and Figure 6–11 on page 6–19.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
6–29
The CLKIN/REFCLK pins are powered by dedicated VCC_CLKIN3A, VCC_CLKIN3B,
VCC_CLKIN8A, and VCC_CLKIN8B power supplies separately in their respective I/O banks
to avoid the different power level requirements in the same bank for GPIO.
Table 6–10. Cyclone IV GX HSSI REFCLK I/O Standard Support Using GPIO CLKIN Pins (1),
(2)
VCC_CLKIN Level
I/O Standard
HSSI Protocol
LVDS
All
LVPECL
All
Differential
AC (Need
off chip
resistor to
restore
VCM)
All
1.2V, 1.5V,
3.3V PCML
Coupling
All
All
HCSL
PCIe
Differential
DC
Termination
I/O Pin Type
Input
Output
Column
I/O
Row
I/O
Supported I/O
Banks
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Off chip
2.5V
Not
supported
Yes
No
3A, 3B, 8A, 8B
Notes to Table 6–10:
(1) The EP4CGX15, EP4CGX22, and EP4CGX30 devices have two pairs of dedicated clock input pins in banks 3A and 8A for HSSI input reference
clock. I/O banks 3B and 8B are not available in EP4CGX15, EP4CGX22, and EP4CGX30 devices.
(2) The EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices have four pairs of dedicated clock input pins in banks 3A, 3B, 8A, and 8B
for HSSI input or single-ended clock input.
f For more information about the AC-coupled termination scheme for the HSSI
reference clock, refer to the Cyclone IV Transceivers Architecture chapter.
LVDS I/O Standard Support in Cyclone IV Devices
The LVDS I/O standard is a high-speed, low-voltage swing, low power, and GPIO
interface standard. Cyclone IV devices meet the ANSI/TIA/EIA-644 standard with
the following exceptions:
■
The maximum differential output voltage (VOD) is increased to 600 mV. The
maximum VOD for ANSI specification is 450 mV.
■
The input voltage range is reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V, or
0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644
specification supports an input voltage range of 0 V to 2.4 V.
f For LVDS I/O standard electrical specifications in Cyclone IV devices, refer to the
Cyclone IV Device Datasheet chapter.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–30
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
Designing with LVDS
Cyclone IV I/O banks support the LVDS I/O standard. The Cyclone IV GX right I/O
banks support true LVDS transmitters while the Cyclone IV E left and right I/O banks
support true LVDS transmitters. On the top and bottom I/O banks, the emulated
LVDS transmitters are supported using two single-ended output buffers with external
resistors. One of the single-ended output buffers is programmed to have opposite
polarity. The LVDS receiver requires an external 100- termination resistor between
the two signals at the input buffer.
Figure 6–12 shows a point-to-point LVDS interface using Cyclone IV devices true
LVDS output and input buffers.
Figure 6–12. Cyclone IV Devices LVDS Interface with True Output Buffer on the Right I/O Banks
Cyclone IV Device
Transmitting Device
txout +
txout +
rxin +
100 Ω
50 Ω
txout -
rxin -
100 Ω
50 Ω
txout -
Input Buffer
Receiving Device
rxin +
50 Ω
Cyclone IV
Device
Family Logic
Array
50 Ω
rxin -
Output Buffer
Figure 6–13 shows a point-to-point LVDS interface with Cyclone IV devices LVDS
using two single-ended output buffers and external resistors.
Figure 6–13. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks
(1)
Cyclone IV Device
Emulated
LVDS Transmitter
LVDS Receiver
Resistor Network
RS
50 Ω
RP
100 Ω
50 Ω
RS
Note to Figure 6–13:
(1) RS = 120 . RP = 170 .
BLVDS I/O Standard Support in Cyclone IV Devices
The BLVDS I/O standard is a high-speed differential data transmission technology
that extends the benefits of standard point-to-point LVDS to multipoint configuration
that supports bidirectional half-duplex communication. BLVDS differs from standard
LVDS by providing a higher drive to achieve similar signal swings at the receiver
while loaded with two terminations at both ends of the bus.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
6–31
Figure 6–14 shows a typical BLVDS topology with multiple transmitter and receiver
pairs.
Figure 6–14. BLVDS Topology with Cyclone IV Devices Transmitters and Receivers
VCC
VCC
100 kΩ
100 kΩ
50 Ω
50 Ω
50 Ω
50 Ω
RT
RT
50 Ω
50 Ω
50 Ω
50 Ω
100 k Ω
50 Ω
RS
50 Ω
Input
Data
OE
RS
50 Ω
OE
Output
Data
GND
Output
Data
Input
Data
Cyclone IV Device Family
Input
Data
Cyclone IV Device Family
Output
Data
Cyclone IV Device Family
RS
RS
OE
RS
GND
RS
50 Ω
50 Ω
50 Ω
100 kΩ
The BLVDS I/O standard is supported on the top, bottom, and right I/O banks of
Cyclone IV devices. The BLVDS transmitter uses two single-ended output buffers
with the second output buffer programmed as inverted, while the BLVDS receiver
uses a true LVDS input buffer. The transmitter and receiver share the same pins. An
output-enabled (OE) signal is required to tristate the output buffers when the LVDS
input buffer receives a signal.
f For more information, refer to the Cyclone IV Device Datasheet chapter.
Designing with BLVDS
The BLVDS bidirectional communication requires termination at both ends of the bus
in BLVDS. The termination resistor (RT) must match the bus differential impedance,
which in turn depends on the loading on the bus. Increasing the load decreases the
bus differential impedance. With termination at both ends of the bus, termination is
not required between the two signals at the input buffer. A single series resistor (RS) is
required at the output buffer to match the output buffer impedance to the
transmission line impedance. However, this series resistor affects the voltage swing at
the input buffer. The maximum data rate achievable depends on many factors.
1
Altera recommends that you perform simulation using the IBIS model while
considering factors such as bus loading, termination values, and output and input
buffer location on the bus to ensure that the required performance is achieved.
f For more information about BLVDS interface support in Altera devices, refer to
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–32
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
RSDS, Mini-LVDS, and PPDS I/O Standard Support in Cyclone IV Devices
The RSDS, mini-LVDS, and PPDS I/O standards are used in chip-to-chip applications
between the timing controller and the column drivers on the display panels such as
LCD monitor panels and LCD televisions. Cyclone IV devices meet the National
Semiconductor Corporation RSDS Interface Specification, Texas Instruments
mini-LVDS Interface Specification, and National Semiconductor Corporation PPDS
Interface Specification to support RSDS, mini-LVDS and PPDS output standards,
respectively.
f For Cyclone IV devices RSDS, mini-LVDS, and PPDS output electrical specifications,
refer to the Cyclone IV Device Datasheet chapter.
f For more information about the RSDS I/O standard, refer to the RSDS specification
from the National Semiconductor website (www.national.com).
Designing with RSDS, Mini-LVDS, and PPDS
Cyclone IV I/O banks support RSDS, mini-LVDS, and PPDS output standards. The
right I/O banks support true RSDS, mini-LVDS, and PPDS transmitters. On the top
and bottom I/O banks, RSDS, mini-LVDS, and PPDS transmitters are supported using
two single-ended output buffers with external resistors. The two single-ended output
buffers are programmed to have opposite polarity.
Figure 6–15 shows an RSDS, mini-LVDS, or PPDS interface with a true output buffer.
Figure 6–15. Cyclone IV Devices RSDS, Mini-LVDS, or PPDS Interface with True Output Buffer on
the Right I/O Banks
Cyclone IV Device
True RSDS, Mini-LVDS,
or PPDS Transmitter
RSDS, Mini-LVDS,
or PPDS Receiver
50 Ω
100 Ω
50 Ω
Figure 6–16 shows an RSDS, mini-LVDS, or PPDS interface with two single-ended
output buffers and external resistors.
Figure 6–16. RSDS, Mini-LVDS, or PPDS Interface with External Resistor Network on the Top and
Bottom I/O Banks (1)
Cyclone IV Device
Emulated RSDS,
Mini-LVDS, or PPDS
Transmitter
Resistor Network
RSDS, Mini-LVDS,
or PPDS Receiver
RS
50 Ω
100 Ω
RP
50 Ω
RS
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
6–33
Figure 6–16. RSDS, Mini-LVDS, or PPDS Interface with External Resistor Network on the Top and
Bottom I/O Banks (1)
Note to Figure 6–16:
(1) RS and RP values are pending characterization.
A resistor network is required to attenuate the output voltage swing to meet RSDS,
mini-LVDS, and PPDS specifications when using emulated transmitters. You can
modify the resistor network values to reduce power or improve the noise margin.
The resistor values chosen must satisfy Equation 6–1.
Equation 6–1. Resistor Network
RP
R S  ------2
-------------------- = 50 
RP
R S + ------2
1
Altera recommends that you perform simulations using Cyclone IV devices IBIS
models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS
requirements.
It is possible to use a single external resistor instead of using three resistors in the
resistor network for an RSDS interface, as shown in Figure 6–17. The external
single-resistor solution reduces the external resistor count while still achieving the
required signaling level for RSDS. However, the performance of the single-resistor
solution is lower than the performance with the three-resistor network.
Figure 6–17 shows the RSDS interface with a single resistor network on the top and
bottom I/O banks.
Figure 6–17. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
(1)
Cyclone IV Device
Emulated
RSDS Transmitter
Single Resistor Network
RSDS Receiver
50 Ω
100 Ω
RP
50 Ω
Note to Figure 6–17:
(1) RP value is pending characterization.
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–34
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
LVPECL I/O Support in Cyclone IV Devices
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
VCCIO. This standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. Cyclone IV
devices support the LVPECL input standard at the dedicated clock input pins only.
The LVPECL receiver requires an external 100- termination resistor between the two
signals at the input buffer.
f For the LVPECL I/O standard electrical specification, refer to the Cyclone IV Device
Datasheet chapter.
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone IV devices LVPECL input common mode voltage.
Figure 6–18 shows the AC-coupled termination scheme. The 50- resistors used at the
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone IV devices LVPECL input buffer
specification (refer to Figure 6–19).
Figure 6–18. LVPECL AC-Coupled Termination (1)
LVPECL
Transmitter
Cyclone IV Device
LVPECL Receiver
0.1 µF
Z0 = 50 Ω
Z0 = 50 Ω
VICM
50 Ω
50 Ω
0.1 µF
Note to Figure 6–18:
(1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA transmitter is used.
Figure 6–19 shows the LVPECL DC-coupled termination.
Figure 6–19. LVPECL DC-Coupled Termination (1)
Cyclone IV Device
LVPECL Receiver
LVPECL Transmitter
50 Ω
100 Ω
50 Ω
Note to Figure 6–19:
(1) The LVPECL DC-coupled termination is applicable only when an Altera FPGA transmitter is used.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
True Differential Output Buffer Feature
6–35
Differential SSTL I/O Standard Support in Cyclone IV Devices
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. Cyclone IV devices support differential
SSTL-2 and SSTL-18 I/O standards. The differential SSTL output standard is only
supported at PLL#_CLKOUT pins using two single-ended SSTL output buffers
(PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output programmed to have
opposite polarity. The differential SSTL input standard is supported on the GCLK
pins only, treating differential inputs as two single-ended SSTL and only decoding
one of them.
The differential SSTL I/O standard requires two differential inputs with an external
reference voltage (VREF) as well as an external termination voltage (VTT) of 0.5 × VCCIO
to which termination resistors are connected.
f For differential SSTL electrical specifications, refer to “Differential I/O Standard
Termination” on page 6–15 and the Cyclone IV Device Datasheet chapter.
1
Figure 6–8 on page 6–15 shows the differential SSTL Class I and Class II interface.
Differential HSTL I/O Standard Support in Cyclone IV Devices
The differential HSTL I/O standard is used for the applications designed to operate in
0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic switching range. Cyclone IV
devices support differential HSTL-18, HSTL-15, and HSTL-12 I/O standards. The
differential HSTL input standard is available on GCLK pins only, treating the
differential inputs as two single-ended HSTL and only decoding one of them. The
differential HSTL output standard is only supported at the PLL#_CLKOUT pins using
two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the
second output programmed to have opposite polarity.
The differential HSTL I/O standard requires two differential inputs with an external
reference voltage (VREF), as well as an external termination voltage (VTT) of 0.5 × VCCIO
to which termination resistors are connected.
f For differential HSTL signaling characteristics, refer to “Differential I/O Standard
Termination” on page 6–15 and the Cyclone IV Device Datasheet chapter.
1
Figure 6–7 on page 6–15 shows the differential HSTL Class I and Class II interface.
True Differential Output Buffer Feature
Cyclone IV devices true differential transmitters offer programmable
pre-emphasis—you can turn it on or off. The default setting is on.
Programmable Pre-Emphasis
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependant attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the VOD specification and the output impedance of the
transmitter. At high frequency, the slew rate may not be fast enough to reach full VOD
May 2013
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–36
Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Timing
before the next edge; this may lead to pattern-dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
The Quartus II software allows two settings for programmable pre-emphasis
control—0 and 1, in which 0 is pre-emphasis off and 1 is pre-emphasis on. The default
setting is 1. The amount of pre-emphasis needed depends on the amplification of the
high-frequency components along the transmission line. You must adjust the setting
to suit your designs, as pre-emphasis decreases the amplitude of the low-frequency
component of the output signal.
Figure 6–20 shows the differential output signal with pre-emphasis.
Figure 6–20. The Output Signal with Pre-Emphasis
Overshoot
Positive channel (p)
VOD
Negative channel (n)
Undershoot
High-Speed I/O Timing
This section discusses the timing budget, waveforms, and specifications for
source-synchronous signaling in Cyclone IV devices. Timing for source-synchronous
signaling is based on skew between the data and clock signals.
High-speed differential data transmission requires timing parameters provided by IC
vendors and requires you to consider the board skew, cable skew, and clock jitter. This
section provides information about high-speed I/O standards timing parameters in
Cyclone IV devices.
Table 6–11 defines the parameters of the timing diagram shown in Figure 6–21.
Table 6–11. High-Speed I/O Timing Definitions (Part 1 of 2)
Parameter
Symbol
Description
TCCS
The timing difference between the fastest and slowest output
edges, including tCO variation and clock skew. The clock is
included in the TCCS measurement.
Sampling window
SW
The period of time during which the data must be valid in order for
you to capture it correctly. The setup and hold times determine
the ideal strobe position in the sampling window.
TSW = TSU + Thd + PLL jitter.
Time unit interval
TUI
The TUI is the data-bit timing budget allowed for skew,
propagation delays, and data sampling window.
Transmitter channel-to-channel skew
Receiver input skew margin
Cyclone IV Device Handbook,
Volume 1
(1)
RSKM
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is:
 TUI – SW – TCCS
RSKM = -------------------------------------------------2
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
Design Guidelines
6–37
Table 6–11. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Symbol
Description
Input jitter tolerance (peak-to-peak)
—
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Output jitter (peak-to-peak)
—
Peak-to-peak output jitter from the PLL.
Note to Table 6–11:
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Figure 6–21. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
TCCS
Receiver
Input Data
RSKM
RSKM
TCCS
Sampling Window (SW)
Figure 6–22 shows the Cyclone IV devices high-speed I/O timing budget.
Figure 6–22. Cyclone IV Devices High-Speed I/O Timing Budget
(1)
Internal Clock Period
0.5 × TCCS
RSKM
SW
RSKM
0.5 × TCCS
Note to Figure 6–22:
(1) The equation for the high-speed I/O timing budget is:
eriod = 0.5  TCCS + RSKM + SW + RSKM + 0.5  TCCS
f For more information, refer to the Cyclone IV Device Datasheet chapter.
Design Guidelines
This section provides guidelines for designing with Cyclone IV devices.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply, you must observe some
restrictions on the placement of single-ended I/O pins in relation to differential pads.
1
May 2013
For guidelines on placing single-ended pads with respect to differential pads in
Cyclone IV devices, refer to “Pad Placement and DC Guidelines” on page 6–23.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
6–38
Chapter 6: I/O Features in Cyclone IV Devices
Software Overview
Board Design Considerations
This section explains how to achieve the optimal performance from a Cyclone IV I/O
interface and ensure first-time success in implementing a functional design with
optimal signal quality. You must consider the critical issues of controlled impedance
of traces and connectors, differential routing, and termination techniques to get the
best performance from Cyclone IV devices.
Use the following general guidelines to improve signal quality:
■
Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
■
Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
■
Longer traces have more inductance and capacitance. These traces must be as
short as possible to limit signal integrity issues.
■
Place termination resistors as close to receiver input pins as possible.
■
Use surface mount components.
■
Avoid 90° corners on board traces.
■
Use high-performance connectors.
■
Design backplane and card traces so that trace impedance matches the impedance
of the connector and termination.
■
Keep an equal number of vias for both signal traces.
■
Create equal trace lengths to avoid skew between signals. Unequal trace lengths
result in misplaced crossing points and decrease system margins as the TCCS
value increases.
■
Limit vias because they cause discontinuities.
■
Keep switching transistor-to-transistor logic (TTL) signals away from differential
signals to avoid possible noise coupling.
■
Do not route TTL clock signals to areas under or above the differential signals.
■
Analyze system-level signals.
f For PCB layout guidelines, refer to AN 224: High-Speed Board Layout Guidelines and
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
Software Overview
Cyclone IV devices high-speed I/O system interfaces are created in core logic by a
Quartus II software megafunction because they do not have a dedicated circuit for the
SERDES. Cyclone IV devices use the I/O registers and LE registers to improve the
timing performance and support the SERDES. The Quartus II software allows you to
design your high-speed interfaces using ALTLVDS megafunction. This megafunction
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation
Chapter 6: I/O Features in Cyclone IV Devices
Document Revision History
6–39
implements either a high-speed deserializer receiver or a high-speed serializer
transmitter. There is a list of parameters in the ALTLVDS megafunction that you can
set to customize your SERDES based on your design requirements. The megafunction
is optimized to use Cyclone IV devices resources to create high-speed I/O interfaces
in the most effective manner.
1
When you use Cyclone IV devices with the ALTLVDS megafunction, the interface
always sends the MSB of your parallel data first.
f For more details about designing your high-speed I/O systems interfaces using the
ALTLVDS megafunction, refer to the ALTLVDS Megafunction User Guide and the
Quartus II Handbook.
Document Revision History
Table 6–12 lists the revision history for this chapter.
Table 6–12. Document Revision History (Part 1 of 2)
Date
Version
May 2013
2.6
February 2013
2.5
October 2012
November 2011
December 2010
July 2010
May 2013
Altera Corporation
2.4
2.3
2.2
2.1
Changes
■
UpdatedTable 6–2 by adding Note (9).
■
Updated Table 6–4 and Table 6–8 to add new device options and packages.
Updated Table 6–4 and Table 6–8 to add new device options and packages.
■
Updated “I/O Banks” and “High Speed Serial Interface (HSSI) Input Reference Clock
Support ” sections.
■
Updated Table 6–3 and Table 6–5.
■
Updated Figure 6–10.
■
Updated “Differential SSTL I/O Standard Support in Cyclone IV Devices” and
“Differential HSTL I/O Standard Support in Cyclone IV Devices” sections.
■
Updated Table 6–1, Table 6–8, and Table 6–9.
■
Updated Figure 6–1.
■
Updated for the Quartus II software version 10.1 release.
■
Added Cyclone IV E new device package information.
■
Added “Clock Pins Functionality” section.
■
Updated Table 6–4 and Table 6–8.
■
Minor text edits.
■
Updated “Cyclone IV I/O Elements”, “Programmable Pull-Up Resistor”, “I/O Banks”,
“High-Speed I/O Interface”, and “Designing with BLVDS” sections.
■
Updated Table 6–6 and Table 6–7.
■
Updated Figure 6–19.
Cyclone IV Device Handbook,
Volume 1
6–40
Chapter 6: I/O Features in Cyclone IV Devices
Document Revision History
Table 6–12. Document Revision History (Part 2 of 2)
Date
Version
February 2010
November 2009
Cyclone IV Device Handbook,
Volume 1
2.0
1.0
Changes
■
Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1
release.
■
Updated Table 6–2, Table 6–3, and Table 6–10.
■
Updated “I/O Banks” section.
■
Added Figure 6–9.
■
Updated Figure 6–10 and Figure 6–11.
■
Added Table 6–4, Table 6–6, and Table 6–8.
Initial release.
May 2013 Altera Corporation