NBXDDA016 - 3.3 V, 133.33 MHz / 137.93 MHz Dual Frequency

NBXDDA016, NBXDDB016
3.3 V, 133.33 MHz
/137.93 MHz Dual
Frequency CML Clock
Oscillator
The NBXDDB016/NBXDDA016 dual frequency crystal oscillator
(XO) is designed to meet today’s requirements for 3.3 V CML clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable
133.33 MHz or 137.93 MHz, ultra low jitter and phase noise CML
differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000. Frequency stability options available as
either 50 PPM NBXDDB016 or 20 PPM NBXDDA016.
Features
•
•
•
•
•
•
•
•
CML Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)
Selectable Output Frequency − 133.33 MHz (default)/137.93 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range 3.3 V ±10%
Total Frequency Stability − ±20 PPM or ±50 PPM
MARKING DIAGRAMS
NBXDDB016
133.33/137.93
AAWLYYWWG
NBXDDA016
NBXDDB016
133.33/137.93
AA
WL
YY
WW
G
NBXDDA016
133.33/137.93
AAWLYYWWG
= NBXDDA016 (±50 PPM)
= NBXDDB016 (±20 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Device
• High−End Servers
• Basestation
• General Purpose Clock Generation and Margining
VDD
6
CLK CLK
5 4
2
FSEL
Package
Shipping†
NBXDDB016LN1TAG*
CLCC−6
1000/
(Pb−Free) Tape & Reel
NBXDDA016LN1TAG
CLCC−6
1000/
(Pb−Free) Tape & Reel
NBXDDA016LNHTAG
CLCC−6
100/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
PLL
Clock
Multiplier
1
OE
6 PIN CLCC
LN SUFFIX
CASE 848AB
ORDERING INFORMATION
Applications
Crystal
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* Please contact sales office for availability
3
GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 4
1
Publication Order Number:
NBXDDA016/D
NBXDDA016, NBXDDB016
OE
1
6
VDD
FSEL
2
5
CLK
GND
3
4
CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2
FSEL
Control Input
Output Frequency Select Pin. Pin will default LOW when left open. See Output Frequency Select Table 3.
3
GND
Power Supply
Ground 0 V.
4
CLK
CML Output
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD.
5
CLK
CML Output
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD.
6
VDD
Power Supply
Positive power supply voltage. Voltage should not exceed 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
Table 3. OUTPUT FREQUENCY SELECT
OE Pin
Output Pins
FSEL Pin
Output Frequency (MHz)
Open
Active
Open
(pin will float Low)
133.33
High Level
137.93
Low Level
133.33
High Level
Active
Low Level
High Z
Table 4. ATTRIBUTES
Characteristic
Value
Input Default State Resistor
ESD Protection
170 kW
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
VDD
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
Rating
Units
4.6
V
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−55 to +120
°C
Tsol
Wave Solder
260
°C
See Figure 6
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NBXDDA016, NBXDDB016
Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
70
100
mA
IDD
Power Supply Current (Note 2)
VIH
OE Input HIGH Voltage
2000
VDD
mV
VIL
OE Input LOW Voltage
GND − 300
800
mV
IIH
Input HIGH Current
OE
FSEL
−100
−100
+100
+100
mA
IIL
Input LOW Current
OE
FSEL
−100
−100
+100
+100
mA
VIH
FSEL Input HIGH Voltage
2000
VDD
mV
VIL
FSEL Input LOW Voltage
0
800
mV
VOH
Output HIGH Voltage (Note 2)
VDD−40
VDD
mV
VOL
Output LOW Voltage (Note 2)
VDD−450
VDD−300
mV
VOUTPP
Output Voltage Amplitude (Note 2)
VDD−380
380
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to VDD. See Figure 5.
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NBXDDA016, NBXDDB016
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Characteristic
Symbol
fCLKOUT
Df
FNOISE
Output Clock Frequency
Conditions
137.93
FSEL = LOW
133.33
(Note 4)
Max.
Units
MHz
±20
±50
ppm
Phase−Noise Performance
100 Hz of Carrier
−102
dBc/Hz
fCLKout = 133.33 MHz/137.93 MHz
(See Figures 3 and 4)
1 kHz of Carrier
−120
dBc/Hz
10 kHz of Carrier
−126
dBc/Hz
100 kHz of Carrier
−126
dBc/Hz
1 MHz of Carrier
−134
dBc/Hz
RMS Phase Jitter
tjitter
Cycle to Cycle, RMS
10 MHz of Carrier
−162
12 kHz to 20 MHz
0.4
0.9
ps
1000 Cycles
1.5
8
ps
Cycle to Cycle, Peak−to−Peak
tDUTY_CYCLE
Typ.
FSEL = HIGH
Frequency Stability − NBXDDB016
Frequency Stability − NBXDDA016
tjit(F)
tOE/OD
Min.
dBc/Hz
1000 Cycles
10
30
ps
Period, RMS
10,000 Cycles
0.8
4
ps
Period, Peak−to−Peak
10,000 Cycles
7
20
ps
200
ns
50
52
%
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
48
tR
Output Rise Time (20% and 80%)
160
300
ps
tF
Output Fall Time (80% and 20%)
160
300
ps
1
tstart
Start−up Time
5
ms
1st Year
3
ppm
Every Year After 1st
1
ppm
Aging
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to VDD. See Figure 5.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
Figure 3. Typical Phase Noise Plot @ 133.33 MHz
Figure 4. Typical Phase Noise Plot @ 137.93 MHz
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NBXDDA016, NBXDDB016
Table 8. RELIABILITY COMPLIANCE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
Standard
Method
Shock
Mechanical
MIL−STD−833, Method 2002, Condition B
Solderability
Mechanical
MIL−STD−833, Method 2003
Vibration
Mechanical
MIL−STD−833, Method 2007, Condition A
Solvent Resistance
Mechanical
MIL−STD−202, Method 215
Thermal Shock
Environment
MIL−STD−833, Method 1011, Condition A
Moisture Level Sensitivity
Environment
MSL1 260°C per IPC/JEDEC J−STD−020D
VTT = VDD
NBXDDB016/NBXDDA016
50 W
Z = 50 W
50 W
CLK
D
Driver
Device
Receiver
Device
Z = 50 W
CLK
D
Figure 5. Typical CML Termination for Output Driver and Device Evaluation
(See Application Note AND8173 − Termination of CML Devices)
temp. 260°C
20 − 40 sec. max.
peak
Temperature (°C)
260
6°C/sec. max.
3°C/sec. max.
217
ramp−up
175
150
cooling
pre−heat
reflow
60180 sec.
Time
60150 sec.
Figure 6. Recommended Reflow Soldering Profile
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NBXDDA016, NBXDDB016
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB−01
ISSUE C
A
D
4X
0.15 C
E2
TERMINAL 1
INDICATOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
B
D1
H E1
DIM
A
A1
A2
A3
b
D
D1
D2
D3
E
E1
E2
E3
e
L
R
E
D2
TOP VIEW
A2
A3
0.10 C
A
SIDE VIEW
A1
C
3
2
R
0.05 C
6X
b
6
5
6.17
6.66
4.37
4.65
1.17
SOLDERING FOOTPRINT*
e
E3
0.10 C A B
0.08
1.30
MILLIMETERS
NOM
MAX
1.80
1.90
0.70 REF
0.36 REF
0.10
0.12
1.40
1.50
7.00 BSC
6.20
6.23
6.81
6.96
5.08 BSC
5.00 BSC
4.40
4.43
4.80
4.95
3.49 BSC
2.54 BSC
1.27
1.37
0.70 REF
SEATING
PLANE
D3
1
MIN
1.70
4
6X
6X
1.50
5.06
L
BOTTOM VIEW
2.54
PITCH
6X
1.50
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
Sales Representative
NBXDDA016/D