ONSEMI NBXDBA012LN1TAG

NBXDBA012
3.3 V, 106.25 MHz /
212.5 MHz LVPECL Clock
Oscillator
The NBXDBA012 dual frequency crystal oscillator (XO) is
designed to meet today's requirements for 3.3V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 106.25
MHz or 212.5 MHz, ultra low jitter and phase noise LVPECL
differential output. This device is a member of ONSemiconductor's
PureEdget clock family that provides accurate and precision clock
solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000.
Features
•LVPECL Differential Output
•Uses High Q Fundamental Mode Crystal and PLL Multiplier
•Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz)
•Selectable Output Frequency - 106.25 MHz / 212.5 MHz
•Frequency Stability - ±50 PPM
•Hermetically Sealed Ceramic SMD Package
•RoHS Compliant
•Operating Range 3.3 V ±10%
•This is a Pb-Free Device
Applications
•1X and 2X Fiber Channel
•Host Bus Adapter
VDD
6
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MARKING DIAGRAM
6 PIN CLCC
TBD SUFFIX
CASE 848AB
DBA012
A
WL
YY
WW
DBA012
AWLYYWW
= NBXDBA012 (±50 PPM)
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NBXDBA012LN1TAG CLCC-6 1000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
CLK CLK
5 4
PLL
Clock
Multiplier
Crystal
1
OE
2
FSEL
3
GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 0
1
Publication Order Number:
NBXDBA012/D
NBXDBA012
OE
1
6
VDD
FSEL
2
5
CLK
GND
3
4
CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2
FSEL
LVTTL/LVCMOS
Control Input
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
3
GND
Power Supply
4
CLK
LVPECL Output
Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD - 2 V.
5
CLK
LVPECL Output
Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD - 2 V.
6
VDD
Power Supply
Ground 0 V.
Positive power supply voltage. Voltage should not exceed 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI-STATE FUNCTION
Table 3. OUTPUT FREQUENCY SELECT
OE Pin
Output Pin
FSEL Pin
Output Frequency (MHz)
Open
Active
Open
(pin will float high)
106.25
HIGH Level
106.25
LOW Level
212.5
HIGH Level
Active
LOW Level
High Z
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD
Positive Power Supply
GND = 0 V
4.6
V
Iout
LVPECL Output Current
Continuous
Surge
25
50
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-55 to +120
°C
Tsol
Wave Solder
260
°C
See Figure 6
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXDBA012
Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = -40°C to +85°C)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
80
95
mA
IDD
Power Supply Current (Note 2)
VIH
OE and FSEL Input HIGH Voltage
2000
VDD
mV
VIL
OE and FSEL Input LOW Voltage
GND - 300
800
mV
IIH
Input HIGH Current
OE
FSEL
-100
-100
+100
+100
mA
IIL
Input LOW Current
OE
FSEL
-100
-100
+100
+100
mA
VDD-1145
2155
VDD-895
2405
mV
VDD = 3.3 V
VDD-1945
1355
VDD-1600
1700
mV
VDD = 3.3 V
VOH
VOL
VOUTPP
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Output Voltage Amplitude (Note 2)
780
mV
NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
2. Measurement taken with outputs terminated with 50 ohm to VDD-2 V.
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = -40°C to +85°C)
Symbol
Characteristic
fCLKOUT
Output Clock Frequency
Df
FNOISE
Frequency Stability
Phase-Noise Performance
fCLKout = 106.25 MHz/212.5 MHz
Conditions
Min.
Typ.
FSEL = HIGH
106.25
FSEL = LOW
212.5
Max.
MHz
±50
10 Years Aging
Units
ppm
100 Hz of Carrier
-103/-90
dBc/Hz
1 kHz of Carrier
-125/-122
dBc/Hz
10 kHz of Carrier
-135/-127
dBc/Hz
100 kHz of Carrier
-137/-128
dBc/Hz
1 MHz of Carrier
-137/-131
dBc/Hz
10 MHz of Carrier
-162/-159
dBc/Hz
12 kHz to 20 MHz
0.4
0.9
ps
tjit(F)
RMS Phase Jitter
tjitter
Cycle to Cycle, RMS
1000 Cycles
3
10
ps
Cycle to Cycle, Peak-to-Peak
1000 Cycles
15
35
ps
Period, RMS
10,000 Cycles
2
5
ps
Period, Peak-to-Peak
10,000 Cycles
10
25
ps
200
ns
50
52
%
tOE/OD
tDUTY_CYCLE
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
48
tR
Output Rise Time (20% and 80%)
150
550
ps
tF
Output Fall Time (80% and 20%)
150
550
ps
1
5
ms
3
ppm
1
ppm
tstart
Start-up Time
Aging
1st
Year
Every Year After 1st
NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
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NBXDBA012
Table 8. RELIABILITY COMPLIANCE
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
Standard
Method
Shock
Mechanical
MIL-STD-833, Method 2002, Condition B
Solderability
Mechanical
MIL-STD-833, Method 2003
Vibration
Mechanical
MIL-STD-833, Method 2007, Condition A
Solvent Resistance
Mechanical
MIL-STD-202, Method 215
Resistance to Soldering Heat
Mechanical
MIL-STD-203, Method 210, Condition I or J
Thermal Shock
Environment
MIL-STD-833, Method 1001, Condition A
Moisture Resistance
Environment
MIL-STD-833, Method 1004
Figure 3. Typical Phase Noise Plot @ 106.25 MHz
Figure 4. Typical Phase Noise Plot @ 212.5 MHz
Figure 5. Typical Output Waveform @ 106.25 MHz
Figure 6. Typical Output Waveform @ 212.5 MHz
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NBXDBA012
NBXDBA012
Zo = 50 W
CLK
D
Receiver
Device
Driver
Device
Zo = 50 W
CLK
D
50 W
50 W
VTT
VTT = VDD - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
temp. 260°C
20 - 40 sec. max.
peak
Temperature (°C)
260
6°C/sec. max.
3°C/sec. max.
217
ramp-up
175
150
cooling
pre-heat
reflow
Time
60180 sec.
60150 sec.
Figure 8. Recommended Reflow Soldering Profile
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5
NBXDBA012
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB-01
ISSUE O
A
D
4X
0.15 C
E2
TERMINAL 1
INDICATOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
B
D1
DIM
A
A1
A2
A3
b
D
D1
D2
D3
E
E1
E2
E3
e
L
R
E
E1
D2
TOP VIEW
A3
A2
0.10 C
A
SIDE VIEW
A1
C
SEATING
PLANE
MIN
1.70
0.08
1.30
6.17
6.66
4.37
4.65
1.17
MILLIMETERS
NOM
MAX
1.80
1.90
0.70 REF
0.36 REF
0.10
0.12
1.40
1.50
7.00 BSC
6.20
6.23
6.81
6.96
5.08 BSC
5.00 BSC
4.40
4.43
4.80
4.95
3.49 BSC
2.54 BSC
1.27
1.37
0.70 REF
SOLDERING FOOTPRINT*
D3
e
2
1
3
6X
1.50
R
5.06
E3
0.10 C A B
0.05 C
6X
6
5
4
b
6X
L
2.54
PITCH
BOTTOM VIEW
6X
1.50
DIMENSION: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NBXDBA012/D