MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
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delay using the FTUNE pin. The FTUNE input takes an analog voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps.
MARKING
The delay section consists of a programmable matrix of gates and
DIAGRAM*
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
MC100
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
EP196
LEN allows a transparent LOAD mode of real time delay values by
AWLYYWWG
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
LQFP−32
FA SUFFIX
current values present against any subsequent changes in D[10:0]. The
32
CASE 873A
approximate delay values for varying tap numbers correlating to D0 (LSB)
1
through D9 (MSB) are shown in Table 5.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
A
= Assembly Location
WL
= Wafer Lot
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
YY
= Year
by LEN, in cascading multiple PDCs for increased programmable
WW
= Work Week
range. The cascade logic allows full control of multiple PDCs.
G
= Pb−Free Package
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
*For additional marking information, refer to
Application Note AND8002/D.
delay equivalent to “D0”, the minimum increment.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
ORDERING INFORMATION
operation is available in PECL mode only. For LVCMOS input levels,
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
leave VCF and VEF open. For ECL operation, short VCF and VEF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to VCF and leave open VEF pin. The 1.5 V reference voltage
to VCF pin can be accomplished by placing a 2.2 kW resistor between
*For additional information on our Pb−Free strategy
VCF and VEE for 3.3 V power supply.
and soldering details, please download the
The VBB pin, an internally generated voltage supply, is available to
ON Semiconductor Soldering and Mounting
this device only. For single−ended input conditions, the unused
Techniques Reference Manual, SOLDERRM/D.
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
• Maximum Frequency > 1.2 GHz Typical
• Open Input Default State
• Programmable Range: 0 ns to 10 ns
• Safety Clamp on Inputs
• Delay Range: 2.4 ns to 12.4 ns
• A Logic High on the EN Pin Will Force Q to Logic
Low
• 10 ps Increments
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
• PECL Mode Operating Range:
Inputs
VCC = 3.0 V to 3.6 V with VEE = 0 V
•
VBB Output Reference Voltage
• NECL Mode Operating Range:
• These are Pb−Free Devices*
VCC = 0 V with VEE = −3.0 V to −3.6 V
© Semiconductor Components Industries, LLC,2014
June, 2014 − Rev. 16
1
Publication Order Number:
MC100EP196/D
MC100EP196
VEE D0 VCC Q
24
23
22
21
Q VCC VCC FTUNE
20
19
18
17
D1
25
16
EN
D2
26
15
CASCADE
D3
27
14
CASCADE
VEE
28
13
VCC
D4
29
12
SETMAX
D5
30
11
SETMIN
D6
31
10
LEN
D7
32
9
VEE
MC100EP196
1
D8
2
3
4
D9 D10 IN
5
6
7
8
IN VBB VEF VCF
Figure 1. 32−Lead LQFP Pinout (Top View)
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MC100EP196
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
LOW
Single−ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
Description
3
D[10]
LVCMOS, LVTTL,
ECL Input
LOW
Single−ended CASCADE/CASCADE Control Input. Internal 75 kW
to VEE. (Note 1)
4
IN
ECL Input
LOW
Noninverted Differential Input. Internal 75 kW to VEE.
5
IN
ECL Input
HIGH
Inverted Differential Input. Internal 75 kW to VEE.
6
VBB
−
−
ECL Reference Voltage Output
7
VEF
−
−
Reference Voltage for ECL Mode Connection
8
VCF
−
−
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 28
VEE
−
−
Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2)
13, 18, 19, 22
VCC
−
−
Positive Supply Voltage. All VCC Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2)
10
LEN
ECL Input
LOW
Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11
SETMIN
ECL Input
LOW
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
12
SETMAX
ECL Input
LOW
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
14
CASCADE
ECL Output
−
Inverted Differential Cascade Output for D[10] Input. Typically Terminated with 50 W to VTT = VCC − 2 V.
15
CASCADE
ECL Output
−
Noninverted Differential Cascade Output for D[10] Input. Typically
Terminated with 50 W to VTT = VCC − 2 V.
16
EN
ECL Input
LOW
17
FTUNE
Analog Input
−
Fine Tuning Input.
21
Q
ECL Output
−
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
20
Q
ECL Output
−
Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
Single−ended Output Enable Pin. Internal 75 kW to VEE.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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3
MC100EP196
Table 2. CONTROL PIN
Pin
State
EN
LOW (Note 3)
HIGH
LEN
LOW (Note 3)
HIGH
SETMIN
SETMAX
D10
Function
Input Signal is Propagated to the Output
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Minimum Output Delay
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Maximum Output Delay
LOW
CASCADE Output LOW, CASCADE Output HIGH
HIGH
CASCADE Output LOW, CASCADE Output High
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
Pin
State
VCF
VEF Pin (Note 4)
VCF
No Connect
VCF
1.5 V $ 100 mV
Function
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value
is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
POWER SUPPLY
LVCMOS
LVTTL
LVPECL
LVNECL
PECL Mode Operating Range
YES
YES
YES
N/A
NECL Mode Operating Range
N/A
N/A
N/A
YES
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4
5
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Figure 2. Logic Diagram
VEE
VEF
VCF
VBB
EN
IN
IN
FTUNE
SET MAX
SET MIN
LEN
512
GD*
D9
1
0
D10
Latch
256
GD*
D8
1
0
D7
1
CASCADE
CASCADE
128
GD*
0
64
GD*
D6
1
0
16
GD*
1
D4
10 BIT LATCH
D5
1
0
8
GD*
D3
1
0
4
GD*
D2
1
0
2
GD*
D1
1
0
(FIXED MINIMUM DELAY APPROX. 2.4 ns)
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
32
GD*
0
D0
1
GD*
1
0
1
GD*
1
0
Q
Q
MC100EP196
MC100EP196
Table 5. THEORETICAL DELTA DELAY VALUES
D(9:0) Value
SETMIN
SETMAX
Programmable Delay*
XXXXXXXXXX
H
L
0 ps
0000000000
L
L
0 ps
0000000001
L
L
10 ps
0000000010
L
L
20 ps
0000000011
L
L
30 ps
0000000100
L
L
40 ps
0000000101
L
L
50 ps
0000000110
L
L
60 ps
0000000111
L
L
70 ps
0000001000
L
L
80 ps
0000010000
L
L
160 ps
0000100000
L
L
320 ps
0001000000
L
L
640 ps
0010000000
L
L
1280 ps
0100000000
L
L
2560 ps
1000000000
L
L
5120 ps
1111111111
L
L
10230 ps
XXXXXXXXXX
L
H
10240 ps
*Fixed minimum delay not included.
Table 6. TYPICAL FTUNE DELAY PIN
Input Range
Output Range
VCC−VEE (V)
0 − 60 (ps)
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MC100EP196
15000
14000
13000
12000
85 °C
11000
25 °C
DELAY ( ps)
10000
−40 °C
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
100
200
300
400
500
600
700
800
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
Table 7. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−32
Flammability Rating Oxygen Index: 28 to 34
> 2 kV
> 100 V
> 2 kV
Pb−Free Pkg
Level 2
UL 94 V−0 @ 0.125 in
Transistor Count
1237 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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7
900
1000
MC100EP196
Table 8. MAXIMUM RATINGS
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
LQFP−32
12 to 17
°C/W
Tsol
Wave Solder
265
°C
Pb−Free
Condition 2
VI ≤ VCC
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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8
MC100EP196
Table 9. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
160
110
130
170
110
135
175
mA
VOH
Output HIGH Voltage (Note 3)
2155
2300
2405
2155
2300
2405
2155
2300
2405
mV
VOL
Output LOW Voltage (Note 3)
1305
1520
1605
1305
1500
1605
1305
1485
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
LVPECL
LVCMOS
LVTTL
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
Input LOW Voltage (Single−Ended)
LVPECL
LVCMOS
LVTTL
1305
0
0
1675
800
800
1305
0
0
1675
800
800
1305
0
0
1675
800
800
VBB
Output Voltage Reference
1775
1875
1975
1775
1875
1975
1775
1875
1975
mV
VCF
LVTTL Mode Input Detect Voltage
@ IVCF = 700 mA
1.4
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
V
VEF
Reference Voltage for
ECL Mode Connection
1900
1960
2050
1875
1953
2050
1850
1945
2050
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current (PECL)
IN, IN, EN, LEN, SETMIN, SETMAX
VIL
mV
mV
2.0
mA
150
IIHH
FTUNE Input High Current @ VCC
50
IIL
Input LOW Current (PECL)
IN, IN, EN, LEN, SETMIN, SETMAX
0.5
IILL
FTUNE Input LOW Current @VEE
−10
87
150
150
50
84
150
0.5
0
10
−10
150
50
82
150
mA
0.5
0
10
−10
mA
0
10
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
3. All loading with 50 W to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP196
Table 10. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V (Note 5)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
125
160
110
130
170
110
135
175
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
−1145
−1000
−895
−1145
−1000
−895
−1145
−1000
−895
mV
VOL
Output LOW Voltage (Note 6)
−1995
−1780
−1695
−1995
−1800
−1695
−1995
−1815
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
LVNECL
−1225
−880
−1225
−880
−1225
−880
Input LOW Voltage (Single−Ended)
LVNECL
−1995
−1625
−1995
−1625
−1995
−1625
VBB
Output Voltage Reference
−1525
−1425
−1325
−1525
−1425
−1325
−1525
−1425
−1325
mV
VEF
Reference Voltage for ECL Mode
Connection
−1400
−1340
−1250
−1425
−1347
−1250
−1450
−1355
−1250
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
0
V
IIH
Input HIGH Current
IN, IN, EN, LEN, SETMIN, SETMAX
VIL
mV
mV
VEE+2.0
VEE+2.0
0
VEE+2.0
mA
150
IIHH
FTUNE Input High Current @ VCC
50
IIL
Input LOW Current
IN, IN, EN, LEN, SETMIN, SETMAX
0.5
FTUNE Input LOW Current @ VEE
−10
IILL
0
87
150
150
50
84
150
150
50
82
150
mA
mA
0.5
0
10
−10
0.5
0
10
−10
0
10
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
6. All loading with 50 W to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP196
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 8)
−40°C
Min
Characteristic
Symbol
Typ
25°C
Max
Min
85°C
Max
Min
Max
Maximum Frequency
tPLH
tPHL
Propagation Delay
IN to Q; D(0−9) = 0
IN to Q; D(0−9) = 1023
EN to Q; D(0−9) = 0
D10 to CASCADE
1810
9500
1780
350
2210
11496
2277
450
2610
13500
2780
550
1960
10000
1930
380
2360
12258
2430
477
2760
14000
2930
580
2180
10955
2150
420
2580
13454
2650
520
2980
15955
3150
620
tRANGE
Programmable Range
{D(0−9) = HI} − {D(0−9) = LO}
8600
9285
10000
9200
9897
10700
9900
10875
12000
90
245
530
1060
2160
4335
7
23
39
58
137
293
590
1158
2317
4647
100
260
560
1130
2290
4590
11
30
48
67
149
313
629
1237
2472
4955
90
270
600
1200
2450
4935
13
32
53
73
154
337
681
1353
2712
5440
Monotonicity (Note 10)
tSKEW
Duty Cycle Skew (Note 11)
|tPHL−tPLH|
tR
Unit
GHz
ps
ps
ps
Mono
th
1.2
Step Delay (Note 9)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
ts
1.2
Typ
fmax
Dt
1.2
Typ
185
335
650
1265
2490
5010
200
370
710
1355
2680
5385
225
410
770
1520
3015
6015
ps
ps
20
22
27
Setup Time
ps
D to LEN
D to IN (Note 12)
EN to IN (Note 13)
150
100
150
−10
−130
−105
150
100
150
−70
−150
−120
150
100
150
−70
−165
−140
LEN to D
IN to EN (Note 14)
225
450
170
275
200
450
70
305
200
450
60
325
EN to IN (Note 15)
SET MAX to LEN
SET MIN to LEN
150
400
300
−105
70
165
150
400
350
−120
110
180
150
400
350
−140
160
205
Hold Time
ps
Release Time
ps
tjit
Random Clock Jitter
@ 1.2 GHz, SETMAX Delay
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Time
20−80% (Q)
20−80% (CASCADE)
3
3
3
ps
150
800
1200
150
800
1200
150
800
1200
85
100
110
150
130
200
95
110
120
160
145
210
110
125
135
175
160
225
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
9. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
10. The monotonicity indicates the increased delay value for each binary count increment on the control inputs D(0−9).
11. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
12. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
13. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
VCC − 1425 mV to that IN/IN transition.
14. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than VCC − 1425 mV to that IN/IN transition.
15. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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11
MC100EP196
IN
VINPP = VIH(D) − VIL(D)
IN
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 4. AC Reference Measurement
Using the FTUNE Analog Input
The analog FTUNE pin on the EP196 device is intended
to add more delay in a tunable gate to enhance the 10 ps
resolution capabilities of the fully digital EP196. The level
of resolution obtained is dependent on the voltage applied to
the FTUNE pin.
To provide this further level of resolution, the FTUNE pin
must be capable of adjusting the additional delay finer than
the 10 ps digital resolution (See Logic Diagram). This
requirement is easily achieved because a 60 ps additional
delay can be obtained over the entire FTUNE voltage range
(See Figure 5). This extra analog range ensures that the
FTUNE pin will be capable even under worst case
conditions of covering a digital resolution. Typically, the
analog input will be driven by an external DAC to provide
a digital control with very fine analog output steps. The final
resolution of the device will be dependent on the width of the
DAC chosen.
To determine the voltage range necessary for the FTUNE
input, Figure 5 should be used. There are numerous voltage
ranges which can be used to cover a given delay range; users
are given the flexibility to determine which one best fits their
designs.
90
80
VCC = 0 V
VEE = −3.3 V
25°C
70
−40°C
DELAY (ps)
60
50
40
30
20
85°C
10
0
−10
−3.3 −2.97 −2.64 −2.31
VEE
−1.98 −1.65 −1.32 −0.99
−0.66 −0.33
FTUNE VOLTAGE (V)
Figure 5. Typical EP196 Delay versus FTUNE Voltage
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12
0
VCC
MC100EP196
Cascading Multiple EP196s
To increase the programmable range of the EP196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
Figure 6 illustrates the interconnect scheme for cascading
two EP196s. As can be seen, this scheme can easily be
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin and when assert
HIGH switches output pin CASCADE to HIGH and
pin CASCADE to LOW. With the interconnect scheme of
Figure 6 when D10 is asserted, it signals the need for a larger
programmable range than is achievable with a single device.
The A11 address can be added to generate a cascade output
for the next EP196. For a 2−device configuration, A11 is not
required.
ADDRESS BUS
Need if Chip #3 is used
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
VEE
D3
D2
D1
D6
D5
D4
VEE
D3
D2
D1
VEE
D8
VEE
D9
D0
D9
D0
VCC
D10
D10
EP196
IN
VCC
EP196
Q
IN
Q
IN
Q
OUTPUT
IN
CHIP #2
Q
CHIP #1
FTUNE
EN
CASCADE
CASCADE
EN
LEN
VCC
VCF
SETMAX
FTUNE
VCF
SETMIN
VCC
LEN
VEF
VEE
VCC
CASCADE
VEF
CASCADE
VCC
VCC
VBB
SETMAX
VCC
SETMIN
VBB
VEE
INPUT
D7
D8
DAC
Figure 6. Cascading Interconnect Architecture
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13
MC100EP196
chip #2 will be deasserted and the SETMAX pin asserted,
resulting in the device delay to be the maximum delay.
Table 12 shows the delay time of two EP196 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 6. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
Furthermore, to fully utilize EP196, the FTUNE pin can
be used for additional delay and for finer resolution than
10 ps. As shown in Figure 5, an analog voltage input from
DAC can adjust the FTUNE pin with an extra 60 ps of delay
for each chip.
An expansion of the latch section of the block diagram is
pictured in Figure 7. Use of this diagram will simplify the
explanation of how the SETMIN and SETMAX circuitry
works in cascade. When D10 of chip #1 in Figure 5 is LOW,
this device’s cascade output will also be LOW while the
CASCADE output will be HIGH. In this condition, the
SETMIN pin of chip #2 will be asserted HIGH and thus all
of the latches of chip #2 will be reset and the device will be
set at its minimum delay.
Chip #1, on the other hand, will have both SETMIN and
SETMAX deasserted so that its delay will be controlled
entirely by the address bus A0−A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0−A9 address bus), D10 will be
asserted to signal the need to cascade the delay to the next
EP196 device. When D10 is asserted, the SETMIN pin of
TO SELECT MULTIPLEXERS
SET
MIN
SET
MAX
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Figure 7. Expansion of the Latch Section of the EP196 Block Diagram
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14
MC100EP196
Table 12. CASCADED DELAY VALUE OF TWO EP196S
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay Value
Delay Value
0
0
0
0
0
0
0
0
0
0
0
0 ps
4400 ps
0
0
0
0
0
0
0
0
0
0
1
10 ps
4410 ps
0
0
0
0
0
0
0
0
0
1
0
20 ps
4420 ps
0
0
0
0
0
0
0
0
0
1
1
30 ps
4430 ps
0
0
0
0
0
0
0
0
1
0
0
40 ps
4440 ps
0
0
0
0
0
0
0
0
1
0
1
50 ps
4450 ps
0
0
0
0
0
0
0
0
1
1
0
60 ps
4460 ps
0
0
0
0
0
0
0
0
1
1
1
70 ps
4470 ps
0
0
0
0
0
0
0
1
0
0
0
80 ps
4480 ps
0
0
0
0
0
0
1
0
0
0
0
160 ps
4560 ps
0
0
0
0
0
1
0
0
0
0
0
320 ps
4720 ps
0
0
0
0
1
0
0
0
0
0
0
640 ps
5040 ps
0
0
0
1
0
0
0
0
0
0
0
1280 ps
5680 ps
0
0
1
0
0
0
0
0
0
0
0
2560 ps
6960 ps
0
1
0
0
0
0
0
0
0
0
0
5120 ps
9520 ps
0
1
1
1
1
1
1
1
1
1
1
10230 ps
14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
0
0
0
10240 ps
14640 ps
1
0
0
0
0
0
0
0
0
0
1
10250 ps
14650 ps
1
0
0
0
0
0
0
0
0
1
0
10260 ps
14660 ps
1
0
0
0
0
0
0
0
0
1
1
10270 ps
14670 ps
1
0
0
0
0
0
0
0
1
0
0
10280 ps
14680 ps
1
0
0
0
0
0
0
0
1
0
1
10290 ps
14690 ps
1
0
0
0
0
0
0
0
1
1
0
10300 ps
14700 ps
1
0
0
0
0
0
0
0
1
1
1
10310 ps
14710 ps
1
0
0
0
0
0
0
1
0
0
0
10320 ps
14720 ps
1
0
0
0
0
0
1
0
0
0
0
10400 ps
14800 ps
1
0
0
0
0
1
0
0
0
0
0
10560 ps
14960 ps
1
0
0
0
1
0
0
0
0
0
0
10880 ps
15280 ps
1
0
0
1
0
0
0
0
0
0
0
11520 ps
15920 ps
1
0
1
0
0
0
0
0
0
0
0
12800 ps
17200 ps
1
1
0
0
0
0
0
0
0
0
0
15360 ps
19760 ps
1
1
1
1
1
1
1
1
1
1
1
20470 ps
24870 ps
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15
Delay Value
Delay Value
MC100EP196
Multi−Channel Deskewing
The most practical application for EP196 is in multiple
channel delay matching. Slight differences in impedance
and cable length can create large timing skews within a
high−speed system. To deskew multiple signal channels,
each channel can be sent through each EP196 as shown in
Figure 8. One signal channel can be used as reference and the
other EP196s can be used to adjust the delay to eliminate the
timing skews. Nearly any high−speed system can be fine
tuned (as small as 10 ps) to reduce the skew to extremely
tight tolerances using the available FTUNE pin.
EP196
IN
IN
Q
Q
#1
EP196
IN
IN
Q
Q
#2
EP196
IN
IN
Q
Q
#N
Control
Logic
Digital
Data
DAC
Figure 8. Multiple Channel Deskewing Diagram
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16
MC100EP196
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Zo = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping†
MC100EP196FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EP196FAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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17
MC100EP196
PACKAGE DIMENSIONS
A
4X
A1
32
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
25
0.20 (0.008) AB T-U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
−Z−
9
S1
4X
0.20 (0.008) AC T-U Z
F
S
8X
M_
J
R
D
DETAIL AD
G
SECTION AE−AE
−AB−
C E
−AC−
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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18
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T-U Z
AE
B1
MC100EP196
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100EP196/D