MICREL SY100EP196V_0607

ECL Pro®
SY100EP196V
ECL Pro®
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY WITH FINE TUNE CONTROL
Micrel, Inc.
SY100EP196V
FEATURES
■ Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
■ Maximum frequency > 2.5GHz
■ Programmable range: 2.2ns to 12.2ns
■ 10ps increments
■ 30ps fine tuning range
■ PECL mode operating range: VCC = 3.0V to 5.5V
with VEE = 0V
■ NECL mode operating range: VCC = 0V
with VEE = –3.0V to –5.5V
■ Open input default state
■ Safety clamp on inputs
■ A logic high on the /EN pin will force Q to logic low
■ D[0:10] can accept either ECL, CMOS, or TTL inputs
■ VBB output reference voltage
■ Available in a 32-pin TQFP package
ECL Pro®
DESCRIPTION
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
CROSS REFERENCE TABLE
APPLICATIONS
■ Clock de-skewing
■ Timing adjustment
■ Aperture centering
Micrel Semiconductor
ON Semiconductor
SY100EP196VTI
MC100EP196FA
SY100EP196VTITR
MC100EP196FAR2
TYPICAL PERFORMANCE
TYPICAL APPLICATIONS CIRCUIT
Delay vs. Tap
12000
D
SY100EP196V
CLOCK+
IN
CLOCK–
/IN
Fine Tune Voltage
Q
Q+
Flip-Flop
CK
10000
Q–
DELAY (ps)
Data Signal
of Unknown Phase
FTUNE /Q
D[9:0]
8000
6000
4000
2000
CONTROL
LOGIC
0
0
200 400 600 800 1000 1200
TAP (DIGITAL WORD)
ECL Pro is a registered trademark of Micrel, Inc.
M9999-072706
[email protected] or (408) 955-1690
Rev.: E
1
Amendment: /0
Issue Date: July 2006
ECL Pro®
SY100EP196V
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
D7
D6
D5
D4
VEE
D3
D2
D1
Ordering Information(1)
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY100EP196VTI
T32-1
Industrial
SY100EP196V
Sn-Pb
SY100EP196VTITR(2)
T32-1
Industrial
SY100EP196V
Sn-Pb
SY100EP196VTG(3)
T32-1
Industrial
SY100EP196V with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY100EP196VTGTR(2, 3)
T32-1
Industrial
SY100EP196V with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
32 31 30 29 28 27 26 25
D8
D9
D10
IN
/IN
VBB
VEF
VCF
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Part Number
VEE
D0
VCC
Q
/Q
VCC
VCC
FTUNE
VEE
LEN
SETMIN
SETMAX
VCC
/CASCADE
CASCADE
/EN
9 10 11 12 13 14 15 16
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
IN
0
0
0
0
/IN
1
1
1
1
512
GD
/EN
16
GD
256
GD
128
GD
64
GD
0
0
0
0
1
1
1
1
8
GD
4
GD
2
GD
0
32
GD
1
0
1
GD
1
FTUNE
D[9:0]
LEN
SETMIN
SETMAX
10-bit
Latch
1
GD
D[10]
Q
1
/Q
CASCADE
Latch
/CASCADE
VBB
VCF
VEF
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2
ECL Pro®
SY100EP196V
Micrel, Inc.
PIN DESCRIPTION
Pin Number
Pin Name
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias ACcoupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01µF
capacitor. Limit current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the “Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most Negative Supply. Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
VCC
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1µF and
0.01µF low ESR capacitors.
14, 15
CASCADE,
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
17
FTUNE
Voltage Control Input: By varying the voltage at this pin from VCC through VEE, the delay
may be fine tuned by approximately ±15ps. Leave pin floating if not used.
20, 21
Q, /Q
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Pin Function
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
3
ECL Pro®
SY100EP196V
Micrel, Inc.
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. –0.5V to +6.0V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ +0.5V to –6.0V
Any Input Voltage (VIN)
PECL Mode ....................................... –0.5V to VCC+0.5V
NECL Mode ....................................... +0.5V to VEE–0.5V
ECL Output Current (IOUT)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
IBB Sink/Source Current .......................................... ±0.5mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature (TS) ....................... –65°C to +150°C
ESD Rating(3) ........................................................... >1.5kV
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. +3.0V to +5.5V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ –3.0V to –5.5V
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance
TQFP-32 (θJA)
Still-air ............................................................. 50°C/W
500lfpm ............................................................ 42°C/W
TQFP-32 (θJC) ..................................................... 20°C/W
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Parameter
VCC
Condition
Min
Typ
Max
Units
Power Supply Voltage (PECL)
3.0
4.5
3.3
5.0
3.6
5.5
V
V
VEE
Power Supply Voltage (NECL)
–3.6
–5.5
–3.3
–5.0
–3.0
–4.5
V
V
IEE
Power Supply Current(4)
150
175
mA
No Load, Over Supply Voltage
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Required 500lfpm air flow when using +5V or –5V power supply.
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ECL Pro®
SY100EP196V
Micrel, Inc.
(100kEP) LVPECL DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V, VEE = 0V; TA = –40°C to +85°C(5, 6)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3, 6
2155
2280
2405
mV
VOL
Output LOW Voltage
Figures 2, 3, 6
1355
1480
1605
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
Figures 1, 4
2075
1815
2000
2420
mV
mV
mV
Input LOW Voltage
PECL
CMOS
TTL
Figures 1, 4
1355
1675
1485
800
mV
mV
mV
VIL
VBB
Output Voltage Reference
1775
1875
1975
mV
VCF
Input Select Voltage
1610
1720
1825
mV
VEF
Mode Connection
1900
2000
2100
mV
VIHCMR
Input HIGH Voltage Common
Mode Range(7)
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IN
/IN
Figure 5
2.0
0.5
–150
µA
µA
Notes:
5. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to –2.2V.
7. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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ECL Pro®
SY100EP196V
Micrel, Inc.
(100kEP) PECL DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V; TA = –40°C to +85°C(8, 9)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3, 6
3855
3980
4105
mV
VOL
Output LOW Voltage
Figures 2, 3, 6
3055
3180
3305
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
Figures 1, 4
3775
2750
2000
4120
mV
mV
mV
Input LOW Voltage
PECL
CMOS
TTL
Figures 1, 4
3055
3375
2250
800
mV
mV
mV
3675
mV
5.0
V
150
µA
VIL
VBB
Output Voltage Reference
VIHCMR
Input HIGH Voltage Common
Mode Range(10)
IIH
Input HIGH Current
IIL
Input LOW Current
IN
/IN
3475
Figure 5
3575
2.0
0.5
–150
µA
µA
(100kEP) NECL DC ELECTRICAL CHARACTERISTICS
VCC = 0V, VEE = –5.5V to –3.0V; TA = –40°C to +85°C(8)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3
–1145
–1020
–895
mV
VOL
Output LOW Voltage
Figures 2, 3
–1945
–1820
–1695
mV
VIH
Input HIGH Voltage NECL
Figures 1, 4
–1225
–880
mV
VIL
Input LOW Voltage NECL
Figures 1, 4
–1945
–1625
mV
VBB
Output Voltage Reference
–1325
mV
VIHCMR
Input HIGH Voltage Common
Mode Range(11)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IN
/IN
–1525
Figure 5
–1425
VEE+2.0
0.5
–150
µA
µA
Notes:
8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to –0.5V.
10. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
11. VIHCMR minimum varies 1:1 with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal.
M9999-072706
[email protected] or (408) 955-1690
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ECL Pro®
SY100EP196V
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C(12, 13)
TA = –40°C
Symbol
Parameter
Min
Frequency(14)
Typ
fMAX
Maximum
tPD
Propagation Delay
IN to Q; D[0-10]=0
IN to Q; D[0-10]=1023
/EN to Q: D[0-10]=0
D10 to CASCADE
1650
9500
1600
300
2000
11500
2150
420
tRANGE
Programmable Range
tPD(max)-tPD(min)
7850
9450
∆t
Step Delay(15)
Linearity(16)
tSKEW
Duty Cycle Skew(17)
Min
2.5
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
Lin
TA = +25°C
Max
Typ
TA = +85°C
Max
Min
2.5
2450
13500
2600
500
1800
9800
1800
325
2050
12200
2300
450
8200
10000
Typ
Max
2.5
2600
14000
2800
550
Unit
GHz
1950
10600
2000
325
2250
13300
2500
525
2750
15800
3000
625
ps
ps
ps
ps
8850
10950
ps
9
25
42
75
142
296
532
1080
2100
4250
10
26
42
80
143
300
540
1095
2150
4300
10
27
43
81
150
310
565
1140
2250
4500
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
±10
±10
±10
%LSB
tPHL-tPLH
25
ps
tS
Setup Time
D to LEN
D to IN(18)
/EN to IN(19)
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
ps
ps
ps
tH
Hold Time
LEN to D
IN to /EN(20)
200
400
60
250
200
400
100
280
200
400
80
300
ps
ps
tR
Release Time
/EN to IN(21)
SETMAX to LEN
SETMIN to LEN
400
350
200
275
400
350
500
250
200
400
350
300
335
ps
ps
ps
tJIT
Cycle-to-Cycle Jitter(22)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Time
20% to 80% (Q)
20% to 80% (CASCADE)
150
0.2
<1
800
1200
180
180
250
250
150
0.2
<1
800
1200
210
210
300
300
150
0.2
<1
psRMS
800
1200
mV
230
230
325
325
ps
ps
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source.
14. Refer to “Typical Operating Characteristics” for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
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7
ECL Pro®
SY100EP196V
Micrel, Inc.
TYPICAL OPERATING CHARACTERISTICS
VCC = 5.5V
700
160
600
140
500
120 V = 5.0V
CC
100
400
300
80
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
M9999-072706
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0
-5
-10
–40
-15
25
-20
20
0
10
5
VCC = 3.0V
40
100
0
VCC = 3.3V
60
200
Propagation Delay
vs. FTUNE Voltage
15
DELAY (ps)
180
IEE (mA)
OUTPUT SWING (mV)
Supply Current
vs. Temperature
Q, /Q Output Swing
vs. Frequency
800
0
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
8
-25
0
85
0.5 1 1.5 2 2.5 3
FTUNE VOLTAGE (V)
3.5
ECL Pro®
SY100EP196V
Micrel, Inc.
VCC
VCC
5;-2'$8
75k9
Q, CASCADE
IN
/Q, /CASCADE
/IN
75k9
75k9
SY100EP196V
Figure 2. Emitter Output Structure
Figure 1a. Differential Input Structure
VCC
SY100EP196V
/EN
LEN
SETMIN
SETMAX
D[0:10]
Q
/Q
CASCADE
/CASCADE
VBB
VOH
VOL
0V
Figure 3a. Output Levels, PECL, LVPECL
75k9
Q
/Q
CASCADE
/CASCADE
Figure 1b. Single-Ended Input Structure
0V
VOH
VOL
Figure 3b. Output Levels, NECL
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ECL Pro®
SY100EP196V
Micrel, Inc.
VCC
VIH(MAX)
0V
VIH(MAX)
Invalid
Logic High
Logic High
VIH(MIN)
VIL(MAX)
VIH(MIN)
VIL(MAX)
Invalid
Invalid
Logic Low
Logic Low
VIL(MIN)
0V
Invalid
VIL(MIN)
VEE
Invalid
Invalid
Figure 4c. Input Levels, NECL
Figure 4a. Input Levels, PECL
IN
VIHCMR
Invalid
VCC
/IN
Logic High
VIH(MIN)
VIL(MAX)
0V
Invalid
Figure 5a. Input Common Mode, PECL, LVPECL
Logic Low
0V
Invalid
0V
Figure 4b. Input Levels, CMOS, TTL
IN
VIHCMR
/IN
VIHCMR
Figure 5b. Input Common Mode, NECL
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ECL Pro®
SY100EP196V
Micrel, Inc.
TERMINATING PECL
+3.3V
+3.3V
ZO = 50Ω
R1
130Ω
R1
130Ω
R2
82Ω
R2
82Ω
+3.3V
ZO = 50Ω
Vt = VCC –2V
Figure 6a. Parallel Termination—Thevenin Equivalent
Note:
1. For +5.0V systems: R1 = 82Ω, R2 = 130Ω.
+3.3V
+3.3V
Z = 50Ω
Z = 50Ω
50Ω
50Ω
“Source”
“Destination”
50Ω
Rb
C1 (optional)
0.01µF
Figure 6b. Three-Resistor “Y-Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +5V systems, Rb = 110Ω.
+3.3V
+3.3V
+3.3V
R1
130Ω
Q
R1
130Ω
+3.3V
ZO = 50Ω
50Ω
/Q
VBB
Vt = VCC –2V
0.01µF
R2
82Ω
R2
82Ω
+3.3V
Figure 6c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. Micrel's differential I/O logic devices include a VBB reference pin .
3. Connect unused input through 50Ω to VBB. Bypass with a 0.01µF capacitor to VCC, not GND, as PECL is referenced to VCC.
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ECL Pro®
SY100EP196V
Micrel, Inc.
VCC +3.3V
VCC
LVPECL
Signals
0.01µF
PECL
Output
D[0:10]
IN
VCF
/IN
VEF
SY100EP196V
VBB
VEE 0V
SY100EP196V
Figure 9b. Connecting LVPECL Signals
to the D Inputs
Figure 7a. Interfacing to a
Single-Ended PECL Signal
VCC +3.3V or +5.0V
VCC
0.01µF
CMOS
Inputs
D[0:10]
IN
PECL
Output
NC VCF
/IN
NC VEF
SY100EP196V
VBB
SY100EP196V
VEE 0V
Figure 7b. Interfacing to and Inverting
a Single-Ended PECL Signal
Figure 9c. Connecting CMOS Signals
to the D Inputs
Note: VCF and VEF are not connected
IN
VCC +3.3V
/IN
VCC
50
50
0.01µF
VBB
TTL
Inputs
SY100EP196V
D[0:10]
Figure 8. Re-Biasing an AC-Coupled Signal
VCF
NC VEF
1.5k9
VCC +5.0V
SY100EP196V
0V
PECL
Signals
VEE 0V
D[0:10]
Figure 9d. Connecting TTL Signals
to the D Inputs with VCC = 3.3V
VCF
VCC +5.0V
VEF
SY100EP196V
TTL
Inputs
VEE 0V
Figure 9a. Connecting PECL Signals
to the D Inputs
D[0:10]
VCF
NC VEF
5009
SY100EP196V
0V
VEE 0V
Figure 9e. Connecting TTL Signals
to the D Inputs with VCC = 5.0V
M9999-072706
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ECL Pro®
SY100EP196V
Micrel, Inc.
FUNCTIONAL DESCRIPTION
SY100EP196V is a programmable delay line, varying the
delay of a PECL or NECL input signal by any amount between
about 2.2ns and 12.2ns. A 10-bit digital control register affords
delay steps of approximately 10ps.
SY100EP196V implements the delay using a multiplexer
chain and a set of fixed delay elements. Under digital control,
various subsets of the delay elements are included in the
signal chain. To simplify interfacing, the 10-bit digital delay
control word interfaces to PECL, CMOS, or TTL interface
standards.
Since multiplexers must appear in the delay path,
SY100EP196V has a minimum delay of about 2.2ns. Delays
below this value are not possible. In addition, when cascading
multiple SY100EP196V to extend the delay range, the
minimum delay is about 2.2ns times the number of
SY100EP196V in cascade. An eleventh control bit, D[10],
along with the CASCADE and /CASCADE outputs and the
SETMIN and SETMAX inputs, simplifies the task of cascading.
Signal Path Logic Standard
The signal path, from IN, /IN to Q, /Q, interfaces to PECL,
LVPECL, or NECL signals, as shown in Table 6. The choice
of signal path logic standard may limit possible choices for
the delay control inputs, D.
Input Enable
The /EN input gates the signal at IN, /IN. When disabled,
the input is effectively gated out, just as if a logic low was
being provided to SY100EP196V.
Digital Control Logic Standard
When used in systems where VEE connects to ground,
SY100EP196V may interface either to PECL, CMOS, or TTL
on its D[0:10] inputs. To this end, the VCF pin sets the
threshold at which the D inputs switch between logic low and
logic high.
As shown in Table 3, connecting VCF to VEF sets the
threshold to PECL (if VCC is 5V) or LVPECL (if VCC is 3.3V).
Leaving VCF and VEF open yields a threshold suitable for
detecting CMOS output logic levels. Leaving VEF open and
connecting VCF to a 1.5V source allows the D inputs to accept
TTL signals.
Logic Standard
VCF Connects To
ECL, PECL
VEF
CMOS
No Connect
TTL
1.5V Source
Table 3. Digital Control Standard Truth Table
If a 1.5V source is not available, connecting VCF to VEE
through an appropriate resistor will bias VCF at about 1.5V.
The value of this resistor depends on the VCC supply, as
indicated in Table 4.
VCC
Resistor Value
3.3V
1.5kΩ
5.0V
500Ω
/EN
Value at Q, /Q
L
IN, /IN Delayed
Table 4. Resistor Values for TTL Input
H
Logic Low Delayed
Cascade Logic
SY100EP196V is designed to ease cascading multiple
devices in order to achieve a greater delay range. The SETMIN
and SETMAX pins accomplish this, as set out in the
applications section below. SETMIN and SETMAX override
the delay by changing the value in the D latch register. Table
5 lists the action of these pins.
Table 1. /EN Truth Table
Digital Control Latch
SY100EP196V can capture the digital delay control word
into its internal 11-bit latch, 10 bits for D[0:9], and an extra bit
for the D[10] cascade control. The LEN input controls the
action of this latch, as per Table 2.
Note that the LEN input is always PECL, LVPECL, or
NECL, the same as the IN, /IN signal pair. The 11-bit delay
control word, however, may also be CMOS or TTL.
LEN
Latch Action
L
Pass Through D[0:10]
H
Latch D[0:10]
SETMAX
Nominal Delay (ps)
L
L
As per D Latch
L
H
2200 + 10 × 1024
H
L
2200
H
H
Not Allowed
Table 5. SETMIN and SETMAX Action
Table 2. LEN Truth Table
The nominal delay value is based on the binary value in
D[0:9], where D[0] is the least significant bit, and D[9] is the
most significant bit. This delay from IN, /IN to Q, /Q is about:
∆t = 2200 + 10 × value(D[9:0]) + delay(FTUNE),ps
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SETMIN
13
ECL Pro®
SY100EP196V
Micrel, Inc.
Fine Tune Control
In addition to the digital delay control, the FTUNE input
permits a continuous variation in delay. Though it may be
set to any voltage between VCC and VEE, most of the delay
variation occurs between VEE and VEE + 1.5V. Refer to
“Typical Operating Characteristics.” For convenience, a VCC
of 3.3V is assumed. Typically, the FTUNE input will be fed
by a DAC whose purpose is to provide extremely fine delay
under digital control.
Signal Path Logic Standard
VCC
VEE
Delay Control Input Choices
PECL
+4.5V to +5.5V
0V
PECL, CMOS, TTL
LVPECL
+3.0V to +3.6V
0V
LVPECL, CMOS, TTL
NECL
0V
–3.0 to –5.5V
NECL
Table 6. Signal Path Logic Standard
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ECL Pro®
SY100EP196V
Micrel, Inc.
APPLICATIONS INFORMATION
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP196V data inputs and outputs.
VBB Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP196V. When unused,
this pin should be left unconnected. The two common uses
for VBB are to handle a single-ended PECL input, and to rebias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, VBB is used
to bias the unused input. Please refer to Figures 9. The
PECL signal driving SY100EP196V may optionally be
inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 10, to re-bias IN, /IN. This ensures that
SY100EP196V inputs are within its acceptable common
mode range.
In all cases, VBB current sinking or sourcing must be
limited to 0.5mA or less.
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP196V VEE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect VCF and
VEF for all possible cases.
Cascading
Two or more SY100EP196V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP196V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP196V. Using this internal circuitry, SY100EP196V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP196V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
Control Word (11bits)
DAC
SY100EP196V
SY100EP196V
C[10]
FTUNE
C[9:0]
D[10]
FTUNE
D[9:0]
#2
#1
IN
Q
IN
Q
/IN
/Q
/IN
/Q
SETMIN
/CASCADE
SETMAX
CASCADE
Figure 10a. Cascading Two SY100EP196V
Control Word (12bits)
DAC
SY100EP196V
SY100EP196V
C[11]
D[10]
SY100EP196V
FTUNE
C[10]
C[9:0]
#3
D[10]
D[9:0]
#2
IN
Q
IN
/IN
/Q
/IN
SETMIN
SETMAX
FTUNE
#1
Q
/Q
SETMIN
/CASCADE
SETMAX
CASCADE
IN
Q
/IN
/CASCADE
/Q
CASCADE
Figure 10b. Cascading Three SY100EP196V
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ECL Pro®
SY100EP196V
Micrel, Inc.
Control Word (12bits)
SY100EP196V
SY100EP196V
DAC
SY100EP196V
C[11]
D[10]
SY100EP196V
FTUNE
C[10]
C[9:0]
IN
Q
IN
Q
IN
/IN
/Q
/IN
/Q
/IN
SETMIN
SETMIN
SETMAX
SETMAX
Q
/Q
SETMIN
/CASCADE
SETMAX
CASCADE
D[10]
FTUNE
D[9:0]
IN
Q
/IN
/CASCADE
/Q
CASCADE
Figure 10c. Cascading Four SY100EP196V
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY100EP195VTI
3.3V/5V 2.5GHz Programmable Delay Chip
http://www.micrel.com/product-info/products/sy100ep195v.shtml
SY55856UHI
2.5V/3.3V 2.5GHz Differential 2-Channel
Precision CML Delay Line
http://www.micrel.com/product-info/products/sy55856u.shtml
M9999-072706
[email protected] or (408) 955-1690
16
ECL Pro®
SY100EP196V
Micrel, Inc.
D[11]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Control Inputs
D[10]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
D[9:0]
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
One Chip
2,200
2,210
2,220
2,240
2,280
2,360
2,520
2,840
3,480
4,760
7,320
12,430
Nominal Delay (ps)
Two Chips
Three Chips
4,400
6,600
4,410
6,610
4,420
6,620
4,440
6,640
4,480
6,680
4,560
6,760
4,720
6,920
5,040
7,240
5,680
7,880
6,960
9,160
9,520
11,720
14,630
16,830
14,640
16,840
14,650
16,850
14,660
16,860
14,680
16,880
14,720
16,920
14,800
17,000
14,960
17,160
15,280
17,480
15,920
18,120
17,200
19,400
19,760
21,960
24,870
27,070
27,080
27,090
27,100
27,120
27,160
27,240
27,400
27,720
28,360
29,640
32,200
37,310
27,080
27,090
27,100
27,120
27,160
27,240
27,400
27,720
28,360
29,640
32,200
37,310
Table 7. List of Nominal Delay Values for Cascaded SY100EP196V
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Four Chips
8,800
8,810
8,820
8,840
8,880
8,960
9,120
9,440
10,080
11,360
13,920
19,030
19,040
19,050
19,060
19,080
19,120
19,200
19,360
19,680
20,320
21,600
24,160
29,270
29,280
29,290
29,300
29,320
29,360
29,440
29,600
29,920
30,560
31,840
34,400
39,510
39,520
39,530
39,540
39,560
39,600
39,680
39,840
40,160
40,800
42,080
44,640
49,750
ECL Pro®
SY100EP196V
Micrel, Inc.
32-PIN TQFP (T32-1)
Rev. 01
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
M9999-072706
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