NB100LVEP56 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both LVECL and LVCMOS input voltage levels. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input operation, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. • • • • • March, 2014 − Rev. 10 N100 VP56 ALYWG G TSSOP−20 DT SUFFIX CASE 948E 24 24 Maximum Input Clock Frequency > 2.5 GHz Typical Maximum Input Data Rate > 2.5 Gb/s Typical 525 ps Typical Propagation Delays Low Profile QFN Package PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V Separate, Common Select, and Individual Select (Compatible with ECL and CMOS Input Voltage Levels) Q Output Will Default LOW with Inputs Open or at VEE Multiple VBB Outputs These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 MARKING DIAGRAMS* 1 Features • • • • • http://onsemi.com 1 24 PIN QFN MN SUFFIX CASE 485L A L Y W G N100 VP56 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. 1 Publication Order Number: NB100LVEP56/D NB100LVEP56 Table 1. PIN FUNCTION DESCRIPTION ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Pin No. TSSOP QFN Name I/O Default State 14,20 3,9,18,19, 20 VCC − − Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. 11 15,24 VEE − − Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. 3,8 6,12 VBB0, VBB1 − − ECL Reference Voltage Output 1 4 D0a ECL Input Low Noninverted Differential Data a Input to MUX 0. Internal 75 kW to VEE. 2 5 D0a ECL Input High Inverted Differential Data a Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. 4 7 D0b ECL Input Low Noninverted Differential Data b Input to MUX 0. Internal 75 kW to VEE. 5 8 D0b ECL Input High Inverted Differential Data b Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. 6 10 D1a ECL Input Low Noninverted Differential Data a Input to MUX 1. Internal 75 kW to VEE. 7 11 D1a ECL Input High Inverted Differential Data a Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. 9 13 D1b ECL Input Low Noninverted Differential Data b Input to MUX 1. Internal 75 kW to VEE. 10 14 D1b ECL Input High Inverted Differential Data b Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. 19 2 Q0 ECL Output − Noninverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. 18 1 Q0 ECL Output − Inverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. 13 17 Q1 ECL Output − Noninverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. 12 16 Q1 ECL Output − Inverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. 17 23 SEL0 ECL, CMOS Input Low Noninverted Differential Select Input to MUX 0. Internal 75 kW to VEE. 16 22 COM_SEL ECL, CMOS Input Low Noninverted Differential Common Select Input to Both MUX. Internal 75 kW to VEE. 15 21 SEL1 ECL, CMOS Input Low Noninverted Differential Select Input to MUX 1. Internal 75 kW to VEE. N/A − EP − Description Exposed Pad. (Note 1) 1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit. http://onsemi.com 2 NB100LVEP56 D0a R1 D0b R1 R2 1 Q0 Q0 Table 2. TRUTH TABLE 0 D0a R1 SEL0 R2 R1 D0b R1 SEL0 SEL1 COM_SEL Q0, Q0 Q1, Q1 X L L H H X L H H L H L L L L a b b a a a b a a b COM_SEL R1 D1a R1 D1b R1 SEL1 R2 R1 1 Q1 Q1 0 D1a R1 VCC VEE R2 D1b R1 COM VEE SEL0 SEL SEL1 VCC VCC VCC Q0 Q0 SEL0 COM_SEL SEL1 VCC Q1 Q1 VEE Figure 1. Logic Diagram 20 19 18 17 16 15 14 13 12 11 24 2 3 4 5 6 7 8 9 10 D0a D0a VBBO D0b D0b D1a D1a VBB1 D1b D1b 22 21 20 19 Q0 1 18 VCC Q0 2 17 Q1 VCC 3 16 Q1 D0a 4 15 VEE D0a 5 14 D1b VBB0 6 13 D1b NB100LVEP56 1 23 Exposed Pad (EP) NB100LVEP56 7 Figure 2. TSSOP−20 Lead Pinout (Top View) 8 9 10 11 12 D0b D0b VCC D1a D1a VBB1 Figure 3. QFN−24 Lead Pinout (Top View) Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (R1) Internal Input Pullup Resistor ESD Protection (R2) 37 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) TSSOP−20 QFN−24 Flammability Rating 75 kW Oxygen Index: 28 to 34 Transistor Count > 2 kV > 150 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 UL 94 V−0 @ 0.125 in 354 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NB100LVEP56 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE Negative Mode Power Supply VCC = 0 V −6 V VI Positive Mode Input Voltage Negative Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source "0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) JEDEC 51−3 (1S − Single Layer Test Board) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 50 °C/W °C/W qJA Thermal Resistance (Junction−to−Ambient) JEDEC 51−6 (2S2P−Multi Layer Test Board) with Filled Thermal Vias 0 lfpm 500 lfpm QFN−24 QFN−24 37 32 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 QFN−24 23 to 41 11 °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2) −40°C Symbol Min Characteristic Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Negative Power Supply Current 35 45 55 35 45 55 35 48 58 mA VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 3) 555 775 900 555 775 900 555 775 900 mV VIH Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) (Note 4) 1335 1335 VCC 1620 1335 1335 VCC 1620 1275 1275 VCC 1620 mV VIL Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) (Note 4) VEE 555 875 875 VEE 555 875 875 VEE 555 875 875 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current (@VIH) 150 mA IIL Input LOW Current (@VIL) 150 D D SEL 0.5 −150 −150 150 0.5 −150 −150 0.5 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.125 V to +1.3 V. 3. All loading with 50 W to VCC − 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB100LVEP56 Table 6. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 35 45 55 35 45 55 35 48 58 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 7) 1355 1575 1700 1355 1575 1700 1355 1575 1700 mV VIH Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) 2135 2135 VCC 2420 2135 2135 VCC 2420 2135 2135 VCC 2420 mV VIL Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) VEE 1355 1675 1675 VEE 1355 1675 1675 VEE 1355 1675 1675 mV VBB Output Reference Voltage (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current (@VIH) 150 mA IIL Input LOW Current (@VIL) 1875 1.2 1875 150 D D SEL 1875 150 0.5 −150 −150 0.5 −150 −150 0.5 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.5 V to −0.3 V. 7. All loading with 50 W to VCC − 2.0 V. 8. Single−Ended input operation is limited to VCC w 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 35 45 55 35 45 55 35 48 58 mA VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1945 −1725 −1600 −1945 −1725 −1600 −1945 −1725 −1600 mV VIH Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) −1165 −1165 VCC −880 −1165 −1165 VCC −880 −1165 −1165 VCC −880 VIL Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) VEE −1945 −1600 −1600 VEE −1945 −1600 −1600 VEE −1945 −1600 −1600 VBB Output Reference Voltage (Note 12) −1525 −1325 −1525 −1325 −1525 VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) IIH Input HIGH Current (@VIH) IIL Input LOW Current (@VIL) −1425 VEE+1.2 0.0 150 D D SEL 0.5 −150 −150 −1425 VEE+1.2 0.0 150 0.5 −150 −150 −1425 VEE+1.2 0.5 −150 −150 mV mV −1325 mV 0.0 V 150 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC − 2.0 V. 12. Single−Ended input operation is limited to VEE from −3.0 V to −5.5 V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB100LVEP56 Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 V to −3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14) −40°C Characteristic Symbol VOUTPP Output Voltage Amplitude (See Figure 4) fin v 1 GHz fin = 2 GHz fin = 2.5 GHz tPLH, tPHL Propagation Delay to Output Differential tSkew Pulse Skew (Note 15) Within Device Input Skew (Note 16) Within Device Output Skew (Note 17) Device−to−Device Skew (Note 18) tJITTER RMS Random Clock Jitter (Note 19) @ v1.0 GHz @ v1.5 GHz @ v2.0 GHz @ v2.5 GHz Peak−to−Peak Data Dependent Jitter (Note 20) @ 0.5 GHz @ 1.25 GHz @ 2.488 GHz D to Q, Q SEL to Q, Q COM_SEL to Q, Q VINPP Input Voltage Swing (Differential Configuration) (Note 21) tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) Q, Q 25°C Min Typ Max Min Typ 525 500 400 700 600 500 550 500 350 700 600 450 375 575 550 500 775 750 625 975 950 400 625 600 525 825 800 10 5 15 50 50 30 50 200 10 5 15 50 0.269 0.306 0.250 0.339 0.4 0.4 0.4 0.8 0.307 0.303 0.305 0.895 4.1 32.2 30.8 16 80 66 150 800 1200 60 110 150 85°C Max Min Typ 500 400 200 700 500 300 450 700 700 575 900 900 700 1100 1100 10 5 15 50 50 30 50 200 0.4 0.4 0.5 2.0 0.371 0.391 0.722 2.443 0.5 0.6 1.2 7.7 4.6 22.6 27.2 15 63 56 4.4 22 24.4 16 53 54 150 800 1200 150 800 1200 60 120 170 90 140 230 650 1025 1000 Max Unit mV ps ps ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 150 ps (20% − 80%). 15. Pulse Skew |tPLH − tPHL| 16. Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input. 17. Worst case difference between Q0 and Q1 outputs. 18. Skew is measured between outputs under identical transitions. 19. Additive RMS jitter with 50% Duty Cycle Clock Signal. 20. Additive Peak−to−Peak jitter with input NRZ data at PRBS 231−1. 21. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 850 750 Q AMP (mV) 650 550 450 350 250 0.5 1.0 1.5 2.0 INPUT FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at VCC = 2.5 V, 255C http://onsemi.com 6 2.5 NB100LVEP56 D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 5. AC Reference Measurement Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 7 NB100LVEP56 ORDERING INFORMATION Package Shipping† NB100LVEP56DTG Device TSSOP−20 (Pb−Free) 75 Units / Rail NB100LVEP56DTR2G TSSOP−20 (Pb−Free) 2500 Tape & Reel NB100LVEP56MNG QFN−24 (Pb−Free) 92 Units / Rail NB100LVEP56MNR2G QFN−24 (Pb−Free) 3000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 NB100LVEP56 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB100LVEP56 PACKAGE DIMENSIONS QFN24, 4x4, 0.5P CASE 485L ISSUE B D PIN 1 REFEENCE 2X 0.15 C 2X ÉÉ ÉÉ ÉÉ 0.15 C L A B DETAIL A E ALTERNATE CONSTRUCTIONS ÉÉÉ ÉÉÉ ÇÇÇ ÇÇÇ EXPOSED Cu DETAIL B 0.10 C A3 ÉÉÉ ÉÉÉ ÇÇÇ A1 SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.05 0.15 RECOMMENDED SOLDERING FOOTPRINT D2 DETAIL A DIM A A1 A3 b D D2 E E2 e L L1 ALTERNATE TERMINAL CONSTRUCTIONS C A1 SIDE VIEW MOLD CMPD A3 DETAIL B A NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 TOP VIEW 0.08 C L L 24X 7 4.30 24X 0.55 2.90 13 E2 1 1 24 19 e e/2 BOTTOM VIEW 24X b 0.10 C A B 0.05 C 4.30 2.90 NOTE 3 0.50 PITCH 24X 0.32 DIMENSIONS: MILLIMETERS ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP56/D