MC100LVEL17 3.3VECL Quad Differential Receiver Description The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a −3.3 V or +3.3 V supply voltage. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. http://onsemi.com SO−20 WB DW SUFFIX CASE 751D Features • • • • • • • • 325 ps Propagation Delay High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors D Inputs; Pullup and Pulldown on D Inputs Q Output will Default LOW with Inputs Open or at VEE Pb−Free Packages are Available* MARKING DIAGRAM* 20 100LVEL17 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 7 1 Publication Order Number: MC100LVEL17/D MC100LVEL17 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 D1 D1 D2 D2 D3 D3 VBB Table 1. PIN DESCRIPTION PIN FUNCTION Dn, Dn Qn, Qn VBB VCC VEE ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V > 4 kV Level 1 UL 94 V−0 @ 0.125 in 141 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVEL17 Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SO−20L SO−20L 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SO−20L 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2) −40°C Symbol Characteristic Typ Max 26 31 Max 26 31 2215 2295 2420 2275 2345 2420 Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 VIH Input HIGH Voltage (Single−Ended) 2135 2420 VIL VBB Input LOW Voltage (Single−Ended) 1490 Output Voltage Reference 1.92 VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 4) Vpp < 500 mV Vpp y 500 mV Power Supply Current VOH Output HIGH Voltage (Note 3) VOL IIH Input HIGH Current IIL Input LOW Current Min 85°C Typ IEE Min 25°C Typ Max Unit 27 33 mA 2275 2345 2420 mV 1680 1490 1595 1680 mV 2135 2420 2135 2420 mV 1825 1490 1825 1490 1825 mV 2.04 1.92 2.04 1.92 2.04 V 1.3 2.9 1.2 2.9 1.2 2.9 V 1.5 2.9 1.4 2.9 1.4 2.9 V 150 mA 150 Min 150 Dn 0.5 0.5 0.5 mA Dn −300 −300 −300 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 3 MC100LVEL17 Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 5) −40°C Symbol Characteristic Min 25°C Typ Max 26 31 Min 85°C Typ Max 26 31 Min Typ Max Unit 27 33 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 6) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 7) Vpp < 500 mV −2.0 −0.4 −2.1 −0.4 −2.1 −0.4 V Vpp y 500 mV −1.8 −0.4 −1.9 −0.4 −1.9 −0.4 V 150 mA IIH Input HIGH Current IIL Input LOW Current 150 150 Dn 0.5 0.5 0.5 mA Dn −300 −300 −300 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 8) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max 1.75 Unit GHz fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay D to Q tSKEW Skew tJITTER Random Clock Jitter (RMS) VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 280 550 280 550 280 550 ps Diff S.E. 330 280 530 580 Output−to−Output (Note 9) Part−to−Part (Diff) (Note 9) Duty Cycle (Diff) (Note 10) 350 300 550 600 75 200 25 360 310 75 200 25 560 610 ps 75 200 25 ps 0.7 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary ±0.3 V. 9. Skews are valid across specified voltage range, part−to−part skew is for a given temperature. 10. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 11. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈ 40. http://onsemi.com 4 MC100LVEL17 Zo = 50 W Q D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC100LVEL17DW SO−20 WB 38 Units / Rail MC100LVEL17DWG SO−20 WB (Pb−Free) 38 Units / Rail MC100LVEL17DWR2 SO−20 WB 1000 / Tape & Reel MC100LVEL17DWR2G SO−20 WB (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVEL17 PACKAGE DIMENSIONS SO−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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