ESD7351, SZESD7351 Series Transient Voltage Suppressors The ESD7351 Series is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. http://onsemi.com MARKING DIAGRAMS 2 SOD−323 CASE 477 1 AF M • • • • • • • • • Low Capacitance (0.6 pF Max, I/O to GND) Low Clamping Voltage Stand−off Voltage: 3.3 V Low Leakage Response Time is < 1 ns Low Dynamic Resistance < 1 W IEC61000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 2 SOD−523 CASE 502 1 AE 1 2 SOD−923 CASE 514AB X, XX M M Features AD M = Specific Device Code = Date Code PIN CONFIGURATION AND SCHEMATIC Typical Applications • RF Signal ESD Protection • RF Switching, PA, and Antenna ESD Protection • Near Field Communications 1 Cathode 2 Anode MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Value Unit ±20 ±20 kV °PD° 150 mW TJ, Tstg −55 to +150 °C TL 260 °C Contact Air Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Junction and Storage Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 2 1 Publication Order Number: ESD7351/D ESD7351, SZESD7351 Series ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IF Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT VC VBR VRWM Working Peak Reverse Voltage V IR VF IT Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current *See Application Note AND8308/D for detailed explanations of datasheet parameters. IPP Uni−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage (Note 2) Symbol Conditions Min Typ VRWM VBR IT = 1 mA Max Unit 3.3 V 50 nA 5.0 V Reverse Leakage Current IR VRWM = 3.3 V < 1.0 Clamping Voltage (Note 3) VC IPP = 1 A 8.0 V Clamping Voltage (Note 3) VC IPP = 3 A 10 V Junction Capacitance CJ VR = 0 V, f = 1 MHz VR = 0 V, f < 1 GHz 0.43 0.43 0.6 0.6 pF Dynamic Resistance RDYN TLP Pulse 0.35 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. http://onsemi.com 2 ESD7351, SZESD7351 Series 1.0 1.E−03 1.E−04 0.8 CAPACITANCE (pF) 1.E−05 I (A) 1.E−06 1.E−07 1.E−08 1.E−09 1.E−10 0.6 0.4 0.2 1.E−11 1.E−12 0 1 2 3 4 5 6 7 0 0 8 0.5 1 1.5 2 2.5 V (V) VBias (V) Figure 1. IV Characteristics Figure 2. CV Characteristics 3 3.5 2.0 2 1.8 0 1.6 CAPACITANCE (pF) −2 TBD −6 −8 −10 1.4 1.2 1.0 0.8 0.6 0.4 −12 0.2 −14 1.E+08 1.E+09 0.0 0.5 1.E+10 1.5 2.5 FREQUENCY (Hz) 4.5 5.5 6.5 7.5 8.5 9.5 FREQUENCY (GHz) Figure 3. RF Insertion Loss Figure 4. Capacitance over Frequency 8 16 −16 14 8 6 10 4 8 6 2 4 EQUIVALENT VIEC (kV) TLP CURRENT (A) −14 12 TLP CURRENT (A) 3.5 2 −12 6 −10 −8 4 −6 −4 2 −2 0 0 NOTE: 2 4 6 8 10 12 14 16 18 0 20 0 0 2 4 6 8 10 12 14 16 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 5. Positive TLP I−V Curve Figure 6. Negative TLP I−V Curve 18 0 20 TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. http://onsemi.com 3 EQUIVALENT VIEC (kV) dB −4 ESD7351, SZESD7351 Series IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 7. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 8. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 10 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. L S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Transmission Line Pulse (TLP) Measurement Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained Figure 9. Simplified Schematic of a Typical TLP System http://onsemi.com 4 ESD7351, SZESD7351 Series Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms ORDERING INFORMATION Package Shipping† ESD7351HT1G, SZESD7351HT1G* SOD−323 (Pb−Free) 3000 / Tape & Reel ESD7351XV2T1G, SZESD7351XV2T1G* SOD−523 (Pb−Free) 3000 / Tape & Reel ESD7351P2T5G, SZESD7351P2T5G* SOD−923 (Pb−Free) 8000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. http://onsemi.com 5 ESD7351, SZESD7351 Series PACKAGE DIMENSIONS SOD−323 CASE 477−02 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. LEAD THICKNESS SPECIFIED PER L/F DRAWING WITH SOLDER PLATING. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 5. DIMENSION L IS MEASURED FROM END OF RADIUS. HE D b 1 2 E MILLIMETERS DIM MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.05 0.10 A3 0.15 REF b 0.25 0.32 0.4 C 0.089 0.12 0.177 D 1.60 1.70 1.80 E 1.15 1.25 1.35 L 0.08 HE 2.30 2.50 2.70 A3 A C NOTE 3 L NOTE 5 A1 SOLDERING FOOTPRINT* 0.63 0.025 0.83 0.033 1.60 0.063 2.85 0.112 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES NOM MAX 0.035 0.040 0.002 0.004 0.006 REF 0.010 0.012 0.016 0.003 0.005 0.007 0.062 0.066 0.070 0.045 0.049 0.053 0.003 0.090 0.098 0.105 MIN 0.031 0.000 ESD7351, SZESD7351 Series PACKAGE DIMENSIONS SOD−523 CASE 502 ISSUE E −X− D NOTES: 6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 7. CONTROLLING DIMENSION: MILLIMETERS. 8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. −Y− E 2X b 0.08 1 M 2 X Y DIM A b c D E HE L L2 TOP VIEW A c HE RECOMMENDED SOLDERING FOOTPRINT* SIDE VIEW 2X 2X 0.48 L L2 BOTTOM VIEW 1.80 2X 0.40 PACKAGE OUTLINE 2X MILLIMETERS MIN NOM MAX 0.50 0.60 0.70 0.25 0.30 0.35 0.07 0.14 0.20 1.10 1.20 1.30 0.70 0.80 0.90 1.50 1.60 1.70 0.30 REF 0.15 0.20 0.25 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 ESD7351, SZESD7351 Series PACKAGE DIMENSIONS SOD−923 CASE 514AB ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. −X− D −Y− E 1 2X b 0.08 X Y 2 DIM A b c D E HE L L2 TOP VIEW A c MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.15 0.20 0.25 0.07 0.12 0.17 0.75 0.80 0.85 0.55 0.60 0.65 0.95 1.00 1.05 0.19 REF 0.05 0.10 0.15 SOLDERING FOOTPRINT* HE SIDE VIEW 1.20 2X 2X 2X 0.36 L PACKAGE OUTLINE 2X INCHES MIN NOM MAX 0.013 0.015 0.016 0.006 0.008 0.010 0.003 0.005 0.007 0.030 0.031 0.033 0.022 0.024 0.026 0.037 0.039 0.041 0.007 REF 0.002 0.004 0.006 L2 0.25 DIMENSIONS: MILLIMETERS See Application Note AND8455/D for more mounting details BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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