ESD11N5.0ST5G Transient Voltage Suppressors Micro−Packaged Diodes for ESD Protection The ESD11N is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. http://onsemi.com Specification Features • • • • • • • • • MARKING DIAGRAM Low Capacitance 0.6 pF Low Clamping Voltage Small Body Outline Dimensions: 0.60 mm x 0.30 mm Low Body Height: 0.3 mm Stand−off Voltage: 5.0 V Low Leakage Response Time is < 1 ns IEC61000−4−2 Level 4 ESD Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Mechanical Characteristics MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C MAXIMUM RATINGS Rating Symbol Contact Air Value Unit ±8.0 ±15 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 250 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −40 to +125 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) XXXX YYY XXXX YYY = Specific Device Code = Year Code ORDERING INFORMATION Device Package Shipping† ESD11N5.0ST5G DSN2 (Pb−Free) 5000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Device Meets MSL 1 Requirements IEC 61000−4−2 (ESD) PIN 1 DSN2 CASE 152AA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 2 1 Publication Order Number: ESD11N5.0S/D ESD11N5.0ST5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM VBR IT I Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Device ESD11N5.0ST5G VRWM (V) IR (mA) @ VRWM VBR (V) @ IT (Note 2) IT Device Marking Max Max Min mA Typ Max N5S0 5.0 1.0 5.8 1.0 0.6 0.9 C (pF) VC Per IEC61000−4−2 (Note 3) Figures 1 and 2 See Below 2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 3. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESD11N5.0ST5G IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 ESD11N5.0ST5G PACKAGE DIMENSIONS DSN2, 0.6x0.3, 0.4P, (0201) CASE 152AA−01 ISSUE O 2X DIM A A1 b D E e L E 0.06 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D 0.06 C TOP VIEW CATHODE BAND MONTH CODING 0.05 C A 2X 0.05 C A1 DEC C SIDE VIEW L 2 2X NOV OCT SEP SEATING PLANE XXXX YYY JUN MAR FEB JAN e 1 2X MILLIMETERS MIN MAX 0.24 0.30 0.00 0.01 0.22 0.28 0.30 BSC 0.60 BSC 0.40 BSC 0.12 0.18 XXXX Y09 b 0.05 C A B BOTTOM VIEW DEVICE CODE YEAR CODE (EXAMPLE) INDICATES AUG 2009 MOUNTING FOOTPRINT* 0.28 0.75 0.28 0.30 DIMENSIONS: MILLIMETERS See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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