EtronTech
EM636165
1M x 16 bit Synchronous DRAM (SDRAM)
Etron Confidential
(Rev.3.4, Apr./2008)
Features
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Overview
Fast access time: 5/5/5.5/5.5 ns
Fast clock rate: 183/166/143 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
JEDEC standard +3.3V±0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
60-ball, 6.4x10.1mm VFBGA package
- Pb free
The EM636165 SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is internally
configured as a dual 512K word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 16 bit banks is organized as 2048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM636165 provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications
Key Specifications
EM636165
tCK3 Clock Cycle time(min.)
tRAS
tAC3
tRC
-55/6/7/7L
5.5/6/7/7
Row Active time(max.)
ns
38.5/42/49/49 ns
Access time from CLK(max.)
Row Cycle time(min.)
5/5/5.5/5.5
ns
56.5/60/70/70 ns
Ordering Information
Part Number
EM636165TS/VE-55G
EM636165TS/VE-6G
EM636165TS/VE-7G
EM636165TS/VE-7LG
Frequency
183MHz
166MHz
143MHz
143MHz
Package
TSOP II, VFBGA
TSOP II, VFBGA
TSOP II, VFBGA
TSOP II, VFBGA
TS : indicates TSOP II package
VE : indicates VFBGA package
L: indicates Low Power
G: indicates Pb and Halogen Free for TSOPII Package
indicates Pb Free for VFBGA Package
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM636165
Ball Assignment (VFBGA Top View)
Pin Assignment (TSOP II Top View)
VDD
1
50
VSS
DQ0
2
49
DQ15
DQ1
3
48
DQ14
VSSQ
4
47
VSSQ
DQ2
5
46
DQ13
DQ3
6
45
DQ12
VDDQ
7
44
VDDQ
DQ4
8
43
DQ11
DQ5
9
42
DQ10
VSSQ
10
41
VSSQ
DQ6
11
40
DQ9
DQ7
12
39
DQ8
VDDQ
13
38
VDDQ
LDQM
14
37
NC
WE#
15
36
UDQM
CAS#
16
35
CLK
RAS#
17
34
CKE
CS#
18
33
NC
A11
19
32
A9
A10/AP
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
VSS
Etron Confidential
2
1
2
A
VSS
B
…
6
7
DQ15
DQ0
VDD
DQ14
VSSQ
VDDQ.
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ.
DQ5
F
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
NC
NC
DQ7
H
NC
NC
NC
NC
J
NC
UDQM
LDQM
WE#
K
NC
CLK
RAS#.
CAS#
L
CKE
NC
NC
CS#
M
A11
A9
NC
NC
N
A8
A7
A0
P
A6
A5
A2
A1
R
VSS
A4
A3
VDD
Rev 3.4
.
.
A10
Apr. 2008
EtronTech
EM636165
Block Diagram
CLK
CLOCK
BUFFER
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
Row Decoder
CKE
2048x256 x 16
CELL ARRAY
(BANK #0)
Column Decoder
DQ0
COLUMN
COUNTER
DQ15
MODE
REGISTER
~
A0
~
A10/AP
DQs Buffer
LDQM, UDQM
ADDRESS
BUFFER
Row Decoder
A9
A11
REFRESH
COUNTER
2048x256 x 16
CELL ARRAY
(BANK #1)
Column Decoder
3
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Pin Descriptions
Table 1. Pin Details of EM636165
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
A11
Input
Bank Activate: A11 (BA) defines to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied.
A0-A10
Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 256K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BA is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BA is switched to the idle state after the
precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
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Rev. 3.4
Apr. 2008
EtronTech
LDQM,
Input
UDQM
EM636165
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
VDDQ
Supply
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
VDD
Supply
Power Supply: +3.3V ± 0.3V
VSS
Supply
Ground
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Rev. 3.4
Apr. 2008
EtronTech
EM636165
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
State
CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
Idle(3)
H
X
X
V
V
V
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
X
V
L
V
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
X
V
H
V
L
H
L
L
Read
Active(3)
H
X
X
V
L
V
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
Burst Stop
SelfRefresh Exit
(SelfRefresh)
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
Active
H
X
H
X
X
X
X
X
X
Note: 1. V=Valid, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by A11 signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
X
Power Down Mode Exit
(PowerDown)
Data Write/Output Enable
Active
H
X
L
X
X
X
Data Mask/Output Disable
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Rev. 3.4
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EtronTech
EM636165
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", A11 = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BA signals. By latching
the row address on A0 to A10 at the time of this command, the selected row access is initiated. The
read or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of
bank activation. A subsequent BankActivate command to a different row in the same bank can only
be issued after the previous active row has been precharged (refer to the following figure). The
minimum time interval between successive BankActivate commands to the same bank is defined by
tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal
circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. tRRD
(min.) specifies the minimum time required between activating different banks. After this command is
used, the Write command and the Block Write command perform the no mask write operation.
T1
T0
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
COMMAND
Bank A
Activate
Bank A
Col Addr.
Bank B
Row Addr.
R/W A with
AutoPrecharge
Bank B
Activate
RAS# - RAS# delay time(tRRD)
RAS# - CAS# delay(tRCD)
NOP
NOP
Bank A
Row Addr.
NOP
NOP
Bank A
Activate
RAS# - Cycle time(tRC)
AutoPrecharge
Begin
“H” or “L”
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A9 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
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Rev. 3.4
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EtronTech
T0
EM636165
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
CAS# latency=2
tCK2, DQ’s
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ’s
DOUT A0 DOUT A1 DOUT A2
DOUT A3
Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2
tCK2, DQ’s
CAS# latency=3
tCK3, DQ’s
READ A
READ B
NOP
DOUT A0
NOP
NOP
NOP
NOP
NOP
DOUT B0 DOUT B1
DOUT B2 DOUT B3
DOUT A0 DOUT B0
DOUT B1 DOUT B2
NOP
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst read
occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least
one clock prior to the Write command to avoid internal bus contention.
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Rev. 3.4
Apr. 2008
EtronTech
T0
EM636165
T1
T2
T3
T4
T5
T6
T7
T8
CLK
1Clk Interval
DQM
COMMAND
NOP
BANKA
ACTIVATE
NOP
READ A WRITE A
NOP
CAS# latency=2
tCK2, DQ’s
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
DIN A0
Must be Hi-Z before
the Write Command
“H” or “L”
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
DQM
COMMAND
NOP
READ A
NOP
NOP
DQ’s
NOP
NOP
WRITE B
DOUT A0
DIN B0
NOP
NOP
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
“H” or “L”
Read to Write Interval (Burst Length ≧ 4, CAS# Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
CAS# latency=2
tCK2, DQ’s
NOP
NOP
READ A
NOP
NOP
WRITE B
DIN B0
Must be Hi-Z before
the Write Command
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
“H” or “L”
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
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T0
T1
EM636165
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
ADDRESS
Bank
Row
Bank(s)
tRP
COMMAND
READ A
NOP
NOP
NOP
Precharge
NOP
CAS# latency=2
tCK2, DQ’s
DOUT A0 DOUT A1
DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ’s
DOUT A0
DOUT A1 DOUT A2
NOP
Activate
NOP
DOUT A3
Read to Precharge (CAS# Latency = 2, 3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Burst Write Operation (Burst Length = 4, CAS# Latency = 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
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EtronTech
T0
EM636165
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
COMMAND
WRITE A
WRITE B
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
NOP
NOP
1 Clk Interval
DQ’s
DIN A0
DIN B0
Write Interrupted by a Write (Burst Length = 4, CAS# Latency =2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
READ B
CAS# latency=2
tCK2, DQ’s
DIN A0
don’t care
CAS# latency=3
tCK3, DQ’s
DIN A0
don’t care
NOP
NOP
NOP
DOUT B0 DOUT B1
don’t care
Input data for the write is masked
DOUT B0
NOP
DOUT B2
DOUT B1
NOP
NOP
DOUT B3
DOUT B2
DOUT B3
Input data must be removed from the
DQ’s at least one clock cycle before the
Read data appears on the outputs to avoid
data contention
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the
last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
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EM636165
T0
T1
T2
T3
T4
T5
T6
Activate
NOP
CLK
DQM
tRP
WRITE
COMMAND
NOP
BANK
COL n
ADDRESS
Precharge
NOP
NOP
BANK(S)
ROW
tWR
DIN
n
DQ
DIN
N+1
Don’t Care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of { (burst length -1) + tWR + tRP(min.) } . At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
T1
T2
Bank A
Activate
NOP
NOP
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2,3
tCK, DQ’s
Write A
Auto Precharge
NOP
NOP
NOP
NOP
Bank A
Activate
tDAL
DIN A0
DIN A1
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
tDAL=tWR+tRP
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)
8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. One clock cycle is required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as both banks are in the idle state.
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Rev. 3.4
Apr. 2008
EtronTech
T0
T1
EM636165
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCK
CKE
Clock min
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
Hi-Z
DQ
PrechargeAll
Mode Register Any
Set Command Command
“H” or “L”
Mode Register Set Cycle (CAS# Latency = 2, 3)
The mode register is divided into various fields depending on functionality.
Address A11,10
Function
RFU*
A9
WBL
A8
A7
Test Mode
A6
A5
A4
CAS Latency
A3
BT
A2
A1
A0
Burst Length
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
•
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
Etron Confidential
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
13
Rev. 3.4
Apr. 2008
EtronTech
•
•
•
EM636165
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
A3
Addressing Mode
0
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Start Address
Burst Length
Sequential
Interleave
A2
A1
A0
X
X
0
0, 1
0, 1
2
X
X
1
1, 0
1, 0
X
0
0
0, 1, 2, 3
0, 1, 2, 3
X
0
1
1, 2, 3, 0
1, 0, 3, 2
4
X
1
0
2, 3, 0, 1
2, 3, 0, 1
X
1
1
3, 0, 1, 2
3, 2, 1, 0
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0
0
1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
8
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1
1
1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
n, n+1, n+2, n+3, …255, 0,
Full page location = 0-255
Not Support
1, 2, … n-1, n, …
CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field.
tCAC(min) ≤ CAS# Latency X tCK
Etron Confidential
A6
A5
A4
CAS# Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
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Rev. 3.4
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EtronTech
•
•
EM636165
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Write Burst Length (A9)
This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-ReadBurst-Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is
selected.
A9
Write Burst Mode
0
Burst-Read-Burst-Write
1
Burst-Read-Single-Write
Note: A10 and A11 should stay “L” during mode set cycle.
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
10
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T1
T2
NOP
NOP
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2
tCK2, DQ’s
CAS# latency=3
tCK3, DQ’s
READ A
NOP
Burst Stop
NOP
NOP
NOP
NOP
The burst ends after a delay equal to the CAS# latency
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency = 2, 3)
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Rev. 3.4
Apr. 2008
EtronTech
T0
T1
EM636165
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2,3
tCK1, DQ’s
NOP
WRITE A
NOP
NOP
Burst Stop
DIN A0
DIN A1
DIN A2
don’t care
NOP
NOP
NOP
NOP
Input data for the Write is masked
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 2, 3)
11
Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
12
AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
13
SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14
SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tXSR(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
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Rev. 3.4
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EtronTech
EM636165
15
Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
(CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
16
Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms, CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
17
Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every
word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output
buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory
system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
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EM636165
Absolute Maximum Rating
Symbol
Rating
Item
Unit
-55/6/7/7L
Note
VIN, VOUT
Input, Output Voltage
- 1.0 ~ 4.6
V
1
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
1
TA
Operating Temperature
0 ~ 70
°C
1
TSTG
Storage Temperature
- 55 ~ 125
°C
1
PD
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (TA = 0~70°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Power Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
－
VDDQ+0.3
V
2
VIL
LVTTL Input Low Voltage
- 0.3
－
0.8
V
2
Capacitance (VDD = 3.3V,
Symbol
CI
CI/O
f = 1MHz, TA = 25°C)
Parameter
Min.
Max.
Unit
Input Capacitance
2
5
pF
Input/Output Capacitance
4
7
pF
Note: These parameters are periodically sampled and are not 100% tested.
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Rev. 3.4
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EtronTech
EM636165
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, TA = 0~70°C)
Description/Test condition
Symbol
Operating Current
tRC ≥ tRC(min), Outputs Open
One bank active
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed every 2clks
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
tCK = 15ns, CKE ≥ VIH(min), CS# ≥ VIH(min)
Input signals are changed every 2clks
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
tRC ≥ tRC(min)
Self Refresh Current
CKE ≤ 0.2V ; for other inputs VIH≧VDD - 0.2V, VIL ≤ 0.2V
- 55
-6
-7
-7L
Max.
115
100
40
110
90
85
15
IDD2P
2
2
2
0.8
IDD2PS
2
2
2
0.8
IDD3P
2
2
2
1.5
IDD3N
100
90
80
20
IDD4
160
150
140
40
3, 4
IDD5
110
100
90
40
3
IDD6
2
2
2
0.6
IDD2N
Description
Min.
Max.
IIL
Input Leakage Current
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )
- 10
10
µA
IOL
Output Leakage Current
Output disable, 0V ≤ VOUT ≤ VDDQ)
- 10
10
µA
VOH
LVTTL Output "H" Level Voltage
( IOUT = -2mA )
2.4
－
V
VOL
LVTTL Output "L" Level Voltage
( IOUT = 2mA )
－
0.4
V
19
3
125
IDD1
Parameter
Etron Confidential
Unit Note
Rev. 3.4
mA
Unit Note
Apr. 2008
EtronTech
EM636165
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, TA = 0~70°C) (Note: 5, 6, 7, 8)
Symbol
tRC
tRCD
tRP
tRRD
tRAS
tWR
tCK
- 55
A.C. Parameter
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate
command (same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
Clock cycle time
-6
-7
-7L
Unit Note
Min.
Max
Min.
Max
Min.
Max
Min.
Max
56.5
-
60
-
70
-
70
-
9
18
-
18
-
21
-
21
-
9
18
-
18
-
21
-
21
-
11
-
12
-
14
-
14
-
42
100k
49
100k
49
100k
38.5 100k
2
-
2
-
2
-
2
-
CL* = 2
7
-
7.5
-
8
-
8
-
CL* = 3
5.5
-
6
-
7
-
7
-
ns
9
9
tCK
10
tCH
Clock high time
2
-
2
-
2.5
-
2.5
-
tCL
Clock low time
2
-
2
-
2.5
-
2.5
-
tAC
Access time from CLK
(positive edge)
CL* = 2
-
5.5
-
6
-
6.5
-
6.5
CL* = 3
-
5
-
5
-
5.5
-
5.5
tCCD
CAS# to CAS# Delay time
1
-
1
-
1
-
1
-
tOH
Data output hold time
2
-
2
-
2
-
2
-
tLZ
Data output low impedance
1
-
1
-
1
-
1
-
tHZ
Data output high impedance
4
-
5
-
5
tIS
Data/Address/Control Input set-up time
2
-
2
-
2
-
2
-
11
tIH
Data/Address/Control Input hold time
1
-
1
-
1
-
1
-
11
tPDE
PowerDown Exit set-up time
tIS+tCK
-
tIS+tCK
-
tIS+tCK
-
tIS+tCK
-
tCK
tREFI
Refresh Interval Time
-
15.6
-
15.6
-
15.6
-
15.6
µs
tXSR
Exit Self-Refresh to Read Command
tRC+tIS
-
tRC+tIS
-
tRC+tIS
-
tRC+tIS
-
ns
3.5
ns
11
tCK
10
ns
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. VIH(Max) = 4.6V for pulse width ≤ 3ns.VIL(Min) = -1.5Vfor pulse width
≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Etron Confidential
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Rev. 3.4
Apr. 2008
8
EtronTech
EM636165
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50 Ω
1.2kΩ
Output
Output
30pF
Z0= 50 Ω
30pF
870Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state .
2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
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Rev. 3.4
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EtronTech
EM636165
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
T1 T2 T3 T4
T0
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK
tCL
tCH
tIS
tIH
tIS
Begin Auto
Precharge Bank A
Begin Auto
Precharge Bank B
tIS
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RAx
RBx
RAy
RAz
RBy
RAz
RBy
tIS
A0-A9
RBx
RBx
CAx
CBx
CAy
RAy
DQM
tRCD
DQ
tDAL
tWR
tIS
tRC
Hi-Z
Ax0
Activate
Command
Bank A
Ax1
tRP
tRRD
tIH
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Activate Write with
Write with
Activate Write
Auto Precharge Command Auto Precharge Command Command
Bank B
Command
Command
Bank A
Bank A
Bank A
Bank B
Ay2
Ay3
Precharge
Command
Bank A
Activate
Activate
Command Command
Bank A
Bank B
“H” or
Etron Confidential
22
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
CLK
T1
T2
tCH tCL
T3
T4
T5
T6
T8
T7
T10
T11
T12
T13
tCK
tIS
CKE
T9
tIS
Begin Auto
Precharge Bank B
tIH
tIH
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RAx
RBx
RAy
tIS
A0-A9
RAx
CAx
CBx
RBx
tRRD
RAy
tRAS
tRC
DQM
tAC
tLZ
tRCD
DQ
Hi-Z
tAC
Ax0
Activate
Command
Bank A
Read
Command
Bank A
tRP
tHZ
Ax1
Bx0
tOH
Read with
Precharge
Activate
Command Auto Precharge Command
Command
Bank A
Bank B
Bank B
Bx1
tHZ
Activate
Command
Bank A
“H” or
Etron Confidential
23
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
tRP
tRC
CAx
tRC
DQM
DQ
Ax0
Precharge All Auto Refresh
Command
Command
Etron Confidential
Activate
Command
Bank A
Auto Refresh
Command
24
Read
Command
Bank A
Ax1
Ax2
“H” or
Rev. 3.4
Ax3
“L”
Apr. 2008
EtronTech
EM636165
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
High Level
is reauired
CKE
Minimum fo 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
DQ
tRP
tRC
Hi-Z
Precharge All
Command
2nd Auto Refresh(*)
Command
1st Auto Refresh(*)
Command
Inputs must be Mode Register
Stable for 200 µs Set Command
Any
Command
“H” or
“L”
Note(*):The Auto Refresh command can be issue before or after Mode Register Set command
Etron Confidential
25
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
*Note 1
*Note 2
CKE
tXSR
*Note 4
*Note 3
tIS tIH
*Note 7
tPDE
*Note 5
*Note 6
tIS
CS#
*Note 8
RAS#
*Note 8
CAS#
A11
A0-A9
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
Self Refresh Exit
Auto Refresh
“H” or
“L”
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
5.
6.
7.
8.
9.
To Exit SelfRefresh Mode
System clock restart and be stable before returning CKE high.
Enable CKE and CKE should be set high for valid setup time and hold time.
CS# starts from high.
Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Etron Confidential
26
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax0
Activate
Cammand
Bank A
Read
Command
Banka
Ax1
Clock Suspend
1 Cycle
Ax2
Ax3
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
“H” or
“L”
Note: CKE to CLK disable/enable = 1 clock
Etron Confidential
27
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax0
Activate
Cammand
Bank A
Read
Command
Banka
Ax1
Ax2
Clock Suspend Clock Suspend
2 Cycles
1 Cycle
Ax3
Clock Suspend
3 Cycles
“H” or “L”
Note: CKE to CLK disable/enable = 1 clock
Etron Confidential
28
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Activate
Cammand
Bank A
DAx1
DAx3
Ax3
DAx2
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Clock Suspend
3 Cycles
“H” or
“L”
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Etron Confidential
29
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Activate
Cammand
Bank A
DAx1
DAx2
Clock Suspend Clock Suspend
2 Cycles
1 Cycle
DAx3
Clock Suspend
3 Cycles
“H” or
“L”
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Etron Confidential
30
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
tPDE
tIS tIH
CKE
Valid
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ
Hi-Z
Ax2
Ax0 Ax1
ACTIVE
STANDBY
Activate
Cammand
Bank A
Power Down
Mode Entry
Read
Command
Bank A
Power Down
Mode Exit
Clock Mask
End
Clock Mask
Start
Ax3
Precharge
Command
Bank A
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Commad
Power Down
Mode Entry
“H” or “L”
Etron Confidential
31
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAw
A0-A9
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Cammand
Bank A
Read
Command
Bank A
Etron Confidential
Read
Read
Command Command
Bank A
Bank A
Precharge
Command
Bank A
32
Az0
Activate
Command
Bank A
Read
Command
Bank A
Az1 Az2
“H” or
Rev. 3.4
Az3
“L”
Apr. 2008
EtronTech
EM636165
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAw
A0-A9
RAw
RAz
CAw
CAx
RAz
CAy
CAz
DQM
DQ
Hi-Z
Az0
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Cammand
Bank A
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
“H” or
Etron Confidential
33
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0-A9
RBw
RAz
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Cammand
Bank A
Write
Command
Bank B
Etron Confidential
Write
Write
Command Command
Bank B
Bank B
Precharge
Command
Bank B
34
DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank B
Write
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0-A9
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Cammand
Bank A
Write
Command
Bank B
Write
Write
Command Command
Bank B
Bank B
DBz0 DBz1 DBz2
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
“H” or “L”
Etron Confidential
35
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
CLK
T1 T2 T3 T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
A0-A9
RBx
RAx
CBx
RBy
RAx
CAx
CBy
RBy
tAC
tRCD
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank B
Bx0 Bx1 Bx2
Read
Command
Bank B
Etron Confidential
Bx3
Bx4
Bx5
Activate
Command
Bank A
Bx6
Bx7
Ax0 Ax1 Ax2 Ax3
Read
Command
Bank A
Precharge
Command
Bank B
36
Activate
Command
Bank B
Ax4 Ax5
Ax6 Ax7
By0
By1
Read
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
A0-A9
RBx
RAx
CBx
RBy
CAx
RAx
RBy
tAC
tRCD
CBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank B
Bx0 Bx1 Bx2
Read
Command
Bank B
Bx3
Activate
Command
Bank A
Bx4
Bx5
Bx6
Read
Command
Bank A
Bx7
Ax0 Ax1 Ax2 Ax3
Precharge
Command
Bank B
Activate
Command
Bank B
Ax4 Ax5
Ax6 Ax7
By0
Read
Precharge
Command Command
Bank B
Bank A
“H” or “L”
Etron Confidential
37
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBx
RAy
CBx
RAy
tRP
tWR*
tRCD
CAy
tWR*
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Write
Command
Bank A
Activate Write
Command Command
Bank B
Bank B
Precharge
Command
Bank A
* tWR > tWR (min.)
Etron Confidential
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
“H” or
38
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBx
RAy
CBx
tRCD
RAy
tRP
tWR*
CAy
tWR*
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Precharge
Command Command
Bank A
Bank B
“H” or
“L”
* tWR > tWR (min.)
Etron Confidential
39
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate
Cammand
Bank A
Read
Command
Bank A
DAy0 DAy1
DAy3
Write
The Write Data
Command is Masked with a
Bank A
Zero Clock
Latency
Az0
Read
Command
Bank A
Az3
Az1
The Read Data
is Masked with a
Two Clock
Latency
“H” or
Etron Confidential
40
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate
Cammand
Bank A
DAy0 DAy1
Az1
41
Read
Command
Bank A
Az3
The Read Data
is Masked with a
Two Clock
Latency
Write
The Write Data
Command is Masked with a
Bank A
Zero Clock
Read
Command
Bank A
Latency
Etron Confidential
Az0
DAy3
“H” or “L”
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RAx
CAy
CBw
CBx
CBy
Hi-Z
Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0
Activate
Cammand
Bank A
CAy
CBz
By0
By1 Ay0 Ay1
tAC
tRCD
DQM
DQ
RAx
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Bx1
Bz0
Read
Read
Read
Read
Command Command Command Command
Bank A
Bank B
Bank B
Bank B
Precharge
Command
Bank A
Etron Confidential
42
Bz1
Bz2
Bz3
Precharge
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 14.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
CAx
tRCD
DQM
DQ
RBx
RBx
CBx
CBy
Ax0 Ax1 Ax2 Ax3
Etron Confidential
CAy
tAC
Hi-Z
Activate
Cammand
Bank A
CBz
Read
Command
Bank A
Activate
Command
Bank B
Bx0
Bx1
By0
Read
Read
Read
Command Command Command
Bank B
Bank B
Bank B
By1
Bz0
Bz1 Ay0 Ay1 Ay2 Ay3
Read
Precharge
Command Command
Bank A
Bank B
Precharge
Command
Bank A
“H” or “L”
43
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CAy
CBz
tRCD
DQM
tRP
tWR
tRP
tRRD
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Cammand
Bank A
Activate
Write
Command Command
Bank B
Bank A
Write
Write
Command Command
Bank B
Bank B
Write
Write
Write
Command Command Command
Bank A
Bank B
Bank B
Precharge
Command
Bank A
Etron Confidential
44
Precharge
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RBw
CAx
RBw
CBw
CBx
tRCD
DQM
CBy
CAy
CBz
tWR
tRP
tWR
tRCD>tRRD(min)
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Cammand
Bank A
Etron Confidential
Write
Command
Bank A
Activate
Command
Bank B
Write
Write
Write
Write
Write
Command Command Command Command Command
Bank B
Bank B
Bank A
Bank B
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
45
“H” or “L”
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBx
RBy
CBx
RAy
RBy
RAz
CBy
RAz
CAz
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax0 Ax1 Ax2 Ax3
Activate
Read
Command Command
Bank B
Bank A
Etron Confidential
Bx0
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2 Bx3 Ay0
Ay1 Ay2 Ay3 By0
By1
Activate
Activate
Read with
Command
Auto Precharge Command
Bank B
Bank A
Command
Read with
Bank A
Auto Precharge
Command
Bank B
46
By2
By3
Az0
Az1 Az2
Read with
Auto Precharge
Command
Bank A
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RBx
CAx
RBx
RBy
CBx
CAy
RBy
CBy
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Etron Confidential
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
By0 By1 By2 By3
Write with
Auto Precharge
Command
Bank B
“H” or “L”
47
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RBx
CAx
RBx
RBy
CBx
CAy
RBy
RAz
CBy
RAz
CAz
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Activate
Write
Command Command
Bank B
Bank A
Etron Confidential
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
48
Activate
Command
Bank B
DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0-A9
RAx
RBx
CAx
RBx
RBy
CBx
CAy
RBy
CBy
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank B
Write
Command
Bank A
Etron Confidential
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
DBy0 DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
“H” or
49
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax
Ax+1 Ax+2 Ax-2 Ax-1 Ax
Read
Activate
Command Cammand
Bank A
Bank B
Etron Confidential
Ax+1 Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
Precharge
Full Page burst operation does not
Read
terminate when the burst length is satisfied;
Command
Command the burst counter increments and continues
Bank B
Bank B bursting beginning with the starting address
Burst Stop
The burst counter wraps
Command
from the highest order
page address back to zero
during this time interval
50
Activate
Command
Bank B
“H” or “L”
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Ax
Read
Activate
Command Cammand
Bank A
Bank B
Ax+1 Ax+2 Ax-2 Ax-1 Ax
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Etron Confidential
51
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter increments
and continues bursting beginning with
the starting address
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
“H” or “L”
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBy
CBx
RBx
RBy
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Write
Activate
Command Cammand
Bank A
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Etron Confidential
Data is ignored
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
52
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBx
RBy
CBx
RBy
DQM
DQ
Hi-Z
Activate
Cammand
Bank A
Data is ignored
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx
Write
Activate
Command Cammand
Bank A
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Etron Confidential
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter increments
and continues bursting beginning with
the starting address
53
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
“H” or
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAy
CAx
CAz
LDQM
UDQM
DQ0-DQ7
Ax0 Ax1 Ax2
DQ8-DQ15
Ax1 Ax2 Ax3
Activate
Cammand
Bank A
Read
Command
Bank A
Upper Bytes
are masked
DAy1 DAy2
DAy0 DAy1
DAy3
Upper Bytes
Lower Byte Write
is masked Command are masked
Bank A
Az0
Read
Command
Bank A
Az1
Az2
Az1
Az2
Lower Byte
is masked
Az3
Lower Byte
is masked
“H” or “L”
Etron Confidential
54
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 21. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
High
Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank B
Bank A
Bank A
CS#
RAS#
CAS#
WE#
A11
A10
RBu
A0-A9
RBu
CBu
RAu
RBv
RAv
RAu CAu
RBv
CBv RAv
tRP
RBw
CAv
tRP
RAw
RBx
RBw CBw RAw CAw
tRP
tRP
RBx
RAx
CBx
tRP
RAx
RBy
CAx
tRP
RBy
RBz
RAy
CBy
tRP
RAy
CAy
tRP
RBz
RAz
CBz
tRP
RAz
tRP
DQM
DQ
Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Command Command Command Command Command Command Command Command Command Command Command Command
Bank B
Bank A
Bank B
Bank A
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank A
Bank B
Bank B
Bank A
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank B
with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
“H” or “L”
Etron Confidential
55
Rev. 3.4
Apr. 2008
EtronTech
EM636165
Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
A0-A9
RAx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
RBw
CBz
tRP
DQM
tRRD
DQ
Hi-Z
tRCD
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Activate
Cammand
Bank A
Read
Activate
Command Command
Bank B
Bank B
Read
Read
Command Command
Bank B
Bank A
Read
Read
Command Command
Bank A
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
“H” or
Etron Confidential
56
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0
CLK
T1 T2 T3 T4
T5
T6
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBx
A0-A9
RAx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
RBw
CBz
tWR
tRP
DQM
tRRD
DQ
Hi-Z
tRCD
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate
Cammand
Bank A
Write
Activate
Write
Write
Command Command
Command Command
Bank B
Bank B
Bank B
Bank A
Write
Write
Command Command
Bank A
Bank A
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Write Data
is masked
Activate
Command
Bank B
“H” or
Etron Confidential
57
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
Figure 24. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
CLK
CKE
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RAy
RAz
RAy
CAx
tWR
CAy
RAz
tRP
tRP
DQM
DQ
Ay0 Ay1 Ay2
DAx0 DAx1
Activate
Cammand
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst
Activate
Command
Bank A
Precharge Termination
of a Read Burst
“H” or
Write Data is masked
Etron Confidential
Precharge
Command
Bank A
58
Rev. 3.4
“L”
Apr. 2008
EtronTech
EM636165
50 Pin TSOP II Package Outline Drawing Information
50
HE
E
0.254
26
θ°
L
L1
1
25
S
Symbol
e
B
y
Dimension in inch
Min
Normal
Max
0.047
－
－
0.002
0.005
0.008
0.035
0.039
0.043
0.008
0.018
－
0.006
－
－
0.82
0.825
0.83
0.395
0.400
0.405
0.031
－
－
0.455
0.463
0.471
0.016
0.020
0.024
0.0315
－
－
0.035
－
－
0.004
－
－
－
0°
8°
Min
－
0.05
0.9
0.2
－
20.82
10.03
－
11.56
0.40
－
－
－
0°
A
A1
A2
B
c
D
E
e
HE
L
L1
S
y
θ
Notes :
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm
Etron Confidential
59
C
A1 A2
A
D
L
Dimension in mm
Normal
－
0.125
1.0
－
0.155
20.95
10.16
0.80
11.76
0.50
0.80
0.88
－
－
L1
Max
1.20
0.20
1.1
0.45
－
21.08
10.29
－
11.96
0.60
－
－
0.10
8°
Rev. 3.4
Apr. 2008
EtronTech
EM636165
60-Ball (6.4mm x 10.1mm)VFBGA
Units in mm
BOTTOM VIEW
♁
TOP VIEW
∅ 0.08 M
C
∅ 0.16 M
C
A1 CORNER
1
2
3
A1 CORNER
A
B
∅=0.30~0.40
4
5
6
7
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
F
G
G
H
J
H
9.10
10.10±0.10
A
J
K
L
L
M
M
N
N
0.65
K
P
P
R
R
0.65
A
3.90
D
B
0.10(4X)
6.40±0.10
C
D
0.23±0.03
1.00 MAX
0.10(4X)
C
SEATING PLANE
Etron Confidential
60
Rev. 3.4
Apr. 2008