CTS HMSD1616

SDRAM Memory
Technical Data Sheet
Description
The HMSD1616 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally
configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The HMSD1616 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize its
performance. These devices are well suited for applications requiring high memory bandwidth and particularly well
suited to high performance PC applications.
Features
• JEDEC Standard Compliant
• Fast access time clock: 5.4 ns
• Fast clock rate: 143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 4M word x 16-bit x 4-bank
• Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Auto Refresh and Self Refresh
• 8192 refresh cycles/64ms
• CKE power down mode
• Single +3.3V power supply
• Interface: LVTTL
• Operating temperature range: -55℃~+125℃
• MIL-STD-883 Screening
• RoHS Compliant in Accordance with EU Directive 2005/95/EC
PAGE 1
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Package Details
• LGA package: 96 pin ceramic LGA(CLGA96)
• LCC package: 64 pin ceramic LCC(CLCC64)
Table 1. Key Specifications
HMSD1616
Unit(ns)
tCK3
Clock Cycle time (min.)
7
tAC3
Access time from CLK (max.)
5.4
tRAS
Row Active time (min.)
49
tRC
Row Cycle time (min.)
63
Table 2. Ordering Information
Part Number
Package
HMSD1616-143GM
CLGA96
HMSD1616-143LM
CLCC64
PAGE 2
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure1. Block Diagram
PAGE 3
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Pin Descriptions
Table 3. (1) Pin Details
Symbol
Type
Description
CLK
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
Input positive edge of CLK. CLK also increments the internal burst counter and controls the output
registers.
CKE
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes
low synchronously with clock (set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burstaddress is frozen as
long as the CKE remains low. When all banks are in the idle state,deactivating the clock
Input controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes,providing low standby power.
Bank Activate: BA0, BA1 input select the bank for operation.
BA0, BA1
A0-A12
CS#
BA1
BA0
Select Bank
0
0
BANK #A
0
1
BANK #B
1
0
BANK #C
1
1
BANK #D
Input
Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0A12) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge)
Input to select one location out of the 4M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The
address inputs also provide the op-code during a Mode Register Set command.
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and
CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or
Input the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BA is turned on to the
active state. When the WE# is asserted "LOW," the Precharge command is selected and the
bank designated by BA is switched to the idle state after the precharge operation.
CAS#
Column Address Strobe: The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is
Input held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS#
"LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
WE#
Write Enable: The WE# signal defines the operation commands in conjunction with the
Input RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
PAGE 4
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
LDM,
UDM
DQ0 - DQ15
NC
Data Input/Output Mask: Controls output buffers in read mode and masks Input data in
Input write mode.
Input Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of
/Output CLK. The I/Os are maskabled during Reads and Writes.
-
No Connect: These pins should be left unconnected.
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V )
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.( 0 V )
VDD
Supply Power Supply: +3.3V ± 0.3V
VSS
Supply Ground
PAGE 5
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table 3. (2) CLGA96 Pin Definitions
Pin No
Define
Pin No
Define
Pin No
Define
Pin No
Define
Pin No
Define
A1
BA1
B1
BA0
C1
RAS#
D1
WE#
E1
VDD
A2
A10
B2
VSS
C2
CS#
D2
CAS#
E2
DQ7
A3
NC
B3
A0
C3
VSS
D3
VSS
E3
DQML
A4
VSS
B4
A1
C4
VSS
D4
VSS
E4
VSS
A5
NC
B5
A2
C5
A3
D5
VSS
-
-
A6
VDD
B6
VDD
C6
VSS
D6
VSS
-
-
A7
VSS
B7
A4
C7
A5
D7
VSS
E7
VDDQ
A8
NC
B8
A6
C8
VSS
D8
VSS
E8
VSS
A9
A7
B9
VSS
C9
A11
D9
CKE
E9
DQMH
A10
A8
B10
A9
C10
A12
D10
CLK
E10
VSS
Pin No
Define
Pin No
Define
Pin No
Define
Pin No
Define
Pin No
Define
F1
VSSQ
G1
NC
H1
VSS
J1
DQ4
K1
DQ3
F2
DQ6
G2
DQ5
H2
VDDQ
J2
VSS
K2
NC
F3
VSS
G3
VSS
H3
VSSQ
J3
DQ2
K3
VDDQ
F4
VSS
G4
VSS
H4
DQ1
J4
VSS
K4
VDD
-
-
G5
DQ0
H5
VDD
J5
VSS
K5
VDD
-
-
G6
VDD
H6
VSS
J6
VSS
K6
VSS
F7
VSS
G7
VDDQ
H7
VSSQ
J7
DQ15
K7
VSS
F8
VSS
G8
VSS
H8
VSS
J8
DQ14
K8
NC
F9
DQ8
G9
DQ9
H9
VSSQ
J9
VSS
K9
DQ13
F10
NC
G10
NC
H10
DQ10
J10
DQ11
K10
DQ12
PAGE 6
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table 3. (3) CLCC64 Pin Definitions
Pin No
Define
Pin No
Define
Pin No
Define
Pin No
Define
1
VDD
17
VSS
33
DQ8
49
VDD
2
DQML
18
VSS
34
VDDQ
50
VDD
3
WE#
19
VSS
35
DQ9
51
VDD
4
CAS#
20
VSS
36
DQ10
52
VDD
5
RAS#
21
A4
37
VSSQ
53
DQ0
6
CS#
22
A5
38
DQ11
54
VDDQ
7
BA0
23
A6
39
DQ12
55
DQ1
8
BA1
24
A7
40
VDDQ
56
DQ2
9
A10
25
A8
41
DQ13
57
VSSQ
10
A0
26
A9
42
DQ14
58
DQ3
11
A1
27
A11
43
VSSQ
59
DQ4
12
A2
28
A12
44
DQ15
60
VDDQ
13
A3
29
CKE
45
VSS
61
DQ5
14
VDD
30
CLK
46
VSS
62
DQ6
15
VDD
31
DQMH
47
VSS
63
VSSQ
16
VDD
32
VSS
48
VSS
64
DQ7
PAGE 7
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4 shows
the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
CKEn-1 CKEn DQM BA0,1 A10 A0-9,12
State
CS# RAS# CAS# WE#
Idle(3)
Any
H
X
X
V
Row address
L
L
H
H
H
X
X
V
L
X
L
L
H
L
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
L
Column
address
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
V
V
H
(A0-A8)
L
H
L
L
Read
Active(3)
H
X
V
V
L
Column
address
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
V
V
H
(A0-A8)
L
H
L
H
Mode Register Set
Idle
H
X
X
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Idle
(SelfRefresh)
L
H
X
X
X
X
H
X
X
X
L
H
H
H
Active
H
L
X
X
X
X
H
X
X
X
BankActivate
Bank Precharge
PrechargeALL
Burst Stop
SelfRefresh Exit
Clock Suspend Mode Entry
Power Down Mode Entry
Any(5)
OP code
L
V
V
V
H
X
X
X
L
H
H
H
X
X
X
X
H
X
X
X
L
H
H
H
H
L
X
X
X
X
Active
L
H
X
X
X
X
Any
(PowerDown)
L
H
X
X
X
X
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Clock Suspend Mode Exit
Power Down Mode Exit
Note:
1. V=Valid, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
PAGE 8
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address)
The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row
address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write
operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure). The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of the two banks. tRRD(min.) specifies the minimum time required between activating different banks.
After this command is used, the Write command and the Block Write command perform the no mask write
operation.
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Bank A
Bank B
Bank A
Row Addr.
Col Addr.
Row Addr.
Row Addr.
R/W A with
Bank B
Activate
RAS#-CAS# delay(tRCD)
COMMAND
Bank A
Activate
NOP
NOP
RAS#-RAS# delay time(tRRD)
AutoPrecharge
NOP
NOP
Bank A
Activate
RAS#-Cycle time(tRC)
AutoPrecharge
Begin
Don’t Care
Figure2.BankActivate Command Cycle (Burst Length = n)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9, A11 and A12 = Don't care)
The BankPrecharge command precharges the bank disignated by BA signal. The precharged bank is
switched from the active state to the idle state. This command can be asserted anytime after t RAS(min.) is
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is
specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within
tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated
again
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9, A11 and A12 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are
not in the active state. All banks are then switched to the idle state.
PAGE 9
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min) before the Read command is issued. During read
bursts, the valid data-out element from the starting column address will be available following the CAS#
latency after the issue of the Read command. Each subsequent data-out element will be valid by the next
positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst
unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the
mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the
page it will wrap to column 0 and continue).
T0
T1
READ A
NOP
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# Latency=2
tCK2, DQ
NOP
DOUT A0
CAS# Latency=3
tck3, DQ
NOP
NOP
NOP
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
NOP
NOP
NOP
DOUT A3
Figure3.Burst Read Operation (Burst Length = 4,CAS# Latency=2,3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM
latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted
by a subsequent Read or Write command to the same bank or the other active bank before the end of the
burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The
interrupt coming from the Read command can occur on any clock cycle following a previous Read command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# Latency=2
tCK2, DQ
CAS# Latency=3
tck3, DQ
READ A
READ B
NOP
DOUT A0
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT A0
DOUT B0
DOUT B1
NOP
NOP
NOP
DOUT B3
DOUT B2
DOUT B3
Figure4.Read Interrupted by a Read (Burst Length = 4,CAS# Latency=2,3)
PAGE 10
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write
command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress
data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with highimpedance on the DQ pins must occur between the last read data and the Write command (refer to the
following three figures). If the data output of the burst read occurs at the second clock of the burst write, the
DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus
contention.
T0
T1
T2
NOP
Bank A
Activate
T3
T4
T5
T6
T7
T8
T9
READ A
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
CLK
DQM
COMMAND
NOP
NOP
NOP
CAS# Latency=2
tCK2, DQ
Figure5.Read to Write Interval(Burst Length ≥ 4,CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
READ A
NOP
NOP
CAS# Latency=2
tCK2, DQ
WRITE B
DIN B0
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure6.Read to Write Interval(Burst Length ≥ 4,CAS# Latency=2)
PAGE 11
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
NOP
NOP
CAS# Latency=3
tck3, DQ
NOP
NOP
WRITE B
NOP
NOP
DIN B0
DIN B1
DIN B2
DOUT A0
Must be Hi-Z before
the Write Command
Don’t Care
Figure7.Read to Write Interval(Burst Length ≥ 4,CAS# Latency=3)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank. The following figure shows the optimum time that BankPrecharge/PrechargeAll
command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
Bank,
Col A
Bank
Row
Bank(S)
tRP
COMMAND
READ A
NOP
CAS# Latency=2
tck2, DQ
NOP
DOUT A0
CAS# Latency=3
tck3, DQ
NOP
Precharge
DOUT A1
DOUT A2
DOUT A3
DOUT A1
DOUT A2
DOUT A0
NOP
NOP
Activate
NOP
DOUT A3
Figure8.Read to Precharge(CAS# Latency=2,3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of
{tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the
auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)
PAGE 12
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ
WRITE A
NOP
NOP
DIN A0
DIN A1
DIN A2
NOP
NOP
NOP
NOP
NOP
don’t care
DIN A3
The first data element and the write
are registered on the same clock edge
Figure9. Burst Write Operation (Burst Length = 4)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
T0
T1
T2
T3
T4
T5
WRITE A
WRITE B
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
T6
T7
T8
CLK
COMMAND
NOP
DQ
NOP
NOP
NOP
Figure10. Write Interrupted by a Write (Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be issued one
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention,
input data must be removed from the DQs at least one clock cycle before the first read data appears on the
outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored
and writes will not be executed.
PAGE 13
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS# Latency=2
tCK2, DQ
DIN A0
don’t care
CAS# Latency=3
tck3, DQ
DIN A0
don’t care
NOP
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
don’t care
NOP
NOP
DOUT B3
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure11. Write Interrupted by a Read(Burst Length = 4, CAS# Latency=2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
function should be issued m cycles after the clock edge in which the last data-in element is registered, where
m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask
input data, starting with the clock edge following the last data-in element and ending with the clock edge on
which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
COMMAND
WRITE
ADDRESS
Bank
Col n
DQ
DIN
n
NOP
NOP
Precharge
NOP
NOP
Bank(s)
Activate
NOP
ROW
tWR
DIN
N+1
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure12. Write to Precharge
7
Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of
PAGE 14
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
{(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command
and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
COMMAND
Bank A
Activate
WRITEA
NOP
NOP
AutoPrecharge
NOP
NOP
NOP
NOP
NOP
Bank A
Activate
tDAL
DQ
DIN A0
DIN A1
Begin AutoPrecharge
Bank can be reactivated at
ompletion of tDAL
tDAL=tWR+trp
Figure13. Burst Write with Auto-Precharge(Burst Length = 2)
8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the
Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode
Register after power-up are undefined; therefore this command must be issued at the power-up sequence.
The state of pins A0~A9 and A12 in the same cycle is the data written to the mode register. Two clock cycles
are required to complete the write in the mode register (refer to the following figure). The contents of the
mode register can be changed using the same command and the clock cycle requirements during operation
as long as all banks are in the idle state.
Table5. Mode Register Bitmap
PAGE 15
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11-A12
DQM
tRP
Hi-Z
DQ
Mode Register
Set Command
PrechargeAll
Any
Command
Don’t Care
Figure14. Mode Register Set Cycle
 Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length
to be 2,4,8, or full page.
Table6. Burst Length Field
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Burst Length
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Full Page Length：512
 Burst Type Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode
supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8.
PAGE 16
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table 7. Addressing Mode Select Field
A3
0
1
Burst Type
Sequential
Interleave
 Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 8. Burst Definition
Burst Length
2
4
8
Full Page
A2
X
X
X
X
X
X
0
0
0
0
1
1
1
1
Start Address
A2
A0
X
0
X
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Location = 0 - 511
Sequential
Interleave
0,1
1,0
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
n,n+1,n+2,n+3,…
511,0,1,2,…,n-1,n,…
0,1
1,0
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Not Support
 CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read
data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole
value satisfying the following formula must be programmed into this field.
tCAC(min) ≤ CAS# Latency X tCK
Table9. CAS Latency
A6
0
0
0
0
1
A5
0
0
1
1
X
A4
0
1
0
1
X
CAS# Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
 Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 10. Test Mode
A8
0
0
1
A7
0
1
X
Test Mode
Normal Mode
Vendor Use Only
Vendor Use Only
 Write Burst Length (A9)
This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write mode
is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected.
PAGE 17
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table 11. Write Burst Length
A9
0
1
Write Burst Mode
Burst-Read-Burst-Write
Burst-Read-Single-Write
Note: A10 and BA0, 1 should stay “L” during mode set cycle.
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only
effective in a read/write burst without the auto precharge function. The terminated read burst ends after a
delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the
following figure.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
Burst
NOP
NOP
NOP
NOP
Stop
The burst ends after a delay equal to the CAS# Latency
CAS# Latency=2
tCK2, DQ
DOUT A0
CAS# Latency=3
tCK3, DQ
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Figure15. Termination of a Burst Read Operation(Burst Length ＞4, CAS# Latency=2,3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
DQ
NOP
WRITE A
NOP
NOP
Burst
NOP
NOP
NOP
NOP
Stop
DIN A0
DIN A1
DIN A2
don’t care
Figure16. Termination of a Burst Write Operation(Burst Length = X)
PAGE 18
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No
Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A12 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued
each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the
address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments
automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 8192
times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min). To
provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power
down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto
refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive
auto refresh operations are performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A12 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data
retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM
become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing
is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an
indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on
CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for tXSR(min) because time is required for the completion of any
bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal
operation, a burst of 8192 auto refresh cycles should be completed just prior to entering and just after exiting
the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while
CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into
the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown
PAGE 19
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period
(64ms) since the command does not perform any refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH", the command should be NOP or
deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are
turned on to the active state. tPDE (min) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input
data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device
selection, byte selection and bus control in a memory system.
PAGE 20
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table12. Absolute Maximum Rating
Symbol
Item
Rating
Unit
Note
VIN,VOUT
Input, Output Voltage
-0.5 ~ 4.6
V
1
VDD,VDDQ
Power Supply Voltage
-0.5 ~ 4.6
V
1
TA
Ambient Temperature
-55 ~ 125
°C
1
TSTG
Storage Temperature
-65 ~ 150
°C
1
0.15
W
1
50
mA
1
PD
Power Dissipation
IOUT
Short Circuit Output Current
Table13. Recommended D.C. Operating Conditions (TA = -55~125°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Power Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
3.0
VDDQ+0.3
V
2
VIL
LVTTL Input Low Voltage
-0.3
0
0.8
V
2
IIL
Input Leakage Current
(0V≤VIN≤VDD, All other pins not under test = 0V )
-10
-
10
uA
IOL
Output Leakage Current
Output disable, 0V≤VOUT≤VDDQ
-10
-
10
uA
VOH
LVTTL Output “H” Level Voltage (IOUT = -2mA )
2.4
-
-
V
VOL
LVTTL Output “L” level Voltage (IOUT = 2mA )
-
-
0.4
V
Table14. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C)
Symbol
CI
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
PAGE 21
www.ctscorp.com
Min.
Max.
Unit
2.5
5
pF
4
6.5
pF
Rev. B
SDRAM Memory
Technical Data Sheet
Table15. D.C. Characteristics (VDD = 3.3V±0.3V, TA = -55~125°C)
Description/Test condition
Symbol
Max.
Operating Current
tRC ≥ tRC(min), Outputs Open, One bank active
IDD1
100
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed every 2clks
IDD2N
40
Precharge Standby Current in non-power down mode
tCK = ∞, CLK≤ VIL(max), CKE ≥ VIH
IDD2NS
30
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
IDD2P
5
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
IDD2PS
5
Unit
Note
3
mA
Active Standby Current in non-power down mode
tCK = 15ns, CKE ≥ VIH(min), CS# ≥ VIH(min)
Input signals are changed every 2clks
IDD3N
65
Active Standby Current in non-power down mode
tCK = ∞, CKE ≥ VIH(min), CLK≤ VIL(max)
IDD3NS
45
Operating Current (Burst mode)
tCK = tCK(min), Outputs Open, Multi-bank interleave
IDD4
150
3,4
Refresh Current
tRC = tRC(min)
IDD5
200
3
Self Refresh Current
CKE ≤ 0.2V,for other inputs VIH ≥ VDD – 0.2V, VIL ≤ 0.2V
IDD6
6
PAGE 22
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Table16. Electrical Characteristics and Recommended A.C. Operating Conditions
Symbol
A.C. Parameter
Min.
Max.
tRC
Row cycle time (same bank)
63
-
tRFC
Refresh cycle time
63
-
tRCD
RAS# to CAS# delay (same bank)
21
-
tRP
Precharge to refresh/row active command
(same bank)
21
-
tRRD
Row active to row active delay
(different banks)
14
-
tMRD
Mode register set cycle time
14
-
tRAS
Row active to precharge time (same bank)
49
120k
tWR
Write recover time
14
-
tCK
Clock cycle time
CL* = 2
12
-
CL* = 3
7
-
Unit
Note
9
ns
tCH
Clock high time
2.5
-
10
tCL
Clock low time
2.5
-
10
tAC
Access time from CLK (positive
edge)
CL* = 2
-
6.5
CL* = 3
-
5.4
tOH
Data output hold time
2
-
tLZ
Data output low impedance
0
-
tHZ
Data output high impedance
-
5.4
8
tIS
Data/Address/Control Input set-up time
1.5
-
10
tIH
Data/Address/Control Input hold time
1
-
10
10
9
tPDE
Power Down Exit set-up time
tIS+ tCK
-
tREFI
Average Refresh interval time
-
7.8
us
tXSR
Exit Self-Refresh to Read Command
tRC+ tIS
-
ns
* CL is CAS# Latency.
PAGE 23
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. Overshoot VIH(max) = VDDQ + 2.0V for pulse width ≤ 3ns. Undershoot VIL(min) =
-2.0V for pulse width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 t CK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions.
Table 17. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed slope
(1 ns)
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be
added to the parameter.
11. Power up Sequence
PAGE 24
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= "LOW", DQM= "HIGH" and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 μs, then bring CKE "HIGH" and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device
* The Auto Refresh command can be issue before or after Mode Register Set command
PAGE 25
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Timing Waveforms
Figure18. AC Parameters for Write Timing (Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCH
tCL
CKE
tIS
tIS
tIH
Begin Auto
Begin Auto
Precharge Bank A
Precharge Bank B
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
RAx
RAY
RBx
tIS
A0-A9,
A11-A12
CAx
RAx
CBx
RBx
RAY
CAY
DQM
tDAL
tRCD
tIS
tRC
DQ
tWR
tIH
Hi-Z
Ax0
Activate
Command
Bank A
Write with
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Activate
Auto Precharge Command
Command
Bank B
Write with
Activate
Write
Precharge
Auto Precharge
Command
Command
Command
Command
Bank A
Bank A
Bank A
Bank A
Bank B
Don’t Care
PAGE 26
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 19. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16
tCH tCL
CKE
Begin Auto
Precharge Bank B
tIS
tIS
tIH
tIH
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
RBx
RAx
RAy
tIS
A0-A9,
A11-A12
RAx
CBx
RBx
CAx
RAy
tRRD
tRAS
DQM
tRC
tAC
tRCD
DQ
Hi-Z
tRP
tHZ
tLZ
Ax0
Bx0
Ax1
Bx1
tHZ
tOH
Activate
Read
Activate
Write with
Precharge
Activate
Command
Command
Command
Auto Precharge
Command
Command
Bank A
Bank A
Bank B
Command
Bank A
Bank A
Bank B
Don’t Care
PAGE 27
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 20. Auto Refresh (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
CAx
RAx
tRC
tRP
tRC
tRCD
DQM
DQ
Ax0
Precharge All
Auto Refresh
Auto Refresh
Activate
Read
Command
Command
Command
Command
Command
Bank A
Bank A
PAGE 28
www.ctscorp.com
Ax1
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 21. Power on Sequence and Auto Refresh
T0
T1 T2
T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
High Level
CKE
Minimum for 2 Refresh Cycles are required
Is reguired
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11-A12
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Inputs must be
Stable for
Command
1st Auto Refresh
Mode Register
(*)
2nd Auto Refresh
(*)
Command
Command
Set Command
Any
Command
Don’t Care
200µs
Note(*) :The Auto Refresh command can be issue before or after Mode Register Set command
PAGE 29
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 22. Self Refresh Entry & Exit Cycle
T0
T1 T2
CLK
T3 T4 T5 T6 T7
T8 T9 T10
*Note 2
tXSR
*Note 5
*Note 1
CKE
T11 T12 T13 T14 T15 T16 T17 T18 T19
tIS tIH
*Note 3,4
*Note 8
tPDE
*Note 6
*Note 7
tIS
CS#
RAS#
*Note 9
CAS#
WE#
BA0,1
A10
A0-A9,
A11-A12
DQM
Hi-Z
Hi-Z
DQ
Self Refresh Entry
Self Refresh Exit
Auto Refresh
Don’t Care
Note: To Enter SelfRefresh Mode
1. CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enter SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
9. 8192 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system
uses burst refresh.
PAGE 30
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 23.1. Clock Suspension During Burst Read (Using CKE)
(Burst length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
CAx
DQM
tHZ
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
Activate
Read
Clock Suspend
Clock Suspend
Clock Suspend
Command
Command
1 Cycle
2 Cycle
3 Cycle
Bank A
Bank A
Don’t Care
PAGE 31
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 23.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
A10
A0-A9,
A11-A12
RAx
CAx
DQM
tHZ
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
Activate
Read
Clock Suspend
Clock Suspend
Clock Suspend
Command
Command
1 Cycle
2 Cycle
3 Cycle
Bank A
Bank A
Don’t Care
PAGE 32
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 24. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
A10
A0-A9,
A11-A12
RAx
CAx
DQM
Hi-Z
DAx0
DQ
Activate
Command
Bank A
Write
DAx1
DAx2
DAx3
Clock Suspend
Clock Suspend
Clock Suspend
1 Cycle
2 Cycle
3 Cycle
Command
Don’t Care
Bank A
PAGE 33
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 25. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
tIH tIS
tPDE
CKE
Valid
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
CAx
DQM
tHZ
Hi-Z
Ax0
DQ
Ax1
Ax2
ACTIVE
Activate
STANDBY
Command
Bank A
Read
Clock Suspension
Clock Suspension
Command
Start
End
Power Down
Power Down Bank A
Mode Entry
Mode Exit
Ax3
Precharge
Command
Bank A
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
Power Down
Mode Entry
PAGE 34
www.ctscorp.com
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 26.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAW
A0-A9,
A11-A12
RAW
RAz
CAW
CAx
CAy
RAz
CAz
DQM
Hi-Z
Aw0
DQ
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Aw3
Read
Command
Bank A
Ax0
Ax1
Ay0
Ay1
Read
Command
Bank A
Ay2
Ay3
Precharge
Command
Bank A
Az0
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
PAGE 35
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 26.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAW
A0-A9,
A11-A12
RAW
RAz
CAW
CAx
CAy
RAz
CAz
DQM
Hi-Z
Aw0
DQ
Aw1
Aw2
Aw3
Ax0
Activate
Read
Read
Read
Command
Command
Command
Command
Bank A
Bank A
Bank A
Bank A
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
Activate
Read
Command
Command
Bank A
Bank A
Don’t Care
PAGE 36
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 27. Random Column Write (Page within same Bank)
(Burst Length=4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBW
A0-A9,
A11-A12
RBW
RBz
CBx
CBW
CBy
RBz
CBz
DQM
Hi-Z
DBw0
DQ
DBw1
DBw2
DBw3 DBx0
DBx1
DBy0
DBy1
Activate
Write
Write
Write
Command
Command
Command
Command
Bank B
Bank B
Bank B
Bank B
DBy2
DBy3
DBz0
Precharge
Command
Bank B
DBz1
Activate
Write
Command
Command
Bank B
Bank B
Don’t Care
PAGE 37
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 28.1. Random Row Read (Interleaving Banks)
(Burst Length=8， CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
A0-A9,
A11-A12
RBx
RBy
RAx
CBx
RAx
tAC
tRCD
RBy
CAx
CBy
tRP
DQM
Hi-Z
Bx0
DQ
Bx1
Bx2
Bx3
Bx4
Bx5
Activate
Read
Activate
Command
Command
Command
Bank B
Bank B
Bank A
Bx6
Bx7
Ax0
Read
Command
Bank A
Precharge
Command
Bank B
PAGE 38
www.ctscorp.com
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
Activate
Read
Command
Command
Bank B
Bank B
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 28.2. Random Row Read (Interleaving Banks)
(Burst Length=8， CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
A0-A9,
A11-A12
RBx
RBy
RAx
RAx
CBx
RBy
CAx
tAC
tRCD
CBy
tRP
DQM
Hi-Z
DQ
Bx0
Bx1
Bx2
Bx3
Activate
Read
Activate
Command
Command
Command
Bank B
Bank B
Bank A
Bx4
Bx5
Bx6
Read
Command
Bank A
Bx7
Ax0
Precharge
Command
Bank B
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Activate
Read
Command
Command
Bank B
Bank B
Ax7
By0
Precharge
Command
Bank A
Don’t Care
PAGE 39
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 29. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
RAy
RBx
CAx
RAy
CBx
tRCD
tWR*
CAy
tWR*
tRP
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3 DAx4
DAx5
DAx6
DAx7
DBx0
DBx1
Activate
Write
Activate
Write
Command
Command
Command
Command
Bank A
Bank A
Bank B
Bank B
DBx2 DBx3
Precharge
Command
Bank A
DBx4
DBx5
DBx6
DBx7
DAy0 DAy1
Activate
Write
Command
Command
Bank A
Bank A
DAy2
DAy3
Precharge
Command
Bank B
Don’t Care
*tWR>tWR (min.)
PAGE 40
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 30.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
CAy
CAx
CAz
DQM
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Activate
Read
Write
The Write Data
Read
Command
Command
Command
is Masked with a
Command
Bank A
Bank A
Bank A
Zero Clock
Bank A
Latency
PAGE 41
www.ctscorp.com
Az1
Az3
The Read Data
s Masked with a
Two Clock
Latency
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 30.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
CAx
CAy
CAz
DQM
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Activate
Read
Write
The Write Data
Command
Command
Command
is Masked with a
Bank A
Bank B
Bank A
Zero Clock
Read
Latency
Command
Bank A
PAGE 42
www.ctscorp.com
Az1
Az3
The Read Data
s Masked with a
Two Clock
Latency
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 31.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
RBx
CAy
CBw
CBx
Ax3
Bw0
CBy
CAy
CBz
tRCD
DQM
tAC
Hi-Z
Ax0
DQ
Ax1
Ax2
Bw1
Bx0
Bx1
By0
By1
Ay0
Ay1
Activate
Read
Activate
Read
Read
Read
Read
Read
Command
Command
Command
Command
Command
Command
Command
Command
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank A
Bank B
Bz0
Precharge
Command
Bank A
Bz1
Bz2
Bz3
Precharge
Command
Bank B
Don’t Care
PAGE 43
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 31.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
CAx
RBx
CBx
CBy
CBz
CAy
tRCD
DQM
tAC
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Activate
Read
Read
Read
Read
Read
Command
Command
Command
Command
Command
Command
Bank B
Bank B
Bank A
Bank A
Bank A Activate
Bank B
Bz1
Precharge
Command
Bank B
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
Command
Bank B
PAGE 44
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 32. Interleaved Column Write Cycle (Burst Length=4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBw
RBw
CAx
CBw
CBx
CBy
CAy
tRCD
CBz
tWR
tWR
DQM
tRRD>tRRD(min)
Hi-Z
DAx0
DQ
DAx1
DAx2 DAx3
DBw0 DBw1 DBx0 DBx1 DBy0
DBy1
DAy0 DAy1 DBz0
DBz1
DBz2
Activate
Write
Write
Write
Write
Write
Write
Command
Command
Command
Command
Command
Command
Bank A
Bank A
Bank B
Bank B
Bank B
Bank A
Command
Bank B Precharge
Command
Bank A
Activate
Command
DBz3
Precharge
Command
Bank B
Don’t Care
Bank B
PAGE 45
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 33.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
Begin Auto
Begin Auto
Precharge
Precharge
Bank B
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
CAx
RBy
RBx
CBx
CAy
RAz
RBy
CBy
RAz
tRP
DQM
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
Activate
Read
Activate
Read with
Read with
Activate
Read with
Activate
Command
Command
Command
Auto Precharge
Auto Precharge
Command
Auto Precharge
Command
Bank A
Bank A
Bank B
Command
Command
Bank B
Command
Bank A
Bank B
Bank A
PAGE 46
www.ctscorp.com
Bank B
By2
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 33.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
Begin Auto
Begin Auto
Precharge
Precharge
Bank B
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBy
RBx
CAx
RBx
CAy
CBx
RBy
CBy
tRP
DQM
Hi-Z
Ax0
DQ
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Activate
Read
Read with
Read with
Activate
Read with
Command
Command
Auto Precharge
Auto Precharge
Command
Auto Precharge
Bank A
Bank A
Command
Command
Bank B
Command
Bank B
Bank A
Activate
Command
Bank B
By0
By1
By2
Don’t Care
Bank B
PAGE 47
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 34. Auto Precharge after Write Burst (Burst Length=4)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
Begin Auto
Begin Auto
Precharge
Precharge
Bank B
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
CAx
RBy
RBx
CBx
CAy
RBy
CBy
tDAL
RAz
DQM
Hi-Z
DAx0 DAx1
DQ
DAx2
DAx3
DBx0
DBx1 DBx2
DBx3
DAy0
DAy1 DAy2
DAy3
DBy0
DBy1 DBy2
Activate
Write
Write with
Write with
Activate
Write with
Command
Command
Auto Precharge
Auto Precharge
Command
Auto Precharge
Bank A
Bank A
Command
Command
Bank B
Command
Bank B
Bank A
Activate
Command
Bank B
DBy3
Don’t Care
Bank B
PAGE 48
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 35.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
Hi-Z
Ax
DQ
Ax+1
Ax+2
Ax-2
Ax-1
Activate
Read
Activate
Command
Command
Command from the highest order
Bank A
Bank A
Bank B
The burst counter wraps
page address back to zero
during this time interval
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Bx+5
Bx+6
Precharge
Command
Bank B
Read
Command
Bank B
Full Page burst operation does not
Burst Stop
terminate when the burst length is satisfied;
Command
Activate
Command
Bank B
Don’t Care
the burst counter increments and continues
Bursting beginning with the starting address
PAGE 49
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 35.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
CAx
RBy
RBx
CBx
RBy
tRP
DQM
Hi-Z
Ax
DQ
Activate
Read
Activate
Command
Command
Command
Bank A
Bank A
Bank B
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Read
Command
Bank B
Bx+2
Bx+3
Bx+4
Bx+5
Precharge
Command
Bank B
The burst counter wraps
from the highest order
Burst Stop
page address back to zero
Command
Activate
Command
Bank B
Don’t Care
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
Bursting beginning with the starting address
PAGE 50
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 36. Full Page Write Cycle (Burst Length=Full Page)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RBx
RBy
RBx
CAx
CBx
RBy
DQM
Data is ignored
Hi-Z
DAx
DQ
DAx+1
DAx+2
Activate
Write
Activate
Command
Command
Command
Bank A
Bank A
Bank B
DAx+3
DAx-1
DAx
DAx+1
DBx
DBx+1
DBx+2
DBx+3
DBx+4
DBx+5
Write
Command
Bank B
The burst counter wraps
from the highest order
Full Page burst operation does not
page address back to zero terminate when the burst length is satisfied;
the burst counter increments and continues
during this time interval
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
Bursting beginning with the starting address
PAGE 51
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 37. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
CAz
CAy
CAx
DQML
DQMH
DQ0-DQ7
Ax0
DQ8-DQ15
Ax1
Ax2
Ax1
Ax2
DAy1
Ax3
DAy0
Activate
Read
Upper Byte
Lower Byte
Command
Command
is masked
is masked
Bank A
Bank A
Day2
DAy1
Write
Command
Bank A
Az1
DAy3
Az0
Upper Byte
Read
is masked
Command
Bank A
PAGE 52
www.ctscorp.com
Az2
Az1
Lower Byte
is masked
Az2
Az3
Lower Byte
is masked
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 38. Random Row Read (Interleaving Banks) (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
Begin Auto
Begin Auto
Begin Auto
Begin Auto
Precharge
Precharge
Precharge
Precharge
Bank B
Bank A
Bank B
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBu Ax
A0-A9,
A11-A12
RBu Ax
RAu Bx
CBu
RBv
CAu
RAu
RAv
RBv
CBv
RBw
RAv
CAv
RBw
tRP
tRP
tRP
DQM
Bu0
DQ
Activate
Command
Bank B
Read
Bank B
with Auto
Bu1
Bu2
Bu3
Au0
Au1
Au2
Au3
Bv0
Bv1
Bv2
Activate
Read
Activate
Activate
Read
Command
Bank A
Command
Command
Bank A
Bank A
with Auto
Bank B
Bank A
with Auto
Precharge
Read
Bank B
with Auto
Precharge
Precharge
PAGE 53
www.ctscorp.com
Bv3
Av0
Av1
Av2
Av3
Activate
Command
Bank B
Precharge
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 39. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
A0-A9,
A11-A12
RAx
RBx
RBw
CAx
CBx
Cay
CBy
CAz
CBz
RBw
tRP
DQM
tRRD
tRCD
Hi-Z
Ax0
DQ
Ax1
Bx0
Ay0
Ay1
By0
By1
Az0
Az1
Az2
Bz0
Bz1
Bz2
Activate
Activate
Read
Read
Read
Read
Precharge
Activate
Command
Command
Command
Command
Command
Command
CommandBank B
Command
Bank A
Bank B
Bank B
Bank B
Bank A
Bank B
(Precharge Temination)
Bank B
Read
Read
Command
Command
Bank A
Bank A
Don’t Care
PAGE 54
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 40. Full Page Random Column Write (Burst Length=Full Page)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
A0-A9,
A11-A12
RAx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
CBz
RBw
tRP
tWR
DQM
tRRD
Hi-Z
tRCD
DQ
DAx0 DAx1
DBx0
DAy0
DAy1 DBy0 DBy1
DAz0
DAz1
DAz2
DBz0
DBz1
DBz2
Activate
Activate
Write
Write
Write
Write
Precharge
Activate
Command
Command
Command
Command
Command
Command
CommandBank B
Command
Bank A
Bank B
Bank B
Bank B
Bank A
Bank B
(Precharge Temination) Bank B
Write
Write
Command
Command
Bank A
Bank A
Write Data
are masked
PAGE 55
www.ctscorp.com
Don’t Care
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 41. Precharge Termination of a Burst (Burst Length=4,8 or Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11-A12
RAx
RAz
RAy
CAx
RAy
tWR
CAy
RAz
tRP
tRP
DQM
DAx0
DQ
DAx1
Activate
Write
Command
Command
Bank B
Bank A
Ay0
Precharge
Command
Bank A
Precharge Termination
Ay1
Ay2
Activate
Read
Precharge
Activate
Precharge Temination
Command
Command
Command
Command
of a Read Burst
Bank A
Bank A
Bank B
Bank A
of a Write Burst
Write Data are masked
Don’t Care
PAGE 56
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 42.1 CLGA96 Package Information
□11.00±0.15
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
TOP VIEW
2X9.16
P. 1.00X9=9.00±0.1
4x
(R0.15)
4X
P.1.00
0.752
P. 1.00X9=9.00±0.1
G
F
E
D
P.1.00
2X9.16
H
4X
J
0.752
K
C
B
A
92X
10
9
8
7
6
5
4
3
2
1
0.60
INDEX MARK
(C0.20)
BOTTOM VIEW
PAD PLATING Ni: 5μm ;Au: 0.5μm.
PAGE 57
www.ctscorp.com
Rev. B
SDRAM Memory
Technical Data Sheet
Figure 42.2 CLCC64 Package Information
□ 18.29±0.2
56
41
57
40
64
1
8
25
9
24
1.016 +0.15
P. 1.016X16=15.24
P. 1.016
63X
1.524±0.1
TOP VIEW
41
56
40
57
64X
R0.19
INDEX MARK
PIN NO.1
64
64X
0.508
1
8
25
0.508 X45
3X
(R0.095 )
9
24
2.16
+0.20
BOTTOM VIEW
PAD PLATING Au: 1.5μm.
PAGE 58
www.ctscorp.com
Rev. B