IDT IDT70V26S55J

IDT70V26S/L
HIGH-SPEED 3.3V
16K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
Low-power operation
– IDT70V26S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V26L
Active: 300mW (typ.)
Standby: 660µW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆
◆
◆
◆
◆
◆
◆
◆
IDT70V26 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA and PLCC
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
I/O0L-I/O7L
(1,2)
(1,2)
BUSYL
A13L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
14
CEL
Address
Decoder
A13R
A0R
14
ARBITRATION
SEMAPHORE
LOGIC
CER
SEMR
SEML
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs are non-tri-stated push-pull.
2945 drw 01
JUNE 2000
1
©2000 Integrated Device Technology, Inc.
DSC 2945/13
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM.
The IDT70V26 is designed to be used as a stand-alone 256K-bit DualPort RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 32-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by CE permits the on-chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 300mW of power.
The IDT70V26 is packaged in a ceramic 84-pin PGA and
84-Pin PLCC.
A10L
A9L
A11L
A13L
A12L
LBL
UBL
SEML
CEL
OEL
VCC
R/WL
I/O1L
I/O0L
GND
I/O2L
I/O3L
I/O5L
I/O4L
INDEX
I/O6L
I/O7L
Pin Configurations(1,2,3)
I/O8L
12
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
11 10 9 8 7 6
I/O9L
13
73
I/O10L
14
72
I/O11L
15
71
I/O12L
16
70
I/O13L
17
69
GND
18
68
I/O14L
19
I/O15L
20
VCC
21
67
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
IDT70V26J
J84-1(4)
66
65
A0L
BUSYL
84-Pin PLCC
Top View(5)
64
GND
28
58
I/O5R
29
57
I/O6R
30
56
I/O7R
31
55
I/O8R
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
A10R
A9R
A8R
59
A11R
27
I/O4R
A12R
I/O3R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
LBR
60
A13R
26
CER
UBR
VCC
GND
SEMR
61
OER
R/WR
25
I/O15R
I/O2R
GND
BUSYR
I/O14R
M/S
62
I/O12R
I/O13R
63
24
I/O11R
23
I/O1R
I/O10R
22
I/O0R
I/O9R
GND
2945 drw 02
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
63
11
61
I/O7L
I/O10L
I/O15L
LBL
CEL
53
45
A12L
47
50
UBL
46
44
43
52
A7L
33
IDT70V26G
G84-3(4)
32
28
VCC
A0R
7
1
I/O6R
2
I/O9R
3
I/O10R
4
I/O11R
B
11
GND
5
8
I/O13R
I/O15R
6
9
I/O12R
I/O14R
C
D
12
10
14
15
OER
E
A6R
17
UBR
R/WR
13
22
20
A9R
A12R
16
18
LBR
CER
A13R
F
G
H
K
A8R
L
2945 drw 03
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
A5R
21
A10R
J
A4R
24
A7R
19
A11R
A2R
25
23
SEMR
GND
BUSYR
27
A3R
I/O7R
A2L
30
26
83
A
M/S
I/O4R
A0L
36
29
80
I/O8R
A1L
A1R
A3L
34
31
GND
84-Pin PGA
Top View(5)
A5L
37
35
BUSYL
VCC
GND
A6L
39
41
78
I/O2R
I/O5R
40
A4L
74
A8L
A9L
R/WL
VCC
42
A11L
A10L
A13L
73
GND
I/O3R
84
01
SEML
OEL
49
I/O1L
48
38
77
82
02
56
I/O3L
GND
I/O14L
I/O1R
81
03
I/O0L
51
I/O12L
I/O0R
79
04
59
I/O6L
54
57
70
76
05
I/O2L
I/O9L
71
75
06
62
55
68
I/O13L
72
07
I/O4L
I/O8L
I/O11L
69
08
58
65
67
09
I/O5L
64
66
10
60
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A 0L - A13L
A0R - A13R
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
2945 tbl 01
6.42
3
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I — Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power-Down
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected: Power-Down
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATA IN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATA IN
Write to Both Bytes
L
H
L
L
H
H
DATA OUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
H
L
L
L
H
DATA OUT
DATAOUT
Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z
Outputs Disabled
Mode
2945 tbl 02
NOTE:
1. A0L — A 13L≠ A 0R — A 13R
Truth Table II — Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
H
H
L
X
X
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
H
↑
X
X
X
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
X
↑
X
H
H
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
L
X
L
____
____
Not Allowed
L
X
X
X
L
L
____
____
Not Allowed
Mode
2945 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A 0-A2.
6.42
4
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
IOUT
DC Output
Current
VTERM(2)
Maximum Operating Temperature
and Supply Voltage(1,2)
Grade
GND
Vcc
0OC to +70OC
0V
3.3V + 0.3
-40OC to +85OC
0V
3.3V + 0.3
Ambient Temperature
Commercial
Industrial
2945 tbl 05
50
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
mA
2945 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
Recommended DC Operating
Conditions(2)
Symbol
VCC
Supply Voltage
GND
Ground
VIH
V IL
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
CIN
COUT
Parameter
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
Input Capacitance
Output Capacitance
Parameter
Input High Voltage
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
(1)
Input Low Voltage
-0.3
V
(2)
VCC + 0.3
____
0.8
V
V
2945 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
pF
2945 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V26S
Symbol
|ILI|
|ILO|
Parameter
Test Conditions
70V26L
Min.
Max.
Min.
Max.
Unit
10
___
5
µA
Input Leakage Current(1)
VCC = 3.6V, VIN = 0V to VCC
___
Output Leakage Current
CE = VIH, VOUT = 0V to V CC
___
10
___
5
µA
0.4
___
0.4
V
___
2.4
___
V
VOL
Output Low Voltage
IOL = +4mA
___
VOH
Output High Voltage
IOH = -4mA
2.4
2945 tbl 08
NOTE:
1. At VCC < 2.0V, input leakages are undefined.
6.42
5
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 3.3V ± 0.3V)
70V26X25
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
70V26X35
Com'l Only
70V26X55
Com'l Only
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
COM'L
S
L
100
100
170
140
90
90
140
120
90
90
140
120
mA
IND
S
L
____
____
____
____
____
____
mA
____
____
____
____
____
____
COM'L
S
L
14
12
30
24
12
10
30
24
12
10
30
24
mA
IND
S
L
____
____
____
____
____
____
mA
____
____
____
____
____
____
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S
L
50
50
95
85
45
45
87
75
45
45
87
75
mA
IND
S
L
____
____
____
____
____
____
mA
____
____
____
____
____
____
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
mA
IND
S
L
____
____
____
____
____
____
mA
____
____
____
____
____
____
COM'L
S
L
60
60
90
80
55
55
85
74
55
55
85
74
mA
IND
S
L
____
____
____
____
____
____
mA
____
____
____
____
____
____
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
2945 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3.3V
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
GND to 3.0V
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
3ns Max.
Input Timing Reference Levels
3.3V
DATAOUT
BUSY
590Ω
DATAOUT
435Ω
30pF
5pF*
435Ω
Figures 1 and 2
2945 tbl 10
2945 drw 04
Figure 1. AC Output Test Load
6.42
6
2945 drw 05
Figure 2. Output Test Load
(for tLZ , tHZ, tWZ, tOW)
* Including scope and jig.
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4,5)
70V26X25
Com'l Only
Symbol
Parameter
70V26X35
Com'l Only
70V26X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
____
35
____
55
____
ns
tAA
Address Access Time
____
25
____
35
____
55
ns
Chip Enable Access Time
(3)
____
25
____
35
____
55
ns
tABE
Byte Enable Access Time
(3)
____
25
____
35
____
55
ns
tAOE
Output Enable Access Time
____
15
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time (1,2)
3
____
3
____
3
____
ns
tHZ
(1,2)
____
15
____
20
____
25
ns
0
____
0
____
0
____
ns
____
25
____
35
____
50
ns
____
15
____
15
____
ns
35
____
45
____
65
tACE
tPU
Output High-Z Time
Chip Enable to Power Up Time
(2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
Semaphore Address Access Time
____
tSAA
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
50%
50%
ISB
2945 drw 06 ,
6.42
7
ns
2945 tbl 11
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
tAOE
(4)
OE
tABE
(4)
UB, LB
R/W
tLZ
tOH
(1)
(4)
DATAOUT
VALID DATA
tHZ
(2)
BUSYOUT
tBDD
(3,4)
2945 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE , tAA or tBDD .
5. SEM = VIH.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,6)
70V26X25
Com'l Only
Symbol
Parameter
70V26X35
Com'l Only
70V26X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
25
____
35
____
55
____
ns
tEW
Chip Enable to End-of-Write (3)
20
____
30
____
45
____
ns
20
____
30
____
45
____
ns
0
____
0
____
0
____
ns
25
____
40
____
ns
0
____
0
____
ns
____
30
____
ns
____
25
ns
____
ns
tAW
tAS
Address Valid to End-of-Write
Address Set-up Time
(3)
tWP
Write Pulse Width
20
____
tWR
Write Recovery Time
0
____
15
____
20
____
15
____
20
0
____
0
____
0
____
tDW
tHZ
tDH
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
(1,2)
(4)
(1,2)
tWZ
Write Enable to Output in High-Z
15
____
20
____
25
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2945 tbl 12
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
8
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
CE or SEM
(9)
(9)
tAS (6)
tWP
(2)
tWR
(3)
R/W
tWZ
(7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
2945 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9)
tAS
(6)
tWR (3)
tEW (2)
(9)
UB or LB
R/W
tDW
tDH
DATAIN
2945 drw 09
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or t WP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
9
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
VALID ADDRESS
A0-A2
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATAIN
VALID
I/O0
tAS
tWP
DATAOUT
VALID(2)
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2945 drw 10
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID' represents all I/O's (I/O 0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
2945 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
10
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
70V26X25
Com'l Only
Symbol
Parameter
70V26X35
Com'l Only
70V26X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
25
____
35
____
45
ns
tBDA
BUSY Disable Time from Address Not Match
____
25
____
35
____
45
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
25
____
35
____
45
ns
tBDC
BUSY Disab le Time from Chip Enable High
____
25
____
35
____
45
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
____
50
ns
tWH
Write Hold After BUSY
20
____
25
____
25
____
ns
(5)
BUSY INPUT TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
20
____
25
____
25
____
ns
____
55
____
65
____
85
ns
50
____
60
____
80
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
____
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS (1)
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
6.42
11
2945 drw 12
2945 tbl 13
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB
BUSY"B"
tWH
R/W"B"
(1)
(2)
2945 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY "B" goes HIGH.
Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
2945 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2945 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
6.42
12
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
A0L-A13L
A0R-A13R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2945 tbl 14
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V26 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table IV — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V26.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V26 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V26 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
2945 tbl 15
RAM is “busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag an
illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in
slave mode with the M/S pin. Once in slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
6.42
13
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V26 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
BUSYL
MASTER
CE
Dual Port
RAM
BUSYL
BUSYR
SLAVE
CE
Dual Port
RAM
BUSYL
BUSYR
MASTER
CE
Dual Port
RAM
BUSYL
BUSYR
SLAVE
CE
Dual Port
RAM
BUSYL
BUSYR
DECODER
When expanding an IDT70V26 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
BUSYR
2945 drw 16
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V26 RAMs.
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V26 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = H), and the BUSY pin is an input if the part used as
a slave (M/S pin = L) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Semaphores
The IDT70V26 is an extremely fast Dual-Port 16K x 16 CMOS
Static RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port SRAM or any other
shared resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic powerdown feature controlled by CE, the Dual-Port SRAM enable, and SEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where CE and SEM are both HIGH.
Systems which can best use the IDT70V26 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V26's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V26 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V26 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
6.42
14
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other side (see Truth Table IV).
That semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same side,
the flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side's semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table IV). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag low and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay low until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V26’s Dual-Port RAM. Say the
16K x 16 RAM was to be divided into two 8K x 16 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 8K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read back a one
in response to the zero it had attempted to write into Semaphore 0. At
this point, the software could choose to try and gain control of the
second 8K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
SEMAPHORE
READ
6.42
15
D
D0
WRITE
SEMAPHORE
READ
,
2945 drw 17
Figure 4. IDT70V26 Semaphore Logic
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
6.42
16
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
J
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
25
35
55
Commercial Only
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70V26
256K (16K x 16) 3.3V Dual-Port RAM
Speed in nanoseconds
2945 drw 18
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
Datasheet Document History
3/25/99:
6/10/99:
8/6/99:
8/30/99:
11/12/99:
6/6/00:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changed drawing format
Page 1 Removed Preliminary
Page 1 Changed 660mW to 660µW
Replaced IDT logo
Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
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800-345-7015 or 408-727-6116
fax: 408-492-8674
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
for Tech Support:
831-754-4613
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