VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM PRELIMINARY IDT70P257/247L Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Industrial: 55ns (max.) Low-power operation IDT70P257/247L Active: 27mW (typ.) Standby: 3.6µW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT70P257/247 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ M/S = VDD for BUSY output flag on Master M/S = VSS for BUSY input on Slave Input Read Register Output Drive Register BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 1.8V (±100mV) power supply Available in 100 Ball 0.5mm-pitch BGA Industrial temperature range (-40°C to +85°C) Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O8R-I/O15R I/O Control I/O0L-I/O7L I/O Control I/O0R-I/O7R (2,3) (2,3) BUSYL A12L(1) A0L , BUSYR Address Decoder Address Decoder MEMORY ARRAY CEL R/WL IRR0,IRR1 A0R CER INPUT READ REGISTER AND OUTPUT DRIVE REGISTER OEL A12R(1) OER R/WR ODR 0 - ODR4 SFEN 13 CEL OEL R/WL SEML (3) INTL 13 ARBITRATION INTERRUPT SEMAPHORE LOGIC M/S CER OER R/WR SEMR INTR(3) 5684 drw 01 NOTES: 1. A12X is a NC for IDT70P247. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. FEBRUARY 2004 1 ©2004 Integrated Device Technology, Inc. DSC-5684/1 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Description The IDT70P257/247 is a very low power 8K/4K x 16 Dual-Port Static RAM. The IDT70P257/247 is designed to be used as a stand-alone 128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE DualPort SRAM for 32-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port SRAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 27mW of power. The IDT70P257/247 is packaged in a 100 ball 0.5mm- pitch Ball Grid Array. The package is a 1mm thick and designed to fit in wireless handset applications. Pin Configurations(2,3,4) 70P257/247BY BY-100 100-Ball 0.5mm Pitch BGA Top View(5) 02/04/04 A1 A5R B1 A3R C1 A0R D1 A2 A8R B2 A4R C2 A1R D2 A3 A11R B3 A7R C3 A2R D3 A4 UBR B4 A9R C4 A6R D4 ODR4 ODR2 BUSYR INT R E1 Vss F1 E2 M/S F2 E3 ODR3 F3 SFEN ODR1 BUSYL G1 ODR 0 H1 A0L J1 A3L K1 A 6L G2 A 2L H2 A4L J2 A7L K2 A8L G3 A5L H3 A9L J3 A10L K3 A 11L E4 INTL F4 A1L G4 A12L(1) H4 LB L J4 IRR0 K4 UBL A5 Vss B5 CER C5 LBR D5 A10R E5 Vss F5 VDD G5 OEL H5 CEL J5 VDD K5 A6 A7 A8 A9 A10 SEMR I/O15R I/O12R I/O10R B6 R/WR C6 IRR 1 B7 OER C7 B8 VDD C8 D7 A12R(1) I/O13R I/O8R E6 E7 F6 Vss G6 B10 I/O9R I/O6R C9 C10 I/O14R I/O11R I/O7R D6 Vss B9 I/O4R F7 I/O3R G7 D8 E8 VDD F8 Vss D9 Vss D10 I/O5R E9 I/O2R E10 I/O1R F9 Vss F10 I/O0R I/O15L VDD G8 G9 G10 I/O3L I/O11L I/O12L I/O14L I/O13L H6 I/O1L J6 Vss K6 SEML R/W L H7 VDD J7 I/O4L K7 I/O0L H8 NC J8 I/O6L K8 H9 H10 NC I/O10L J9 J10 I/O8L I/O9L K10 K9 I/O2L I/O5L I/O7L 5684 drw 02b NOTES: 1. A12X is a NC for IDT70P247. 2. All VDD pins must be connected to power supply. 3. All V SS pins must be connected to ground supply. 4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2 , IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Pin Names Left Port Right Port Names CEL CER Chip Enable (Input) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A12L(1) A 0R - A 12R(1) Address (Input) I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable (Input) UBL UBR Upper Byte Select (Input) LBL LBR Lower Byte Select (Input) INTL INTR Interrupt Flag (Output) BUSYL BUSYR Busy Flag IRR0, IRR1 Input Read Register (Input) ODR0 - ODR4 Output Drive Register (Output) SFEN(2) Special Function Enable (Input) M/S Master or Slave Select (Input) VDD Power (1.8V) (Input) VSS Ground (0V) (Input) NOTE: 1. A12X is a NC for IDT70P247. 2. SFEN is active when either CEL = V IL or CER = VIL. SFEN is inactive when CEL = CER = VIH. 5684 tbl 01 Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 H X X X X H High-Z High-Z Deselected: Power Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only L H L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled Mode 5684 tbl 02 NOTE: 1. A0L — A12L ≠ A0R — A12R for IDT70P257; A0L — A11L ≠ A0R — A11R for IDT70P247. 6.42 3 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Truth Table II: Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H ↑ X X X L DATAIN DATAIN Write DIN0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN Write DIN0 into Semaphore Flag L X X L X L ____ ____ Not Allowed L X X X L L ____ ____ Not Allowed Mode 5684 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0-A2. Absolute Maximum Ratings(1) Symbol Rating Industrial Unit -0.5 to VDDMAX +0.3V V VTERM(2) Terminal Voltage with Respect to GND TBIAS(3) Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C TJN Junction Temperature +150 o C IOUT DC Output Current 20 mA 5684 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over VTERM = VDD + 0.3V. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. 6.42 4 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Capacitance Maximum Operating Temperature and Supply Voltage(1) (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 11 pF Grade Industrial Parameter Supply Voltage(3) VSS Ground VIH Input High Voltage VIL Input Low Voltage VDD -40OC to +85OC 0V 1.8V + 100mV NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions VDD GND 5684 tbl 05 5684 tbl 07 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Symbol Ambient Temperature Min. Typ. Max. Unit 1.7 1.8 1.9 V 0 0 0 V 1.2 ___ VDD + 0.2 V -0.2 ___ 0.4 V 5684 tbl 06 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VDD + 0.3V. 3. M/S operates at the VDD and VSS voltage levels. 6.42 5 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV) Symbol Parameter ILI Input Leakage Current Output Leakage Current ILO Min. Max. Unit VDD = 1.8V, VIN = 0V to VDD ___ 1 µA CE = VIH, VOUT = 0V to VDD ___ 1 µA IOL = +0.1mA ___ 0.2 V IOH = -0.1mA VDD - 0.2V ___ V Test Conditions VOL Output Low Voltage VOH Output High Voltage 5684 tbl 08 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 1.8V ±100mV) 70P257/247 Ind'l Only Symbol Parameter Test Condition Version Typ. (1) Max. Unit IDD Dynamic Operating Current (Both Ports Active) CE = VIL, Outputs Open f = fMAX(2) IND'L L 15 25 mA ISB1 Standby Current (Both Ports TTL Level Inputs) CE R and CEL = VIH, SEM = VIH f = fMAX(2) IND'L L 2 8 µA ISB2 Standby Current (One Port TTL Level Inputs) CE"A" = V IL and CE"B" = VIH(4), Active Port Outputs Open f = fMAX(2) IND'L L 8.5 14 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, SEML and SEMR > V DD - 0.2V, V IN > VDD - 0.2V or V IN < 0.2V f = fMAX(2), M/S = V DD or V SS(4) IND'L L 2 8 ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE "B" > VDD - 0.2V (4) V IN > V DD - 0.2V or V IN < 0.2V, Active Port Outputs Open f = fMAX(2) IND'L L 8.5 14 NOTES: 1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.) 2. At f = fMAX , address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. If M/S = V SS, then f BUSYL = fBUSYR = 0 for full standby mode. 6.42 6 µA mA 5684 tbl 09 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Test Conditions Input Pulse Levels GND to 1.8V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 0.9V Output Reference Levels 0.9V Output Load Figure 1 5684 tbl 10 1.8V 1.8V R1 R1 13500Ω R2 10800Ω 5684 tbl 10_5 R2 30pF 5684 drw 03 Figure 1. AC Output Test Load (5pF for tLZ , tHZ, tWZ, tOW ) Timing of Power-Up Power-Down CE ICC tPU tPD 50% ISB 50 % , 5684 drw 04 6.42 7 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit READ CYCLE tRC Read Cycle Time 55 ____ ns tAA Address Access Time ____ 55 ns Chip Enable Access Time (3) ____ 55 ns tABE Byte Enable Access Time (3) ____ 55 ns tAOE Output Enable Access Time (3) ____ 30 ns tOH Output Hold from Address Change 5 ____ ns (1,2,5) 5 ____ ns (1,2,5) ____ 25 ns 0 ____ ns ____ 55 ns ns tACE tLZ tHZ tPU Output Low-Z Time Output High-Z Time Chip Enable to Power Up Time (1,2) (1,2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ tSAA Semaphore Address Access (3) ____ 55 ns 5684 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW . 5. At any given temperature and voltage condition, t HZ is less than tLZ for any given device. 6.42 8 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Waveform of Read Cycles(5) tRC ADDR CE tAA (4) (4) tACE (4) tAOE OE (4) tABE UB, LB R/W tLZ DATAOUT tOH (1) (4) VALID DATA tHZ (2) BUSYOUT (3,4) tBDD , 5684 drw 05 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6.42 9 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(4) 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 55 ____ ns tEW Chip Enable to End-of-Write (3) 45 ____ ns tAW Address Valid to End-of-Write 45 ____ ns 0 ____ ns ns (3) tAS Address Set-up Time tWP Write Pulse Width 40 ____ tWR Write Recovery Time 0 ____ ns tDW Data Valid to End-of-Write 30 ____ ns tHZ Output High-Z Time (1,2) ____ 25 ns ns tDH tWZ Data Hold Time (4) 0 ____ (1,2) ____ 25 ns (1,2,4) 0 ____ ns ns Write Enable to Output in High-Z tOW Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 10 ____ tSPS SEM Flag Contention Window 10 ____ ns 5684 tbl 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = V IH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW . 6.42 10 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW (9) CE or SEM CE or SEM (9) tAS (6) tWR (3) tWP (2) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN , 5684 drw 06 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS CE or SEM UB or LB tAW (9) (9) tAS(6) tWR(3) tEW (2) R/W tDW tDH DATAIN 5684 drw 07 ,, NOTES: 1. R/W or CE or UB & LB must be high during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output Test Load. 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 6.42 11 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tO H tSAA A0-A2 VALID ADDRESS tWR tAW VALID ADDRESS tACE tEW SEM tDW DATAIN VALID I/O0 tAS tWP tSOP DATA OUT VALID(2) tDH R/W tSWRD tAOE OE Write Cycle Read Cycle , 5684 drw 08 NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O 0-I/O15)equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 5684 drw 09 NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = V IH. 2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag. 6.42 12 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit BUSY TIMING (M/S = VDD) tBAA BUSY Access Time from Address Match ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 45 ns tBAC BUSY Access Time from Chip Enable LOW ____ 45 ns tBDC BUSY Disable Time from Chip Enable HIGH ____ 45 ns 5 ____ ns (2) tAPS Arbitration Priority Set-up Time tBDD BUSY Disable to Valid Data(3) ____ 40 ns tWH Write Hold After BUSY(5) 35 ____ ns BUSY TIMING (M/S = VSS) tWB BUSY Input to Write (4) 0 ____ ns tWH Write Hold After BUSY(5) 35 ____ ns ____ 80 ns ____ 65 ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) 5684 tbl 13 NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VDD)" or "Timing Waveform of Write With Port-To-Port Delay (M/S = VSS)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6.42 13 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATA OUT "B" VALID tDDD(3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VSS (slave), BUSY is an input. Then for this example BUSY "A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A". Timing Waveform of Slave Write (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH(1) R/W"B" (2) 5684 drw 11 , NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. Busy is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the “slave” version. 6.42 14 , 5684 drw 10 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" , 5684 drw 12 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" ADDRESS "N" tAPS ADDR"B" (2) MATCHING ADDRESS "N" tBAA tBDA BUSY"B" , 5684 drw 13 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ ns tWR Write Recovery Time 0 ____ ns tINS Interrupt Set Time ____ 45 ns tINR Interrupt Reset Time ____ 45 ns 5684 tbl 14 6.42 15 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Waveform of Interrupt Timing(1) tWC (2) ADDR"A" INTERRUPT SET ADDRESS tAS (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 5684 drw 14 , tRC INTERRUPT CLEAR ADDRESS ADDR"B" (2) tAS (3) CE"B" OE"B" tINR(3) , INT"B" 5684 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 6.42 16 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Truth Table III — Interrupt Flag(1) Left Port R/WL CEL OEL Right Port (4) A12L-A0L INTL R/WR CER OER A12R-A0R(4) INTR Function (2) L L X 1FFF X X X X X L Set Right INTR Flag X X X X X X L L 1FFF H(3) Reset Right INTR Flag X X X X L(3) L L X 1FFE X Set Left INTL Flag X L L 1FFE H(2) X X X X X Reset Left INTL Flag NOTES: 1. Assumes BUSYL = BUSY R = VIH. 2. If BUSY L = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A12X is a NC for IDT70P247, therefore Interrrupt Addresses are FFF and FFE. 5684 tbl 15 Truth Table IV — Address BUSY Arbitration Inputs Outputs (4) CEL CER A0L-A12L A0R-A12R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 5684 tbl 16 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70P257/247 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A0L — A11L and A 0R — A11R for IDT70P247. 6.42 17 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D15 Left D0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P257/247. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table VI — Input Read Register Operation(3) SFEN CE R/W OE UB LB ADDR I/O0-I/O1 I/O2-I/O15 Mode H L H L L(1) L(1) x0000 - Max VALID(1) VALID(1) Standard Memory Access L L H L X L x0000 VALID(2) X IRR Read (3) 5684 tbl 18 NOTES: 1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O 7 are VALID. If UB = VIL, then I/O 8 - I/O15 are VALID. 2. LB must be active (LB = VIL) for these bits to be valid. 3. SFEN = V IL to activate IRR reads. Truth Table VII — Output Drive Register Operation(5) SFEN CE R/W H L H L L L L L H OE UB LB (1) (2) (2) X X L L X X L L L ADDR x0000 - Max I/O0-I/O4 (2) VALID I/O5-I/O15 (2) VALID Mode Standard Memory Access x0001 VALID(3) X ODR Write (4,5) x0001 (3) X ODR Read (5) VALID 5684 tbl 19 NOTES: 1. Output enable must be low (OE = Vil) during reads for valid data to be output. 2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O 7 are VALID. If UB = V IL, then I/O8 - I/O15 are VALID. 3. LB must be active (LB = VIL) for these bits to be valid. 4. During ODR writes data will also be written to the memory. 5. SFEN = VIL to activate ODR reads and writes. 6.42 18 5684 tbl 17 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Device 1 IRR0 Preliminary Industrial Temperature Range Device 2 IRR1 Input Read Register (ADDRESS x0000) A0L - A12L(1) A0R - A12R(1) Address & I/O Control I/O0L - I/O15L I/O0R - I/O15R Memory Array 5684 drw 16 Figure 3. Input Read Register Device 2 Device 1 Device 4 Device 3 Device 5 ODR0 ODR1 ODR2 ODR3 ODR4 Output Drive Register (ADDRESS x0001) A0L - A12L(1) I/O0L - I/O15L A0R - A12R(1) Address & I/O Control I/O0R - I/O15R Memory Array 5684 drw 17 Figure 4. Output Drive Register NOTE: 1. A12X is a NC for IDT70P247. 6.42 19 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM BUSYL MASTER Dual Port SRAM BUSYL CE SLAVE Dual Port SRAM BUSYL BUSYR SLAVE Dual Port SRAM BUSYL CE BUSYR CE BUSYR DECODER MASTER Dual Port SRAM BUSYL Preliminary Industrial Temperature Range CE BUSYR BUSYR , 5684 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P257/247 SRAMs. Functional Description The IDT70P257/247 provides two ports with separate control, address and I/O pins that permit independent access to any location in memory. The IDT70P257/247 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX) (FFE for IDT70P247), where a write is defined as the CE=R/W=VIL per Truth Table III. The left port clears the interrupt by accessing address location 1FFE when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) (FFF for IDT70P247) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attemp-ted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The busy outputs on the IDT 70P257/247 SRAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with BUSY Logic Master/Slave Arrays When expanding an IDT70P257/247 SRAM array in width while using busy logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70P257/247 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = VDD), and the BUSY pin is an input if the part used as a slave (M/S pin = VSS) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Input Read Register The Input Read Register (IRR) of the IDT70P257/247 captures the status of two external binary input devices connected to the Input Read pins (e.g. DIP switches). The contents of the IRR are read as a standard memory access to address x0000 from either port and the data is output via the standard I/Os (Truth Table VI). During Input Register reads I/O0 - I/O1 are valid bits and I/O2 - I/O15 are "Dont' Care". Writes to address x0000 are not allowed from either port. When SFEN = VIL, the IRR is active and address x0000 is not available for standard memory operations. When SFEN = VIH, the IRR is inactive and address x0000 can be used as part of the main memory. The IRR supports inputs up to 3.5V (VIL < 0.4V, VIH > 1.4V). Refer to Figure 3 and Truth Table VI for Input Read Register operation. 6.42 20 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Output Drive Register The Output Drive Register (ODR) of the IDT70P257/247 determines the state of up to five external binary-state devices by providing a path to VSS for the external circuit. The five external devices supported by the ODR can operate at different voltages (1.5V < VSUPPLY < 3.5V), but the combined current of the devices must not exceed 40 mA (8mA IMAX for each external device). The status of the ODR bits is set using standard write accesses from either port to address x0001with a “1” corresponding to “on“ and a “0” corresponding to “off”. The status of the ODR bits can also be read (without changing the status of the bits) via a standard read to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for standard memory operations. When SFEN = VIH, the ODR is inactive and address x0001 can be used as part of the main memory. During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 I/O15 are "Don't Care". Refer to Figure 4 and Truth Table VII for Output Drive Register operation. Semaphores The IDT70P257/247 is an extremely fast Dual-Port 8K/4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are LOW. Systems which can best use the IDT70P257/247 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70P257/247's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70P257/247 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active HIGH. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70P257/247 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the 6.42 21 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT70P257/247’s Dual-Port SRAM. Say the 8K/ 4K x 16 SRAM was to be divided into two 4K/2K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K/2K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D SEMAPHORE READ Q SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ 5684 drw 19 Figure 4. IDT70P257/247 Semaphore Logic assume control of the lower 4K/2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K/2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K/2K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned SRAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. 6.42 22 , IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Ordering Information IDT XXXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range I Industrial (-40°C to +85°C) BY 100 Ball 0.5mm-pitch BGA(BY100) 55 Industrial Only Speed in nanoseconds L Low Power 70P257 70P247 128K (8K x 16) 1.8V Dual-Port SRAM 64K (4K x 16) 1.8V Dual-Port SRAM 5684 drw 20 Preliminary Datasheet: Definition "PRELIMINARY' datasheets contain descriptions for products that are in early release. Datasheet Document History 02/04/04: Initial Datasheet CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 23 for Tech Support: 831-754-4613 [email protected]