20160407112425966

APL5934
3A, Ultra Low Dropout (0.23V Typical) Linear Regulator
Features
•
General Description
The APL5934 is a 3A ultra low dropout linear regulator.
The IC needs two supply voltages, one is a control voltage
Ultra Low Dropout
- 0.23V(typical) at 3A Output Current
•
(VCNTL) for the control circuitry, the other is a main supply
voltage (VIN) for power conversion, to reduce power dissi-
Low ESR Output Capacitor (Multi-layer
Chip Capacitors (MLCC)) Applicable
•
•
pation and provide extremely low dropout voltage.
The APL5934/B integrates many functions. A Power-On-
0.8V Reference Voltage
High Output Accuracy
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
- ±1.5% over Line, Load, and Temperature Range
•
•
•
Fast Transient Response
The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A
Adjustable Output Voltage
POK indicates the output voltage status with a delay time
set internally. It can control other converter for power
Power-On-Reset Monitoring on Both VCNTL and
VIN Pins
•
•
•
•
•
•
•
sequence. The APL5934/B can be enabled by other power
systems. Pulling and holding the EN/ENB voltage below
Internal Soft-Start
Current-Limit and Short Current-Limit Protections
0.4V shut/enable off the output.
The APL5934 is available in a SOP-8P package which
Thermal Shutdown with Hysteresis
Open-Drain VOUT Voltage Indicator (POK)
Low Shutdown Quiescent Current
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance to extend power
Shutdown/Enable Control Function
range of applications.
Simple SOP-8P and TDFN3x3-10 Packages with
Applications
Exposed Pad
•
Lead Free and Green Devices Available
•
•
•
(RoHS Compliant)
Front Side Bus VTT (1.2V/3A)
Note Book PC Applications
Motherboard Applications
Simplified Application Circuit
VCNTL
VCNTL
VIN
VIN
POK
VCNTL
VIN
POK
POK
APL5934B/D
APL5934/C
Enable
EN
GND
VOUT
VOUT
VOUT
VOUT
EN
VCNTL
VIN
POK
Enable
FB
ENB
ENB
GND
FB
Optional
Optional
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
1
www.anpec.com.tw
APL5934
Pin Configuration
APL5934/C
APL5934/C
8
7
6
5
1
2
3
4
GND
FB
VOUT
VOUT
POK 1
FB 2
VOUT 3
VOUT 4
VOUT 5
EN
POK
VCNTL
VIN
SOP-8P (Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)
APL5934B/D
APL5934B/D
8
7
6
5
1
2
3
4
POK 1
FB 2
VOUT 3
VOUT 4
VOUT 5
ENB
POK
VCNTL
VIN
SOP-8P (Top View)
10 VCNTL
9 ENB
8 VIN
7 VIN
6 VIN
GND
TDFN3X3-10
(Top View)
= Exposed Pad
(connected to ground plane
for better heat dissipation)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
GND
TDFN3X3-10
(Top View)
= Exposed Pad
(connected to ground plane
for better heat dissipation)
GND
FB
VOUT
VOUT
10 VCNTL
9 EN
8 VIN
7 VIN
6 VIN
= Exposed Pad
(connected to ground plane for better heat dissipation)
2
www.anpec.com.tw
APL5934
Ordering and Marking Information
Product Code (Enable Function)
Blank : Avtive High/Initial On B : Active Low/ Intitial On
C : Active High/Initial Off D : Active Low/Initial Off
Package Code
KA : SOP-8P QB : TDFN3x3-10
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL5934
Assembly Material
Handling Code
Temperature Range
Package Code
Product Code
APL5934
XXXXX
XXXXX - Date Code
APL5934 QB :
APL
5934
XXXXX
APL5934B KA :
L5934B
XXXXX
XXXXX - Date Code
APL5934B QB :
APL
5934B
XXXXX
XXXXX - Date Code
APL5934C KA :
L5934C
XXXXX
XXXXX - Date Code
APL5934C QB :
APL
5934C
XXXXX
XXXXX - Date Code
APL5934D KA :
L5934D
XXXXX
XXXXX - Date Code
APL5934D QB :
APL
5934D
XXXXX
XXXXX - Date Code
APL5934 KA :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
S ymbol
V IN
(Note 1)
Pa ram ete r
VIN Su pply Vo ltag e (VIN to GND)
VCN TL
VCNTL Su pply Vo ltag e ( VCNTL to GND)
VOUT
VOUT to GND Vo ltag e
POK to GND Voltage
EN, FB to G ND Volta ge
PD
Power Dissipation, T A=25oC
I OUT(PK)
VOUT Peak Cu rrent (<3 0µs)
TJ
Rating
Unit
-0.3 ~ 6
V
-0.3 ~ 6
V
-0.3 ~ VIN +0.3
V
-0.3 ~ 6
V
-0.3 ~ VC NTL +0.3
V
1 .5
W
9
Ma xim um Junction Tempera tu re
T STG
Sto rage Temperature
T SDR
Ma xim um Le ad So lderin g Tempe ratu re, 1 0 S econd s
A
15 0
o
C
-65 ~ 1 50
o
C
26 0
o
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
3
www.anpec.com.tw
APL5934
Thermal Characteristics
S ymbol
Pa ramete r
Ju nctio n-to-Ambi ent Resistance in Fre e Ai r
Typica l Value
θ JA
65
50
o
SOP- 8P
8
o
TDFN3 x3- 10
8
SOP- 8P
TDFN3 x3- 10
Ju nctio n-to-Case Resistance in Free Air
Unit
(No te 2 )
C/W
(Note 3)
θ JC
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P/ TDFN3x3-10 is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
VCNTL
VIN
Parameter
VOUT Output Voltage (when VCNTL-VOUT>1.9V)
IOUT
VOUT Output Current
COUT
VOUT Output Capacitance
TA
TJ
Unit
V
1.2 ~ 5.5
V
0.8 ~ VIN – VDROP
V
VIN Supply Voltage
VOUT
ESRCOUT
Range
3.0 ~ 5.5
VCNTL Supply Voltage
Continuous Current
0~3
Peak Current
0~4
IOUT = 3A at 25% nominal VOUT
8 ~ 1100
IOUT = 2A at 25% nominal VOUT
8 ~ 1700
IOUT = 1A at 25% nominal VOUT
8 ~ 2400
A
µF
ESR of VOUT Output Capacitor
0 ~ 200
Ambient Temperature
-40 ~ 85
o
-40 ~ 125
o
Junction Temperature
mΩ
C
C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values
are at TA=25oC.
S ymbol
Param eter
Tes t Condit ions
APL5934
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
I VCN TL
I SD
VCNTL Sup ply Cur rent
EN = High or ENB = Low, I OUT =0A
-
100
120
µA
VCNTL Sup ply Cur rent at Sh utd own
EN = Low, or ENB = High
-
-
3
µA
VIN Su pply Cu rrent at Sh utd own
EN = Low, or ENB = High
-
-
1
µA
2.5
2.7
2.9
V
PO WER-ON-RES ET ( POR)
Ri sin g V CNTL PO R Threshol d
VCNTL PO R Hystere sis
Ri sin g V IN PO R Thresho ld
VIN POR Hystere sis
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
4
-
0.4
-
V
0.8
0.9
1.0
V
-
0.5
-
V
www.anpec.com.tw
APL5934
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values
are at TA=25oC.
Symbol
Param eter
APL5 934
Test Conditions
Unit
Min.
Typ.
Max.
-
0.8
-
V
-1 .5
-
+1.5
%
-
0 .06
0.25
%
%/V
OUTPUT V OLTAGE
V REF
Referen ce Vo ltag e
FB=VOUT
O utp ut Voltage Accu racy
VCN TL =3.0 ~ 5.5V, IOUT = 0~3A,
o
T J= -40~125 C
Lo ad Regula tio n
I OUT =0A ~3A
Li ne Re gula tio n
I OUT =10mA, V CNTL= 3 .0 ~ 5.5V
- 0.15
-
+ 0 .1 5
VOUT Pu ll-low Re sistance
VCN TL =5V , VEN=0V, VOUT <0.8V
-
85
-
Ω
FB Input Cu rrent
VFB=0 .8V
-10 0
-
100
nA
-
0 .26
0.31
-
-
0.42
T J=25 C
-
0 .24
0.29
T J=-40 ~12 5oC
-
-
0.40
-
0 .23
0.28
DROPO UT VO LTAG E
V OU T=2.5V
T J=25 oC
o
T J=-40 ~12 5 C
o
V DROP
VIN-to-VOUT Dropo ut Voltage
VC NTL =5.0V,
I OUT =3A
V OU T=1.8V
o
V OU T=1.2V
T J=25 C
o
T J=-40 ~12 5 C
I LIM
Curre nt-Limit Level
T J=25 oC
V
-
-
0.38
4.7
5.7
6.7
4.2
-
-
-
1.1
-
A
0.6
1.5
-
ms
-
150
-
o
o
A
o
T J= -40 ~ 12 5 C
PROTECTIONS
ISH ORT
T SD
Short Cu rrent-Limit Level
VFB<0 .2V
Short Cu rrent-Limit Blankin g
Time
From begin ning of so ft-start
Ther mal Shutdown Temper ature
T J risin g
Ther mal Shutdown Hystere sis
C
-
50
-
C
0.5
0.8
1.1
V
-
0.1
-
V
-
3
-
µA
ENABLE AND SOFT-START
V EN/VENB
EN Log ic High Thresho ld
Voltage
VEN rising o r V ENB ri sin g
ENB L ogic Low Thre sh old
Voltage
EN/ENB Hystere sis
t SS
EN/ENB Pu ll-High Curre nt
EN=GND or ENB = G ND
EN/ENB Pu ll-Low Curren t
EN=VCNTL or ENB = VCNTL
Soft-Sta rt Interval
VOUT =10 % to 90 %
0.3
0.6
1.2
ms
Turn On Dela y
From being e nabl ed to VOUT risi ng 1 0%
60
120
230
µs
VFB r isin g
90
92
94
%
-
8
-
%
-
0 .25
0.4
V
PO WER-OK AND DELAY
VTHPOK
Rising POK Th reshold Voltage
POK Th reshold Hystere sis
POK Pull -low Vol tag e
PO K sin ks 5mA
POK Debou nce Interval
VFB<falli ng POK voltage thresho ld
-
10
-
µs
POK Delay Time
From VFB =VTHPOK to r isin g edge of th e V POK
1
2
4
ms
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
5
www.anpec.com.tw
APL5934
Pin Description
PIN
NO.
FUNCTION
NAME
SOP -8P
TDFN3 x3-10
1
-
G ND
Gro und pin of the circui try. All voltage levels are measure d with respect to th is
pin .
2
2
FB
Vo lta ge Fe edba ck Pin. Co nnecting this pi n to an exte rnal resistor divider
receives th e fe edback vol ta ge of the regu lator.
VOUT
Ou tpu t pin o f the regu lator. Conne cting this pin to load an d output ca pacito rs
(10 µF at le ast) is requ ired for stabi lity and imp roving transien t respo nse. The
outpu t voltage is prog rammed by th e resistor-divide r conne cted to FB pin. The
VO UT can provide 3A (max.) loa d curr ent to load s. Du ring shutdown, the ou tp ut
voltage is q uickly discharg ed by an i nte rnal pu ll-low MO SFET.
3,4
3,4,5
5
6,7,8
VIN
Main supp ly inp ut pin for voltage conversions. A d ecoupli ng cap acito r ( ≥10µF
recommen ded) i s usua lly con necte d near this pi n to filter the voltage n oise and
impro ve transie nt respo nse. The voltage on this p in is monitore d for
Po wer -On-Re se t pu rpose.
6
10
VCNTL
Bia s voltag e inpu t pi n fo r internal co ntr ol circu itry. Conn ect this pin to a voltage
source (+5V recommen ded). A decoup ling capacitor (0.1µF typi ca l) i s usual ly
conne cted nea r this pin to filter the voltage noise. The voltag e at this pin is
mon itor ed fo r Power-On -Reset pu rpose.
7
1
POK
Po wer -OK signa l o utp ut pin . Th is pin is a n o pen-d rain outpu t used to ind ica te
the statu s o f ou tp ut voltag e by sensing FB voltage . This pi n is pulled low wh en
outpu t voltage is n ot within the Power-O K voltage windo w.
EN
(A PL5 934/C)
Active -high en able control pin. Applying an d h oldin g the voltage on th is pin
bel ow the ena ble voltage thresho ld sh uts down the outpu t. Wh en re-en abled ,
the IC und ergoe s a new soft-start proce ss. W hen l eave this pin o pen, an
intern al pull- up/low curr ent (3 µA typ ica l) pulls the E N voltage an d e nables/shuts
down the regu lator.
ENB
(APL59 34B/D)
Active -low enab le control pin . Ap plying and holdi ng the vo ltage on this pin
bel ow the ena ble voltage thresho ld sh uts down the outpu t. Wh en re-en abled ,
the IC und ergoe s a new soft-start proce ss. W hen l eave this pin o pen, an
intern al pull-u p/low curre nt (3µA typical ) pu lls the ENB vo ltage and shuts
down/en ables the regu lator.
G ND
Gro und pin of th e circuitry. Conn ect th e exp osed pad to the system grou nd plan
with la rge copp er area for dissipating hea t into the ambient air.
8
Exposed
Pad
9
E xpo se d
P ad
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
6
www.anpec.com.tw
APL5934
Typical Operating Characteristics
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
400
VCNTL=5V
VOUT=1.2V
SOP-8P
300
O
TJ=125 C
200
VCNTL=3.3V
VOUT=1.2V
SOP-8P
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
400
TJ=25OC
100
O
TJ=-40 C
300
TJ=125OC
200
TJ=25OC
100
TJ=-40OC
0
0
0
0.5
1
1.5
2.5
2
0
3
0.5
Dropout Voltage vs. Output Current
2
2.5
3
400
VCNTL=5V
VOUT=1.8V
SOP-8P
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
1.5
Dropout Voltage vs. Output Current
400
300
O
TJ=125 C
200
TJ=25OC
100
TJ=-40OC
0
VCNTL=5V
VOUT=2.5V
SOP-8P
300
TJ=125OC
200
TJ=25OC
100
TJ=-40OC
0
0
0.5
1
1.5
2.5
2
0
3
0.5
Output Current, IOUT (A)
Reference Voltage vs. Junction
Temperature
0
0.805
0.8
0.795
0.79
-50
-10
30
70
O
110
-20
-40
1.5
2
2.5
3
VIN Power Supply Rejection Ratio
(PSRR)
VCNTL =5V
VIN=1.2V
VINPK-PK=100mV
VOUT =0.8V
RL=10Ω
CIN=10µF
COUT =10µF
-60
-80
- 100
20
150
100
1k
10k
200k
Frequency (Hz)
Junction Temperature ( C)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
1
Output Current, IOUT (A)
Power Supply Rejection Ratio (dB)
0.81
Reference Voltage, VREF (V)
1
Output Current, IOUT (A)
Output Current, IOUT (A)
7
www.anpec.com.tw
APL5934
Typical Operating Characteristics (Cont.)
Power Supply Rejection Ratio (dB)
0
-20
-40
VCNTL Power Supply Rejection
Ratio (PSRR)
VCNTL =4.6~5.4V
VIN=1.2V
VOUT =0.8V
RL=10Ω
CIN=10µF
COUT =10µF
-60
-80
- 100
20
100
1k
10k
200k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
8
www.anpec.com.tw
APL5934
Operating Waveforms
Power On
Power Off
VCNTL
VCNTL
1
1
VIN
VIN
2
2
VOUT
3
VOUT
3
VPOK
VPOK
4
4
COUT=10µF,CIN=10µF
CH1:VCNTL,5V/Div, DC
CH2:VIN,1V/Div, DC
CH3:VOUT,1V/Div, DC
CH4:VPOK,5V/Div, DC
TIME:4ms/Div
COUT=10µF,CIN=10µF
CH1:VCNTL,5V/Div, DC
CH2:VIN,1V/Div, DC
CH3:VOUT,1V/Div, DC
CH4:VPOK,5V/Div, DC
TIME:40ms/Div
Over Current Protection
Load Transient Response
VOUT
VOUT
1
1
VIN
IOUT
IOUT
VPOK
2
2
C OUT =10 µF,C IN=10µF
CH1:V OUT,500 mV/Div, DC
CH2:I OUT ,2 A/Div, DC
TIME:100 µs/Div
I OUT =10mA to 3 A to 10mA
C OUT =10 µF,C IN=10µF
CH1:V OUT,200 mV/Div, AC
CH2:I OUT ,1 A/Div, DC
TIME:40µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
9
www.anpec.com.tw
APL5934
Operating Waveforms (Cont.)
Enable
Shutdown
V EN
1
1
VEN
VOUT
VOUT
2
2
V POK
VPOK
3
3
IOUT
4
4
C OUT =10 µF,C IN=10µF
CH1:VEN,5V/Div, DC
CH2:VOUT ,1V /Div, DC
CH3:VPOK,5V /Div, DC
CH4:IOUT ,2A/Div, DC
TIME:2µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
IOUT
COUT=10µF,CIN=10µF
CH1:VEN,5V/Div, DC
CH2:VOUT,1V/Div, DC
CH3:VPOK,5V/Div, DC
CH4:IOUT,2A/Div, DC
TIME:1ms/Div
10
www.anpec.com.tw
APL5934
Block Diagram
APL5934
VCNTL
Thermal
Shutdown
VCNTL
POR
Power-OnReset
(POR )
3µA
EN
Turn on
Delay
Enable
Control Logic
and
Soft -Start
0.8V
Enable
S oft -S tart
POK
Enable
VIN
VREF
0.8V
VOUT
POK
Delay
Error Amplifier
IS EN
PWOK
GND
VREF_OK
Current-Limit
Short Current -Limit
92%
VREF
FB
APL5934C
VCNTL
Thermal
Shutdown
EN
Turn on
Delay
3µA
POR
Power-OnReset
(POR )
Enable
Control Logic
and
Soft -Start
0.8V
Enable
Enable
S oft -S tart
POK
VIN
VREF
0.8V
VOUT
POK
Delay
Error Amplifier
IS EN
PWOK
GND
VREF_OK
Current-Limit
Short Current -Limit
92%
VREF
FB
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
11
www.anpec.com.tw
APL5934
Block Diagram (cont.)
APL5934B
VCNTL
Thermal
Shutdown
VCNTL
Power-OnReset
(POR )
POR
3µA
ENB
Turn on
Delay
Enable
Control Logic
and
Soft -Start
0.8V
Enable
S oft -S tart
POK
Enable
VIN
VREF
0.8V
VOUT
POK
Delay
Error Amplifier
IS EN
PWOK
GND
VREF_OK
Current-Limit
Short Current -Limit
92%
VREF
FB
APL5934D
VCNTL
Thermal
Shutdown
ENB
Turn on
Delay
3µA
POR
Power-OnReset
(POR )
Enable
Control Logic
and
Soft -Start
0.8V
Enable
Enable
S oft -S tart
POK
VIN
VREF
0.8V
VOUT
POK
Delay
Error Amplifier
IS EN
PWOK
GND
VREF_OK
Current-Limit
Short Current -Limit
92%
VREF
FB
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
12
www.anpec.com.tw
APL5934
Typical Application Circuit
VCNTL
(+5V is preferred)
CCNTL
0.1µF
R3
5.1kΩ
VCNTL
POK
VIN
+1.8V
CIN
10µF
VIN
POK
VOUT
VOUT
+1.2V / 3A
COUT
10µF
APL5934/C
EN
EN
FB
(X5R/X7R Recommended)
GND
Enable
R2
24kΩ
R1
12kΩ
C1
Optional
(X5R/X7R Recommended)
10µF: GRM31MR60J106KE19 Murata
VCNTL
(+5V is preferred)
CCNTL
0.1µF
R3
5.1kΩ
POK
VIN
+1.8V
CIN
10µF
VCNTL
VIN
POK
VOUT
VOUT
+1.2V / 3A
COUT
10µF
APL5934B/D
ENB
Enable
ENB
FB
(X5R/X7R Recommended)
GND
R2
24kΩ
R1
12kΩ
C1
Optional
(X5R/X7R Recommended)
10µF: GRM31MR60J106KE19 Murata
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
13
www.anpec.com.tw
APL5934
Function Description
Power-On-Reset
Thermal Shutdown
A Power-On-Reset (POR) circuit monitors both of supply
voltages on VCNTL and VIN pins to prevent wrong logic
A thermal shutdown circuit limits the junction temperature of APL5934. When the junction temperature exceeds
+170oC, a thermal sensor turns off the output NMOS, al-
controls. The POR function initiates a soft-start process
after both of the supply voltages exceed their rising POR
lowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start pro-
voltage thresholds during powering on. The POR function also pulls low the POK voltage regardless the output
cess after the junction temperature cools by 50oC, resulting in a pulsed output during continuous thermal over-
status when one of the supply voltages falls below its
load conditions. The thermal shutdown is designed with
a 50oC hysteresis to lower the average junction tempera-
falling POR voltage threshold.
Internal Soft-Start
ture during continuous thermal overload conditions, extending lifetime of the device.
An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The
For normal operation, the device power dissipation should
be externally limited so that junction temperatures will
typical soft-start interval is about 0.6 ms.
not exceed +125oC.
Output Voltage Regulation
Enable Control
An error amplifier works with a temperature-compensated 0.8V reference and an output NMOS regulates
The APL5934/C has a dedicated enable pin (EN). A logic
output to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very
low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the
fast transient response and less load regulation. It compares the reference with the feedback voltage and ampli-
output through initiation of a new soft-start cycle. When
left open, this pin is pulled up/low by an internal current
source (3µA typical) to enable/shutdown normal
fies the difference to drive the output NMOS which provides load current from VIN to VOUT.
operation. It’s not necessary to use an external transistor
to save cost.
Current-Limit Protection
The APL5934B/D has a dedicated enable pin (ENB). A
The APL5934 monitors the current flowing through the
output NMOS and limits the maximum current to prevent
logic high signal applied to this pin shuts down the output.
Following a shutdown, a logic low signal re-enables the
load and APL5934 from damages during current overload conditions.
output through initiation of a new soft-start cycle. When
left open, this pin is pulled up/low by an internal current
Short Current-Limit Protection
source (3µA typical) to shutdown/enable normal
operation. It’s not necessary to use an external transistor
The short current-limit function reduces the current-limit
level down to 1.1A (typical) when the voltage on FB pin
to save cost.
Power-OK and Delay
falls below 0.2V (typical) during current overload or shortcircuit conditions.
The APL5934 indicates the status of the output voltage by
monitoring the feedback voltage (VFB) on FB pin. As the
The short current-limit function is disabled for successful start-up during soft-start interval.
VFB rises and reaches the rising Power-OK voltage threshold (VTHPOK), an internal delay function starts to work. At
the end of the delay time, the IC turns off the internal
NMOS of the POK to indicate that the output is ok. As the
V FB falls and reaches the falling Power-OK voltage
threshold, the IC turns on the NMOS of the POK (after a
debounce time of 10µs typical).
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
14
www.anpec.com.tw
APL5934
Application Information
Power Sequencing
However, if the drop of the input voltage is not cared, the
The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to
input capacitance can be less than 10µF. More capacitance reduces the variations of the supply voltage on VIN
VOUT for a long time when the main voltage applied at
VIN is not present. The reason is the internal parasitic
pin.
Setting Output Voltage
diode from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
The output voltage is programmed by the resistor divider
connected to FB pin. The preset output voltage is calcu-
Output Capacitor
lated by the following equation :
The APL5934 requires a proper output capacitor to maintain stability and improve transient response. The output
R1 

VOUT = 0.8 ⋅ 1 +

 R2 
capacitor selection is dependent upon ESR (equivalent
series resistance) and capacitance of the output capaci-
........... (V)
Where R1 is the resistor connected from VOUT to FB with
Kelvin sensing connection and R2 is the resistor connected from FB to GND. A bypass capacitor(C1) may be
tor over the operating temperature.
Ultra-low-ESR capacitors (such as ceramic chip
connected with R1 in parallel to improve load transient
response and stability.
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as output capacitors.
During load transients, the output capacitors, depending
on the stepping amplitude and slew rate of load current,
are used to reduce the slew rate of the current seen by
the APL5934 and help the device to minimize the variations of output voltage for good transient response. For
the applications with large stepping load current, the lowESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the
load and ground pins as close as possible and the impedance of the layout must be minimized.
Input Capacitor
The APL5934 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance. Ultra-low-ESR capacitors (such as ceramic
chip capaci- tors) and low-ESR bulk capacitors (such as
solid tantalum, POSCap, and Aluminum electrolytic
capacitors) can all be used as an input capacitor of VIN.
For most applications, the recommended input capacitance of VIN is 10µF at least.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
15
www.anpec.com.tw
APL5934
Layout Consideration
1.
Please solder the Exposed Pad on the ground pad
on the top-layer of PCBs. The ground pad must have
Thermal Consideration
Refer to the figure 2, the SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a
wide size to conduct heat into the ambient air through
the ground plane and PCB as a heat sink.
2.
3.
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current applica-
Please place the input capacitors for VIN and VCNTL
pins near the pins as close as possible for
tions. The exposed pad must be soldered to the top-layer
VIN plane. The copper of the VIN plane on the Top layer
decoupling high-frequency ripples.
Ceramic decoupling capacitors for load must be
conducts heat into the PCB and ambient air. Please enlarge the area of the top-layer pad and the VIN plane to
placed near the load as close as possible for
decoupling high-frequency ripples.
4.
5.
reduce the case-to-ambient resistance (θCA).
To place APL5934 and output capacitors near the
load reduces parasitic resistance and inductance
102 mil
for excellent load transient response.
The negative pins of the input and output capacitors
1
and the GND pin must be connected to the ground
plane of the load.
6.
Large current paths, shown by bold lines on the figure 1, must have wide tracks.
7.
Place the R1, R2, and C1 near the APL5934 as close
as possible to avoid noise coupling.
8.
Connect the ground of the R2 to the GND pin by using a dedicated track.
9.
Connect the one pin of the R1 to the load for Kelvin
sensing.
2
118 mil
3
8
SOP-8P
7
6
5
4
Exposed Pad
Top VOUT plane
Die
Top ground
plane
Ambient
Air
PCB
10. Connect one pin of the C1 to the VOUT pin for reliable feedback compensation.
Figure 2
Recommended Minimum Footprint
8
7
6
5
CCNTL
CIN
0.072
0.024
VCNTL
VCNTL
VIN
0.138
0.212
VOUT
VOUT
COUT
C1
FB
GND
R1
0.118
VIN
APL5934
Load
R2
1
2
0.050
Figure 1
3
4
Unit : Inch
SOP-8P
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
16
www.anpec.com.tw
APL5934
Application Information (Cont.)
Recommanded Minimum Footprint (Cont.)
Layout
Package outline
0.06
Unit: Inch
0.04
0.1
0.011
1
10
2
9
3
8
4
7
5
6
0.011
0.06
0.029
TDFN3x3-10
The via diameter = 0.012
Hole size = 0.008
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
17
www.anpec.com.tw
APL5934
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
THERMAL
PAD
E1
E2
D1
c
A1
0.25
A2
A
b
e
GAUGE PLANE
SEATING PLANE
θ
L
VIEW A
S
Y
M
B
O
L
SOP-8P
MIN.
MAX.
MAX.
1.60
A
A1
INCHES
MILLIMETERS
MIN.
0.063
0.000
0.15
0.00
0.006
0.049
A2
1.25
b
0.31
0.51
c
0.17
0.25
0.007
0.010
0.197
0.012
0.020
D
4.80
5.00
0.189
D1
2.50
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
0.157
0.118
E1
3.80
4.00
0.150
E2
2.00
3.00
0.079
0.020
0.050
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
L
0.40
1.27
0.016
0
o
0C
o
o
8C
0C
8oC
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
18
www.anpec.com.tw
APL5934
Package Information
TDFN3x3-10
D
E
A
b
Pin 1
A1
D2
A3
L
K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
A
A1
TDFN3x3-10
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.031
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
2.90
3.10
0.114
0.122
D2
2.20
2.70
0.087
0.106
3.10
0.114
0.122
1.75
0.055
E
2.90
E2
1.40
e
0.50 BSC
L
0.30
K
0.20
0.069
0.020 BSC
0.012
0.50
0.020
0.008
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
19
www.anpec.com.tw
APL5934
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
OD1
B
A
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-8P
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
Application
TDFN3x3-10
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP- 8P
Tape & Reel
2500
TDFN-3x3-10
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
20
www.anpec.com.tw
APL5934
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
TDFN3x3-10
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
21
www.anpec.com.tw
APL5934
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
22
www.anpec.com.tw
APL5934
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
23
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APL5934
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2016
24
www.anpec.com.tw