APL5315 Selectable Adjustable/Fixed Low dropout 300mA Linear Regulator Features General Description • • The APL5315 is a P-channel low dropout linear regulator Wide Operating Voltage: 2.8~6V which needs only one input voltage from 2.8~6V, and delivers current up to 300mA to set output voltage. It also Low Dropout Voltage: 230mV(typical) @ 300mA • • can work with low ESR ceramic capacitors and is ideal for using in the battery-powered applications such as note- Guaranteed 300mA Output Current book computers and cellular phones. Typical dropout voltage is only 230mV at 300mA loading. Two Modes for Setting Output Voltage - Fixed Output Voltage: 1~5V - Adjustable Output Voltage: 0.8~5.5V • • • • • • The APL5315 provides two kinds of output voltage Current Limit Protection with Foldback Current operation modes for setting the output voltage. Fixed output voltage mode senses the output voltage on Internal Soft-Start VOUT, adjustable output voltage mode needs two resistors as a voltage divider. Current limit with current Over Temperature Protection Stable with Low ESR Ceramic Capacitor foldback and thermal shutdown functions protect the device against current over-loads and over temperature. SOT-23-5 Package Lead Free and Green Devices Available The APL5315 is available in a SOT-23-5 package. (RoHS Compliant) Simplified Application Circuit APL5315 VIN 3 CIN 1 VOUT VIN SHDN SET 4 Applications • • • VOUT 5 GND COUT Cellular Phones Portable and Battery-powered Equipment Notebook and Personal Computers 2 Ordering and Marking Information APL5315 Assembly Material Handling Code Temperature Range Package Code Voltage Code Package Code B : SOT-23-5 Operating Junction Temperature Range I : -40 to 85 °C Handling Code TR : Tape & Reel Voltage Code 12 : 1.2V Blank : Adjustable Assembly Material L : Lead Free Device G : Halogen and Lead Free Device Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 1 www.anpec.com.tw APL5315 Marking Information Product Name Marking Product Name Marking Product Name Marking APL5315 35RX APL5315-12 355X APL5315-15 359X APL5315-18 35CX APL5315-25 35JX APL5315- 33 35RX (Note2) Note1 : Other voltage version please contact ANPEC for detail. Note2 : Because APL5315 and APL5315-33 are identical, the marking of APL5315 is same as APL5315-33. Pin Configuration SHDN 1 GND 2 VIN 3 5 SET 4 VOUT SOT-23-5 Absolute Maximum Ratings Symbol VIN VSHDN Rating Unit VIN Supply Voltage (VIN to GND) Parameter -0.3 ~ 6.5 V SHDN Input Voltage (SHDN to GND) -0.3 ~ 6.5 V PD Power Dissipation Internally Limited W TJ Junction Temperature -40 ~ 150 °C TSTG Storage Temperature -65 ~ 150 °C TSDR Lead Soldering Temperature, 10 Seconds 260 °C Thermal Characteristics Symbol θJA θJC Parameter Typical Value Thermal Resistance-Junction to Ambient (Note 3) Thermal Resistance-Junction to Case Unit 240 o 130 o C/W C/W Note3 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol VIN Parameter Range 2.8 ~ 6 V VOUT Output Voltage 0.8 ~ 5.5 V IOUT VOUT Output Current 0 ~ 300 mA CIN Input Capacitor 0.22 ~ 100 µF 1.5 ~ 33 µF COUT TJ VIN Supply Voltage Unit Output Capacitor Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 -40 ~ 125 2 o C www.anpec.com.tw APL5315 Electrical Characteristics Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.8V), IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA = -40 to 85oC. Typical values are at TA = 25oC. APL5315 Symbol VIN VOUT Parameter Test Conditions Unit Min. Typ. Max. Input Voltage 2.8 - 6 V Output Voltage Range 0.8 - 5.5 V IQ Quiescent Current IOUT =10mA ~300mA - 135 160 µA VREF Reference Voltage Measured on SET, VIN=2.8V, IOUT=10mA - 0.8 - V Output Voltage Accuracy TA=25° C, IOUT=10mA -1 - +1 % Output Voltage Accuracy TA=-40° C ~ 85° C, IOUT=10mA -2 - +2 % Line Regulation ∆VOUT%/∆VIN, IOUT=10mA -0.06 - +0.06 %/V ∆VOUT%/∆IOUT -0.2 - +0.2 %/A VOUT = 2.5V, IOUT = 300mA - 230 360 VOUT = 3.3V, IOUT = 300mA - 170 300 f = 10kHz, IOUT = 300mA - 45 - dB f = 80Hz to 100KHz, IOUT = 300mA - 160 - µVRMS 450 600 - mA - 80 - mA SHDN Input Voltage High 1.6 - - SHDN Input Voltage Low - - 0.4 - 0.1 1 µA - 3 - mΩ - 60 - Ω Over Temperature Threshold - 160 - ° C Over Temperature Hysteresis - 40 - ° C - 100 - mV -100 - 100 nA - 60 - µs REGLINE REGLOAD Load Regulation VDROP PSRR Dropout Voltage Power Supply Ripple Rejection Ratio Noise ILIMIT ISHORT Current Limit Foldback Current VOUT = 0V mV V Shutdown VIN Supply Current SHDN = Low, VIN = 6V SHDN Pull Low Resistance VOUT Discharge MOSFET SHDN = Low RDS(ON) SET Input Threshold for Fixed/Adjustable Output Voltage Mode SET Input Bias Current TSS VSET=0.8V Soft-Start Interval Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 3 www.anpec.com.tw APL5315 Typical Operating Characteristics Quiescent Current vs. Supply Voltage Quiescent Current vs. Junction Temperature 160 138 IOUT= 0mV 136 Quiescent Current, IQ (µA) Quiescent Current, IQ (µA) 140 120 100 80 60 40 134 132 130 128 20 126 0 0 1 2 3 4 5 6 7 -50 -25 Supply Voltage, VIN (V) Quiescent Current vs. Output Current 50 75 100 125 PSRR vs. Frequency -10 140 -20 PSRR (dB) 160 VIN=5.5V 120 100 VIN=3.3V, VOUT=1.2V CIN=1µF, COUT=2.2µF IOUT=300mA -30 -40 VIN=4.5V -50 80 -60 60 0 50 100 150 200 250 1000 300 10000 100000 1000000 Frequency (Hz) Output Current, I OUT (mA) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current 300 250 250 TJ=25° C TJ=75° C TJ=125° C 200 150 100 TJ=25° C VOUT=3.3V Dropout Voltage, VDROP (mV) VOUT=2.5V Dropout Voltage, VDROP (mV) 25 0 180 Quiescent Current, IQ (µA) 0 Junction Temperature, T J (° C) TJ=0° C TJ=-50° C 50 TJ=75° C 200 TJ=125° C 150 100 TJ=0° C 50 TJ=-50° C 0 0 0 100 200 Output Current, I OUT (mA) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 0 300 4 100 200 Output Current, IOUT (mA) 300 www.anpec.com.tw APL5315 Typical Operating Characteristics (Cont.) Loop Gain vs. Frequency Phase vs. Frequency 160 50 VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF 40 30 140 IOUT=100mA IOUT=300mA Phase (degree) 120 20 Loop Gain (dB) VIN=3.3V, VOUT=1.2V, CIN=1µF, C OUT=2.2µF 10 0 100 80 60 -10 40 IOUT=300mA -20 IOUT=100mA 20 -30 0 -40 1000 10000 100000 1000 1000000 Frequency (Hz) 10000 100000 1000000 Frequency (Hz) Current Limit vs. Junction Temperature 650 Current Limit, ILIMIT (mA) VIN=5V 600 550 500 450 -50 -25 0 25 50 75 Junction Temperature, T J (° C) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 100 125 5 www.anpec.com.tw APL5315 Operating Waveforms Load Transient Line Transient VIN=3.3V, CIN=1µF, COUT=2.2µF, TR=1µs CIN=1µF, COUT=2.2µF, TR=10µs, IOUT=10mA V OUT V IN V OUT IOUT CH1 : VOUT, 50mV/div, AC CH2 : IOUT, 100mA/div, DC Time : 100µs/div CH1 : VIN, 1V/div, DC CH2 : VOUT, 20mV/div, AC Time : 100µs/div Enable Shutdown V OUT V OUT V SHDN V SHDN I OUT I OUT CH1 : VOUT, 500mV/div CH2 : VSHDN, 5V/div CH3 : IOUT, 200mA/div Time : 50µs/div Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 CH1 : VOUT, 500mV/Div CH2 : V , 5V/Div SHDN CH3 : IOUT, 200mA/Div DC Time : 10µs/Div 6 www.anpec.com.tw APL5315 Operating Waveforms (Cont.) Power on Power off V IN V IN V OUT V OUT I OUT I OUT CH1 : VIN, 2V/div CH2 : VOUT, 500mV/div CH3 : IOUT, 100mA/div Time : 200µs/Div CH1 : VIN, 2V/div CH2 : VOUT,, 500mV/div, CH3 : IOUT, 100mA/div Time : 50ms/Div Pin Description PIN No NAME 1 2 3 4 SHDN GND VIN VOUT 5 SET FUNCTION Shutdown control pin, logic high: enable; logic low: shutdown Ground pin Voltage supply input pin Regulator output pin Connect this pin to ground for fixed output voltage operation. Connect this pin to an external resistor divider for adjustable output voltage mode operation. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 7 www.anpec.com.tw APL5315 Block Diagram SHDN VIN Shutdown Logic Foldback current limit Thermal Shutdown + VOUT Low 3MΩ SET High + 0.8V 100mV GND Typical Application Circuits 1. Fixed Output Voltage Mode APL5315 VIN 3 CIN 1µF 1 VIN VOUT SHDN SET 4 VOUT 5 GND COUT 2.2µF 2 Enable Shutdown 2.2µF/GRM155R60J225M Murata Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 8 www.anpec.com.tw APL5315 Typical Application Circuits (Cont.) 2. Adjustable Output Voltage Mode APL5315 VIN 3 CIN 1µF 1 VOUT VIN SET SHDN VOUT 4 5 R1 GND COUT 2.2µF 2 Enable R2 Shutdown R1 VOUT = 0.8 ⋅ 1 + R2 Function Description Internal Soft-Start allowing the device to cool down. The regulator regulates the output again through initiation of a new soft- An internal soft-start function controls rising rate of the output voltage to limit the surge current at start-up. The start cycle after the junction temperature is cooled down by 40oC.The thermal shutdown designed with a 40oC hys- typical soft-start interval is about 80µs. teresis lowers the average junction temperature during continuous thermal overload conditions, extending life- Output Voltage Regulation The APL5315 can work in either fixed or adjustable mode time of the device. For normal operation, device power dissipation should by connecting the SET to GND or a resistor-divider which receives the feedback voltage of the regulator. The output be externally limited so that junction temperature will not exceed 125oC. voltage set by the resistor-divider is determined by: R1 VOUT = 0.8 ⋅ 1 + R2 Shutdown Control The APL5315 has an active-low shutdown function. Force Where R1 is connected from VOUT to SET with Kelvin sensing and R2 is connected from SET to GND. The SHDN high (>1.6V) enables the VOUT; force SHDN low (<0.4V) disables the VOUT. SHDN is internally pulled low recommended value of R2 is in the range of 100~100kΩ. An error amplifier working with a temperature compen- by a resistor (3mΩ typical). If it is not used, connect to VIN for normal operation. sated 0.8V reference and an output PMOS regulates the output to the presetting voltage. The error amplifier designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load current from VIN to VOUT. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5315. When the junction temperature exceeds +160οC, a thermal sensor turns off the output PMOS, Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 9 www.anpec.com.tw APL5315 Application Information Input Capacitor The APL5315 requires proper input capacitors to supply Operation Region and Power dissipation The APL5315 maximum power dissipation depends surge current during stepping load transients to prevent the input rail from dropping . Because the parasitic induc- on the thermal resistance and temperature difference between the die junction and ambient air. The power dis- tor from the voltage sources or other bulk capacitors to the VIN limit the slew rate of the surge current, place the sipation PD across the device is: PD = (TJ - TA) / θJA Input capacitors near VIN as close as possible. Input capacitors should be larger than 1µF and a minimum where (TJ-TA) is the temperature difference between the junction and ambient air. θ JA is the thermal resistance ceramic capacitor of 1µF is necessary. Output Capacitor between Junction and ambient air. Assuming the TA=25 oC and maximum TJ=160 oC (typical thermal limit The APL5315 needs a proper output capacitor to maintain circuit stability and to improve transient response over threshold), the maximum power dissipation is calculated as: temperature and current. In order to insure the circuit stability, the proper output capacitor value should be larger PD(max)=(160-25)/240 = 0.56(W) than 2.2µF. With X5R and X7R dielectrics, 2.2µF is sufficient at all operating temperatures. Large output capaci- For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power tor value can reduce noise and improve load-transient response and PSRR, however, it also affects power on dissipation should less than: issue. Equation (1) shows the relationship between the maximum COUT value and VOUT. COUT(max) = 31 - PD =(125-25)/240 = 0.41(W) 6 ...............................(1) VOUT The GND provides an electrical connection to ground and channels heat away. Connect the GND to ground by using a large pad or ground plane. Where the unit of COUT is µF and VOUT is V. Figure 1 shows the curve of maximum output capacitor over the output Layout Consideration Figure 2 illustrates the layout. Below is a checklist for voltage. The output voltage range is from 0.8 to 5.5V and the output capacitor value should be under the line. Out- your layout: 1. Please place the input capacitors close to the VIN. put capacitors must be placed at the load and ground pin as close as possible and the impedance of the layout 2. Ceramic capacitors for load must be placed near the load as close as possible. 31 3. To place APL5315 and output capacitors near the load is good for performance. 28 4. Large current paths, the bold lines in figure 2, must have wide tracks. 25 5. Divider resistor R1 and R2 must be placed near the SET as close as possible. Output Capacitor (µF) must be minimized. 22 0 1 2 3 4 5 6 Output voltage (V) Figure 1 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 10 www.anpec.com.tw APL5315 Application Information (Cont.) Layout Consideration (Cont.) CIN APL5315 VIN VOUT SET VIN 3 VOUT 4 5 R1 COUT GND 2 LOAD R2 Figure 2 Recommended Minimum Footprint SOT-23-5 0.05 0.1 0.076 0.038 0.02 Unit : Inch Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 11 www.anpec.com.tw APL5315 Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 MILLIMETERS MIN. INCHES MAX. MIN. MAX. A 0.057 1.45 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c A1 0.08 0.22 0.003 0.009 D 2.70 3.10 0.016 0.122 E 2.60 3.00 0.102 0.118 1.80 0.055 0.071 E1 1.40 e 0.95 BSC e1 0.037 BSC 1.90 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 12 www.anpec.com.tw APL5315 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 178.0±2.00 50 MIN. SOT-23-5 T1 C d D 8.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. P0 P1 P2 D0 D1 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 20.2 MIN. T W E1 8.0±0.30 1.75±0.10 A0 B0 F 3.5±0.05 K0 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 13 www.anpec.com.tw APL5315 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 14 www.anpec.com.tw APL5315 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Package Thickness Volume mm3 <350 Volume mm3 ≥350 <2.5 mm ≥2.5 mm 240 +0/-5°C 225 +0/-5°C 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 Package Thickness 3 Volume mm <350 Volume mm 350-2000 3 Volume mm >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 15 www.anpec.com.tw