CMOS STATIC RAM 256K (32K x 8-BIT) IDT71256SA70 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 32K x 8 CMOS static RAM • Equal access and cycle times -- Commercial: 70ns • One Chip Select plus one Output Enable pin • Bidirectional data inputs and outputs directly TTL-compatible • Low power consumption via chip deselect • Available in 28-pin 30 mil Plastic SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I, and 28-pin 600 mil Plastic Dip. The IDT71256SA is a 262,144-bit medium-speed Static RAM organized as 32K x 8. It is fabricated using IDT’s highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for your memory needs. All bidirectional inputs and outputs of the IDT71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA is packaged in a 28-pin 300 mil Plastic SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I and 28-pin 600 mil Plastic Dip. FUNCTIONAL BLOCK DIAGRAM A0 V CC ADDRESS DECODER 262,144 BIT MEMORY ARRAY GND A14 I/O 0 INPUT DATA CIRCUIT I/O CONTROL I/O 7 CS OE WE CONTROL CIRCUIT 3567 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE JULY 1996 1996 Integrated Device Technology, Inc. 3567/1 1 IDT71256SA70 CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Rating Com’l. Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V TA Operating Temperature 0 to +70 °C TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –55 to +125 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA (2) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 VCC 2 27 WE 3 26 4 25 24 A13 A8 A9 A11 5 6 7 SO28-5 P28-1 P28-2 23 22 OE 21 20 A10 11 19 18 12 17 13 16 14 15 I/O7 I/O6 I/O5 I/O4 I/O3 8 9 10 CS NOTES: 3567 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3567 drw 02 SOJ/DIP TOP VIEW OE 22 21 A 10 A 11 A9 A8 A 13 23 20 CS 24 19 25 18 26 17 WE 27 16 V CC A 14 A 12 A7 A6 A5 A4 A3 28 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A0 A1 A2 15 SO28-8 1 14 2 13 3 12 4 11 5 10 6 9 7 8 CAPACITANCE (TA = +25°C, f = 1.0MHz, SOJ package) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 11 pF VOUT = 3dV 11 pF NOTE: 3567 tbl 03 1. This parameter is guaranteed by device characterization, but not production tested. 3567 drw 03 TSOP TOP VIEW TRUTH TABLE(1,2) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data RECOMMENDED DC OPERATING CONDITIONS Function Symbol Parameter Min. Typ. Max. Unit L H H High-Z Outputs Disabled VCC Supply Voltage 4.5 5.0 5.5 V H X X High-Z Deselected — Standby (ISB) X X High-Z Deselected — Standby (ISB1) GND VIH VIL Supply Voltage 0 Input High Voltage Input Low Voltage 0 2.2 (1) –0.5 0 V — VCC+0.5 V — 0.8 V NOTE: 3567 tbl 01 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. VHC(3) NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC –0.2V. 3. Other inputs ≥VHC or ≤VLC. 3567 tbl 04 DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% IDT71256SA Symbol Min. Max. Unit |ILI| Input Leakage Current Parameter VCC = Max., VIN = GND to VCC Test Condition — 5 µA |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC — 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 V VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V 3567 tbl 05 2 IDT71256SA70 CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V) 71256SA70 Symbol Parameter Com’l. Unit ICC Dynamic Operating Current (2) CS ≤ VIL, Outputs Open, VCC = Max., f = fMAX 130 mA ISB Standby Power Supply Current (TTL Level) (2) CS ≥ VIH, Outputs Open, VCC = Max., f = fMAX 20 mA ISB1 Standby Power Supply Current (CMOS Level) (2) CS ≥ VHC, Outputs Open, VCC = Max., f = 0 VIN ≤ VLC or VIN ≥ VHC 15 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 3567 tbl 06 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 3567 tbl 07 5V 5V 480Ω 480Ω DATA OUT 30pF* DATA OUT 255Ω 5pF* 255Ω 3567 drw 04 3567 drw 05 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 3 IDT71256SA70 CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, CommercialTemperature Range Only) 71256SA70 Symbol Parameter Min. Max. Unit Read Cycle tRC Read Cycle Time 70 — ns tAA Address Access Time — 70 ns tACS Chip Select Access Time — 70 ns tCLZ(2) Chip Select to Output in Low-Z 4 — ns tCHZ(2) Chip Deselect to Output in High-Z 0 11 ns tOE Output Enable to Output Valid — 11 ns (2) Output Enable to Output in Low-Z 0 — ns (2) Output Disable to Output in High-Z 0 10 ns Output Hold from Address Change 3 — ns tPU (2) Chip Select to Power Up Time 0 — ns tPD (2) Chip Deselect to Power Down Time — 25 ns 70 — ns tOLZ tOHZ tOH Write Cycle tWC Write Cycle Time tAW Address Valid to End of Write 20 — ns tCW Chip Select to End of Write 20 — ns tAS Address Set-up Time 0 — ns tWP Write Pulse Width 20 — ns tWR Write Recovery Time 0 — ns tDW Data Valid to End of Write 13 — ns tDH Data Hold Time 0 — ns tOW(2) Output Active from End of Write 4 — ns tWHZ(2) Write Enable to Output in High-Z 0 11 NOTES: 1. 0° to +70°C temperature range only. 2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. ns 3567 tbl 08 TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS (5) tACS tCLZ VCC SUPPLY CURRENT ICC tPU tOHZ (5) HIGH IMPEDANCE DATAOUT (3) tCHZ (5) (5) DATA OUT VALID tPD ISB 3567 drw 06 4 IDT71256SA70 CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 3567 drw 07 TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5) tWC ADDRESS tAW CS tWP(3) tAS tWR WE tWHZ DATAOUT (6) tOW tCHZ (6) HIGH IMPEDANCE (4) tDW DATAIN (6) (4) tDH DATAIN VALID 3567 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID NOTES: 3567 drw 09 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state. 5 IDT71256SA70 CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 71256 Device Type SA XX XXX X Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) P TP Y PZ 600-mil Plastic Dip (P28-1) 300-mil Plastic DIP (P28-2) 300-mil SOJ (SO28-5) TSOP Type I (SO28-8) 70 Speed in nanoseconds 3567 drw 10 6