GA20JT12 CAL

Die Datasheet
Normally – OFF Silicon Carbide
Junction Transistor
GA20JT12-CAL
VDS
=
1200 V
=
50 mΩ
ID @ 25 C
=
45 A
hFE
=
80
RDS(ON)
o
Features








210 °C Maximum Operating Temperature
Gate Oxide Free SiC Switch
Exceptional Safe Operating Area
Excellent Gain Linearity
Temperature Independent Switching Performance
Low Output Capacitance
Positive Temperature Coefficient of RDS,ON
Suitable for Connecting an Anti-parallel Diode
Die Size = 2.85 mm x 2.85 mm
Advantages
Applications














Compatible with Si MOSFET/IGBT Gate Drive ICs
> 20 µs Short-Circuit Withstand Capability
Lowest-in-class Conduction Losses
High Circuit Efficiency
Minimal Input Signal Distortion
High Amplifier Bandwidth
Down Hole Oil Drilling, Geothermal Instrumentation
Hybrid Electric Vehicles (HEV)
Solar Inverters
Switched-Mode Power Supply (SMPS)
Power Factor Correction (PFC)
Induction Heating
Uninterruptible Power Supply (UPS)
Motor Drives
Table of Contents
Section I: Absolute Maximum Ratings ...........................................................................................................1
Section II: Static Electrical Characteristics ....................................................................................................2
Section III: Dynamic Electrical Characteristics .............................................................................................2
Section IV: Figures ...........................................................................................................................................3
Section V: Driving the GA20JT12-CAL ...........................................................................................................6
Section VI: Mechanical Parameters ............................................................................................................. 10
Section VII: Chip Dimensions ....................................................................................................................... 10
Section VIII: SPICE Model Parameters ........................................................................................................ 12
Section I: Absolute Maximum Ratings
o
(TC = 25 C unless otherwise specified)
Parameter
Drain – Source Voltage
Continuous Drain Current
Continuous Drain Current
Continuous Gate Current
Symbol
VDS
ID
ID
IG
Turn-Off Safe Operating Area
RBSOA
Short Circuit Safe Operating Area
SCSOA
Reverse Gate – Source Voltage
Reverse Drain – Source Voltage
Operating Junction and Storage
Temperature
Maximum Processing Temperature
Feb 2016
Conditions
VGS = 0 V
TC = 25°C
TC > 125°C, assumes RthJC < 0.53 oC/W
TVJ = 210 oC,
Clamped Inductive Load
TVJ = 210 oC, IG = 1 A, VDS = 800 V,
Non Repetitive
Value
1200
45
20
1.3
ID,max = 20
@ VDS ≤ VDSmax
Unit
V
A
A
A
Notes
A
Fig. 16
>20
µs
VSG
VSD
30
25
V
V
Tj, Tstg
-55 to 210
°C
325
°C
TProc
10 min. maximum
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Die Datasheet
GA20JT12-CAL
Section II: Static Electrical Characteristics
Parameter
Symbol
Conditions
Min.
Value
Typical
Max.
Unit
Notes
mΩ
Fig. 4
V
Fig. 7
–
Fig. 5
μA
Fig. 8
A: On State
Drain – Source On Resistance
RDS(ON)
ID = 20 A, Tj = 25 °C
ID = 20 A, Tj = 150 °C
ID = 20 A, Tj = 175 °C
Gate – Source Saturation Voltage
VGS,SAT
ID = 20 A, ID/IG = 40, Tj = 25 °C
ID = 20 A, ID/IG = 30, Tj = 175 °C
hFE
VDS = 8 V, ID = 20 A, Tj = 25 °C
VDS = 8 V, ID = 20 A, Tj = 125 °C
VDS = 8 V, ID = 20 A, Tj = 175 °C
Drain Leakage Current
IDSS
VDS = 1200 V, VGS = 0 V, Tj = 25 °C
VDS = 1200 V, VGS = 0 V, Tj = 150 °C
VDS = 1200 V, VGS = 0 V, Tj = 175 °C
Gate Leakage Current
ISG
VSG = 20 V, Tj = 25 °C
DC Current Gain
50
85
95
3.44
3.24
80
50
45
B: Off State
1
1
2
20
nA
Section III: Dynamic Electrical Characteristics
Parameter
Symbol
Conditions
Min.
Value
Typical
Unit
Notes
3825
56
22
pF
pF
µJ
Fig. 9
Fig. 9
Fig. 10
100
pF
Max.
A: Capacitance and Gate Charge
Input Capacitance
Reverse Transfer/Output Capacitance
Output Capacitance Stored Energy
Effective Output Capacitance,
time related
Effective Output Capacitance,
energy related
Gate-Source Charge
Gate-Drain Charge
Gate Charge - Total
B: Switching
VGS = 0 V, VDS = 800 V, f = 1 MHz
VDS = 800 V, f = 1 MHz
VGS = 0 V, VDS = 800 V, f = 1 MHz
Coss,tr
ID = constant, VGS = 0 V, VDS = 0…800 V
Coss,er
VGS = 0 V, VDS = 0…800 V
70
pF
QGS
QGD
QG
VGS = -5…3 V
VGS = 0 V, VDS = 0…800 V
25
80
105
nC
nC
nC
VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC
0.13
12
15
25
12
15
13
30
10
320
40
360
300
30
330
Ω
ns
ns
ns
ns
ns
ns
ns
ns
µJ
µJ
µJ
µJ
µJ
µJ
1
Internal Gate Resistance – ON
Turn On Delay Time
Fall Time, VDS
Turn Off Delay Time
Rise Time, VDS
Turn On Delay Time
Fall Time, VDS
Turn Off Delay Time
Rise Time, VDS
Turn-On Energy Per Pulse
Turn-Off Energy Per Pulse
Total Switching Energy
Turn-On Energy Per Pulse
Turn-Off Energy Per Pulse
Total Switching Energy
1
Ciss
Crss/Coss
EOSS
RG(INT-ON)
td(on)
tf
td(off)
tr
td(on)
tf
td(off)
tr
Eon
Eoff
Etot
Eon
Eoff
Etot
Tj = 25 ºC, VDS = 800 V,
ID = 20 A, Resistive Load
Refer to Section V for additional
driving information.
Tj = 175 ºC, VDS = 800 V,
ID = 20 A, Resistive Load
Tj = 25 ºC, VDS = 800 V,
ID = 20 A, Inductive Load
Refer to Section V.
Tj = 175 ºC, VDS = 800 V,
ID = 20 A, Inductive Load
Fig. 11, 13
Fig. 12, 14
Fig. 11
Fig. 12
Fig. 11, 13
Fig. 12, 14
Fig. 11
Fig. 12
– All times are relative to the Drain-Source Voltage VDS
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Die Datasheet
GA20JT12-CAL
Section IV: Figures
A: Static Characteristics
Figure 1: Typical Output Characteristics at 25 °C
Figure 2: Typical Output Characteristics at 150 °C
Figure 3: Typical Output Characteristics at 175 °C
Figure 4: On-Resistance vs. Gate Current
Figure 5: Normalized On-Resistance vs. Temperature
Figure 6: DC Current Gain vs. Drain Current
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Die Datasheet
Figure 7: Typical Gate – Source Saturation Voltage
GA20JT12-CAL
Figure 8: Typical Blocking Characteristics
B: Dynamic Characteristics
Figure 9: Input, Output, and Reverse Transfer Capacitance
Figure 10: Energy Stored in Output Capacitance
Figure 11: Typical Switching Times and Turn On Energy
Losses vs. Temperature
Figure 12: Typical Switching Times and Turn Off Energy
Losses vs. Temperature
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Die Datasheet
2
GA20JT12-CAL
Figure 13: Typical Switching Times and Turn On Energy
Losses vs. Drain Current
Figure 14: Typical Switching Times and Turn Off Energy
Losses vs. Drain Current
Figure 15: Typical Hard Switched Device Power Loss vs.
Switching Frequency 2
Figure 16: Turn-Off Safe Operating Area
– Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
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Die Datasheet
GA20JT12-CAL
Section V: Driving the GA20JT12-CAL
Drive Topology
TTL Logic
Constant Current
High Speed – Boost Capacitor
High Speed – Boost Inductor
Proportional
Pulsed Power
Gate Drive Power
Consumption
High
Medium
Medium
Low
Lowest
Medium
Switching
Frequency
Low
Medium
High
High
High
N/A
Application Emphasis
Availability
Wide Temperature Range
Wide Temperature Range
Fast Switching
Ultra Fast Switching
Wide Drain Current Range
Pulse Power
Coming Soon
Coming Soon
Production
Coming Soon
Coming Soon
Coming Soon
A: Static TTL Logic Driving
The GA20JT12-CAL may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must
meet or exceed the steady state gate current (I G,steady) required to operate the GA20JT12- CAL. The power level of the supply can be
estimated from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and
the DC current gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 6.
5V
SiC SJT
TTL
Gate Signal
D
G
5/0V
TTL i/p
IG,steady
S
Figure 17: TTL Gate Drive Schematic
B: High Speed Driving
The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate
current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 18 which features a positive
current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on.
Figure 18: An idealized gate current waveform for fast switching of an SJT.
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
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Die Datasheet
GA20JT12-CAL
Ideally, IG,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady
on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A
voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin
to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to
counter these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in
order to speed up the turn-off transition.
Two high-speed drive topologies for the SiC SJTs are presented below.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA20JT12- CAL may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a
gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while
in on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology.
C2
+12 V
GA03IDDJT30-FR4
Gate Driver Board
VGL
VCC High
U3
C5
VCC High RTN
CG1
VGL
VGH
Signal
R1
R2
U1
CG2
U5
R4
C9
VEE C6
Gate
Signal
VEE C10
VGL
R3
U2
VEE
VCC Low RTN
G
SiC SJT
RG2
S
C8
VGH
VCC Low
C1
VEE
IG
RG1
U6
D1
Signal RTN
+12 V
D
Gate
VGL
U4
C3
C4
Source
VEE
Voltage Isolation Barrier
Figure 19: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance3 of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA20JT12- CAL. The steady state current supplied to the gate pin of the GA20JT12- CAL with on-board RG = 3.75 Ω, is
shown in Figure 20. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 21.
For the GA20JT12-CAL, RG must be reduced for ID ≥ ~13 A for safe operation with the GA03IDDJT30-FR4.
For operation at ID ≥ ~13 A, RG may be calculated from the following equation, which contains the DC current gain hFE (Figure 6) and the gatesource saturation voltage VGS,sat (Figure 7).
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Die Datasheet
Figure 20: Typical steady state gate current supplied by the
GA03IDDJT30-FR4 board for the GA20JT12-CAL with the on
board resistance of 3.75 Ω
GA20JT12-CAL
Figure 21: Maximum gate resistance for safe operation of
the GA20JT12-CAL at different drain currents using the
GA03IDDJT30-FR4 board.
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA20JT12- CAL at high-speed. It utilizes a gate drive
inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a
specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S 1, S2, S3, and S4, as shown in Figure 22.
After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer
to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional
information on this driving topology.4
VCC
S1
VCC
S2
L
VEE
S3
SiC SJT
D
G
RG
S4
S
VEE
Figure 22: Simplified Inductive Pulsed Drive Topology
3
– RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω
4
– Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013
Feb 2016
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Die Datasheet
GA20JT12-CAL
C: Proportional Gate Current Driving
For applications in which the GA20JT12- CAL will operate over a wide range of drain current conditions, it may be beneficial to drive the
device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous
drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA20JT12- CAL
C:1: Voltage Controlled Proportional Driver
The voltage controlled proportional driver relies on a gate drive IC to detect the GA20JT12- CAL drain-source voltage VDS during on-state to
sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power
consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the
drain and sense protects the IC from high-voltage when the driver and GA20JT12- CAL are in off-state. A simplified version of this topology is
shown in Figure 23, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
HV Diode
Sense
Gate Signal
Proportional
Gate Current
Driver
Signal
D
G
Output
IG,steady
SiC SJT
S
Figure 23: Simplified Voltage Controlled Proportional Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA20JT12CAL during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain
which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA20JT12- CAL is initially tuned-on using a gate current pulse
supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption,
to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 24,
additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/.
N2
SiC SJT
Gate Signal
D
G
S
N3
N1
N2
Figure 24: Simplified Current Controlled Proportional Driver
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Die Datasheet
GA20JT12-CAL
Section VI: Mechanical Parameters
Die Dimensions
Die Area total / active
2.85 x 2.85
mm2
112 x 112
mil2
8.12/6.60
mm2
12544/10237
mil2
360
µm
14
mil
100
mm
3937
mil
0
deg
0
deg
Die Thickness
Wafer Size
Flat Position
Die Frontside Passivation
Polyimide
Gate/Source Pad Metallization
4000 nm Al
Bottom Drain Pad Metallization
400 nm Ni + 200 nm Au
Die Attach
Electrically conductive glue or solder
Wire Bond
Al ≤ 10 mil (Source)
Al ≤ 3 mil (Gate)
Φ ≥ 0.3 mm
Reject ink dot size
Store in original container, in dry nitrogen,
Recommended storage environment
< 6 months at an ambient temperature of 23 °C
Section VII: Chip Dimensions
A
C
E
DIE
F
G
D
B
SOURCE
WIREBONDABLE
H
GATE
WIREBONDABLE
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mm
mil
A
2.85
112
B
2.85
112
C
2.23
88
D
2.29
90
E
0.30
12
F
0.53
21
G
0.44
17
H
0.43
17
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Die Datasheet
GA20JT12-CAL
Revision History
Date
2015/02/06
2014/07/14
Revision
1
0
Comments
Updated Electrical Characteristics
Initial release
Supersedes
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
Feb 2016
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Die Datasheet
GA20JT12-CAL
Section VIII: SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/hit_sic/baredie/sjt/GA20JT12-CAL_SPICE.pdf) into LTSPICE
(version 4) software for simulation of the GA20JT12-CAL.
*
MODEL OF GeneSiC Semiconductor Inc.
*
*
$Revision:
2.2
$
*
$Date:
26-FEB-2016
$
*
*
GeneSiC Semiconductor Inc.
*
43670 Trade Center Place Ste. 155
*
Dulles, VA 20166
*
*
COPYRIGHT (C) 2016 GeneSiC Semiconductor Inc.
*
ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA20JT12 NPN
+ IS
9.833E-48
+ ISE
1.073E-26
+ EG
3.23
+ BF
88
+ BR
0.55
+ IKF
5000
+ NF
1
+ NE
2
+ RB
3.09
+ IRB
0.006
+ RBM
0.101
+ RE
0.005
+ RC
0.035
+ CJC
910E-12
+ VJC
3.2509
+ MJC
0.51624
+ CJE
2.77e-9
+ VJE
2.896
+ MJE
0.472
+ XTI
3
+ XTB
-1.5
+ TRC1
8.500E-3
+ VCEO
1200
+ ICRATING 20
+ MFG
GeneSiC_Semiconductor
*
* End of GA20JT12 SPICE Model
Feb 2016
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