AMD Tech Day:Intel s new Core™ Microarchitecture (Holger Gruen)

!
"#
$ %
"
!
'
"
!
"
*
"
"
( " )'
""
"
4
/
+
, 0/ 5 6778'
"
)
" (" )
!
)
" (" )
'
'
"
"
'
"
'
)
$
. .
23.
2
'
) %
"
)
+ ,+ - ./ 0
, + ' /
.$
1
"&
"
'
./ 0
+ ,2 . +
$
.
/
.
'
.$
/
,
/
$
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
!
&'
( ) *+
'
*
/
$"
%
&'
( ) *+
'
*
$"
%
( ) *+
'
*
0 #
,
%
( ) *+
'
*
* %
"
+
.
( ) *+
1
= >
.
( ) *+
'
*
( ) *+
'
*
A2
" #
"
( ) *+
'
*
=
:.
+ 2 .
1 0 .
?
#
.
./ .
@
:
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
Innovations
"
+
(
.
./ .
#
A
1 C
!
#
B
1
.
@6
.
./ .
./
+
1
+
!
- 0
/
2
.
./ .
1
+
+
/
9 /
9=
9 +
+
+
1
, ..
./
1
+
1
.
1 0
1+
?
?=A
0
0
.,
+ ,
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
2
.
4
/
/
/5 "
/
:
.
EF
A
D
#
#
$
7
6
%
"#
/
7
.
. : +
( "6'6$
88
G'=788
0+
,
.
" >= >% "
7*
7
Q
7
7
7
7
4 / 8A4 %87
.
F
6I= ("6
./ '6$
87
GH
(H
= 7;
# % "
% "
26 7 5 "
"
"
-?
1
" # % "
7
7
G
7
7
F
"#
F
"#
7
7
7
7
1=
F
"#
1=
1=
1=
F
"#
F
"#
1=
+
G
4 / 8A4 %87
.
F
6I= ( "6
./ '6$
87
GH
$
"
- % "
7
?
:*
"
@A "
/
":
@
1
B
0:
#
77
;7
'7 7
!: = 7
D %E% :
$ -C
1
3
E
$
)
7
%
)- " 8
9F
A ( "6
./ '6$
88
G'=788
G (H
'
# JKL% I
/
'+
# JKL%(% 2
' :
.
(
M + ,= (
6 88KL:L:L:=L F
6IL=6 (H
M
# /
,
K$
6$
6$
=778M
/:
:
;&
F
6I= ('6$
87
GH
' 4
4 I
4677./
'
"
,
%677 :
2
'(
% 6C$
(
=6*
6C*
677L' 1 N
L:O: 0 PI :6-P P...P +P 2P0 P
P6L67C$I M + ,= (
A776:6:6:L F
6IL=6 (H
M
- % " <
4
4%=J77% %
'
, 8$
C 1
?
, 1 1
?O$
6C$
=M I 4
+
I4=78(C77 7C77 ( ;
F
K677
'=8 ( . ./ H
'
.% J$
7.'
0 , +?!
4%
(
6877 6
$! " #
$
#
$
"
#
#
$%
#
$ "
&#
"#
"'
$
#
$
(
$"
"
#
$)
")
$
"
#
"
"
"#
(*
$
" "#
"#
"
#
#
$
(+ #
" #
"#
$
"#
"'
$
,
%
%
)))(
( #% " #
%
% $ &( #
4 /
. +
3
+
2
/
,
+ ,2
/
/ 6#
//!
##
"
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
G
/
#
9;
9 +
9
Instruction Fetch
and PreDecode
Instruction Queue
uCode
ROM
5
Decode
4
Rename/Alloc
Retirement Unit
(ReOrder Buffer)
"
.
.
./
>
+>
9A
.
1 =
(
2M/4M
9A:L
.
.
shared L2
9
BR + . :
=S
Cache
9 +
1 S
B +.
up to
9A
10.4 Gb/s
9A
FSB
4
9A
0
S
+ 0
.
S
+
Schedulers
ALU
Branch
MMX/SSE
FPmove
ALU
FAdd
MMX/SSE
FPmove
ALU
FMul
MMX/SSE
FPmove
Load
Store
L1 D-Cache and D-TLB
9
9
./
I.
0
"# =
$$'# % "
,
. .-.,.
"
.,
= .,. 1 C.,.
"# =
"
>/
"
>
)
"1
"
>
"
!
"
A
%
"
)
= )
"
)
"1
E
%
G
A
%
C!
T
6
G
/
$ 1 H
!
"
C!
>
6
T
)
= )
)
G
/ "1
$ 1 H
E
# % "$
"# = E
>D
%
"# =
"
>
)
- %
/
"6
"=
>
"
"
"
"
A
C
6
=
./
./
"
>
%
>
"# =
"
>
)
- %
/
"6
"=
>
"
"
"
"
A
C
6
=
./
./
%
>
=
"# =
"
>
)
- %
/
"6
"=
>
"
"
"
"
A
C
6
=
./
./
- %
##
%
#
"# =
"
>
)
- %
"=
>
"
"
"
"
A
C
6
=
./
/
"6
./
1
=
"# =
"
>
)
- %
9
>
"
"
"
"
O
/
"=.
U
U
U
6
= ./ .
2
/
A
C
1
9 6
6
.--0%
+
##
=9
.
/
+
%
0
D 00
>
2
/
.
"6:.
./
.
.
/
.
.
/
+
+
./
#
/ "6 . ./
.
+
.
=
E
=
%
"# =
A
$
% )
9;
9;
9I
-
;$A
1
#
)
9 & AG
9 $#
>
E
/
$
/ 1,
:
3
./
1
G
/
E
#
(
+ + ./
./ . / /
/ . ./
E
>+
E
"# =
9
9
9 1
-
0
, >
0
+
+
1
$=
.
0. , +
. I.
'
1 0
1
+
.
+
2
.
%
%
7
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
$ ""
>
9
./
V (00
1
:
I.
>
96 .
.,
1
9
,
200
+
9
./
9
.+ +
1
1 .
0+
I.
?
/ 0 $
0
*
!
W
$
.+
9
:
+
9
.
9
+
+
9
.
./ .
9
++ ,
9;<
.
BJ