DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30700,30700L,30710
VR10000TM, VR12000TM
64-BIT MICROPROCESSORS
DESCRIPTION
The µPD30700 and 30700L (VR10000) and µPD30710 (VR12000) are new members of NEC’s VR seriesTM RISC
(Reduced Instruction Set Computer) microprocessors. These new high-performance 64-bit microprocessors employ
a new RISC architecture developed by MIPSTM, ANDESTM architecture.
The VR10000 and VR12000 are designed to be used in high-performance computers and achieve considerably
higher processing speed through the employment of a super scalar pipeline.
Remark ANDES: Architecture with Non-sequential Dynamic Execution Scheduling
The functions of these microprocessors are described in detail in the following manuals. Be sure to read these
manuals when designing systems.
VR10000, VR12000 User’s Manual
: U10278E
VR5000TM, VR10000 User’s Manual - Instruction : U12754E
FEATURES
• MIPS 64-bit RISC architecture
• High-speed operation processing
• Operating frequency
<VR10000>
Super scalar pipeline executing five instructions in parallel
• Internal: 250 MHz MAX.
<VR10000>
• External: 250 MHz MAX.
• 14SPECint95, 23SPECfp95
• External/internal multiplication factor selectable from
<VR12000>
1 to 4
• 17SPECint95, 27SPECfp95
•
•
<VR12000>
Instruction set upward-compatible with V R4000 TM,
• Internal: 300 MHz MAX.
VR4200TM,
• External: 150 MHz MAX.
and
VR4400TM
(conforms to MIPS-I/II/III/IV)
High-speed translation lookaside buffer (TLB) (64 double
• External/internal multiplication factor selectable from
entries)
•
2 to 10
Address space Physical: 40 bits
Virtual: 44 bits
•
Multi-processor function
• Up to four buses of cluster connection can be connected.
•
• Supply voltage
• Primary cache memory (32K bytes for each of instruction <VR10000>
Floating-point unit (FPU)
and data, 2-way set associative)
• Secondary cache memory interface
• 128-bit secondary cache interface
• SSRAM interface (VR10000: 250 MHz MAX., VR12000:
VDD = 3.3 V ±0.165 V (µPD30700)
VDD = 2.6 V ±0.1 V (µPD30700L)
<VR12000>
VDD = 2.6 V ±0.1 V (µPD30710)
200 MHz MAX.)
• Supports up to 16M bytes
Unless otherwise specified, the VR10000 is treated as the representative model throughout this document.
The information in this document is subject to change without notice.
Date No. U12703EJ1V0DS00 (1st edition)
Date Published June 1998 N CP(K)
Printed in Japan
1998
©
© MIPS Technologies Inc. 1998
µPD30700,30700L,30710
APPLICATIONS
• UNIXTM servers
• Windows NTTM servers
• Desktop workstations, etc.
ORDERING INFORMATION
Part Number
Maximum Internal Operating Frequency
µPD30700RS-180
599-pin ceramic LGA
180
µPD30700RS-200
599-pin ceramic LGA
200
µPD30700LRS-225Note
599-pin ceramic LGA
225
µPD30700LRS-250Note
599-pin ceramic LGA
250
µPD30710RS-300Note
599-pin ceramic LGA
300
Note
Under development
Remark LGA: Land Grid Array
2
Package
µPD30700,30700L,30710
PIN CONFIGURATION
• 599-pin ceramic LGA
µPD30700RS-180
µPD30700RS-200
µPD30700LRS-225
µPD30700LRS-250
µPD30710RS-300
Top View
Bottom View
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
Index
3
µPD30700,30700L,30710
(1/4)
No.
No.
Name
No.
Name
No.
Name
A1
–
B9
SCADCS
C17
SysAD41
D25
VSS
A2
VDD
B10
SCAAddr5
C18
VDD
D26
VDD
A3
VSS
B11
VSS
C19
SysAD36
D27
SCData68
A4
VDDQSC
B12
SCData78
C20
SysAD32
D28
SCData64
A5
SCData89
B13
SCClk0
C21
VSS
D29
VSS
A6
SCData85
B14
VDD
C22
VSS
D30
SCAAddr12
A7
VSS
B15
SCData72
C23
SysClkRet
D31
SCAAddr16
A8
SCADWr
B16
SysAD44
C24
VSS
D32
VSS
A9
SCAAddr8
B17
VSS
C25
VDDPa
D33
SCDataChk0
A10
VDDQSC
B18
SysAD40
C26
SCData71
D34
SCData29
A11
SCAAddr1
B19
VSS
C27
VSS
D35
VDDQSC
A12
SCData76
B20
SysAD33
C28
SCData67
E1
SCClk5
A13
VSS
B21
VSS
C29
SCDataChk2
E2
VSS
A14
SCData74
B22
DCOK
C30
VDDQSC
E3
VDD
A15
SysAD46
B23
SysClkRet
C31
SCAAddr13
E4
SCDataChk6
A16
VDDQSys
B24
VSSPa
C32
SCAAddr18
E5
VDD
A17
SysAD42
B25
VSSPa
C33
VDDQSC
E6
SCData90
A18
SysAD37
B26
SCClk1
C34
VDD
E7
SCData86
A19
SysAD35
B27
SCDataChk9
C35
VSS
E8
VDDQSC
A20
VDDQSys
B28
VDD
D1
VDDQSC
E9
SCData80
A21
VSS
B29
SCData65
D2
SCTCS
E10
SCADWay
A22
SysClk
B30
SCAAddr9
D3
SCDataChk8
E11
VSS
A23
SysClk
B31
VSS
D4
VSS
E12
SCAAddr4
A24
VSSPa
B32
SCAAddr15
D5
SCData92
E13
SCAAddr0
A25
NC
B33
SCAAddr17
D6
SCData88
E14
VDDQSC
A26
SCClk1
B34
VSS
D7
VSS
E15
SCClk0
A27
VSS
B35
VDD
D8
SCData82
E16
SysAD47
A28
SCData70
C1
VSS
D9
SCADOE
E17
VSS
A29
VSS
C2
VDD
D10
VDD
E18
SysAD39
A30
SCDataChk4
C3
VDDQSC
D11
SCAAddr6
E19
VSS
A31
SCAAddr11
C4
SCData94
D12
SCAAddr2
E20
SysCyc
A32
VDDQSC
C5
SCData91
D13
VSS
E21
VSS
A33
VSS
C6
VDDQSC
D14
SCData77
E22
VDDPd
A34
VDD
C7
SCData84
D15
SCData73
E23
VSS
A35
VSS
C8
SCData81
D16
VDD
E24
VSS
B1
VDD
C9
VSS
D17
SysAD43
E25
VSS
B2
VSS
C10
SCAAddr7
D18
SysAD38
E26
SCData69
B3
SCData95
C11
SCAAddr3
D19
SysAD34
E27
SCData66
B4
SCData93
C12
VDDQSC
D20
VDD
E28
VDDQSC
B5
VSS
C13
SCData79
D21
VSS
E29
SCAAddr10
B6
SCData87
C14
SCData75
D22
VSSPd
E30
SCAAddr14
B7
SCData83
C15
VSS
D23
VSS
E31
VDD
B8
VDD
C16
SysAD45
D24
VSS
E32
SCData31
Note
4
Name
Connect this pin via a100-Ω resistor.
µPD30700,30700L,30710
(2/4)
No.
Name
No.
Name
No.
Name
No.
Name
E33
VDD
K1
VDDQSC
P4
SCTag6
V32
SysAD6
E34
VSS
K2
SCTag14
P5
VDDQSC
V33
VDD
E35
SCData27
K3
SCTag17
P31
VDDQSC
V34
SysAD4
F1
VDD
K4
VDD
P32
SCData4
V35
SysAD2
F2
SCTWr
K5
SCTag19
P33
SCData2
W1
SCClk4
F3
VDDQSC
K31
SCData18
P34
VDD
W2
VSS
F4
SCClk5
K32
VDD
P35
SysAD15
W3
SCTagChk1
F5
VSSNote
K33
SCData16
R1
SCTag0
W4
SCClk4
F31
SCData30
K34
SCData11
R2
VDDQSC
W5
VSS
F32
SCData28
K35
VDDQSC
R3
VSS
W31
VSS
F33
VDDQSC
L1
SCTag12
R4
SCTag1
W32
SysAD1
F34
SCData25
L2
VSS
R5
SCTag3
W33
JTCK
F35
SCData23
L3
VDD
R31
SCData0
W34
VSS
G1
VSS
L4
SCTag15
R32
SysAD13
W35
JTDI
G2
SCTag22
L5
VSS
R33
VSS
Y1
VCCQSys
G3
SCTag24
L31
VSS
R34
SysAD14
Y2
SysCmd0
G4
VSS
L32
SCData14
R35
SysAD12
Y3
SysCmd1
G5
SCTOE
L33
SCData9
T1
VDDQSC
Y4
VDD
G31
SCData26
L34
VSS
T2
NC
Y5
SysCmd3
G32
VSS
L35
SCData7
T3
SCTWay
Y31
JTDO
G33
SCData21
M1
SCTag7
T4
VDD
Y32
VDD
G34
SCData19
M2
SCTag9
T5
SCTagLSBAddr
Y33
VrefSys
G35
VSS
M3
VDDQSC
T31
SysAD11
Y34
SysAD0
H1
SCTag20
M4
SCTag11
T32
VDD
Y35
VDDQSys
H2
VDD
M5
SCTag13
T33
SysAD9
AA1
SysCmd2
H3
VDDQSC
M31
SCData12
T34
SysAD10
AA2
SysCmd4
H4
SCTag25
M32
SCData10
T35
VDDQSys
AA3
VSS
H5
VDDQSC
M33
VDDQSC
U1
SCTagChk6
AA4
SysCmd5
H31
VDDQSC
M34
SCData5
U2
VSS
AA5
SysCmd7
H32
SCData24
M35
SCData3
U3
SCTagChk5
AA31
SCClk2
H33
VDDQSC
N1
VSS
U4
VSSNote
AA32
SCData32
H34
VDD
N2
SCTag5
U5
VSS
AA33
VSS
H35
SCData17
N3
SCTag8
U31
VSS
AA34
JTMS
J1
SCTag16
N4
VSS
U32
SysAD7
AA35
VrefSC
J2
SCTag18
N5
SCTag10
U33
SysAD5
AB1
SysCmd6
J3
VSS
N31
SCData8
U34
VSS
AB2
VDD
J4
SCTag21
N32
VSS
U35
SysAD8
AB3
SysCmd8
J5
SCTag23
N33
SCData6
V1
SCTagChk4
AB4
SysCmd10
J31
SCData22
N34
SCData1
V2
SCTagChk2
AB5
VDDQSys
J32
SCData20
N35
VSS
V3
VDD
AB31
VDDQSC
J33
VSS
P1
SCTag2
V4
SCTagChk0
AB32
SCData35
J34
SCData15
P2
VDD
V5
SCTagChk3
AB33
SCClk2
J35
SCData13
P3
SCTag4
V31
SysAD3
AB34
VDD
Note
Connect this pin via a100-Ω resistor.
5
µPD30700,30700L,30710
(3/4)
No.
No.
Name
No.
Name
No.
Name
AB35
SCData33
AG3
VSS
AL6
SCData124
AM14
SCData110
AC1
VSS
AG4
SysGblPerf
AL7
SCData120
AM15
SCClk3
AC2
SysCmd9
AG5
SysWrRdy
AL8
VDDQSC
AM16
VDD
AC3
SysCmdPar
AG31
SCData53
AL9
SCData114
AM17
SysAD58
AC4
VSS
AG32
SCData51
AL10
SCBDOE
AM18
SysAD54
AC5
SysReq
AG33
VSS
AL11
SCBAddr8
AM19
SysAD52
AC31
SCData39
AG34
SCData48
AL12
SCBAddr4
AM20
VDD
AC32
VSS
AG35
SCData46
AL13
SCBAddr0
AM21
SysADChk4
AC33
SCData37
AH1
SysResp2
AL14
VDDQSC
AM22
SysAD30
AC34
SCData34
AH2
VDD
AL15
SCData106
AM23
VSS
AC35
VSS
AH3
VDDQSys
AL16
SCData104
AM24
SysAD26
AD1
SysCmd11
AH4
SysStatePar
AL17
SysAD60
AM25
SysAD22
AD2
SysVal
AH5
VDDQSys
AL18
SysAD56
AM26
VDD
AD3
VDDQSys
AH31
VDDQSC
AL19
SysAD50
AM27
SCData102
AD4
SysGnt
AH32
SCData55
AL20
SysADChk6
AM28
SCData98
AD5
SysReset
AH33
VDDQSC
AL21
SysADChk2
AM29
VSS
AD31
SCData43
AH34
VDD
AL22
VDDQSys
AM30
SCBAddr11
AD32
SCData41
AH35
SCData50
AL23
SysAD28
AM31
SCBAddr15
AD33
VDDQSC
AJ1
VSS
AL24
SysAD24
AM32
VSS
AD34
SCData38
AJ2
SysResp0
AL25
SysAD20
AM33
SCData63
AD35
SCData36
AJ3
SysRdRdy
AL26
SysAD16
AM34
SCData62
AE1
SysRel
AJ4
VSS
AL27
SCData100
AM35
VDDQSC
AE2
VSS
AJ5
SysState1
AL28
VDDQSC
AN1
VSS
AE3
VDD
AJ31
SCData57
AL29
SCBAddr9
AN2
VDD
AE4
SysRespPar
AJ32
VSS
AL30
SCBAddr13
AN3
VDDQSC
AE5
VSS
AJ33
SCData54
AL31
VDD
AN4
SCDataChk7
AE31
VSS
AJ34
SCData52
AL32
SCDataChk1
AN5
SCData125
AE32
SCData45
AJ35
VSS
AL33
VDD
AN6
VDDQSC
AE33
SCData42
AK1
SysStateVal
AL34
VSS
AN7
SCData118
AE34
VSS
AK2
SysState2
AL35
SCData60
AN8
SCData115
AE35
SCData40
AK3
VDDQSys
AM1
VDDQSys
AN9
VSS
AF1
VDDQSys
AK4
SysCorErr
AM2
SysUncErr
AN10
SCBDCS
AF2
DCOk
AK5
SysNMI
AM3
VSSNote
AN11
SCBAddr5
AF3
SysResp3
AK31
SCData61
AM4
VSS
AN12
VDDQSC
AF4
VDD
AK32
SCData59
AM5
SCData126
AN13
SCData109
AF5
SysResp1
AK33
VDDQSC
AM6
SCData122
AN14
SCData108
AF31
SCData49
AK34
SCData58
AM7
VSS
AN15
VSS
AF32
VDD
AK35
SCData56
AM8
SCData116
AN16
SysAD62
AF33
SCData47
AL1
SysState0
AM9
SCData112
AN17
SysAD59
AF34
SCData44
AL2
VSS
AM10
VDD
AN18
VDD
AF35
VDDQSC
AL3
VDD
AM11
SCBAddr6
AN19
SysAD51
AG1
SysRespVal
AL4
VSSNote
AM12
SCBAddr2
AN20
SysAD48
AG2
SysResp4
AL5
VDD
AM13
VSS
AN21
VSS
Note
6
Name
Connect this pin via a100-Ω resistor.
µPD30700,30700L,30710
(4/4)
No.
Name
No.
Name
No.
Name
No.
Name
AN22
SysADChk0
AP8
VDD
AP29
SCData97
AR15
SysAD63
AN23
SysAD29
AP9
SCBDWr
AP30
SCBAddr10
AR16
VDDQSys
AN24
VDDQSys
AP10
SCBAddr7
AP31
VSS
AR17
SysAD57
AN25
SysAD21
AP11
VSS
AP32
SCBAddr16
AR18
SysAD55
AN26
SysAD18
AP12
SCBAddr1
AP33
SCBAddr17
AR19
SysAD49
AN27
VSS
AP13
SCData107
AP34
VSS
AR20
VDDQSys
AN28
SCData99
AP14
VDD
AP35
VDD
AR21
SysADChk5
AN29
SCData96
AP15
SCData105
AR1
VSS
AR22
SysADChk1
AN30
VDDQSC
AP16
SysAD61
AR2
VDD
AR23
VSS
AN31
SCBAddr14
AP17
VSS
AR3
VSS
AR24
SysAD27
AN32
SCBAddr18
AP18
SysAD53
AR4
VSSQSC
AR25
SysAD23
AN33
VDDQSC
AP19
VSS
AR5
SCData123
AR26
VDDQSys
AN34
VDD
AP20
SysADChk7
AR6
SCData119
AR27
SysAD17
AN35
VSS
AP21
SysADChk3
AR7
VSS
AR28
SCData101
AP1
VDD
AP22
VDD
AR8
SCData113
AR29
VSS
AP2
VSS
AP23
SysAD31
AR9
SCBDWay
AR30
SCDataChk3
AP3
SCDataChk5
AP24
SysAD25
AR10
VDDQSC
AR31
SCBAddr12
AP4
SCData127
AP25
VSS
AR11
SCBAddr3
AR32
VDDQSC
AP5
VSS
AP26
SysAD19
AR12
SCData111
AR33
VSS
AP6
SCData121
AP27
SCData103
AR13
VSS
AR34
VDD
AP7
SCData117
AP28
VDD
AR14
SCClk3
AR35
VSS
7
µPD30700,30700L,30710
PIN NAMES
8
DCOK
: DC Voltage OK
JTCK
: JTAG Clock
JTDI
: JTAG Serial Data Input
JTDO
: JTAG Serial Data Output
JTMS
: JTAG Mode Select
SCAAddr (18 : 0), SCBAddr (18 : 0)
: Secondary Cache Address Bus
SCADCS, SCBDCS
: Secondary Cache Data Chip Select
SCADOE, SCBDOE
: Secondary Cache Data Output Enable
SCADWay, SCBDWay
: Secondary Cache Data Way
SCADWr, SCBDWr
: Secondary Cache Data Write Enable
SCClk (5 : 0), SCClk (5 : 0)
: Secondary Cache Clock
SCData (127 : 0)
: Secondary Cache Data Bus
SCDataChk (9 : 0)
: Secondary Cache Data Check Bus
SCTag (25 : 0)
: Secondary Cache Tag Bus
SCTagChk (6 : 0)
: Secondary Cache Tag Check Bus
SCTagLSBAddr
: Secondary Cache Tag LSB Address
SCTCS
: Secondary Cache Chip Select
SCTOE
: Secondary Cache Tag Output Enable
SCTWay
: Secondary Cache Tag Way
SCTWr
: Secondary Cache Tag Write Enable
SysAD (63 : 0)
: System Address/Data Bus
SysADChk (7 : 0)
: System Address/Data Check Bus
SysClk, SysClk
: System Clock
SysClkRet, SysClkRet
: System Clock Return
SysCmd (11 : 0)
: System Command Bus
SysCmdPar
: System Command Bus Parity
SysCorErr
: System Correctable Error
SysCyc
: System Cycle
SysGbPerf
: System Globally Performed
SysGnt
: System Grant
SysNMI
: System Non-maskable Interrupt
SysRdRdy
: System Read Ready
SysReset
: System Reset
SysResp (4 : 0)
: System Response Bus
SysRespPar
: System Response Bus Parity
SysRespVal
: System Response Bus Valid
SysUncErr
: System Uncorrectable Error
SysVal
: System Valid
SysWrRdy
: System Write Ready
SysRel
: System Release
SysReq
: System Request
µPD30700,30700L,30710
SysState (2 : 0)
: System State Bus
SysStatePar
: System State Bus Parity
SysStateVal
: System State Bus Valid
VDD
: Power Supply
VDDPa
: VDD for the PLL Analog
VDDPd
: VDD for the PLL Digital
VDDQSC
: VDD for the Secondary Cache
VDDQSys
: VDD for the System Interface
VrefSC
: Voltage Reference for the Secondary Cache
VrefSys
: Voltage Reference for the System Interface
VSS
: Ground
VSSPa
: VSS for the PLL Analog
VSSPd
: VSS for the PLL Digital
NC
: No Connection
9
µPD30700,30700L,30710
Up to four VR10000s can be directly connected.
System interface
Secondary cache memory interface
Instruction cache
32K bytes
2-way set associative
19 + way Secondary cache address
Data cache
32K bytes
2-way set associative
26 + 7
Data
128 + 10
Address 32-bit instruction fetch × 4
Address 64-bit load/store
Secondary cache
(512K bytes to 16M bytes)
SSRAM
VR10000
FP
queue
Integer register × 64
Integer
queue
TLB
FP register × 64
Address
queue
Instruction decode
register mapping
Clock
Branch unit
Switch
10
Secondary cache
Tag
System bus
External agent/
cluster controller
Main memory, I/O
BLOCK DIAGRAM
Address
generation
ALU1
ALU2
Adder
Multiplier
µPD30700,30700L,30710
TABLE OF CONTENTS
1. PIN FUNCTIONS ...........................................................................................................................
1.1 Pin Function List .................................................................................................................
1.2 Recommended Connection of Unused Pins ...................................................................
13
13
16
2. CPU INTERNAL ARCHITECTURE ..............................................................................................
2.1 Pipeline .................................................................................................................................
17
17
2.1.1
Configuration .............................................................................................................................
17
2.1.2
Operation ...................................................................................................................................
18
2.2 CPU Registers (virtual registers) ......................................................................................
2.3 System Control Coprocessor (CP0) .................................................................................
19
20
CP0 registers .............................................................................................................................
20
2.4 Data Format and Addressing ............................................................................................
2.5 Virtual Storage .....................................................................................................................
2.3.1
22
24
2.5.1
Virtual address space ................................................................................................................
24
2.5.2
Address translation ...................................................................................................................
27
2.6 Cache ....................................................................................................................................
29
2.6.1
Primary cache ............................................................................................................................
29
2.6.2
Secondary cache .......................................................................................................................
29
INTERNAL ARCHITECTURE ...............................................................................................
Internal Function Block ......................................................................................................
FPU Registers ......................................................................................................................
Data Format .........................................................................................................................
30
30
30
31
4. INTERFACE ...................................................................................................................................
4.1 System Interface .................................................................................................................
32
32
3. FPU
3.1
3.2
3.3
Setting operating frequency of system interface .....................................................................
32
4.2 Secondary Cache Interface ...............................................................................................
4.3 Clock Interface ....................................................................................................................
4.1.1
33
33
4.3.1
System interface clock and processor clock ............................................................................
33
4.3.2
Secondary cache clock .............................................................................................................
33
4.4 System Configuration Example ........................................................................................
33
4.4.1
Uni-processor system ...............................................................................................................
33
4.4.2
Multi-processor system .............................................................................................................
35
4.5 BTMC Interface ....................................................................................................................
4.6 DSD (Delay Speculative Dirty) Mode (VR12000 only) .....................................................
36
38
4.6.1
DSD mode delay .......................................................................................................................
38
4.6.2
Secondary cache status in DSD mode ....................................................................................
38
4.6.3
Other features ............................................................................................................................
38
5. INTERNAL/EXTERNAL CONTROL FUNCTIONS.......................................................................
5.1 Reset Function ....................................................................................................................
39
39
5.1.1
Power-ON reset and cold reset ................................................................................................
39
5.1.2
Software reset ...........................................................................................................................
39
5.2 Interrupt Functions .............................................................................................................
5.3 JTAG Function .....................................................................................................................
39
40
11
µPD30700,30700L,30710
6. INSTRUCTION SET ......................................................................................................................
6.1 Instruction Formats ............................................................................................................
6.2 CPU Instruction Set List ....................................................................................................
6.3 FPU Instruction Set List .....................................................................................................
6.4 Delay of Instruction ............................................................................................................
41
41
41
46
49
7. ELECTRICAL SPECIFICATIONS .................................................................................................
50
8. PUSH-PULL OUTPUT BUFFER CIRCUIT ..................................................................................
64
9. PACKAGE DRAWING ...................................................................................................................
65
12
µPD30700,30700L,30710
1. PIN FUNCTIONS
1.1 Pin Function List
(1/3)
Pin Name
I/O
Function
SCClk (5 : 0)
Output
Secondary cache clock signals.
SCClk (5 : 0)
Output
Secondary cache clock signals.
Inverted SCClk (5:0) signals.
SCAAddr (18 : 0),
SCBAddr (18 : 0)
Output
Secondary cache address bus.
19-bit address bus for secondary cache.
SCTagLSBAddr
Output
Secondary cache tag LSB address.
Specifies the LSB address of a secondary cache tag.
SCADWay,
SCBDWay
Output
Secondary cache data way.
Specifies a way of secondary cache data.
SCData (127 : 0)
I/O
Secondary cache data bus.
128-bit bus to read or write data from or to the secondary cache.
SCDataChk (9 : 0)
I/O
Secondary cache data check bus.
10-bit bus used to read or write ECC and even parity for secondary cache data.
SCADOE,
SCBDOE
Output
Secondary cache data output enable.
Signals enabling output of secondary cache data.
SCADWr,
SCBDWr
Output
Secondary cache data write enable.
Signals enabling writing of secondary cache data.
SCADCS,
Output
Secondary cache data chip select.
SCBDCS
Signals enabling access of secondary cache data.
SCTWay
Output
Secondary cache tag way.
Specifies the way of a secondary cache tag.
SCTag (25 : 0)
I/O
Secondary cache tag bus.
26-bit bus to read or write a tag to or from the secondary cache.
SCTagChk (6 : 0)
I/O
Secondary cache tag check bus.
7-bit bus used to read or write ECC for secondary cache tag.
SCTOE
Output
Secondary cache tag output enable.
Signal enabling output of a secondary cache tag.
SCTWr
Output
Secondary cache tag write enable.
Signal enabling writing of a secondary cache tag.
SCTCS
Output
Secondary cache tag chip select.
Signal enabling access to a secondary cache tag.
SysClk
Input
System clock.
System clock input.
SysClk
Input
System clock.
System clock input. Inverted SysClk signal.
SysClkRet
Output
System clock.
System clock output used for termination of system clock.
SysClkRet
Output
System clock.
System clock output used for termination of system clock. Inverted SysClkReset signal.
SysReq
Output
System request.
Signal requesting enabling issuance of a processor request when the VR10000 serves
as a slave.
13
µPD30700,30700L,30710
(2/3)
Pin Name
I/O
Function
SysGnt
Input
System enable.
Signal used by an external agent to request the VR10000 for use of the system interface.
SysRel
I/O
System release.
The master side of the system interface asserts this signal active for the duration of 1
SysClk cycle when it releases the right to use the system interface in the subsequent
SysClk cycle.
SysRdRdy
Input
System read ready.
Indicates that the external agent is ready to accept a processor read request and upgrade
request.
SysWrRdy
Input
System write ready.
Indicates that the external agent is ready to accept a processor write request and processor
eliminate request.
SysAD (63 : 0)
I/O
System address/data bus.
64-bit address/data bus for communication between the VR10000 and external agent.
SysADChk (7 : 0)
I/O
System address/data check bus.
8-bit ECC bus for SysAD bus.
SysCmd (11 : 0)
I/O
System command bus.
12-bit bus for command communication between the VR10000 and external agent.
SysCmdPar
I/O
System command bus parity.
One odd parity bit for the system command bus.
SysVal
I/O
System valid.
Signal indicating that the master side of the system interface drives a valid address/
command/data onto the SysAD bus and SysCmd bus.
SysState (2 : 0)
Output
System state bus.
3-bit bus indicating issuance or addition of a processor coherent status response.
SysStatePar
Output
System state bus parity.
One odd parity bit for the system state bus.
SysStateVal
Output
System state bus valid.
The VR10000 asserts this signal active for the duration of 1 SysClk cycle when it issues
a processor coherent response status to the SysState bus.
SysResp (4 : 0)
Input
System response bus.
5-bit bus used by the external agent to issue an external end response.
SysRespPar
Input
System response bus parity.
One odd parity bit for the system response bus.
SysRespVal
Input
System response bus valid.
The external agent asserts this signal active for 1 SysClk cycle when it issues an external
end response to the SysResp bus.
SysReset
Input
System reset.
Signal used by the external agent to reset the VR10000.
SysNMI
Input
System non-maskable interrupt.
Signal used by the external agent to issue NMI.
SysCorErr
Output
System correctable error.
The VR10000 asserts this signal active for 1 SysClk cycle when it finds and correct a
correctable error.
SysUncErr
Output
System uncorrectable error.
The VR10000 asserts this signal active for 1 SysClk cycle when it finds an uncorrectable
tag error.
14
µPD30700,30700L,30710
(3/3)
Pin Name
I/O
Function
SysGblPerf
Input
System global perfect.
An external agent uses this signal to indicate completion of a processor request to all
external agents.
SysCyc
Input
System cycle.
The external agent uses this signal to define a virtual system interface clock in hardware
emulation environment.
JTDI
Input
JTAG data input.
Inputs JTAG serial data.
JTDO
Output
JTAG data output.
Outputs JTAG serial data.
JTCK
Input
JTAG clock input.
Inputs JTAG serial clock. Keep this signal low when the JTAG interface is not used.
JTMS
Input
JTAG mode select.
Selects a mode of JTAG.
DCOK
Input
DC voltage enable.
The external agent asserts this signal active when the following signals are stable:
VDD, VDDQSC, VDDQSys, VrefSC, VrefSys, VDDPa, VDDPd, SysClk
VDD
Input
Power supply pin.
Power supply for the CPU core.
VDDQSC
Input
Secondary cache VDD.
Power supply for the output driver of the secondary cache interface.
VDDQSys
Input
System interface VDD.
Power supply for the output driver of the system interface.
VrefSC
Input
Secondary cache voltage.
Reference voltage for the input pins of the secondary cache interface.
VrefSys
Input
System interface voltage.
Reference voltage for the input pins of the system interface.
VDDPa
Input
PLL analog VDD.
Power supply for the PLL analog circuit.
VDDPd
Input
PLL digital VDD.
Power supply for the PLL digital circuit.
VSS
Input
Ground potential pin.
Ground for the CPU core and output driver.
VSSPa
Input
PLL analog GND.
Ground for the PLL analog.
VSSPd
Input
PLL digital GND.
Ground for PLL digital.
NC
—
No connection. Leave this pin unconnected.
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µPD30700,30700L,30710
1.2 Recommended Connection of Unused Pins
Table 1-1 shows the recommended connection of unused pins.
Table 1-1. Recommended Connection of Unused Pins
Pin Name
JTDI
I/O
Input
Recommended Connection
Connect each of these pins to VDD via a resistor.
JTCK
JTMS
SysNMI
Connect this pin to VDDQSys via resistor of 100 Ω or more.
SysRdRdy
Connect each of these pins to VSS via a resistor of 100 Ω or more.
SysWrRdy
SysGblPerf
SysCyc
SysADChk (7 : 0)
16
I/O
Connect each of these pins to VSS or VDDQSys via a resistor or 100 Ω or more.
µPD30700,30700L,30710
2. CPU INTERNAL ARCHITECTURE
2.1 Pipeline
2.1.1 Configuration
The VR10000 has a 5-way super scalar pipeline as illustrated below. This pipeline can simultaneously fetch and
decode four instructions in 1 Pcycle.
(1) FP addition pipeline
(2) FP multiplication pipeline
(3) Integer ALU1 pipeline
(4) Integer ALU2 pipeline
(5) Load/store pipeline
Figure 2-1. Pipeline
7 pipeline stages
Stage 1
Fetch
5-instruction
parallel execution
pipeline
Stage 2
Decode
Stage 3
Issue
Stage 4
Execute
Stage 5
Execute
Stage 6
Execute
FAdd-1
FAdd-2
FAdd-3
FP addition pipeline
(FP queue)
Issue
FP multiplication pipeline
(FP queue)
Issue
RF
FMpy-1
Integer ALU1 pipeline
(integer queue)
Issue
RF
ALU1
Result
Integer ALU2 pipeline
(integer queue)
Issue
RF
ALU2
Result
Load/store pipeline
(address queue)
Issue
RF
Addr.Calc
RF
Result
FP queue,
FP register
Queue
Primary
instruction
cache
Stage 7
Store
FMpy-2
Data Cache
FMpy-3
Result
Integer register operand
Result
TLB
Instruction
decode
Branch
unit
Instruction fetch, decode (4 instructions/1 cycle)
Branch address
Instruction execution
17
µPD30700,30700L,30710
2.1.2 Operation
The pipeline of the VR10000 has seven stages. The operation of each stage is described below:
(1) Stage 1 (fetch)
Four instructions are fetched in 1 cycle and stored to the instruction register.
(2) Stage 2 (decode)
The four instructions fetched in stage 1 are decoded.
(3) Stage 3 (issue)
The decoded instructions are written to a queue. The VR10000 has an FP queue, integer queue, and address
queue. In addition, an operand is read from the register file.
(4) Stage 4 through stage 6 (execute)
The instructions are executed. The execution pipeline and execution cycle differ depending on the type of
instruction.
(a) FP addition pipeline
Executes floating-point addition instructions in 3 PCycle.
(b) FP multiplication pipeline
Executes floating-point multiplication, division, and square root instructions in 3 PCycle.
(c) Integer ALU1 pipeline
Executes integer addition, subtraction, shift, and logic instructions in 1 Pcycle.
(d) Integer ALU2 pipeline
Executes integer addition, subtraction, and logic instructions in 1 PCycle.
(e) Load/store pipeline
Generates a memory address used for integer or floating-point load/store instructions.
(5) Stage 7 (store)
The results of executing the instructions are stored to registers.
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µPD30700,30700L,30710
2.2 CPU Registers (virtual registers)
Figure 2-2 shows the CPU registers of the VR10000. Physically, sixty-four general-purpose registers are available.
Of these, however, only thirty-two can be accessed by software or an external agent. Mapping of the other registers
is automatically controlled by the CPU. The bit width of a register is determined by the operation mode of the VR10000
(32 bits in 32-bit mode, or 64 bits in 64-bit mode).
Of the thirty-two general-purpose registers, the following two have special meanings.
• Register r0 : The contents of this register are always 0. Register r0 can be used as the target register of
an instruction when the result of an operation is to be discarded. This register can also be
used as a source register when the value of 0 is necessary.
• Register r31 : This is a link system for the JAL and JALR instructions. Therefore, do not use this register
with any other instructions.
Two multiplication/division registers (HI and LO) are used to store the result of integer multiplication, or quotient
(LO) and remainder (HI) resulting from integer division.
The load link register is used to synchronize two or more VR10000s in a multi-processor system.
Figure 2-2. CPU Registers
General-purpose registers
63
0
r0 = 0
Multiplication/division register
63
r1
r2
0
HI
63
0
LO
Program counter
63
r29
0
PC
r30
r31 (link address)
Load link register
0
LLbit
There is no program status word (PSW). The function of PSW is substituted by the status register and cause register
incorporated into the system control coprocessor (CP0).
19
µPD30700,30700L,30710
2.3 System Control Coprocessor (CP0)
The CP0 registers/CP0 instructions access the TLB and cache. Manipulating a mode in which the VR10000 is used,
exceptions, and interrupts are also controlled by the CP0. In addition, the CP0 also has a test/debug function.
2.3.1 CP0 registers
All the CP0 registers that can be used with the VR10000 are listed below. Writing or reading an unused register
(RFU) is undefined.
Figure 2-3. CPU0 Registers and TLB
Registers used by memory management system
Registers used for exception processing
Entry Lo0
2*
Context
4*
BadVAddr
8*
Random
1*
Count
9*
Compare
11*
Page mask
5*
Status
12*
Cause
13*
Wired
6*
EPC
14*
PRld
15*
Config
16*
LLAddr
17*
Watch Lo
18*
Watch Hi
19*
X context
20*
Diagnosis
22*
ECC
26*
Cache error
27*
Tag Lo
28*
Tag Hi
29*
Error EPC
30*
Index
0*
Entry Hi
10*
Entry Lo1
3*
63
TLB
("Safe" entry)
0 127/255
Frame mask
21*
0
PC
25*
Remark “*” indicates a register number.
20
µPD30700,30700L,30710
Table 2-1. CP0 Register List
No.
Register
Description
0
Index
TLB entry programmable pointer
1
Random
TLB entry random pointer
2
Entry Lo0
Second half of TLB entry for even number VPN
3
Entry Lo1
Second half of TLB entry for odd number VPN
4
Context
Pointer to virtual PTE table of kernel in 32-bit mode
5
Page mask
TLB page mask
6
Wired
Number of wired TLB entries
7
—
RFU (Reserved for Future Use)
8
BadVAddr
Virtual address at which last error has occurred
9
Count
Timer count
10
Entry Hi
First half of TLB entry (including VPN and ASID)
11
Compare
Timer comparison
12
Status
Status register
13
Cause
Cause of last exception
14
EPC
Exception program counter
15
PRld
Processor revision identifier
16
Config
Configuration register
17
LLAddr
Address of LL instruction
18
Watch Lo
Low-order bits of memory reference trap address
19
Watch Hi
High-order bits of memory reference trap address
20
X context
Pointer to virtual PTE table of kernel in 64-bit mode
21
Frame mask
Bit mask of entry Lo register
22
Diagnosis
Branch diagnosis
23, 24
—
RFU
25
PC
Performance counter
26
ECC
ECC of secondary cache and parity of primary cache
27
Cache error
Index of cache error and status field
28
Tag Lo
Cache tag register, low-order
29
Tag Hi
Cache tag register, high-order
30
Error EPC
Error exception program counter
31
—
RFU
21
µPD30700,30700L,30710
2.4 Data Format and Addressing
The VR10000 has the following four types of data formats:
Double word (64 bits)
Word (32 bit)
Half word (16 bits)
Byte (8 bits)
If the data format is double word, word, or half word, the byte order can be set to bit endian or little endian by using
the BE bit of the config register.
Figure 2-4. Byte Address in Word: Big Endian
31
High-order
address
Low-order
address
Remarks 1.
2.
24
23
16
15
8
7
0
Word
address
12
13
14
15
12
8
9
10
11
8
4
5
6
7
4
0
1
2
3
0
The most significant byte is the least significant address.
A word is addressed by the address of the most significant byte.
Figure 2-5. Byte Address in Word: Little Endian
31
High-order
address
Low-order
address
Remarks 1.
2.
22
24
23
16
15
8
7
0
Word
address
15
14
13
12
12
11
10
9
8
8
7
6
5
4
4
3
2
1
0
0
The least significant byte is the least significant address.
A word is addressed by the address of the least significant byte.
µPD30700,30700L,30710
Figure 2-6. Byte Address in Double Word: Big Endian
Word
Half word
63
High-order
address
Low-order
address
32 31
Byte
16 15
8 7
0
Double word
address
16
17
18
19
20
21
22
23
16
8
9
10
11
12
13
14
15
8
0
1
2
3
4
5
6
7
0
Remarks 1.
The most significant byte is the least significant address.
2.
A word is addressed by the address of the most significant byte.
Figure 2-7. Byte Address in Double Word: Little Endian
Word
Half word
63
High-order
address
Low-order
address
Remarks 1.
2.
32 31
Byte
16 15
0
8 7
Double word
address
23
22
21
20
19
18
17
16
16
15
14
13
12
11
10
9
8
8
7
6
5
4
3
2
1
0
0
The least significant byte is the least significant address.
A word is addressed by the address of the least significant byte.
23
µPD30700,30700L,30710
2.5 Virtual Storage
2.5.1 Virtual address space
The VR10000 has two operation modes, the 32-bit and 64-bit modes. In addition, it has three operating modes:
the user mode, supervisor mode, and kernel mode. Figures 2-8 through 2-11 show the virtual address spaces in the
respective modes.
Figure 2-8. User Mode Address Space
32 bitsNote
64 bits
0xFFFF FFFF
0xFFFF FFFF FFFF FFFF
Address error
0x8000 0000
0x0000 1000 0000 0000
0x7FFF FFFF
0x0000 0FFF FFFF FFFF
2G bytes
w/TLB mapping
0x0000 0000
Note
24
Address error
16T bytes
w/TLB mapping
useg
0x0000 0000 0000 0000
In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63.
xuseg
µPD30700,30700L,30710
Figure 2-9. Supervisor Mode Address Space
Note
64 bits
32 bits
0xFFFF FFFF
0xFFFF FFFF FFFF FFFF
Address error
Address error
0xE000 0000
0xFFFF FFFF E000 FFFF
0xDFFF FFFF
0xFFFF FFFF DFFF FFFF
0.5G bytes
w/TLB mapping
0.5G bytes
sseg
w/TLB mapping
0xC000 0000
0xFFFF FFFF C000 0000
0xBFFF FFFF
0xFFFF FFFF BFFF FFFF
csseg
Address error
0x4000 1000 0000 0000
Address error
0x4000 0FFF FFFF FFFF
16T bytes
w/TLB mapping
0x8000 0000
0x7FFF FFFF
xsseg
0x4000 0000 0000 0000
0x3FFF FFFF FFFF FFFF
Address error
2G bytes
0x0000 1000 0000 0000
0x0000 0FFF FFFF FFFF
w/TLB mapping
16T bytesNote 2
w/TLB mapping
suseg
0x0000 0000
xsuseg
0x0000 0000 0000 0000
Notes 1. In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63.
2. If the UX bit of the status register is 0, 0x0000 0000 8000 0000 through 0x0000 0FFF FFFF FFFF cause
an address error.
25
µPD30700,30700L,30710
Figure 2-10. Kernel Mode Address Space
32 bitsNote 1
64 bits
0xFFFF FFFF
0xFFFF FFFF FFFF FFFF
0.5G bytes
w/TLB mapping
kseg3
0xE000 0000
0xDFFF FFFF
ksseg
0xC000 0000
0xBFFF FFFF
ckseg3
0.5G bytes
w/TLB mapping
cksseg
0.5G bytes
w/o TLB mapping
Non-cacheable
ckseg1
0.5G bytes
w/o TLB mapping
Cacheable
ckseg0
0xFFFF FFFF E000 0000
0xFFFF FFFF DFFF FFFF
0xFFFF FFFF C000 0000
0xFFFF FFFF BFFF FFFF
0.5G bytes
w/TLB mapping
0.5G bytes
w/TLB mapping
0xFFFF FFFF A000 0000
0xFFFF FFFF 9FFF FFFF
0xFFFF FFFF 8000 0000
0xFFFF FFFF 7FFF FFFF
Address error
0.5G bytes
w/o TLB mapping
Non-cacheable
kseg1
0xA000 0000
0x9FFF FFFF
0xC000 0FFF 0000 0000
0xC000 0FFE FFFF FFFF
0xC000 0000 0000 0000
0xBFFF FFFF FFFF FFFF
0.5G bytes
w/o TLB mapping
cacheable
kseg0
0x8000 0000 0000 0000
0x7FFF FFFF FFFF FFFF
w/TLB mapping
xkseg
w/o TLB mapping
(For details, refer
to Figure 2-11.)
xkphys
Address error
0x8000 0000
0x7FFF FFFF
0x4000 1000 0000 0000
0x4000 0FFF FFFF FFFF
2G bytes
w/TLB mapping
16T bytesNote 2
w/TLB mapping
xksseg
0x4000 0000 0000 0000
0x3FFF FFFF FFFF FFFF
Address error
kuseg
0x0000 1000 0000 0000
0x0000 0FFF FFFF FFFF
16T bytesNote 3
w/TLB mapping
0x0000 0000
xkuseg
0x0000 0000 0000 0000
Notes 1. In the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63.
2. If the SX bit of the status register is 0, this area causes an address error.
3. If the UX bit of the status register is 0, 0x0000 0000 8000 0000 through 0x0000 0FFF FFFF FFFF cause
an address error.
26
µPD30700,30700L,30710
Figure 2-11. Details of xkphys Area
0xBFFF FFFF FFFF FFFF
Address error
0xB800 0001 0000 0000
0xB800 0000 FFFF FFFF
0xB800 0000 0000 0000
0xB7FF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0xB000 0001 0000 0000
0xB000 0000 FFFF FFFF
0xB000 0000 0000 0000
0xAFFF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0xA800 0001 0000 0000
0xA800 0000 FFFF FFFF
0xA800 0000 0000 0000
0xA7FF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0xA000 0001 0000 0000
0xA000 0000 FFFF FFFF
0xA000 0000 0000 0000
0x9FFF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0x9800 0001 0000 0000
0x9800 0000 FFFF FFFF
0x9800 0000 0000 0000
0x97FF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0x9000 0001 0000 0000
0x9000 0000 FFFF FFFF
0x9000 0000 0000 0000
0x8FFF FFFF FFFF FFFF
4 G bytes
w/o TLB mapping
Non-cacheable
Address error
0x8800 0001 0000 0000
0x8800 0000 FFFF FFFF
0x8800 0000 0000 0000
0x87FF FFFF FFFF FFFF
4G bytes
w/o TLB mapping
Cacheable
Address error
0x8000 0001 0000 0000
0x8000 0000 FFFF FFFF
0x8000 0000 0000 0000
4G bytes
w/o TLB mapping
Cacheable
2.5.2 Address translation
Virtual addresses are translated into physical addresses by the internal TLB (Translation Lookaside Buffer) in page
units. The TLB is of full-associative configuration and has 64 entries at the virtual address side and 32 entries at the
physical address side. The page size can be changed from 4K bytes to 16M bytes.
If a hit of a TLB entry does not occur, a TLB non-coincidence exception occurs in the 32-bit mode and an XTLB
non-coincidence exception occurs in the 64-bit mode. If this happens, replace the contents of the TLB by software.
Figure 2-12 outlines address translation.
27
µPD30700,30700L,30710
Figure 2-12. Outline of Address Translation
y+8
y+1 y
ASID
x+1 x x–1
VPN
0
Offset
Virtual address
<1>
A virtual address page number (VPN) is
compared with VPN in TLB.
<2>
If the two VPNs coincide, a page frame number
(PFN) indicating the high-order bits of a physical
address is output to the selector.
<3>
If the least significant bit of VPN is 0, an even
page is selected; if it is 1, an odd page is selected.
The selected page is output to the high-order bits
of the physical address.
<4>
The offset is output to the low-order bits of the
physical address without via TLB.
<1>
63
0
TLB
<2>
Selector
x = 12, 14, 16, 18, 20, 22, 24
y = 31 (in 32-bit mode)
63 (in 64-bit mode)
<3>
<4>
Physical address
40
x x–1
0
TLB entries are read or written by loading/storing the TLB entry indicated by the index register and the random
register from or to the entry Hi, entry Lo1, Entry Lo0, and page mask registers.
Figure 2-13 outlines TLB manipulation.
Figure 2-13. Outline of TLB Manipulation
Page mask register
Entry Hi register
Entry Lo1 register
Entry Lo0 register
Index register
Random register
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µPD30700,30700L,30710
2.6 Cache
The VR10000 has a primary instruction cache and primary data cache. In addition, it has a secondary cache
interface to connect an external secondary cache.
2.6.1 Primary cache
(1) Primary instruction cache
Here are the features of the primary instruction cache:
• Internal cache memory
• Capacity: 32K bytes
• 16-word cache line
• 2-way set associative
• Physical index address
• Physical tag check
(2) Primary data cache
Here are the features of the primary data cache.
• Internal cache memory
• Capacity: 32K bytes
• 8-word cache line
• 2-bank configuration
• 2-way set associative
• Non-Blocking method
• Write back method
• Physical index address
• Physical tag check
2.6.2 Secondary cache
The VR10000 can use an external secondary cache. The features of the secondary cache are as follows:
• Capacity: 512K to 16M bytes
• 16-/32-word cache line
• 2-way set associative
• Way prediction table
• Write back method
• Non-Blocking method
• Physical index address
• Physical tag check
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µPD30700,30700L,30710
3. FPU INTERNAL ARCHITECTURE
3.1 Internal Function Block
Figure 3-1 shows the internal block of the FPU.
The FPU can execute all the floating-point instructions defined by MIPS ISA.
Figure 3-1. Internal Block of FPU
VR10000 internal bus
64
FP queue
64
64
FP register file
FP addition
64
FP
multiplication
FP division
+
FP square root
64
64
64
Data cache
Internal bus
3.2 FPU Registers
(1) Floating-point general-purpose registers (FGR)
These are physical general-purpose registers that can be directly accessed. Thirty-two of these registers are
available. The bit length of each register differs depending on the content of the FR bit of the status register.
(2) Floating-point registers (FPR)
These are logical 64-bit registers that hold a floating-point value when a floating-point operation is executed.
The number of these registers varies depending on the content of the FR bit of the status register.
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µPD30700,30700L,30710
Figure 3-2. Registers of FPU
(a) When FR bit = 0
(b) When FR bit = 1
(MIPS I, MIPS II)
Floating-point registers
(FPR)
Floating-point
general-purpose registers (FGR)
31
FPR0
(MIPS III, MIPS IV)
Floating-point registers
Floating-point
(FPR)
general-purpose registers (FGR)
0
63
0
(low-order)
FGR0
FPR0
FGR0
(high-order)
FGR1
FPR1
FGR1
(low-order)
FGR2
FPR2
FGR2
(high-order)
FGR3
FPR3
FGR3
(low-order)
FGR28
FPR28
FGR28
(high-order)
FGR29
FPR29
FGR29
(low-order)
FGR30
FPR30
FGR30
(high-order)
FGR31
FPR31
FGR31
FPR2
FPR28
FPR30
3.3 Data Format
(1) Floating-point format
The FPU supports IEEE754 floating-point operations of 32 bits (single precision) and 64 bits (double precision).
(2) Fixed-point format
A fixed-point value is calculated in the form of 2’s complement.
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µPD30700,30700L,30710
4. INTERFACE
4.1 System Interface
The I/O timing of the VR10000 is as follows:
• Output starts changing at the rising edge of SysClk.
• Input is latched at the rising edge of SysClk.
The following two buses are used for system interfacing.
• SysAD (63:0) : This bus transfers addresses and data.
• SysCmd (11:0) : This bus transfers command data identifiers.
Both SysAD and SysCmd are bidirectional buses and are driven by the VR10000 or external agent. Depending
on the direction in which they are driven, these buses are in the following two statuses.
• Master status : Driven by the VR10000 to issue a processor request.
• Slave status
: Driven by the external agent to issue an external request.
The following two cycles are used depending on the information included in the SysAD bus.
• Address cycle : A valid address is included in the SysAD bus.
• Data cycle
: Valid data is included in the SysAD bus.
Next, the interface control signals are briefly explained.
• SysReq
: Signal used by the VR10000 to request the right to use the system interface.
• SysGnt
: Signal used by the external agent to grant the VR10000 the right to use the system interface.
• SysRel
: Asserted active when the master of the system interface releases the right of use.
• SysRdRdy
: Indicates that the external agent is ready to accept a processor read request and upgrade
• SysWrRdy
: Indicates that the external agent is ready to accept a processor write request and processor
• SysVal
: Asserted active when the master of the system interface outputs valid data to the SysAD and
request.
eliminate request.
SysCmd buses.
• SysState (2:0) : Signal used by the VR10000 to issue a coherent status request.
• SysResp (4:0) : Signal used by the external agent to issue an external end response.
• SysGblPerf
: Signal used by the external agent to indicate that all processor requests have been completed.
4.1.1 Setting operating frequency of system interface
The VR10000 can select the operating frequency of the system interface.
The clock (PClk) for pipeline operation is generated based on the clock (SysClk) input from an external source.
The factor by which SysClk is multiplied to generate PClk is set by using the BTMC interface at reset. For details,
refer to SysAD (9:12) in Table 4-1 Mode Setting in Boot Time Mode.
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µPD30700,30700L,30710
4.2 Secondary Cache Interface
The VR10000 has a secondary cache control circuit, so that an external secondary cache memory can be connected.
The VR10000 can also selects the operating frequency of the secondary cache interface.
SCClk, at which the secondary cache is to operate, is generated based on the operating clock (PClk) of the
VR10000. The factor by which SysClk is multiplied to generate PClk is set by using the BTMC interface at reset. For
details, refer to SysAD (9:12) in Table 4-1 Mode Setting in Boot Time Mode.
4.3 Clock Interface
4.3.1 System interface clock and processor clock
The VR10000 generates a processor clock (PClk), which is the internal operating clock, from the clock (SysClk and
SysClk) input to the VR10000, by using the PLL. It always samples the SysClk and SysClk signals during operation,
in order to check to see if the following expression is satisfied.
PClk = SysClk × (SysClkDiv + 1)/2
Example Where SysClk = 50 MHz and SysClkDiv = 7
PClk = 50 × 8/2 = 200 MHz
4.3.2 Secondary cache clock
The VR10000 supplies clocks for secondary cache (SCClk (5:0) and SCClk (5:0)) to the external secondary cache.
SCClk (5:0) are generated from SysClk.
The relation between SCClk (5:0) and SysClk can be expressed by the following expression.
SCClk = SysClk × (SysClkDiv + 1)/(SCClkDiv + 1)
Example Where SysClk = 50 MHz, SysClkDiv = 7, and SCClkDiv = 2
SCClk = 50 × 8/3 = 133 MHz
4.4 System Configuration Example
Because the VR10000 employs a cluster bus, it can also support a multi-processor system. Examples of configuration
of a uni-processor system and a multi-processor system are shown below.
4.4.1 Uni-processor system
This system uses only one VR10000, as shown in Figure 4-1.
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µPD30700,30700L,30710
Figure 4-1. Example of Configuration of Uni-Processor System
External agent
SysReq
SysGnt
SysRel
SysRdRdy
SysWrRdy
Main memory,
I/O
SysCmd (11 : 0)
SysCmdPar
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
SysState(2 : 0)
SysStatePar
SysStateVal
SysResp (4 : 0)
SysRespPar
SysRespVal
34
VR10000
SysReq
SysGnt
SysRel
SysRdRdy
SysWrRdy
SCTWr
SCTCS
SCTOE
SCTag(25 : 0)
SCTagChk(6 : 0)
SCTWay
SCTagLSBAddr
SysCmd (11 : 0)
SysCmdPar
SC(A, B)Addr(18 : 0)
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
SysState (2 : 0)
SysStatePar
SysStateVal
SCData (127 : 0)
SysResp (4 : 0)
SysRespPar
SysRespVal
SCDataChk (9 : 0)
SC(A, B)DWr
SC(A, B)DCS
SC(A, B)DOE
SC(A, B)DWay
Secondary cache tag
Wr
CS
OE
Data
Addr
Addr
Data
Wr
CS
OE
Secondary cache data
µPD30700,30700L,30710
4.4.2 Multi-processor system
Up to four VR10000s can be connected to the cluster bus. While a VR10000 stands by for a response after it has
issued a request, it can receive up to four processings. Figure 4-2 shows an example of multi-processor system
configuration.
Figure 4-2. Example of Configuration of Multi-Processor System
SysRel
SysRdRdy
SysWrRdy
SysCmd (11 : 0)
SysCmdPar
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
SysResp (4 : 0)
SysRespPar
SysRespVal
VR10000
SysReq
SysGnt
SysRel
SysReq0
SysGnt0
SysRdRdy
SysWrRdy
Main memory,
I/O
SysState0 (2 : 0)
SysStatePar0
SysStateVal0
SysReq1
SysGnt1
SysState1 (2 : 0)
SysStatePar1
SysStateVal1
Cluster bus
Cluster controller
SCTWr
SCTCS
SCTOE
SCTag (25 : 0)
SCTagChk (6 : 0)
SCTWay
SCTagLSBAddr
SysCmd (11 : 0)
SysCmdPar
SC (A, B) Addr (18 : 0)
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
SysState (2 : 0)
SysStatePar
SysStateVal
Secondary cache tag
Wr
CS
OE
Data
Addr
Secondary cache data
Addr
SC (A, B) DWay
SCData (127 : 0)
SCDataChk (9 : 0)
SysResp (4 : 0)
SC (A, B) DWr
SysRespPar
SC (A, B) DCS
SysRespVal
SC (A, B) DOE
VR10000
SCTWr
SysReq
SCTCS
SysGnt
SCTOE
SysRel
SCTag (25 : 0)
SysRdRdy
SCTagChk (6 : 0)
SysWrRdy
SCTWay
SCTagLSBAddr
SysCmd (11 : 0)
SysCmdPar
SC (A, B) Addr (18 : 0)
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
Data
Wr
CS
OE
Secondary cache tag
Wr
CS
OE
Data
Addr
Secondary cache data
Addr
SysState (2 : 0)
SysStatePar
SysStateVal
SC (A, B) DWay
SysResp (4 : 0)
SysRespPar
SysRespVal
SCDataChk (9 : 0)
SC (A, B) DWr
SC (A, B) DCS
SC (A, B) DOE
SCData (127 : 0)
Data
Wr
CS
OE
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µPD30700,30700L,30710
4.5 BTMC Interface
The operation of the VR10000 is set by the mode bit. The content of the mode bit is stored to the processor via
SysAD (63:0) at power-ON reset or by cold reset sequence while SysGnt is active. The content of the mode bit that
is set via SysAD (24:0) is stored to bits 24 through 0 of the config register.
Table 4-1 shows the correspondence between the SysAD bus and mode setting in the boot time mode.
Table 4-1. Mode Setting in Boot Time Mode (1/2)
SysAD
Mode Setting
VR10000
VR12000
0:2
Kseg0CA: Kseg0 cache status
0, 1: RFU
2: Non-cacheable
3: Cacheable, non-coherent
4: Cacheable, coherent exclusive
5: Cacheable, coherent exclusive on write
6: RFU
7: Non-cacheable, accelerate
3, 4
DevNum: Processor number
5
CohPrcReqTar: Issuance destination of processor coherent request
0: External agent
1: All
6
PrcElmReq: Enables processor eliminate request
0: Disabled
1: Enabled
7, 8
PrcReqMax: Number of processor requests that can be kept pending on system bus
0: 1
1: 2
2: 3
3: 4
9 : 12
SysClkDiv: Multiple of PClk in respect to SysClk
0: RFU
1: × 1
2: × 1.5
3: × 2
4: × 2.5
5: × 3
6: × 3.5
7: × 4
8 to F: RFU
13
SCBlkSize: Line size of secondary cache
0: 16 words
1: 32 words
36
SysClkDiv: Multiple of PClk in respect to SysClk
0: RFU
1: RFU
2: RFU
3: × 2
4: × 2.5
5: × 3
6: × 3.5
7: × 4
8: × 4.5
9: × 5
A: × 5.5
B: × 6
C: × 7
D: × 8
E: × 9
F: × 10
µPD30700,30700L,30710
Table 4-1. Mode Setting in Boot Time Mode (2/2)
SysAD
Mode Setting
VR10000
14
SCCorEn: ECC error correction of secondary cache data
0: Re-access
1: Always access
15
MemEnd: Endian
0: Little endian
1: Big endian
16 : 18
SCSize: Secondary cache size
0: 512K
1: 1M bytes
2: 2M bytes
3: 4M bytes
4: 8M bytes
5: 16M bytes
6 and 7: RFU
19 : 21
SCClkDiv: Multiple of PClk in respect to SCClk
0: RFU
1: × 1
2: × 1.5
3: × 2
4: × 2.5
5: × 3
6 and 7: RFU
VR12000
SCClkDiv: Multiple of PClk in respect to SCClk
0: RFU
1: × 1
2: × 1.5
3: × 2
4: × 2.5
5: × 3
6: RFU
7: × 4
DSDNote 1: DSD (Delay Speculative Dirty) mode
0 to 3: RFU
4: DSD
5 to 7: RFU
22 : 24
RFU
25 : 28
SCClkTap: Internal secondary cache: Phase comparison of clock and SysClk (5:0), SysClk (5:0)
0: Same phase
1: SCClk leads 1/12PClk cycle
2: SCClk leads 2/12PClk cycle
3: SCClk leads 3/12PClk cycle
4: SCClk leads 4/12PClk cycle
5: SCClk leads 5/12PClk cycle
6 and 7: Undefined
8: SCClk leads 6/12PClk cycle
9: SCClk leads 7/12PClk cycle
A: SCClk leads 8/12PClk cycle
B: SCClk leads 9/12PClk cycle
C: SCClk leads 10/12PClk cycle
D: SCClk leads 11/12PClk cycle
E and F: Undefined
29
RFU
30
ODrainSys: Processing of system interface signalNote 2
31 : 63
RFU
Notes 1. Refer to 4.6 DSD (Delay Speculative Dirty) mode.
2. SysReq, SysRel, SysCmd (11:0), SysCmdPar, SysAD (63: 0), SysADChk (7:0), SysVal, SysState (2:0),
SysStatePar, SysStateVal, SysCorErr, SysUncErr
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µPD30700,30700L,30710
4.6 DSD (Delay Speculative Dirty) Mode (VR12000 only)
The DSD (Delay Speculative Dirty) mode prevents a dirty bit from being set by speculative storing.
Bit 24 in the boot mode coincides with bit 24 of the config register and sets the DSD mode in the kernel mode and
supervisor mode. However, the DSD mode can be also executed in the user mode by setting bit 24 of the status
register. Bit 24 of the config register is read-only and can be set only during boot time.
When the DSD mode has been set, the dirty bit of the secondary cache block of the VR12000 are not set until the
store instruction has become the oldest instruction in the active list and ready to be executed (the dirty bit may be
set by an interrupt (and the store instruction is no longer in the speculative status), but the store instruction is not
immediately completed).
4.6.1 DSD mode delay
The DSD mode delays setting of a dirty bit but slightly slows down the processing speed. This slowdown occurs
each time a block is refilled from the main memory if it is necessary to set the dirty bit. It takes 10 cycles to set the
dirty bit. During this time, the processor executes the other instructions in parallel.
Once a block becomes dirty in the secondary cache, this mode does not affect the performance.
4.6.2 Secondary cache status in DSD mode
The secondary cache in the DSD mode enters the Clean Exclusive status if a miss hit occurs when the store
instruction is no longer the oldest instruction in the pipeline.
Because the cache is upgraded to the Clean Exclusive status immediately after a hit occurs in a line in the Shared
status, bus manipulation is started in the speculative status (the processing speed relatively slows down).
4.6.3 Other features
The VR12000 delays loading of the non-coherent cache until this instruction becomes the oldest, regardless of the
DSD mode. This is because speculative loading that accesses an address of the xkphys area not mapped as a noncoherent cache may send data to the secondary cache without appropriate coherency check.
38
µPD30700,30700L,30710
5. INTERNAL/EXTERNAL CONTROL FUNCTIONS
5.1 Reset Function
The following three types of reset functions are available:
• Power-ON reset
• Cold reset
• Software reset
Cold reset and software reset are executed with the power turned on.
As a result of reset, the internal status is initialized. However, software reset does not affect the internal clock and
secondary cache clock.
5.1.1 Power-ON reset and cold reset
Power-ON reset and cold reset are executed when the SysGnt and SysRespVal signals are deasserted inactive
and the SysReset signal is asserted active. During reset, 64-bit data is received from the mode bit, and the internal
status of the processor is initialized (for further information, refer to 4.5 BTMC Interface).
5.1.2 Software reset
Software reset is executed when the SysGnt and SysRespVal signals are deasserted inactive and the SysReset
signal is asserted active. As a result, all the statuses of the external interface are initialized, but the internal clock
and secondary cache clock continues operating. Like the primary and secondary cache, the contents of the CP0 and
FPU registers are retained.
5.2 Interrupt Functions
There are two major types of interrupt requests:
• Maskable interrupt request
• Non-maskable interrupt (NMI) request
(1) Maskable interrupt requests
These interrupts can be masked by using the status register (each interrupt can be serviced independently,
or all interrupts can be serviced in batch).
There is no priority assigned to the interrupts.
(a) Hardware interrupt requests (five sources)
These interrupts are acknowledged when the corresponding external interrupt request is issued.
(b) Software interrupt requests (two sources)
These interrupts are acknowledged when the IP0 and IP1 bits of the cause register are set.
(c) Timer interrupt request (1 source)
This interrupt is acknowledged when the IP7 bit of the cause register is set because the value of the count
register has become equal to the value of the compare register, or when one of the two performance
counters has overflown.
(2) NMI request (1 source)
This is an interrupt request that cannot be masked and is acknowledged when the SysNMI signal is asserted
active.
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µPD30700,30700L,30710
5.3 JTAG Function
The JTAG boundary scan function is a mechanism to test mutual connections among the VR10000 and other
components, and not to test the processor itself.
As the minimum functions of JTAG, the following functions are provided to the VR10000. Functionally, however,
the VR10000 only has the external test function of the JTAG boundary scan register.
• TAP controller
• JTAG instruction register
• JTAG bypass register
• JTAG boundary scan register
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µPD30700,30700L,30710
6. INSTRUCTION SET
The instructions of the VR10000 consists of 1 word (32 bits) located at a word boundary, and come in three formats
as shown in Figure 6-1. Because only three types of instructions are provided, decoding instructions is simplified.
Complicated operations and addressing modes that are not so often used are implemented by a compiler.
6.1 Instruction Formats
The instruction formats of the VR10000 are shown below.
Figure 6-1. CPU Instruction Format
I - type (immediate format)
31
26 25
op
21 20
rs
16 15
0
rt
immediate
J - type (jump format)
31
26 25
0
op
target
R - type (register format)
31
26 25
op
21 20
rs
16 15
rt
11 10
rd
6 5
sa
op
6-bit instruction code
rs
5-bit source register specifier
rt
5-bit target (source/destination) register, or branch condition
immediate
16-bit immediate value, branch displacement, or address displacement
target
26-bit unconditional branch target address
rd
5-bit destination register specifier
sa
5-bit shift amount
funct
6-bit function field
0
funct
6.2 CPU Instruction Set List
The CPU instructions of the VR10000 can be classified into an instruction set common to all the VR series processors
(ISA: Instruction Set Architecture), instruction set that is executed by the VR4000 series and VR10000 series (expanded
ISA), and system control coprocessor instruction set. Tables 6-1 through 6-4 list each instruction set.
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µPD30700,30700L,30710
Table 6-1. CPU Instruction Set: MIPS I (1/2)
Instruction
Description
Load/store instruction
op
Format
base
rt
offset
LB
Load Byte
LB
rt, offset (base)
LBU
Load Byte Unsigned
LBU
rt, offset (base)
LH
Load Halfword
LH
rt, offset (base)
LHU
Load Halfword Unsigned
LHU
rt, offset (base)
LW
Load Word
LW
rt, offset (base)
LWL
Load Word Left
LWL
rt, offset (base)
LWR
Load Word Right
LWR
rt, offset (base)
SB
Store Byte
SB
rt, offset (base)
SH
Store Halfword
SH
rt, offset (base)
SW
Store Word
SW
rt, offset (base)
SWL
Store Word Left
SWL
rt, offset (base)
SWR
Store Word Right
SWR
rt, offset (base)
ALU immediate instruction
op
rs
rt
offset
ADDI
Add Immediate
ADDI
rt, rs, immediate
ADDIU
Add Immediate Unsigned
ADDIU
rt, rs, immediate
SLTI
Set On Less Than Immediate
SLTI
rt, rs, immediate
SLTIU
Set On Less Than Immediate Unsigned
SLTIU
rt, rs, immediate
ANDI
And Immediate
ANDI
rt, rs, immediate
ORI
Or Immediate
ORI
rt, rs, immediate
XORI
Exclusive Or Immediate
XORI
rt, rs, immediate
LUI
Load Upper Immediate
LUI
rt, immediate
3-operand type instruction
op
rs
rt
rd
sa
funct
ADD
Add
ADD
rd, rs, rt
ADDU
Add Unsigned
ADDU
rd, rs, rt
SUB
Subtract
SUB
rd, rs, rt
SUBU
Subtract Unsigned
SUBU
rd, rs, rt
SLT
Set On Less Than
SLT
rd, rs, rt
SLTU
Set On Less Than Unsigned
SLTU
rd, rs, rt
AND
And
AND
rd, rs, rt
OR
Or
OR
rd, rs, rt
XOR
Exclusive Or
XOR
rd, rs, rt
NOR
Nor
NOR
rd, rs, rt
Shift instruction
op
rs
rt
rd
sa
funct
SLL
Shift Left Logical
SLL
rd, rt, sa
SRL
Shift Right Logical
SRL
rd, rt, sa
SRA
Shift Right Arithmetic
SRA
rd, rt, sa
SLLV
Shift Left Logical Variable
SLLV
rd, rt, rs
SRLV
Shift Right Logical Variable
SRLV
rd, rt, rs
SRAV
Shift Right Arithmetic Variable
SRAV
rd, rt, rs
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µPD30700,30700L,30710
Table 6-1. CPU Instruction Set: MIPS I (2/2)
Instruction
Description
Multiplication/division instruction
Format
op
rs
rt
rd
sa
funct
MULT
Multiply
MULT
rs, rt
MULTU
Multiply Unsigned
MULTU
rs, rt
DIV
Divide
DIV
rs, rt
DIVU
Divide Unsigned
DIVU
rs, rt
MFHI
Move From HI
MFHI
rd
MFLO
Move From LO
MFLO
rd
MTHI
Move To HI
MTHI
rs
MTLO
Move To LO
MTLO
rs
Jump instruction (1)
op
target
J
Jump
J
target
JAL
Jump And Link
JAL
target
Jump instruction (2)
op
rs
rt
rd
sa
funct
JR
Jump Register
JR
rs
JALR
Jump And Link Register
JALR
rs
JALR
rs, rd
Branch instruction (1)
BEQ
op
rs
rt
offset
Branch On Equal
BEQ
rs, rt, offset
BNE
Branch On Not Equal
BNE
rs, rt, offset
BLEZ
Branch On Less Than Or Equal To Zero
BLEZ
rs, offset
BGTZ
Branch On Greater Than Zero
BGTZ
rs, offset
Branch instruction (2)
REGIMM
rs
sub
offset
BLTZ
Branch On Less Than Zero
BLTZ
rs, offset
BGEZ
Branch On Greater Than Or Equal to Zero
BGEZ
rs, offset
BLTZAL
Branch On Less Than Zero And Link
BLTZAL
rs, offset
BGEZAL
Branch On Greater Than Or Equal To Zero And Link
BGEZAL
rs, offset
Special instruction
SPECIAL
rs
rt
rd
sa
SYSCALL
System Call
SYSCALL
BREAK
Breakpoint
BREAK
Coprocessor instruction (1)
op
base
rt
funct
offset
LWCz
Load Word To Coprocessor z
LWCz
rt, offset (base)
SWCz
Store Word From Coprocessor z
SWCz
rt, offset (base)
COPz
cofun
Coprocessor instruction (2)
COPz
Coprocessor z Operation
COPz
CO
cofun
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µPD30700,30700L,30710
Table 6-2. CPU Instruction Set: MIPS II
Instruction
Description
Load/store instruction
op
Format
base
rt
offset
LL
Load Linked
LL
rt, offset (base)
SC
Store Conditional
SC
rt, offset (base)
Branch instruction (1)
op
rs
rt
offset
BEQL
Branch On Equal Likely
BEQL
rs, rt, offset
BNEL
Branch On Not Equal Likely
BNEL
rs, rt, offset
BLEZL
Branch On Less Than Or Equal To Zero Likely
BLEZL
rs, offset
BGTZL
Branch On Greater Than Zero Likely
BGTZL
rs, offset
Branch instruction (2)
REGIMM
rs
sub
offset
BLTZL
Branch On Less Than Zero Likely
BLTZL
rs, offset
BGEZL
Branch On Greater Than Or Equal To Zero Likely
BGEZL
rs, offset
BLTZALL
Branch On Less Than Zero And Link Likely
BLTZALL
rs, offset
BGEZALL
Branch On Greater Than Or Equal To Zero And Link Likely
BGEZALL rs, offset
Exception instruction
SPECIAL
rs
rt
rd
sa
funct
TGE
Trap If Greater Than Or Equal
TGE
rs, rt
TGEU
Trap If Greater Than Or Equal Unsigned
TGEU
rs, rt
TLT
Trap If Less Than
TLT
rs, rt
TLTU
Trap If Less Than Unsigned
TLTU
rs, rt
TEQ
Trap If Equal
TEQ
rs, rt
TNE
Trap If Not Equal
TNE
rs, rt
Exception immediate instruction
REGIMM
rs
sub
immediate
TGEI
Trap If Greater Than Or Equal Immediate
TGEI
rs, immediate
TGEIU
Trap If Greater Than Or Equal Immediate Unsigned
TGEIU
rs, immediate
TLTI
Trap If Less Than Immediate
TLTI
rs, immediate
TLTIU
Trap If Less Than Immediate Unsigned
TLTIU
rs, immediate
TEQI
Trap If Equal Immediate
TEQI
rs, immediate
TNEI
Trap If Not Equal Immediate
TNEI
rs, immediate
Special instruction
SYNC
SPECIAL
rs
rt
Synchronize
Coprocessor instruction
rd
sa
funct
SYNC
op
base
rt
offset
LDCz
Load Doubleword To Coprocessor z
LDCz
rt, offset (base)
SDCz
Store Doubleword From Coprocessor z
SDCz
rt, offset (base)
44
µPD30700,30700L,30710
Table 6-3. CPU Instruction Set: MIPS III
Instruction
Description
Load/store instruction
op
Format
base
rt
offset
LD
Load Doubleword
LD
rt, offset (base)
LDL
Load Doubleword Left
LDL
rt, offset (base)
LDR
Load Doubleword Right
LDR
rt, offset (base)
LLD
Load Linked Doubleword
LLD
rt, offset (base)
LWU
Load Word Unsigned
LWU
rt, offset (base)
SCD
Store Conditional Doubleword
SCD
rt, offset (base)
SD
Store Doubleword
SD
rt, offset (base)
SDL
Store Doubleword Left
SDL
rt, offset (base)
SDR
Store Doubleword Right
SDR
rt, offset (base)
ALU immediate instruction
op
rs
rt
immediate
DADDI
Doubleword Add Immediate
DADDI
rt, rs, immediate
DADDIU
Doubleword Add Immediate Unsigned
DADDIU
rt, rs, immediate
3-operand type instruction
op
rs
rt
rd
sa
DADD
Doubleword Add
DADDU
Doubleword Add Unsigned
DADDU
rd, rs, rt
DSUB
Doubleword Subtract
DSUB
rd, rs, rt
DSUBU
Doubleword Subtract Unsigned
DSUBU
rd, rs, rt
Shift instruction
DADD
funct
op
rs
rt
rd
sa
rd, rs, rt
funct
DSLL
Doubleword Shift Left Logical
DSLL
rd, rt, sa
DSRL
Doubleword Shfit Right Logical
DSRL
rd, rt, sa
DSRA
Doubleword Shift Right Arithmetic
DSRA
rd, rt, sa
DSLLV
Doubleword Shift Left Logical Variable
DSLLV
rd, rt, rs
DSRLV
Doubleword Shift Right Logical Variable
DSRLV
rd, rt, rs
DSRAV
Doubleword Shift Right Arithmetic Variable
DSRAV
rd, rt, rs
DSLL32
Doubleword Shift Left Logical + 32
DSLL32
rd, rt, sa
DSRL32
Doubleword Shift Right Logical + 32
DSRL32
rd, rt, sa
DSRA32
Doubleword Shift Right Arithmetic +32
DSRA32
rd, rt, sa
Multiplication/division instruction
op
rs
rt
rd
sa
funct
DMULT
Doubleword Multiply
DMULT
rs, rt
DMULTU
Doubleword Multiply Unsigned
DMULTU
rs, rt
DDIV
Doubleword Divide
DDIV
rs, rt
DDIVU
Doubleword Divide Unsigned
DDIVU
rs, rt
45
µPD30700,30700L,30710
Table 6-4. CPU Instruction Set: MIPS IV
Instruction
Description
3-operand type instruction
op
Format
rs
rt
rd
sa
funct
MOVN
Move Conditional On Not Zero
MOVN
rd, rs, rt
MOVZ
Move Conditional On Zero
MOVZ
rd, rs, rt
Prefetch instruction
PREF
op
base
hint
offset
Prefetch
PREF
hint, offset (base)
6.3 FPU Instruction Set List
All the FPU instructions are 32 bits long and located at a word boundary.
Tables 6-5 through 6-8 list the FPU instruction set.
Table 6-5. FPU Instruction Set: MIPS I
Instruction
Description
Load/store instruction
op
Format
base
ft
offset
LWC1
Load Word To FPU
LWC1
ft, offset (base)
SWC1
Store Word From FPU
SWC1
ft, offset (base)
Transfer instruction
COP1
sub
rt
fs
0
MTC1
Move Word To FPU
MTC1
rt, fs
MFC1
Move Word From FPU
MFC1
rt, fs
CTC1
Move Control Word To FPU
CTC1
rt, fs
CFC1
Move Control Word From FPU
CFC1
rt, fs
Conversion instruction
COP1
fmt
0
fs
fd
funct
CVT.S.fmt
Floating-point Convert To Single Floating-point Format
CVT.S.fmt
fd, fs
CVT.D.fmt
Floating-point Convert To Double Floating-point Format
CVT.D.fmt
fd, fs
CVT.W.fmt
Floating-point Convert To Single Fixed-point Format
CVT.W.fmt
fd, fs
Operation instruction
ADD.fmt
COP1
fmt
ft
fs
Floating-point Add
fd
funct
ADD.fmt
fd, fs, ft
SUB.fmt
Floating-point Subtract
SUB.fmt
fd, fs, ft
MUL.fmt
Floating-point Multiply
MUL.fmt
fd, fs, ft
DIV.fmt
Floating-point Divide
DIV.fmt
fd, fs, ft
ABS.fmt
Floating-point Absolute Value
ABS.fmt
fd, fs
MOV.fmt
Floating-point Move
MOV.fmt
fd, fs
NEG.fmt
Floating-point Negate
NEG.fmt
fd, fs
Compare instruction
C.cond.fmt
COP1
fmt
ft
fs
Floating-point Compare
FPU branch instruction
cc
0
funct
C.cond.fmt
COP1
BC
cc
0
cc, fs, ft
offset
BC1T
Branch On FPU True
BC1T
cc, offset
BC1F
Branch On FPU False
BC1F
cc, offset
46
µPD30700,30700L,30710
Table 6-6. FPU Instruction Set: MIPS II
Instruction
Description
Load/store instruction
op
Format
base
ft
offset
LDC1
Load Doubleword To FPU
LDC1
ft, offset (base)
SDC1
Store Doubleword From FPU
SDC1
ft, offset (base)
Conversion instruction
COP1
fmt
0
fs
fd
funct
ROUND.W.fmt
Floating-point Round To Single Fixed-point Format
ROUND.W.fmt
fd, fs
TRUNC.W.fmt
Floating-point Truncate To Single Fixed-point Format
TRUNC.W.fmt
fd, fs
CEIL.W.fmt
Floating-point Ceiling To Single Fixed-point Format
CEIL.W.fmt
fd, fs
FLOOR.W.fmt
Floating-point Floor To Single Fixed-point Format
FLOOR.W.fmt
fd, fs
Operation instruction
SQRT.fmt
COP1
fmt
ft
fs
Floating-point Square Root
fd
funct
SQRT.fmt
FPU branch instruction
COP1
BC
cc
0
fd, fs
offset
BC1TL
Branch On FPU True Likely
BC1TL
cc, offset
BC1FL
Branch On FPU False Likely
BC1FL
cc, offset
Table 6-7. FPU Instruction Set: MIPS III
Instruction
Description
Transfer instruction
COP1
Format
sub
rt
fs
0
DMTC1
Doubleword Move To FPU
DMTC1
rt, fs
DMFC1
Doubleword Move From FPU
DMFC1
rt, fs
Conversion instruction
COP1
fmt
0
fs
fd
funct
CVT.S.fmt
Floating-point Convert To Single Floating-point Format
CVT.S.fmt
fd, fs
CVT.D.fmt
Floating-point Convert To Double Floating-point Format
CVT.D.fmt
fd, fs
CVT.L.fmt
Floating-point Convert To Long Fixed-point Format
CVT.L.fmt
fd, fs
ROUND.L.fmt
Floating-point Round To Long Fixed-point Format
ROUND.L.fmt
fd, fs
TRUNC.L.fmt
Floating-point Truncate To Long Fixed-point Format
TRUNC.L.fmt
fd, fs
CEIL.L.fmt
Floating-point Ceiling To Long Fixed-point Format
CEIL.L.fmt
fd, fs
FLOOR.L.fmt
Floating-point Floor To Long Fixed-point Format
FLOOR.L.fmt
fd, fs
47
µPD30700,30700L,30710
Table 6-8. FPU Instruction Set: MIPS IV
Instruction
Description
Load index instruction
op
Format
base
index
0
fd
funct
LWXC1
Load Word Indexed To Floating-point
LWXC1
fd, index (base)
LDXC1
Load Doubleword Indexed To Floating-point
LDXC1
fd, index (base)
Store index instruction
op
base
index
fs
0
funct
SWXC1
Store Word Indexed From Floating-point
SWXC1
fs, index (base)
SDXC1
Store Doubleword Indexed From Floating-point
SDXC1
fs, index (base)
Conversion instruction
COP1
fmt
0
fs
fd
funct
RECIP.fmt
Reciprocal Approximation
RECIP.fmt
fd, fs
RSQRT.fmt
Reciprocal Square Root Approximation
RSQRT.fmt
fd, fs
Multiplication instruction (1)
COP1
fmt
ft
fs
fd
funct
MSUB.fmt
Floating-point Multiply Subtract
MSUB.fmt
fd, fr, fs, ft
NMSUB.fmt
Floating-point Negative Multiply Subtract
NMSUB.fmt
fd, fr, fs, ft
MADD.fmt
Floating-point Multiply Add
MADD.fmt
fd, fr, fs, ft
NMADD.fmt
Floating-point Negative Multiply Add
NMADD.fmt
fd, fr, fs, ft
MOVN.fmt
Floating-point Move Conditional On Not Zero
MOVN.fmt
fd, fs, ft
MOVZ.fmt
Floating-point Move Conditional On Zero
MOVZ.fmt
fd, fs, ft
Operation instruction (2)
COP1
fmt
cc
0
fs
fd
funct
MOVF.fmt
Floating-point Move Conditional On FPU False
MOVF.fmt
fd, fs, cc
MOVT.fmt
Floating-point Move Conditional On FPU True
MOVT.fmt
fd, fs, cc
Compare instruction
C.cond.fmt
COP1
fmt
ft
fs
Floating-point Compare
FPU branch instruction
cc
0
funct
C.cond.fmt
COP1
BC
cc
0
cc, fs, ft
offset
BC1T
Branch On FPU True
BC1T
cc, offset
BC1F
Branch On FPU False
BC1F
cc, offset
BC1TL
Branch On FPU True Likely
BC1TL
cc, offset
BC1FL
Branch On FPU False Likely
BC1FL
cc, offset
Conditional transfer instruction
op
rs
cc
tf
rd
funct
MOVF
Move Conditional On FPU False
MOVF
rd, rs, cc
MOVT
Move Conditional On FPU True
MOVT
rd, rs, cc
Prefetch instruction
PREFX
48
op
Prefetch Indexed
base
index
hint
0
PREFX
funct
hint, index (base)
µPD30700,30700L,30710
6.4 Delay of Instruction
(1) Delay of integer instructions
Table 6-9 shows execution delay of the integer instructions.
For details of each instruction, refer to VR5000, VR10000 User’s Manual – Instruction.
Table 6-9. Integer Operation Instruction Delay Time
Instruction Type
Execution Unit
PClk
Repeat Rate
1
1
1
1
1
1
Conditional Branch
1
1
Conditional Move
1
1
ADD, SET, SUB, Logical
ALU1, ALU2
MFHI, MTHI, MFLO, MTLO
Shift, LUI
ALU1
MULT
ALU2
Remark
5/6
6
Delay of LO/HI
MULTU
6/7
7
Delay of LO/HI
DMULT
9/10
10
Delay of LO/HI
DMULTU
10/11
11
Delay of LO/HI
DIV, DIVU
34/35
35
Delay of LO/HI
DDIV, DDIVU
66/67
67
Delay of LO/HI
Load (except for CP1 instruction)
Load/store
Store
2
1
In the case of cache hit
—
1
In the case of cache hit
(2) Delay of floating-point instructions
Table 6-10 shows the execution delay of the floating-point instruction.
For details of each instruction, refer to VR5000, VR10000 User’s Manual – Instruction.
Table 6-10. Floating-Point Instruction Delay Time
Instruction Type
Execution Unit
PClk
Repeat Rate
Remark
MTC1, DMTC1
ALU1
3
1
ADD, SUB, ABS, NEG, ROUND,
TRUNC, CEIL, FLOOR, C.cond
Fp adder
2
1
CVT.S.W, CVT.S.L
4
2
CVT (other than above)
2
1
2
1
MFC1, DMFC1
2
1
Conditional MOVE/CVT.S.L
2
1
DIV.S, RECIP.S
12
14
DIV.D, RECIP.D
19
21
SQRT.S
18
20
SQRT.D
33
35
RSQRT.S
30
20
RSQRT.D
52
35
2/4
1
“2” if other MADD instruction uses operation
result
3
1
In the case of cache hit
MUL
Fp multiplier
MADD
Fp adder + Fp
multiplier
LWC1, LDC1, LWXC1, LDXC1
Load/store
Average value of repeat rate
49
µPD30700,30700L,30710
7. ELECTRICAL SPECIFICATIONS
(1) µPD30700RS-180 and 30700RS-200
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Supply voltage
VDD
Input voltage
VI
Condition
Pulse of less than 10 ns
Storage temperature
Tstg
Rating
Unit
–0.5 to +3.8
V
–0.5 to VDD + 0.3
V
–1.5 to VDD + 0.3
V
–40 to +125
°C
Cautions 1. Do not short-circuit two or more outputs at the same time.
2. If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Use the product(s) with these rated values never exceeded. The
specifications and conditions shown in DC Characteristics and AC Characteristics below are
the range in which the product(s) operate normally and the quality of the product is guaranteed.
Operating Case Temperature (VDD = 3.3 V ±0.165 V)
Parameter
Symbol
Operating case temperature TC
50
Condition
Rating
Unit
0 to 70
°C
µPD30700,30700L,30710
DC Characteristics (TC = 0 to 70 °C, VDD = 3.3 V ±0.165 V)
(a) Common to CMOS/TTL and HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
Cin
5
pF
Output capacitance
Cout
7
pF
Power consumption
PD
200 MHz (VDD = 3.3 V)
30
W
180 MHz (VDD = 3.3 V)
27
W
Input leakage power
ILI
±10
µA
I/O leakage current
ILIO
±10
µA
MIN.
MAX.
Unit
3.135
3.465
V
1.2
1.6
V
(b) CMOS/TTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
VDDQ
voltageNote 2
Condition
VDDQ = VDD
VREF
High-level output voltage
VOH
VDD = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDD = MAX., IOL = 4 mA
High-level input voltage
VIH
Low-level input voltage
VIL
2.4
V
0.4
V
2.0
VDD + 0.3
V
–0.5
+0.8
V
MIN.
MAX.
Unit
VDDQ
1.4
1.6
V
VREF
0.65
0.75
V
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins.
(c) HSTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
voltageNote 2
High-level output threshold
voltageNote 3
Low-level output threshold
voltageNote 3
Condition
VOH
IOH = –4 mA
VOL
IOL = 4 mA
VDDQ/2 + 0.3
V
VDDQ/2 – 0.3
V
VREF + 0.1
VDD + 0.3
V
VIL
–0.3
VDD – 0.1
V
VDIH
VDIL + 0.8
VDD + 0.3
V
VDIL
–0.3
VDIH – 0.8
V
High-level differential input threshold voltage
1Note 4
VIH
Low-level differential input threshold voltage
1Note 4
High-level differential input threshold voltage
2Note 5
Low-level differential input threshold voltage
2Note 5
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins.
3. The VR10000 supports 1a and 1b of the HSTL specifications of SGI.
4. Applied to the input pins other than SysClk and SysClk.
5. Applied to the SysClk and SysClk pins.
51
µPD30700,30700L,30710
AC Characteristics (TC = 0 to 70 °C, VDD = 3.3 V ±0.165 V)
Clock parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
System clock high-level width
tCH
tCR, tCF ≤ 2.0 ns
0.5
ns
System clock low-level width
tCL
tCR, tCF ≤ 2.0 ns
0.5
ns
200-MHz model
50
200
MHz
180-MHz model
45
180
MHz
200-MHz model
5
20
ns
180-MHz model
5.56
22.2
ns
tji
±125
ps
tjo
±500
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
System clock
frequencyNotes 1,2
System clock
cycleNotes 1,2
Input system clock jitter
Output system clock
jitterNote 3
tCP
Notes 1. The operation of the VR10000 is guaranteed only when PLL operates.
2. The operation is guaranteed when the internal operating frequency is 100 MHz or higher.
3. Changes between clock edges are undefined.
52
µPD30700,30700L,30710
System Interface Parameter
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
Secondary Cache Tag Interface Parameter
Applied to SCTag (25:0) and SCTagChk (6:0)
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
53
µPD30700,30700L,30710
(2) µPD30700LRS-225 and 30700LRS-250 (preliminary)
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Supply voltage
VDD
Input voltage
VI
Condition
Pulse of less than 10 ns
Storage temperature
Tstg
Rating
Unit
–0.5 to +3.3
V
–0.5 to VDD + 0.3
V
–1.5 to VDD + 0.3
V
–40 to +125
°C
Cautions 1. Do not short-circuit two or more outputs at the same time.
2. If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Use the product(s) with these rated values never exceeded. The
specifications and conditions shown in DC Characteristics and AC Characteristics below are
the range in which the product(s) operate normally and the quality of the product is guaranteed.
Operating Case Temperature (VDD = 2.6 V ±0.1 V)
Parameter
Symbol
Operating case temperature TC
54
Condition
Rating
Unit
0 to 70
°C
µPD30700,30700L,30710
DC Characteristics (TC = 0 to 70 °C, VDD = 2.6 V ±0.1 V)
(a) Common to CMOS/TTL and HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
Cin
5
pF
Output capacitance
Cout
7
pF
Power consumption
PD
250 MHz (VDD = 2.6 V)
20
W
225 MHz (VDD = 2.6 V)
17
W
Input leakage power
ILI
±10
µA
I/O leakage current
ILIO
±10
µA
MIN.
MAX.
Unit
2.5
2.7
V
1.2
1.6
V
(b) CMOS/TTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
VDDQ
voltageNote 2
Condition
VDDQ = VDD
VREF
High-level output voltage
VOH
VDD = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDD = MAX., IOL = 4 mA
High-level input voltage
VIH
Low-level input voltage
VIL
2.4
V
0.4
V
2.0
VDD + 0.3
V
–0.5
+0.8
V
MIN.
MAX.
Unit
VDDQ
1.4
1.6
V
VREF
0.65
0.75
V
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins.
(c) HSTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
voltageNote 2
High-level output threshold
voltageNote 3
Low-level output threshold
voltageNote 3
Condition
VOH
IOH = –4 mA
VOL
IOL = 4 mA
VDDQ/2 + 0.3
V
VDDQ/2 – 0.3
V
VREF + 1
VDD + 0.3
V
VIL
–0.3
VDD – 0.1
V
VDIH
VDIL + 0.8
VDD + 0.3
V
VDIL
–0.3
VDIH – 0.8
V
High-level differential input threshold voltage
1Note 4
VIH
Low-level differential input threshold voltage
1Note 4
High-level differential input threshold voltage
2Note 5
Low-level differential input threshold voltage
2Note 5
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins.
3. The VR10000 supports 1a and 1b of the HSTL specifications of SGI.
4. Applied to the input pins other than SysClk and SysClk.
5. Applied to the SysClk and SysClk pins.
55
µPD30700,30700L,30710
AC Characteristics (TC = 0 to 70 °C, VDD = 2.6 V ±0.1 V)
Clock parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
System clock high-level width
tCH
tCR, tCF ≤ 2.0 ns
0.5
ns
System clock low-level width
tCL
tCR, tCF ≤ 2.0 ns
0.5
ns
250-MHz model
62.5
250
MHz
225-MHz model
56.3
225
MHz
250-MHz model
4
16
ns
225-MHz model
4.44
17.8
ns
tji
±125
ps
tjo
±500
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
System clock
frequencyNotes 1, 2
System clock
cycleNotes 1, 2
Input system clock jitter
Output system clock
jitterNote 3
tCP
Notes 1. The operation of the VR10000 is guaranteed only when PLL operates.
2. The operation is guaranteed when the internal operating frequency is 100 MHz or higher.
3. Changes between clock edges are undefined.
56
µPD30700,30700L,30710
System Interface Parameter
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
Secondary Cache Tag Interface Parameter
Applied to SCTag (25:0) and SCTagChk (6:0)
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
57
µPD30700,30700L,30710
(3) µPD30710RS-300 (preliminary)
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Supply voltage
VDD
Input voltage
VI
Condition
Pulse of less than 10 ns
Storage temperature
Tstg
Rating
Unit
–0.5 to +3.3
V
–0.5 to VDD + 0.3
V
–1.5 to VDD + 0.3
V
–40 to +125
°C
Cautions 1. Do not short-circuit two or more outputs at the same time.
2. If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Use the product(s) with these rated values never exceeded. The
specifications and conditions shown in DC Characteristics and AC Characteristics below are
the range in which the product(s) operate normally and the quality of the product is guaranteed.
Operating Case Temperature (VDD = 2.6 V ±0.1 V)
Parameter
Symbol
Operating case temperature TC
58
Condition
Rating
Unit
25 to 70
°C
µPD30700,30700L,30710
DC Characteristics (TC = 25 to 70 °C, VDD = 2.6 V ±0.1 V)
(a) Common to CMOS/TTL and HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
Cin
5
pF
Output capacitance
Cout
7
pF
Power consumption
PD
30
W
Input leakage power
ILI
±10
µA
I/O leakage current
ILIO
±10
µA
MIN.
MAX.
Unit
2.5
2.7
V
1.2
1.6
V
300 MHz (VDD = 2.6 V)
(b) CMOS/TTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
VDDQ
voltageNote 2
Condition
VDDQ = VDD
VREF
High-level output voltage
VOH
VDD = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDD = MAX., IOL = 4 mA
High-level input voltage
VIH
Low-level input voltage
VIL
2.4
V
0.4
V
2.0
VDD + 0.3
V
–0.5
+0.8
V
MIN.
MAX.
Unit
VDDQ
1.4
1.6
V
VREF
0.65
0.75
V
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins.
(c) HSTL
Parameter
Output supply
Input supply
Symbol
voltageNote 1
voltageNote 2
High-level output threshold
voltageNote 3
Low-level output threshold
voltageNote 3
Condition
VOH
IOH = –4 mA
VOL
IOL = 4 mA
VDDQ/2 + 0.3
V
VDDQ/2 – 0.3
V
VREF + 0.1
VDD + 0.3
V
VIL
–0.3
VDD – 0.1
V
VDIH
VDIL + 0.8
VDD + 0.3
V
VDIL
–0.3
VDIH – 0.8
V
High-level differential input threshold voltage
1Note 4
VIH
Low-level differential input threshold voltage
1Note 4
High-level differential input threshold voltage
2Note 5
Low-level differential input threshold voltage
2Note 5
Notes 1. VDDQ is applied to the VDDQSC and VDDQSys pins.
2. VREF is applied to the VrefSC and VrefSys pins
3. The VR12000 supports 1a and 1b of the HSTL specifications of SGI.
4. Applied to the input pins other than SysClk and SysClk.
5. Applied to the SysClk and SysClk pins.
59
µPD30700,30700L,30710
AC Characteristics (TC = 25 to 70 °C, VDD = 2.6 V ±0.1 V)
Clock parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
System clock high-level width
tCH
tCR, tCF ≤ 2.0 ns
0.5
ns
System clock low-level width
tCL
tCR, tCF ≤ 2.0 ns
0.5
ns
300-MHz model
30
300
MHz
300-MHz model
3.33
33.3
ns
tji
±125
ps
tjo
±500
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
System clock
frequencyNotes 1, 2
System clock
cycleNotes 1, 2
Input system clock jitter
Output system clock
jitterNote 3
tCP
Notes 1. The operation of the VR12000 is guaranteed only when PLL operates.
2. The operation is guaranteed when the internal operating frequency is 100 MHz or higher.
3. Changes between clock edges are undefined.
60
µPD30700,30700L,30710
System Interface Parameter
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tDO
Data input setup time
tDS
1.0
ns
Data input hold time
tDH
1.0
ns
Secondary Cache Tag Interface Parameter
Applied to SCTag (25:0) and SCTagChk (6:0)
(a) CMOS/TTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
2.0
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
(b) HSTL
Parameter
Symbol
Condition
MIN.
MAX.
Unit
1.5
ns
Data output delay time
tSDO
Data input setup time
tSDS
1.5
ns
Data input hold time
tSDH
0.5
ns
61
µPD30700,30700L,30710
Timing Chart
Secondary Cache Interface Timing
SCCIk
tDO
SCData (127 : 0)
SCDataChk (9 : 0)
tDH
tDS
Output
Input
tDO
tDO
SCAAddr (18 : 0)
SCBAddr (18 : 0)
SCTagLSBAddr
SCADOE
SCBDOE
SCADWr
SCBDWr
SCADCS
SCBDCS
SCTWay
SCTOE
SCTWr
SCTCS
tSDO
SCTag (25 : 0)
SCTagChk (6 : 0)
Output
Secondary cache clock jitter
tJO
SCCIk
62
(VOL + VOH)/2
tSDH
tSDS
tJO
Input
µPD30700,30700L,30710
System Interface Timing
SysCIk
tDO
SysRel
SysCmd (11 : 0)
SysCmdPar
SysAD (63 : 0)
SysADChk (7 : 0)
SysVal
SysReq
SysState (2 : 0)
SysStatePar
SysStateVal
SysCorErr
SysUncErr
tDH
tDS
Output
Input
tDO
tDO
tDS
tDH
SysGnt
SysRdRdy
SysWrRdy
SysResp (4 : 0)
SysRespPar
SysRespVal
SysReset
SysNMI
SysGblPerf
SysCyc
Input
System Clock
tCP
tCH
VDIH
tCL
SysClk
VDIL
tCR
tCF
System Clock Jitter
tji
SysCIk
tji
(VDIL + VDIH)/2
63
µPD30700,30700L,30710
8. PUSH-PULL OUTPUT BUFFER CIRCUIT
The configuration of the push-pull output buffer circuit is shown below.
Push-pull output buffer circuit (without load of termination)
VCCQ
VCCQ
VREF
VREF
Push-pull output buffer circuit (with load of termination)
VCCQ
VCCQ
VREF
64
VREF
µPD30700,30700L,30710
9. PACKAGE DRAWING
599 PIN CERAMIC LGA
A
A
W1
U
X
S
E
F
C
W2 V Y
T
I
J
B
D
Index mark
C
G
B
R
L
QL
NM
C A S B S *1
C *2
H
NOTE
*1 Each land centerline is located within 0.30 mm (0.012 inch) of
its true position (T.P.) at least material condition.
*2 Each land centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
47.50±0.25
1.870±0.010
B
29.00
1.142
C
47.50±0.25
1.870±0.010
D
29.00
1.142
E
2.16
0.085
F
1.27 (T.P.)
0.050 (T.P.)
G
1.27 (T.P.)
0.050 (T.P.)
H
0.70 MAX.
0.028 MAX.
I
2.54±0.25
0.100±0.010
J
3.81±0.38
0.150±0.015
L
0.76±0.13
0.030 +0.005
–0.006
N
0.20
0.008
Q
0.30
0.012
R
2.16
0.085
S
43.18
1.700
T
43.18
1.700
U
32.54
1.281
V
32.54
1.281
W1
37.00
1.457
W2
37.00
1.457
X
30.00
1.181
Y
30.00
1.181
X599RS-50A
65
µPD30700,30700L,30710
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
66
µPD30700,30700L,30710
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.1.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
J98. 2
67
µPD30700,30700L,30710
Related Documents: VR10000, VR12000 User’s Manual (U10278E)
VR5000, VR10000 User’s Manual - Instruction (U12754E)
The related documents referred to in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
VR4000, VR4200, VR4400, VR5000, VR10000, VR12000, and VR series are trademarks of NEC Corporation.
MIPS and ANDES are trademarks of MIPS Technologies, Inc.
UNIX is a registered trademark licensed by X/Open Company Limited in the US and other countries.
Windows NT is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
This product employs technology which is restricted by the export control regulations of the United States of
America. Permission of the United States government might be required in case of exporting this product or
products in which this product is installed.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5