STLS2E02 Loongson 2E: 700MHz 64-bit superscalar MIPS® based microprocessor Data Brief Features ■ 64 bit superscalar architecture ■ 700MHz clock frequency (typical conditions) ■ Single/double precision floating-point units ■ New Streaming Multimedia instruction set support (SIMD) ■ 64KB instruction cache, 64KB data cache, onchip 512KB unified L2 cache ■ On-chip DDR-333 controller ■ Thermal Design Power (TDP) – 4W @ 700MHz ■ Leading edge 90nm process technology ■ 35x35 BGA package ■ MIPS based ■ MIPS bus interface (Sysad) PBGA452 The memory hierarchy is composed by the first level of 64KB 4-way set associative cache for instructions and data, the second level of 512KB unified 4-ways set associative cache and the Memory Management Unit with Table Lookside Buffer. Description The STLS2E02, is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64bit SIMD and one load/store unit. The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science. Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performance and low power dissipation. The microarchitecture is organized with nine stages of pipeline and support of dynamic branch prediction. Table 1. April 2007 Device summary Part numbers Package Packing STLS2E02 PBGA452 (35x35x2.33mm) Tray Rev 2 For further information contact your local STMicroelectronics sales office. 1/5 www.st.com 5 Architectural features and block diagram 1 Architectural features and block diagram ● CPU ● – Out-of-order superscalar 64bit architecture – MIPS based – 9 stage pipeline organized in fetch, pre-decode, decode, reg-map, dispatch, issue, reg-read,execution and commit – Up to 64 instructions executed out-of-order with four issue mechanism – 64bit register file (32 fix+32 float) – Register renaming unit composed by 64-entry physical register files – Branch prediction unit – Six functional units: two integer, two float, one SIMD unit, one load/store unit Memory Hierarchy – Figure 1. STLS2E02 64KB + 64KB four-ways set-associative first level instruction and data cache – 512KB four-ways set associative unified second level cache – Up to 24 non-blocking accesses with on-the-fly Memory Disambiguation – Load speculation through value return from previous pending stores – Miss word first access for cache miss access – Instruction 16-entry TLB (Table Lookside Buffer) and unified 64-entry TLB with page size from 4KB to 4MB Block diagram Commit Bus Reorder Queue Branch Bus BRQ Writeback Bus ROQ BTB ITLB I-Cache 64KB Refill Bus Fix RS Integer Register File Float RS Floating Point Register File ALU1 D-Cache 64KB TAG Compare Decoder PC Pre-Decoder BHT Register Mapper PC + 16 Map Bus ALU2 AGU FPU1 CP0 Queue TLB FPU2 Miss Writeback Cache Interface Queue Queue L2 cache SysAD Controller SysAD64 2/5 Arbitrator DDR Controller DDR AC00116 STLS2E02 2 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. PBGA452 mechanical data & package dimensions mm inch DIM. MIN. TYP. A A1 MIN. TYP. 2.460 0.360 A2 b MAX. 0.0142 0.750 0.0681 0.900 0.0236 0.0295 0.0354 D 35.000 1.3780 D1 31.750 1.2500 D2 30.000 1.1811 E 35.000 1.3780 E1 31.750 1.2500 E2 30.000 1.1811 e 1.270 0.0500 F H 1.630 22.500 OUTLINE AND MECHANICAL DATA 0.0969 1.730 0.600 MAX. 0.0642 23.500 0.8858 0.9252 ddd 0.200 0.0079 eee 0.300 0.0118 fff 0.150 0.0059 HS/PBGA452 (35x35x2.33mm) Slug Plastic Ball Grid Array 7656604 A 3/5 Revision history 3 STLS2E02 Revision history Table 2. 4/5 Document revision history Date Revision Changes 23-Mar-2007 1 Initial release. 26-Apr-2007 2 Text modifications. STLS2E02 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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