HD74LV2GT245A Dual Bus Transceivers with 3–state Outputs / CMOS Logic Level Shifter REJ03D0153–0200Z (Previous ADE-205-694A (Z)) Rev.2.00 Oct.23.2003 Description The HD74LV2GT245A has two buffers with three state output in a 8 pin package. When DIR is high, data is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs to the A outputs. The A and B buses are separated by making the enable input (OE) high level. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV2GT245AUSE SSOP-8 pin TTP-8DBV US E (3,000 pcs/reel) Rev.2.00, Oct.23.2003, page 1 of 9 HD74LV2GT245A Outline and Article Indication • HD74LV2GT245A Index band Lot No. Y M W T 4 5 Y : Year code (the last digit of year) M : Month code W : Week code SSOP-8 Marking Function Table Inputs OE DIR Operation L L B data to A bus L H A data to B bus H X Isolation H : High level L : Low level X : Immaterial Rev.2.00, Oct.23.2003, page 2 of 9 HD74LV2GT245A Pin Arrangement DIR 1 8 VCC A1 2 7 OE A2 3 6 B1 GND 4 5 B2 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Test Conditions Supply voltage range VCC –0.5 to 7.0 V Input voltage range *1 VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V Output voltage range *1, 2 –0.5 to 7.0 Output : H or L VCC : OFF or output : Z Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00, Oct.23.2003, page 3 of 9 HD74LV2GT245A Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage VCC 3.0 to 5.5 V Input voltage VIN 0 to 5.5 V Output voltage VOUT 0 to VCC V 0 to 5.5 Output : Z Operating temperature Topr –40 to +85 Input rise / fall time tr, tf 0 to 100 (VCC = 3.0 to 3.6 V) ns 0 to 20 (VCC = 4.5 to 5.5 V) Rev.2.00, Oct.23.2003, page 4 of 9 Test Conditions °C HD74LV2GT245A Electrical Characteristics • Ta = –40 to 85°C Item Symbol VCC (V) * Min Typ Max Unit Input voltage VIH 3.0 to 3.6 1.5 — — V 4.5 to 5.5 2.0 — — 3.0 to 3.6 — — 0.6 4.5 to 5.5 — — 0.8 3.3 — 0.10 — 5.0 — 0.15 — Min to Max VCC–0.1 — — 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA VIL Hysteresis voltage VH Output voltage VOH VOL Test condition V VT+ – VT– V IOH = –50 µA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Off state output current IOZ Min to Max — — ±5 µA VO = 5.5 V or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 ∆ICC 5.5 — — 1.5 mA One input VIN = 3.4 V, other input VCC or GND IOFF 0 — — 5 µA VO = 5.5 V Input capacitance CIN 5.0 — 3.0 — pF VIN = VCC or GND Output capacitance 5.0 — 5.5 — pF VO = VCC or GND Output leakage current CO Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00, Oct.23.2003, page 5 of 9 HD74LV2GT245A Switching Characteristics • VCC = 3.3 ± 0.3 V Ta = 25°C Test Ta = –40 to 85°C FROM Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 6.0 8.5 1.0 10.0 ns — 8.0 12.0 1.0 13.5 Enable time tZH tZL — 8.0 13.5 1.0 15.5 — 10.0 17.0 1.0 19.0 tHZ tLZ — 9.5 16.5 1.0 19.5 — 14.0 20.0 1.0 22.0 Disable time CL = 15 pF TO (Output) A or B B or A OE A or B OE A or B FROM TO CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF • VCC = 5.0 ± 0.5 V Ta = 25°C Test Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Conditions (Input) (Output) Propagation delay time tPLH tPHL — 4.3 5.5 1.0 6.5 ns A or B B or A — 5.6 7.5 1.0 8.5 Enable time tZH tZL — 5.7 8.5 1.0 10.0 OE A or B — 7.0 10.6 1.0 12.0 tHZ tLZ — 7.8 12.8 1.0 14.2 OE A or B — 10.9 14.7 1.0 16.0 Disable time CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 5.0 25.0 — pF f = 10 MHz Rev.2.00, Oct.23.2003, page 6 of 9 — HD74LV2GT245A Test Circuit VCC Pulse Generator Z OUT = 50 Ω See Function Table Input VCC OE Output A1 S1 1 kΩ S2 B1 CL = 15 or 50 pF OPEN See under table *1 GND DIR TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ Notes: 1. C L includes probe and jig capacitance. 2. A2–B2 are idential to above load circuit. 3. S1 : Input–Output change switch. Rev.2.00, Oct.23.2003, page 7 of 9 S2 OPEN GND VCC HD74LV2GT245A • Waveforms – 1 Input tr tf VI 90 % Vref 90 % Vref 10 % 10 % t PLH GND t PHL VOH In phase output 50% 50% VOL • Waveforms – 2 Input OE tr tf VI 90 % Vref 90 % Vref 10 % t ZL 10 % GND t LZ VCC 50% Waveform – A VOL + 0.3 V t ZH Waveform – B t HZ VOH – 0.3 V 50% VOL VOH GND INPUTS VCC (V) VI Vref tr / tf 3.3±0.3 2.5 V ≤ 3.0 ns 50% ≤ 3.0 ns 1.5 V 5.0±0.5 3V Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct.23.2003, page 8 of 9 HD74LV2GT245A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.2.00, Oct.23.2003, page 9 of 9 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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