ADVANCED INFORMATION IDT72251 CMOS SyncFIFO 8192 X 9 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • 8192 x 9-bit organization Pin/function compatible with IDT72421/722x1 family 15 ns read/write cycle time Read and write clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in 32-pin plastic leaded chip carrier (PLCC) Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications DESCRIPTION: The IDT72251 SyncFIFO is a very high-speed, lowpower First-In, First-Out (FIFO) memory with clocked read and write controls. The IDT72251 has a 8192 x 9-bit memory array. This FIFO is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. This FIFO has a 9-bit input and output port. The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1 , WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two read enable pins (REN1, REN2). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFO has two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin (LD). The IDT72251 is fabricated using IDT’s high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM D0 - D8 WCLK WEN2 INPUT REGISTER OFFSET REGISTER FLAG LOGIC WRITE CONTROL LOGIC RAM ARRAY 8192 x 9 WRITE POINTER READ POINTER READ CONTROL LOGIC OUTPUT REGISTER RESET LOGIC RCLK Q0 - Q8 3545 drw 01 SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc DECEMBER 1996 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.14 DSC-3545/- 1 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES D8 2 D7 3 D6 D4 4 D5 D3 INDEX D2 PIN CONFIGURATION 1 32 31 30 29 RS D1 5 D0 6 28 WEN1 PAF 7 27 WCLK PAE 8 26 WEN2/LD GND 9 25 VCC J32-1 12 22 Q6 OE 13 21 14 15 16 17 18 19 20 Q5 PLCC TOP VIEW Q4 Q7 REN2 Q3 23 Q2 11 Q1 Q8 RCLK Q0 24 FF 10 EF REN1 2655 drw 02b PIN DESCRIPTIONS Symbol D0-D8 RS Name Data Inputs Reset WCLK Write Clock WEN1 Write Enable 1 WEN2/LD Write Enable 2/ Load Q0-Q8 RCLK Data Outputs Read Clock REN1 Read Enable 1 REN2 Read Enable 2 OE Output Enable EF Empty Flag PAE I/O Description I Data inputs for a 9-bit bus. I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/ LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. O Data outputs for a 9-bit bus. I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is Empty+7. PAE is synchronized to RCLK. FF Programmable Almost-Empty Flag Programmable O Almost-Full Flag Full Flag O VCC GND Power Ground PAF When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is Full-7. PAF is synchronized to WCLK. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. One +5 volt power supply pin. One 0 volt ground pin. 2655 tbl 01 5.14 2 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial –0.5 to +7.0 Symbol VCCC Unit V 0 to +70 °C GND VIH –55 to +125 °C VIL –55 to +125 °C 50 mA 2655 tbl 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Commercial Min. 4.5 Typ. 5.0 Max. 5.5 Unit V 0 2.0 0 — 0 — V V — — 0.8 V CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN(2) (1,2) Parameter Conditions Max. Unit Input Capacitance VIN = 0V 10 pF VOUT = 0V 10 pF Output Capacitance COUT NOTES: 1. With output deselected (OE = HIGH). 2. Characterized values, not currently tested. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C) Symbol Parameter Min. IDT72251 Commercial tCLK = 15, 20, 25, 35 Typ. Max. Unit ILI(1) Input Leakage Current (Any Input) -1 — 1 µA ILO(2) Output Leakage Current -10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2mA 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8mA — — 0.4 V ICC1(4) Active Power Supply Current — — 80 mA NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3 & 4. Measurements are made with outputs unloaded. Tested at fCLK = 20MHz. (3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA (4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA fCLK = 1/tCLK. CL = external capacitive load (30pF typical) 5.14 3 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C Symbol 72251L15 Min. Max. Parameter Commercial 72251L20 72251L25 Min. Max. Min. Max. 72251L35 Min. Max. Unit fS Clock Cycle Frequency — 66.7 — 50 — 40 — 28.6 MHz tA Data Access Time 2 10 2 12 3 15 3 20 ns tCLK Clock Cycle Time 15 — 20 — 25 — 35 — ns tCLKH Clock HIGH Time 6 — 8 — 10 — 14 — ns tCLKL Clock LOW Time 6 — 8 — 10 — 14 — ns tDS Data Set-up Time 4 — 5 — 6 — 8 — ns tDH Data Hold Time 1 — 1 — 1 — 2 — ns tENS Enable Set-up Time 4 — 5 — 6 — 8 — ns tENH Enable Hold Time 1 — 1 — 1 — 2 — ns tRS Reset Pulse Width(1) 15 — 20 — 25 — 35 — ns tRSS Reset Set-up Time 15 — 20 — 25 — 35 — ns tRSR Reset Recovery Time 15 — 20 — 25 — 35 — ns tRSF Reset to Flag Time and Output Time — 15 — 20 — 25 — 35 ns tOLZ Output Enable to Output in Low-Z(2) 0 — 0 — 0 — 0 — ns tOE Output Enable to Output Valid 3 8 3 10 3 13 3 15 ns tOHZ Output Enable to Output in High-Z(2) 3 8 3 10 3 13 3 15 ns tWFF Write Clock to Full Flag — 10 — 12 — 15 — 20 ns tREF Read Clock to Empty Flag — 10 — 12 — 15 — 20 ns tPAF Write Clock to Programmable Almost-Full Flag — 10 — 12 — 15 — 20 ns tPAE Read Clock to Programmable Almost-Empty Flag — 10 — 12 — 15 — 20 ns tSKEW1 Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag 6 — 8 — 10 — 12 — ns tSKEW2 Skew Time Between Read Clock and Write Clock for Programmable Almost-Empty Flag and Programmable Almost-Full Flag 28 — 35 — 40 — 42 — ns NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 5V 1.1K D.U.T. 680Ω AC TEST CONDITIONS In Pulse Levels Input Rise/Fall Times 30pF* GND to 3.0V 3ns 2655 drw 03 Input Timing Reference Levels 1.5V or equivalent circuit Output Reference Levels 1.5V Figure 1. Output Load Output Load See Figure 1 *Includes jig and scope capacitances. 2655 tbl 09 5.14 4 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES SIGNAL DESCRIPTIONS INPUTS: Data In (D0 - D8) — Data inputs for 9-bit wide data. CONTROLS: Reset (RS) — Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. Write Clock (WCLK) — A write cycle is initiated on the LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag (FF) and Programmable Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. Write Enable 1 (WEN1) — If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only enable control pin. In this configuration, when Write Enable 1 (WEN1) is low, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. If the FIFO is configured to have two write enables, which allows for depth expansion, there are two enable control pins. See Write Enable 2 paragraph below for operation in this configuration. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1) is ignored when the FIFO is full. Read Clock (RCLK) — Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). The write and read clocks can be asynchronous or coincident. Read Enables (REN1, REN2) — When both Read Enables (REN1, REN2) are LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK). When either Read Enable (REN1, REN2) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO is empty. Output Enable (OE) — When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. Write Enable 2/Load (WEN2/LD) — This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If Write Enable 2/Load (WEN2/LD) is set high at Reset (RS = LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/ LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. In this configuration, when Write Enable (WEN1) is HIGH and/or Write Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. The FIFO is configured to have programmable flags when the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS=low). The IDT7225 device contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values. If the FIFO is configured to have programmable flags when the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/ LD) are set low, data on the inputs D is written into the Empty (Least Significant Bit) offset register on the first LOW-to-HIGH transition of the write clock (WCLK). Data is written into the Empty (Most Significant Bit) offset register on the second LOW-to-HIGH transition of the write clock (WCLK), into the Full (Least Significant Bit) offset register on the third transition, and into the Full (Most Significant Bit) offset register on the fourth transition. The fifth transition of the write clock (WCLK) again writes to the Empty (Least Significant Bit) offset register. 5.14 5 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the Write Enable 2/Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write Enable 1 (WEN1) is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the Write Enable 2/Load (WEN2/LD) pin is set low and both Read Enables (REN1, REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the read clock (RCLK). A read and write should not be performed simultaneously to the offset registers. WCLK(1) LD WEN1 0 0 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Selection 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation NOTE: 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register OUTPUTS: Full Flag (FF) — The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 8192 writes for the IDT72251. The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK). 72251 — 8192 x 9-BIT 8 7 0 Empty Offset (LSB) Default Value 007H 8 Empty Flag (EF) — The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Data Outputs (Q0 - Q8) — Data outputs for a 9-bit wide data. 0 (MSB) 00000 8 7 0 Full Offset (LSB) Programmable Almost-Full Flag ( PAF ) — The Programmable Almost-Full Flag (PAF) will go LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the Programmable Almost-Full Flag (PAF) will go LOW after 8192 writes for the IDT72251. The offset “m” is defined in the Full offset registers. If there is no Full offset specified, the Programmable Almost-Full Flag (PAF) will go LOW at Full-7 words. The Programmable Almost-Full Flag (PAF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). Programmable Almost-Empty Flag (PAE) — The Programmable Almost-Empty Flag (PAE) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty offset registers. If no reads are performed after Reset the Programmable AlmostEmpty Flag (PAE) will go HIGH after "n+1" for the IDT72251. If there is no Empty offset specified, the Programmable Almost-Empty Flag (PAE) will go LOW at Empty+7 words. The Programmable Almost-Empty Flag ( PAE ) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). 4 Default Value 007H 8 4 0 (MSB) 00000 Figure 3. Offset Register Location and Default Values TABLE 1: STATUS FLAGS NUMBER OF WORDS IN FIFO FF PAF PAE EF 0 H H L L 1 to n(1) H H L H (n+1) to (8192-(m+1) H H H H (8192-m)(2) to 8191 8192 H L H H L L H H NOTES: 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value) 5.14 6 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tRS RS tRSS tRSR tRSS tRSR tRSS tRSR REN1, REN2 WEN1 WEN2/LD (1) tRSF EF, PAE tRSF FF, PAF tRSF OE = 1 Q0 - Q8 OE = 0 (2) 2655 drw 06 NOTES: 1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. 2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 3. The clocks (RCLK, WCLK) can be free-running during reset. Figure 4. Reset Timing 5.14 7 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tCLK tCLKH tCLKL WCLK tDH tDS D0 - D 8 DATA IN VALID tENS tENH WEN1 NO OPERATION WEN2/ (If Applicable) NO OPERATION tWFF tWFF FF tSKEW1(1) RCLK REN1, REN2 2655 drw 07 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 5. Write Cycle Timing 5.14 8 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tCLK tCLKL tCLKH RCLK tENH REN1, REN2 tENS NO OPERATION tREF tREF EF tA Q0 - Q8 VALID DATA tOLZ tOHZ tOE OE tSKEW1 (1) WCLK WEN1 WEN2 2655 drw 08 NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle Timing Figure 6. Read Cycle Timing 5.14 9 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES WCLK tDS D0 - D8 D1 D2 D3 D0 (First Valid tENS WEN1 WEN2 (If Applicable) tFRL (1) tSKEW1 RCLK tREF EF REN1, REN2 tA Q 0 - Q8 tA D0 D1 tOLZ tOE OE 2655 drw 09 NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW). Figure 7. First Data Word Latency Timing 5.14 10 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES NO WRITE NO WRITE WCLK tDS tSKEW1 tDS tSKEW1 DATA WRITE D0 - D8 tWFF tWFF tWFF FF WEN1 WEN2 (If Applicable) RCLK tENS REN1, REN2 OE tENH tENS tENH tA LOW tA Q0 - Q8 DATA READ DATA IN OUTPUT REGISTER NEXT DATA READ 2655 drw 10 Figure 8. Full Flag Timing 5.14 11 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES WCLK tDS tDS DATA WRITE 1 D 0 - D8 DATA WRITE 2 tENH tENH tENS tENS WEN1 tENS tENH tENH tENS WEN2 (If Applicable) (1) tFRL(1) tFFL tSKEW1 tSKEW1 RCLK tREF tREF tREF EF REN1, REN2 OE Q 0 - Q8 LOW tA DATA READ DATA IN OUTPUT REGISTER 2655 drw 11 NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW). Figure 9. Empty Flag Timing 5.14 12 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tCLKH tCLKL (4) WCLK tENS tENH tENS tENH WEN1 WEN2 (If Applicable) tPAF (1) PAF Full - m words in FIFO(2) Full - (m+1) words in FIFO tSKEW2 (3) tPAF RCLK REN1, REN2 tENS tENH 2655 drw 12 NOTES: 1. PAF offset = m. 2. 8192 - m words in FIFO IDT72251. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge. 4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW. Figure 10. Programmable Full Flag Timing 5.14 13 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tCLKH tCLKL WCLK tENS tENH tENS tENH WEN1 WEN2 (If Applicable) (1) PAE n words in FIFO tSKEW2 (2) n+1 words in FIFO tPAE tPAE (3) RCLK tENS tENH REN1, REN2 2655 drw 13 NOTES: 1. PAE offset = n. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge. 3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW. Figure 11. Programmable Empty Flag Timing 5.14 14 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES tCLK tCLKH tCLKL WCLK tENS tENH LD tENS WEN1 tDS tDH D 0 - D7 PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) PAF OFFSET (MSB) 2655 drw 14 Figure 12. Write Offset Registers Timing tCLK tCLKH tCLKL RCLK tENS tENH LD tENS REN1, REN2 tA Q0 - Q7 DATA IN OUTPUT REGISTER EMPTY OFFSET (LSB) EMPTY OFFSET (MSB) FULL OFFSET (LSB) FULL OFFSET (MSB) 2655 drw 15 Figure 13. Read Offset Registers Timing 5.14 15 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - A single IDT72251 may be used when the application requirements are for 8192 words or less. When the IDT72251 is in a Single Device Configuration, the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. RESET ( WRITE CLOCK (WCLK) READ CLOCK (RCLK) ) WRITE ENABLE 1 ( IDT 72251 DATA IN (D0 - D8) FULL FLAG ( PROGRAMMABLE ALMOST FULL ( ) READ ENABLE 1 ( ) WRITE ENABLE 2/LOAD (WEN2/ ) OUTPUT ENABLE ( ) DATA OUT (Q0 - Q8) ) EMPTY FLAG ( ) PROGRAMMABLE ALMOST EMPTY ( READ ENABLE 2 ( ) ) 3545 drw 16 ) Figure 14. Block Diagram of Single 8192 x 9 Synchronous FIFO WIDTH EXPANSION CONFIGURATION - Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (AE and AF) can be detected from any one device. Figure 15 demonstrates a 18-bit word width by RESET ( DATA IN (D) 18 using two IDT72251. Any word width can be attained by adding additional IDT72251s. When the IDT72251is in a Width Expansion Configuration, the Read Enable 2 (REN2) control input can be grounded (see Figure 15). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. RESET ( ) 9 ) 9 READ CLOCK (RCLK) WRITE CLOCK (WCLK) WRITE ENABLE1 ( READ ENABLE ( ) WRITE ENABLE2/LOAD (WEN2/ OUTPUT ENABLE ( ) IDT 72251 FULL FLAG ( ) #1 FULL FLAG ( ) #2 PROGRAMMABLE ( ) IDT 72251 READ ENABLE 2 ( EMPTY FLAG ( ) #1 EMPTY FLAG ( ) #2 9 DATA OUT (Q) 9 ) PROGRAMMABLE ( ) READ ENABLE 2 ( ) ) ) 18 3545 drw 17 Figure 15. Block Diagram of 8192 x 18 Synchronous FIFO Used in a Width Expansion Configuration 5.14 16 IDT72251 CMOS SyncFIFO 8192 x 9 COMMERCIAL TEMPERATURE RANGES DEPTH EXPANSION - The IDT72251 can be adapted to applications when the requirements are for greater than 8192 words. The existence of two enable pins on the read and write port allow depth expansion. The Write Enable 2/Load pin is used as a second write enable in a depth expansion configuration thus the Programmable flags are set to the default values. Depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data access from one device to the next in a sequential manner. The IDT72251 operates in the Depth Expansion configuration when the following conditions are met: 1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a second Write Enable. 2. External logic is used to control the flow of data. Please see the Application Note" DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details of this configuration. ORDERING INFORMATION IDT XXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range BLANK Commercial (0°C to +70°C) J Plastic Leaded Chip Carrier (PLCC) 15 20 25 35 Com'l. Only L Low Power 72251 8192 x 9 Synchronous FIFO Clock Cycle Time (tCLK) Speed in ns 3545a drw 18 5.14 17