CY7C4221 CY7C42311 K / 2 K × 9 Synchronous FIFOs CY7C4221 / CY7C4231 1 K / 2 K × 9 Synchronous FIFOs 1 K / 2 K × 9 Synchronous FIFOs Features Functional Description ■ High-speed, low-power, first-in first-out (FIFO) memories ❐ 1 K × 9 (CY7C4221) ❐ 2 K × 9 (CY7C4231) ■ High-speed 66.7 MHz operation (15 ns read/write cycle time) ■ Low power (ICC = 35 mA) ■ Fully asynchronous and simultaneous read and write operation ■ Empty, Full, and Programmable Almost Empty and Almost Full status flags ■ TTL-compatible ■ Output Enable (OE) pin to three-state the output bus ■ Independent read and write enable pins ■ Center power and ground pins for reduced noise ■ Width-expansion capability ■ Space saving 7 mm × 7 mm 32-pin TQFP and 32-pin PLCC packages available ■ Pin-compatible and functionally equivalent to IDT72221 & 72231 ■ Pb-free packages available The CY7C42X1 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C42X1 are pin-compatible to IDT722X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read-enable pins (REN1, REN2). In addition, the CY7C42X1 has an output enable pin (OE). The Read (RCLK) and Write (WCLK) clocks can be tied together for single-clock operation or the two clocks can run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.The CY7C42X1 provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty – 7 and Full – 7. The flags are synchronous, they change state relative to either the Read clock (RCLK) or the Write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. All configurations are fabricated using advanced 0.65 N-Well CMOS technology. Input ESD protection is greater than 2001 V, and latch up is prevented by the use of guard rings. Cypress Semiconductor Corporation Document Number: 38-06016 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 17, 2012 CY7C4221 / CY7C4231 Selection Guide Description Maximum frequency -15 Unit 66.7 MHz Maximum access time 10 ns Minimum cycle time 15 ns Minimum data or enable setup 4 ns Minimum data or enable hold 1 ns Maximum flag delay 10 ns Commercial 35 mA Industrial 40 Active power supply current Density CY7C4221 CY7C4231 1K×9 2K×9 Logic Block Diagram D0 - 8 INPUT REGISTER WCLK WEN1 WEN2/LD FLAG PROGRAM REGISTER Write CONTROL FLAG LOGIC Dual Port RAM Array 1K x 9 Write POINTER RS EF PAE PAF FF Read POINTER 2Kx 9 RESET LOGIC THREE-STATE OUTPUT REGISTER Read CONTROL OE Q0 - 8 Document Number: 38-06016 Rev. *H RCLK REN1 REN2 Page 2 of 22 CY7C4221 / CY7C4231 Contents Pin Configuration ............................................................. 4 Pin Definitions .................................................................. 4 Architecture ...................................................................... 5 Resetting the FIFO ............................................................ 5 FIFO Operation ................................................................. 5 Programming .................................................................... 5 Programmable Flag (PAE, PAF) Operation ................ 6 Width Expansion Configuration ...................................... 7 Flag Operation .................................................................. 7 Full Flag ....................................................................... 7 Empty Flag .................................................................. 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 Electrical Characteristics ................................................. 8 Capacitance ...................................................................... 8 AC Test Loads and Waveforms ....................................... 9 Document Number: 38-06016 Rev. *H Switching Characteristics ................................................ 9 Switching Waveforms .................................................... 10 Typical AC and DC Characteristics .............................. 16 Ordering Information ...................................................... 17 1 K × 9 Synchronous FIFO ........................................ 17 2 K × 9 Synchronous FIFO ........................................ 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Page 3 of 22 CY7C4221 / CY7C4231 Pin Configuration Figure 1. Pin Diagram 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 9 10 11 12 13 14 15 16 Q3 Q4 PAF PAE GND REN1 RCLK REN2 1 2 3 4 5 6 7 8 Q2 D1 D0 OE EF FF Q0 Q1 EF FF Q0 Q1 Q2 Q3 Q4 RS WEN1 WCLK WEN2/LD V CC Q8 Q7 Q6 Q5 D4 D5 D6 D7 D8 RS D2 D2 D3 D4 D5 D6 D7 D8 4 3 2 1 32 3130 29 5 28 6 27 7 26 8 9 25 10 24 11 23 12 22 21 13 14151617181920 D1 D0 PAF PAE GND REN1 RCLK REN2 OE D3 TQFP Top View PLCC Top View Pin Definitions Pin Name I/O Description D0–8 Data Inputs I Q0–8 Data Outputs O Data outputs for 9-bit bus. WEN1 Write Enable 1 I The only write enable to have programmable flags when device is configured. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. WEN2/LD Write Enable 2 Dual Mode Load Pin I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data is not written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. REN1, REN2 Read Enable Inputs I Enables device for read operation. WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. I Data inputs for 9-bit bus. Document Number: 38-06016 Rev. *H Page 4 of 22 CY7C4221 / CY7C4231 Architecture The CY7C42X1 consists of an array of 1K or 2K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF). Resetting the FIFO During powerup, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0–8) go LOW tRSF after the rising edge of RS. For the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW. FIFO Operation When the WEN1 signal is active LOW and WEN2 is active HIGH, data present on the D0–8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW, data in the FIFO memory is presented on the Q0–8 outputs. New data is presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 must set up tENS before RCLK for it to be a valid read function. WEN1 and WEN2 must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0–8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register is available to the Q0–8 outputs after tOE. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0–8 outputs even after additional reads occur. Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. Document Number: 38-06016 Rev. *H Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS = LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2 / Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. Programming When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42X1 for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 2 on page 6 shows the registers sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK Read register contents to the data outputs. Writes and reads should not be preformed simultaneously on the offset registers. Page 5 of 22 CY7C4221 / CY7C4231 Figure 2. Offset Register Location and Default Values 1K × 9 8 2K × 9 0 7 Empty Offset (LSB) Reg. Default Value = 007h Empty Offset (LSB) Reg. Default Value = 007h 0 1 8 0 7 8 (MSB) 00 (MSB) 000 0 7 8 Full Offset (LSB) Reg Default Value = 007h 0 1 0 7 8 Full Offset (LSB) Reg Default Value = 007h 8 0 2 8 Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. 0 2 8 (MSB) 000 (MSB) 00 equal to CY7C4221 (1K – m) or CY7C4231 (2K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. Table 1. Writing the Offset Registers LD WEN WCLK [1] Selection The number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n + 1) or greater unread words. 0 0 Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) 0 1 No operation The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF. PAF is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or 1 0 Write into FIFO 1 1 No operation Table 2. Status Flags Number of Words in FIFO CY7C4221 0 CY7C4231 0 [2] [2] FF PAF PAE EF H H L L H H L H 1 to n 1 to n (n + 1) to 512 (n + 1) to 1024 H H H H 513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) H H H H (1024 – m)[3] to 1023 (2048 – m)[3] to 2047 H L H H 1024 2048 L L H H Notes 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK. 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value). Document Number: 38-06016 Rev. *H Page 6 of 22 CY7C4221 / CY7C4231 Width Expansion Configuration Flag Operation Word width may be increased by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 3 demonstrates a 18-bit word width by using two CY7C42X1s. Any word width can be attained by adding additional CY7C42X1s. The CY7C42X1 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) goes LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK - it is exclusively updated by each rising edge of WCLK. When the CY7C42X1 is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (See Figure 3). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Empty Flag The Empty Flag (EF) goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK - it is exclusively updated by each rising edge of RCLK. Figure 3. Block Diagram of 1024 × 9, 2048 × 9 Synchronous FIFO Memory Used in a Width Expansion Configuration Reset (RS) Data In (D) 18 Write Write Write Clock Reset (RS) 9 9 Read Clock (WCLK) Read Enable 1 (REN1) Enable 1 (WEN1) Output Enable 2/LOAD (WEN2/LD) Programmable CY7C42X1 (PAF) Full Flag (FF) # 1 Full Flag (FF) # 2 (RCLK) CY7C42X1 Programmable (PAE) Empty Flag (EF) #1 EF Empty EF FF FF Enable (OE) 9 Flag (EF) #2 Data Out (Q) 18 9 Read Enable 2 (REN2) Document Number: 38-06016 Rev. *H Read Enable 2 (REN2) Page 7 of 22 CY7C4221 / CY7C4231 Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings[4] may shorten the useful life of the device. User guidelines are not tested. Storage temperature .................................. –65 °C to +150 °C Ambient temperature with power applied ............................................ –55 °C to +125 °C Supply voltage to ground potential ..............–0.5 V to +7.0 V DC voltage applied to outputs in High Z state .............................................–0.5 V to +7.0 V Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch up current ..................................................... > 200 mA Operating Range Range Ambient Temperature VCC Commercial 0 °C to +70 °C 5 V ± 10% Industrial [5] –40 °C to +85 °C 5 V ± 10% DC input voltage ..........................................–3.0 V to +7.0 V Electrical Characteristics Over the Operating Range Parameter Description -15 Test Conditions Unit Min Max 2.4 – V – 0.4 V VOH Output HIGH voltage VCC = Min, IOH = –2.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage 2.2 VCC V VIL Input LOW voltage –3.0 0.8 V IIX Input leakage current VCC = Max –10 +10 A IOS[6] Output short circuit current VCC = Max, VOUT = GND –90 – mA IOZL Output OFF, High Z current OE > VIH, VSS < VO < VCC –10 +10 mA Commercial – 35 mA Industrial – 40 mA Commercial – 10 mA Industrial – 15 mA Max Unit 5 pF 7 pF IOZH ICC1[7] ICC2[8] Active power supply current Average standby current Capacitance Parameter [9] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Notes 4. The voltage on any input or I/O pin cannot exceed the power pin during powerup. 5. TA is the “instant on” case temperature. 6. Test no more than one output at a time for not more than one second. 7. Outputs open. Tested at frequency = 20 MHz. 8. All inputs = VCC – 0.2 V, except WCLK and RCLK, which are switching at 20 MHz. 9. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-06016 Rev. *H Page 8 of 22 CY7C4221 / CY7C4231 AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms [10, 11] R1 1.1 K All Input Pulses 5V Output 3.0 V R2 680 CL Including JIG and Scope GND 3 ns Equivalent to: Thé venin Equivalent 420 Output 90% 10% 90% 10% 3 ns 1.91 V Switching Characteristics Over the Operating Range Parameter Description -15 Min Max Unit tS Clock Cycle Frequency – 66.7 MHz tA Data Access Time 2 10 ns tCLK Clock Cycle Time 15 – ns tCLKH Clock HIGH Time 6 – ns tCLKL Clock LOW Time 6 – ns tDS Data Setup Time 4 – ns tDH Data Hold Time 1 – ns tENS Enable Setup Time 4 – ns tENH Enable Hold Time 1 – ns tRS Reset Pulse Width [12] 15 – ns tRSS Reset Setup Time 10 – ns tRSR Reset Recovery Time 10 – ns tRSF Reset to Flag and Output Time – 15 ns tOLZ Output Enable to Output in Low Z [13] 0 – ns tOE Output Enable to Output Valid 3 8 ns tOHZ Output Enable to Output in High Z [13] 3 8 ns tWFF Write Clock to Full Flag – 10 ns tREF Read Clock to Empty Flag – 10 ns tPAF Clock to Programmable Almost-Full Flag – 10 ns tPAE Clock to Programmable Almost-Full Flag – 10 ns tSKEW1 Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag 6 – ns tSKEW2 Skew Time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag 15 – ns Notes 10. CL = 30 pF for all AC parameters except for tOHZ. 11. CL = 5 pF for tOHZ. 12. Pulse widths less than minimum values are not allowed. 13. Values guaranteed by design, not currently tested. Document Number: 38-06016 Rev. *H Page 9 of 22 CY7C4221 / CY7C4231 Switching Waveforms Figure 5. Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 –D8 tENS tENH WEN1 No Operation No Operation WEN2 (if applicable) tWFF tWFF FF [14] tSKEW1 RCLK REN1,REN2 Figure 6. Read Cycle Timing tCKL tCLKH tCLKL RCLK tENS tENH REN1,REN2 NO OPERATION tREF tREF EF tA Q0 –Q8 Valid Data tOLZ tOHZ tOE OE [15] tSKEW1 WCLK WEN1 WEN2 Notes 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge. Document Number: 38-06016 Rev. *H Page 10 of 22 CY7C4221 / CY7C4231 Switching Waveforms (continued) Figure 7. Reset Timing [16] tRS RS REN1, REN2 tRSS tRSR tRSS tRSR tRSS tRSR WEN1 WEN2/LD [17] tRSF EF,PAE tRSF FF,PAF, tRSF OE = 1 Q0 - Q8 [18] OE = 0 Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write WCLK t DS D 0 –D8 D0 (First D1 Valid Write) tENS D2 D3 D4 [19] tFRL WEN1 WEN2 (if applicable) tSKEW1 RCLK tREF EF tA REN1, REN2 Q0 –Q8 [20] tA D0 tOLZ D1 tOE OE Notes 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the programmable flag offset registers. 18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1. 19. When tSKEW1 > minimum specification, tFRL(maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL(maximum) = either 2 × tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 20. The first word is available the cycle after EF goes HIGH, always. Document Number: 38-06016 Rev. *H Page 11 of 22 CY7C4221 / CY7C4231 Switching Waveforms (continued) Figure 9. Empty Flag Timing WCLK tDS tDS Data Write 2 Data Write 1 D0 –D8 tENS tENH tENH tENS WEN1 WEN2 (if applicable) tENS tENH tFRL tENS [21] tENH [21] tFRL RCLK tSKEW1 tREF tREF tREF tSKEW1 EF REN1, REN2 LOW OE tA Q0 –Q8 Data in Output Register Data Read Note 21. When tSKEW1 > minimum specification, tFRL(maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL(maximum) = either 2 × tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). Document Number: 38-06016 Rev. *H Page 12 of 22 CY7C4221 / CY7C4231 Switching Waveforms (continued) Figure 10. Full Flag Timing NO Write NO Write NO Write WCLK tSKEW1[22] tSKEW1[22] tDS Data Write Data Write D0 –D8 tWFF tWFF tWFF FF WEN1 WEN2 (if applicable) RCLK OE tENH tENS REN1, REN2 tENS LOW tA Q0 –Q8 tENH Data in Output Register tA Data Read Next Data Read Note 22. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. Document Number: 38-06016 Rev. *H Page 13 of 22 CY7C4221 / CY7C4231 Switching Waveforms (continued) Figure 11. Programmable Almost Empty Flag Timing tCLKL tCLKH WCLK tENS tENH WEN1 WEN2 (if applicable) tENS tENH PAE tSKEW2[23] Note 24 N + 1 Words INFIFO tPAE Note 25 tPAE RCLK tENS tENS tENH REN1, REN2 Figure 12. Programmable Almost Full Flag Timing tCLKL tCLKH Note 26 WCLK tENS tENH WEN1 Note 27 WEN2 (if applicable) tENS tENH PAF tPAF FULL M Words IN FIFO [28] FULL M+1 Words IN FIFO tSKEW2[29] tPAF RCLK tENS tENS tENH REN1, REN2 Notes 23. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 24. PAE offset = n. 25. If a read is performed on this rising edge of the read clock, there are Empty + (n – 1) words in the FIFO when PAE goes LOW. 26. If a write is performed on this rising edge of the write clock, there are Full – (m – 1) words of the FIFO when PAF goes LOW. 27. PAF offset = m. 28. 1024 – m words for CY7C4221, 2048 – m words for CY7C4231. 29. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK. Document Number: 38-06016 Rev. *H Page 14 of 22 CY7C4221 / CY7C4231 Switching Waveforms (continued) Figure 13. Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH WEN2/LD tENS WEN1 tDS tDH D0 –D8 PAE Offset LSB PAE Offset MSB PAF Offset LSB PAF Offset MSB Figure 14. Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH WEN2/LD tENS PAF Offset MSB REN1, REN2 tA Q0 –Q8 Document Number: 38-06016 Rev. *H Unknown PAE Offset LSB PAE Offset MSB PAF Offset LSB Page 15 of 22 CY7C4221 / CY7C4231 Typical AC and DC Characteristics Normalized Supply Current vs. Ambient Temperature Normalized Supply Current vs. Supply Voltage 1.20 1.2 1.0 VIN = 3.0 V TA = 25 °C f = 100 MHz 0.8 0.6 4 4.5 5 5.5 1.10 1.00 0.90 0.80 55 6 Supply Voltage (V) 25 125 0.90 0.80 0.70 0.60 1.0 0.9 0.8 5 5.5 1.25 1.00 0.75 Output Source Current vs. Output Voltage 55 45 35 25 0 1 2 3 4 Output Voltage (V) Document Number: 38-06016 Rev. *H 100 25 10 VCC = 5.0 V TA = 25 °C 0 125 25 Ambient Temperature (°C) OUTPUT SINK CURRENT (mA) Supply Voltage (V) 75 40 0.50 55 6 50 VCC = 5.0 V Delta tA (ns) NORMALIZED tA 1.1 25 Typical tA Change vs. Output Loading 1.50 4.5 0 Frequency (MHz) Normalized tA vs. Ambient Temperature 1.2 4 VCC = 5.0 V TA = 25 °C VIN = 3.0 V 1.00 Ambient Temperature (C) Normalized tA vs. Supply Voltage normalized tA 1.10 VIN = 3.0 V VCC = 5.0 V f = 100 MHz NORMALIZED ICC NORMALIZED ICC Normalized ICC 1.4 Output Source Current (mA) Normalized Supply Current vs. Frequency 0 200 400 600 800 1000 Capacitance (pF) Output Sink Current vs. Output Voltage 160 140 120 100 80 60 40 20 0 0 1 2 3 4 Output Voltage (V) Page 16 of 22 CY7C4221 / CY7C4231 Ordering Information 1 K × 9 Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type CY7C4221-15AXC 51-85063 32-pin Thin Quad Flat Pack (7 × 7 × 1.0 mm) Pb-free CY7C4221-15JXC 51-85002 32-pin Plastic Leaded Chip Carrier (0.453 × 0.553 inches) Pb-free Operating Range Commercial 2 K × 9 Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type CY7C4231-15AXC 51-85063 32-pin Thin Quad Flat Pack (7 × 7 × 1.0 mm) Pb-free CY7C4231-15JXC 51-85002 32-pin Plastic Leaded Chip Carrier (0.453 × 0.553 inches) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 4 2X 1 - 15 X X C Temperature Range: C = Commercial Pb-free Package Type: X = A or J A = 32-pin TQFP; J = 32-pin PLCC Speed Grade: 15 ns Width: × 9 Density: 2X = 22 or 23 22 = 1K; 23 = 2K 4 = FIFO Technology Code: C = CMOS Marketing Code: 7 = Dual Port Company ID: CY = Cypress Document Number: 38-06016 Rev. *H Page 17 of 22 CY7C4221 / CY7C4231 Package Diagrams Figure 15. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063 51-85063 *D Document Number: 38-06016 Rev. *H Page 18 of 22 CY7C4221 / CY7C4231 Package Diagrams (continued) Figure 16. 32-pin PLCC (0.453 × 0.553 Inches) J32 Package Outline, 51-85002 51-85002 *D Document Number: 38-06016 Rev. *H Page 19 of 22 CY7C4221 / CY7C4231 Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor EF empty flag °C degree Celsius ESD electrostatic discharge k kilohm FF full flag MHz megahertz FIFO first-in first-out µA microampere LSB least significant bit mA milliampere MSB most significant bit mm millimeter OE output enable ns nanosecond PLCC plastic leaded chip carrier ohm RCLK read clock % percent RS reset pF picofarad TQFP thin quad flat pack V volt TTL transistor-transistor logic W watts WCLK write clock Document Number: 38-06016 Rev. *H Symbol Unit of Measure Page 20 of 22 CY7C4221 / CY7C4231 Document History Page Document Title: CY7C4221 / CY7C4231, 1 K / 2 K × 9 Synchronous FIFOs Document Number: 38-06016 Orig. of Rev. ECN No. Submission Description of Change Date Change ** 106477 09/10/01 SZV Change from Spec number: 38-00419 to 38-06016 *A 110725 03/20/02 FSG Change Input Leakage current IIX unit from mA to A (typo) *B 122268 12/26/02 RBI Power up requirements added to Maximum Ratings Information *C 386306 See ECN ESH Added Pb-free logo to top of front page Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC, CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC, CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC, CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC, CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI, CY7C4251-15AXC, CY7C4251-15JXC *D 2863896 01/22/10 VKN / Removed inactive/pruned parts from the Ordering Information table PYRS Added Table of Contents Updated TQFP package diagram *E 2896378 03/19/2010 RAME Removed inactive parts from Ordering information and updated package diagram. *F 3091024 12/22/10 ADMU Modified PAE and PAF flags information Added Ordering Code Definition, Acronym, and Document Conventions. *G 3372970 09/15/2011 ADMU Updated title to read “CY7C4221 / CY7C4231, 1 K / 2 K × 9 Synchronous FIFOs”. Updated Features (Removed CY7C4421, CY7C4201, CY7C4211, CY7C4241, CY7C4251 information). Updated Selection Guide (Removed CY7C4421, CY7C4201, CY7C4211, CY7C4241, CY7C4251 information). Updated Figure 2 and Table 2 in Programming (Removed CY7C4421, CY7C4201, CY7C4211, CY7C4241, CY7C4251 information). Updated Figure 3 in Width Expansion Configuration (Removed CY7C4421, CY7C4201, CY7C4211, CY7C4241, CY7C4251 information). Updated Electrical Characteristics (Removed -10 and -25 speed bin information). Updated Switching Characteristics (Removed -10 and -25 speed bin information). Updated Typical AC and DC Characteristics. Updated Package Diagrams. Updated in new template. *H 3744106 09/17/2012 SMCH Updated Pin Definitions (Included overbar on WEN pin). Updated Programming (Updated Programmable Flag (PAE, PAF) Operation (Updated Table 1 (Included overbars on LD and WEN in the table heading))). Document Number: 38-06016 Rev. *H Page 21 of 22 CY7C4221 / CY7C4231 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06016 Rev. *H Revised September 17, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 22 of 22